1185924Simp# $FreeBSD$ 2185924Simp 3217123Simp.if ${TARGET_ARCH:Mmips*el} != "" 4208737Sjmallett_EMULATION_ENDIAN=little 5208737Sjmallett.else 6208737Sjmallett_EMULATION_ENDIAN=big 7208737Sjmallett.endif 8208737Sjmallett 9217123Simp.if ${TARGET_ARCH:Mmips64*} != "" 10217123SimpDEFAULT_VECTOR= bfd_elf64_trad${_EMULATION_ENDIAN}mips_vec 11217123Simp.elif ${TARGET_ARCH:Mmipsn32*} != "" 12208737SjmallettDEFAULT_VECTOR= bfd_elf32_ntrad${_EMULATION_ENDIAN}mips_vec 13217123Simp.else 14217123SimpDEFAULT_VECTOR=bfd_elf32_trad${_EMULATION_ENDIAN}mips_vec 15208737Sjmallett.endif 16208737Sjmallett 17185924SimpSRCS+= coff-mips.c \ 18185924Simp cpu-mips.c \ 19185924Simp ecoff.c \ 20185924Simp ecofflink.c \ 21185924Simp elf32.c \ 22185924Simp elf64.c \ 23185924Simp elfn32-mips.c \ 24185924Simp elf32-mips.c \ 25185924Simp elf64-mips.c \ 26185924Simp elfxx-mips.c \ 27185924Simp elf32-target.h \ 28185924Simp elf64-target.h \ 29185924Simp elflink.c 30185924Simp 31185924SimpVECS= bfd_elf32_tradbigmips_vec \ 32185924Simp bfd_elf32_tradlittlemips_vec \ 33185924Simp bfd_elf32_ntradbigmips_vec \ 34185924Simp bfd_elf32_ntradlittlemips_vec \ 35185924Simp bfd_elf64_tradbigmips_vec \ 36185924Simp bfd_elf64_tradlittlemips_vec \ 37185924Simp ecoff_little_vec \ 38185924Simp ecoff_big_vec 39