1193323Sed//===- FastISelEmitter.cpp - Generate an instruction selector -------------===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This tablegen backend emits code for use by the "fast" instruction 11193323Sed// selection algorithm. See the comments at the top of 12193323Sed// lib/CodeGen/SelectionDAG/FastISel.cpp for background. 13193323Sed// 14193323Sed// This file scans through the target's tablegen instruction-info files 15193323Sed// and extracts instructions with obvious-looking patterns, and it emits 16193323Sed// code to look up these instructions by type and operator. 17193323Sed// 18193323Sed//===----------------------------------------------------------------------===// 19193323Sed 20239462Sdim#include "CodeGenDAGPatterns.h" 21218893Sdim#include "llvm/ADT/SmallString.h" 22223017Sdim#include "llvm/Support/Debug.h" 23223017Sdim#include "llvm/Support/ErrorHandling.h" 24239462Sdim#include "llvm/TableGen/Error.h" 25239462Sdim#include "llvm/TableGen/Record.h" 26239462Sdim#include "llvm/TableGen/TableGenBackend.h" 27193323Sedusing namespace llvm; 28193323Sed 29193323Sed 30193323Sed/// InstructionMemo - This class holds additional information about an 31193323Sed/// instruction needed to emit code for it. 32193323Sed/// 33239462Sdimnamespace { 34193323Sedstruct InstructionMemo { 35193323Sed std::string Name; 36193323Sed const CodeGenRegisterClass *RC; 37208599Srdivacky std::string SubRegNo; 38193323Sed std::vector<std::string>* PhysRegs; 39193323Sed}; 40239462Sdim} // End anonymous namespace 41239462Sdim 42221345Sdim/// ImmPredicateSet - This uniques predicates (represented as a string) and 43221345Sdim/// gives them unique (small) integer ID's that start at 0. 44239462Sdimnamespace { 45221345Sdimclass ImmPredicateSet { 46221345Sdim DenseMap<TreePattern *, unsigned> ImmIDs; 47221345Sdim std::vector<TreePredicateFn> PredsByName; 48221345Sdimpublic: 49221345Sdim 50221345Sdim unsigned getIDFor(TreePredicateFn Pred) { 51221345Sdim unsigned &Entry = ImmIDs[Pred.getOrigPatFragRecord()]; 52221345Sdim if (Entry == 0) { 53221345Sdim PredsByName.push_back(Pred); 54221345Sdim Entry = PredsByName.size(); 55221345Sdim } 56221345Sdim return Entry-1; 57221345Sdim } 58221345Sdim 59221345Sdim const TreePredicateFn &getPredicate(unsigned i) { 60221345Sdim assert(i < PredsByName.size()); 61221345Sdim return PredsByName[i]; 62221345Sdim } 63221345Sdim 64221345Sdim typedef std::vector<TreePredicateFn>::const_iterator iterator; 65221345Sdim iterator begin() const { return PredsByName.begin(); } 66221345Sdim iterator end() const { return PredsByName.end(); } 67221345Sdim 68221345Sdim}; 69239462Sdim} // End anonymous namespace 70193323Sed 71193323Sed/// OperandsSignature - This class holds a description of a list of operand 72193323Sed/// types. It has utility methods for emitting text based on the operands. 73193323Sed/// 74239462Sdimnamespace { 75193323Sedstruct OperandsSignature { 76221345Sdim class OpKind { 77221345Sdim enum { OK_Reg, OK_FP, OK_Imm, OK_Invalid = -1 }; 78221345Sdim char Repr; 79221345Sdim public: 80221345Sdim 81221345Sdim OpKind() : Repr(OK_Invalid) {} 82221345Sdim 83221345Sdim bool operator<(OpKind RHS) const { return Repr < RHS.Repr; } 84221345Sdim bool operator==(OpKind RHS) const { return Repr == RHS.Repr; } 85193323Sed 86221345Sdim static OpKind getReg() { OpKind K; K.Repr = OK_Reg; return K; } 87221345Sdim static OpKind getFP() { OpKind K; K.Repr = OK_FP; return K; } 88221345Sdim static OpKind getImm(unsigned V) { 89221345Sdim assert((unsigned)OK_Imm+V < 128 && 90221345Sdim "Too many integer predicates for the 'Repr' char"); 91221345Sdim OpKind K; K.Repr = OK_Imm+V; return K; 92221345Sdim } 93221345Sdim 94221345Sdim bool isReg() const { return Repr == OK_Reg; } 95221345Sdim bool isFP() const { return Repr == OK_FP; } 96221345Sdim bool isImm() const { return Repr >= OK_Imm; } 97221345Sdim 98221345Sdim unsigned getImmCode() const { assert(isImm()); return Repr-OK_Imm; } 99221345Sdim 100221345Sdim void printManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates, 101221345Sdim bool StripImmCodes) const { 102221345Sdim if (isReg()) 103221345Sdim OS << 'r'; 104221345Sdim else if (isFP()) 105221345Sdim OS << 'f'; 106221345Sdim else { 107221345Sdim OS << 'i'; 108221345Sdim if (!StripImmCodes) 109221345Sdim if (unsigned Code = getImmCode()) 110221345Sdim OS << "_" << ImmPredicates.getPredicate(Code-1).getFnName(); 111221345Sdim } 112221345Sdim } 113221345Sdim }; 114221345Sdim 115221345Sdim 116221345Sdim SmallVector<OpKind, 3> Operands; 117221345Sdim 118193323Sed bool operator<(const OperandsSignature &O) const { 119193323Sed return Operands < O.Operands; 120193323Sed } 121221345Sdim bool operator==(const OperandsSignature &O) const { 122221345Sdim return Operands == O.Operands; 123221345Sdim } 124193323Sed 125193323Sed bool empty() const { return Operands.empty(); } 126193323Sed 127221345Sdim bool hasAnyImmediateCodes() const { 128221345Sdim for (unsigned i = 0, e = Operands.size(); i != e; ++i) 129221345Sdim if (Operands[i].isImm() && Operands[i].getImmCode() != 0) 130221345Sdim return true; 131221345Sdim return false; 132221345Sdim } 133221345Sdim 134221345Sdim /// getWithoutImmCodes - Return a copy of this with any immediate codes forced 135221345Sdim /// to zero. 136221345Sdim OperandsSignature getWithoutImmCodes() const { 137221345Sdim OperandsSignature Result; 138221345Sdim for (unsigned i = 0, e = Operands.size(); i != e; ++i) 139221345Sdim if (!Operands[i].isImm()) 140221345Sdim Result.Operands.push_back(Operands[i]); 141221345Sdim else 142221345Sdim Result.Operands.push_back(OpKind::getImm(0)); 143221345Sdim return Result; 144221345Sdim } 145221345Sdim 146221345Sdim void emitImmediatePredicate(raw_ostream &OS, ImmPredicateSet &ImmPredicates) { 147221345Sdim bool EmittedAnything = false; 148221345Sdim for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 149221345Sdim if (!Operands[i].isImm()) continue; 150221345Sdim 151221345Sdim unsigned Code = Operands[i].getImmCode(); 152221345Sdim if (Code == 0) continue; 153221345Sdim 154221345Sdim if (EmittedAnything) 155221345Sdim OS << " &&\n "; 156221345Sdim 157221345Sdim TreePredicateFn PredFn = ImmPredicates.getPredicate(Code-1); 158221345Sdim 159221345Sdim // Emit the type check. 160221345Sdim OS << "VT == " 161221345Sdim << getEnumName(PredFn.getOrigPatFragRecord()->getTree(0)->getType(0)) 162221345Sdim << " && "; 163221345Sdim 164221345Sdim 165221345Sdim OS << PredFn.getFnName() << "(imm" << i <<')'; 166221345Sdim EmittedAnything = true; 167221345Sdim } 168221345Sdim } 169221345Sdim 170193323Sed /// initialize - Examine the given pattern and initialize the contents 171193323Sed /// of the Operands array accordingly. Return true if all the operands 172193323Sed /// are supported, false otherwise. 173193323Sed /// 174221345Sdim bool initialize(TreePatternNode *InstPatNode, const CodeGenTarget &Target, 175221345Sdim MVT::SimpleValueType VT, 176221345Sdim ImmPredicateSet &ImmediatePredicates) { 177221345Sdim if (InstPatNode->isLeaf()) 178221345Sdim return false; 179221345Sdim 180221345Sdim if (InstPatNode->getOperator()->getName() == "imm") { 181221345Sdim Operands.push_back(OpKind::getImm(0)); 182221345Sdim return true; 183193323Sed } 184221345Sdim 185221345Sdim if (InstPatNode->getOperator()->getName() == "fpimm") { 186221345Sdim Operands.push_back(OpKind::getFP()); 187221345Sdim return true; 188221345Sdim } 189218893Sdim 190193323Sed const CodeGenRegisterClass *DstRC = 0; 191218893Sdim 192193323Sed for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) { 193193323Sed TreePatternNode *Op = InstPatNode->getChild(i); 194218893Sdim 195221345Sdim // Handle imm operands specially. 196221345Sdim if (!Op->isLeaf() && Op->getOperator()->getName() == "imm") { 197221345Sdim unsigned PredNo = 0; 198221345Sdim if (!Op->getPredicateFns().empty()) { 199221345Sdim TreePredicateFn PredFn = Op->getPredicateFns()[0]; 200221345Sdim // If there is more than one predicate weighing in on this operand 201221345Sdim // then we don't handle it. This doesn't typically happen for 202221345Sdim // immediates anyway. 203221345Sdim if (Op->getPredicateFns().size() > 1 || 204221345Sdim !PredFn.isImmediatePattern()) 205221345Sdim return false; 206221345Sdim // Ignore any instruction with 'FastIselShouldIgnore', these are 207221345Sdim // not needed and just bloat the fast instruction selector. For 208221345Sdim // example, X86 doesn't need to generate code to match ADD16ri8 since 209221345Sdim // ADD16ri will do just fine. 210221345Sdim Record *Rec = PredFn.getOrigPatFragRecord()->getRecord(); 211221345Sdim if (Rec->getValueAsBit("FastIselShouldIgnore")) 212221345Sdim return false; 213221345Sdim 214221345Sdim PredNo = ImmediatePredicates.getIDFor(PredFn)+1; 215221345Sdim } 216221345Sdim 217221345Sdim // Handle unmatched immediate sizes here. 218221345Sdim //if (Op->getType(0) != VT) 219221345Sdim // return false; 220221345Sdim 221221345Sdim Operands.push_back(OpKind::getImm(PredNo)); 222221345Sdim continue; 223221345Sdim } 224221345Sdim 225221345Sdim 226193323Sed // For now, filter out any operand with a predicate. 227205407Srdivacky // For now, filter out any operand with multiple values. 228221345Sdim if (!Op->getPredicateFns().empty() || Op->getNumTypes() != 1) 229193323Sed return false; 230218893Sdim 231193323Sed if (!Op->isLeaf()) { 232221345Sdim if (Op->getOperator()->getName() == "fpimm") { 233221345Sdim Operands.push_back(OpKind::getFP()); 234193323Sed continue; 235193323Sed } 236193323Sed // For now, ignore other non-leaf nodes. 237193323Sed return false; 238193323Sed } 239221345Sdim 240221345Sdim assert(Op->hasTypeSet(0) && "Type infererence not done?"); 241221345Sdim 242221345Sdim // For now, all the operands must have the same type (if they aren't 243221345Sdim // immediates). Note that this causes us to reject variable sized shifts 244221345Sdim // on X86. 245221345Sdim if (Op->getType(0) != VT) 246221345Sdim return false; 247221345Sdim 248243830Sdim DefInit *OpDI = dyn_cast<DefInit>(Op->getLeafValue()); 249193323Sed if (!OpDI) 250193323Sed return false; 251193323Sed Record *OpLeafRec = OpDI->getDef(); 252221345Sdim 253193323Sed // For now, the only other thing we accept is register operands. 254193323Sed const CodeGenRegisterClass *RC = 0; 255224145Sdim if (OpLeafRec->isSubClassOf("RegisterOperand")) 256224145Sdim OpLeafRec = OpLeafRec->getValueAsDef("RegClass"); 257193323Sed if (OpLeafRec->isSubClassOf("RegisterClass")) 258193323Sed RC = &Target.getRegisterClass(OpLeafRec); 259193323Sed else if (OpLeafRec->isSubClassOf("Register")) 260224145Sdim RC = Target.getRegBank().getRegClassForRegister(OpLeafRec); 261193323Sed else 262193323Sed return false; 263218893Sdim 264212904Sdim // For now, this needs to be a register class of some sort. 265193323Sed if (!RC) 266193323Sed return false; 267212904Sdim 268212904Sdim // For now, all the operands must have the same register class or be 269212904Sdim // a strict subclass of the destination. 270193323Sed if (DstRC) { 271212904Sdim if (DstRC != RC && !DstRC->hasSubClass(RC)) 272193323Sed return false; 273193323Sed } else 274193323Sed DstRC = RC; 275221345Sdim Operands.push_back(OpKind::getReg()); 276193323Sed } 277193323Sed return true; 278193323Sed } 279193323Sed 280195340Sed void PrintParameters(raw_ostream &OS) const { 281193323Sed for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 282221345Sdim if (Operands[i].isReg()) { 283208599Srdivacky OS << "unsigned Op" << i << ", bool Op" << i << "IsKill"; 284221345Sdim } else if (Operands[i].isImm()) { 285193323Sed OS << "uint64_t imm" << i; 286221345Sdim } else if (Operands[i].isFP()) { 287234353Sdim OS << "const ConstantFP *f" << i; 288193323Sed } else { 289223017Sdim llvm_unreachable("Unknown operand kind!"); 290193323Sed } 291193323Sed if (i + 1 != e) 292193323Sed OS << ", "; 293193323Sed } 294193323Sed } 295193323Sed 296195340Sed void PrintArguments(raw_ostream &OS, 297221345Sdim const std::vector<std::string> &PR) const { 298193323Sed assert(PR.size() == Operands.size()); 299193323Sed bool PrintedArg = false; 300193323Sed for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 301193323Sed if (PR[i] != "") 302193323Sed // Implicit physical register operand. 303193323Sed continue; 304193323Sed 305193323Sed if (PrintedArg) 306193323Sed OS << ", "; 307221345Sdim if (Operands[i].isReg()) { 308208599Srdivacky OS << "Op" << i << ", Op" << i << "IsKill"; 309193323Sed PrintedArg = true; 310221345Sdim } else if (Operands[i].isImm()) { 311193323Sed OS << "imm" << i; 312193323Sed PrintedArg = true; 313221345Sdim } else if (Operands[i].isFP()) { 314193323Sed OS << "f" << i; 315193323Sed PrintedArg = true; 316193323Sed } else { 317223017Sdim llvm_unreachable("Unknown operand kind!"); 318193323Sed } 319193323Sed } 320193323Sed } 321193323Sed 322195340Sed void PrintArguments(raw_ostream &OS) const { 323193323Sed for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 324221345Sdim if (Operands[i].isReg()) { 325208599Srdivacky OS << "Op" << i << ", Op" << i << "IsKill"; 326221345Sdim } else if (Operands[i].isImm()) { 327193323Sed OS << "imm" << i; 328221345Sdim } else if (Operands[i].isFP()) { 329193323Sed OS << "f" << i; 330193323Sed } else { 331223017Sdim llvm_unreachable("Unknown operand kind!"); 332193323Sed } 333193323Sed if (i + 1 != e) 334193323Sed OS << ", "; 335193323Sed } 336193323Sed } 337193323Sed 338193323Sed 339221345Sdim void PrintManglingSuffix(raw_ostream &OS, const std::vector<std::string> &PR, 340221345Sdim ImmPredicateSet &ImmPredicates, 341221345Sdim bool StripImmCodes = false) const { 342193323Sed for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 343193323Sed if (PR[i] != "") 344193323Sed // Implicit physical register operand. e.g. Instruction::Mul expect to 345193323Sed // select to a binary op. On x86, mul may take a single operand with 346193323Sed // the other operand being implicit. We must emit something that looks 347193323Sed // like a binary instruction except for the very inner FastEmitInst_* 348193323Sed // call. 349193323Sed continue; 350221345Sdim Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes); 351193323Sed } 352193323Sed } 353193323Sed 354221345Sdim void PrintManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates, 355221345Sdim bool StripImmCodes = false) const { 356221345Sdim for (unsigned i = 0, e = Operands.size(); i != e; ++i) 357221345Sdim Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes); 358193323Sed } 359193323Sed}; 360239462Sdim} // End anonymous namespace 361193323Sed 362239462Sdimnamespace { 363193323Sedclass FastISelMap { 364193323Sed typedef std::map<std::string, InstructionMemo> PredMap; 365193323Sed typedef std::map<MVT::SimpleValueType, PredMap> RetPredMap; 366193323Sed typedef std::map<MVT::SimpleValueType, RetPredMap> TypeRetPredMap; 367193323Sed typedef std::map<std::string, TypeRetPredMap> OpcodeTypeRetPredMap; 368218893Sdim typedef std::map<OperandsSignature, OpcodeTypeRetPredMap> 369212904Sdim OperandsOpcodeTypeRetPredMap; 370193323Sed 371193323Sed OperandsOpcodeTypeRetPredMap SimplePatterns; 372193323Sed 373221345Sdim std::map<OperandsSignature, std::vector<OperandsSignature> > 374221345Sdim SignaturesWithConstantForms; 375221345Sdim 376193323Sed std::string InstNS; 377221345Sdim ImmPredicateSet ImmediatePredicates; 378193323Sedpublic: 379193323Sed explicit FastISelMap(std::string InstNS); 380193323Sed 381221345Sdim void collectPatterns(CodeGenDAGPatterns &CGP); 382221345Sdim void printImmediatePredicates(raw_ostream &OS); 383221345Sdim void printFunctionDefinitions(raw_ostream &OS); 384193323Sed}; 385239462Sdim} // End anonymous namespace 386193323Sed 387193323Sedstatic std::string getOpcodeName(Record *Op, CodeGenDAGPatterns &CGP) { 388193323Sed return CGP.getSDNodeInfo(Op).getEnumName(); 389193323Sed} 390193323Sed 391193323Sedstatic std::string getLegalCName(std::string OpName) { 392193323Sed std::string::size_type pos = OpName.find("::"); 393193323Sed if (pos != std::string::npos) 394193323Sed OpName.replace(pos, 2, "_"); 395193323Sed return OpName; 396193323Sed} 397193323Sed 398193323SedFastISelMap::FastISelMap(std::string instns) 399193323Sed : InstNS(instns) { 400193323Sed} 401193323Sed 402221345Sdimstatic std::string PhyRegForNode(TreePatternNode *Op, 403221345Sdim const CodeGenTarget &Target) { 404221345Sdim std::string PhysReg; 405221345Sdim 406221345Sdim if (!Op->isLeaf()) 407221345Sdim return PhysReg; 408221345Sdim 409243830Sdim Record *OpLeafRec = cast<DefInit>(Op->getLeafValue())->getDef(); 410221345Sdim if (!OpLeafRec->isSubClassOf("Register")) 411221345Sdim return PhysReg; 412221345Sdim 413243830Sdim PhysReg += cast<StringInit>(OpLeafRec->getValue("Namespace")->getValue()) 414243830Sdim ->getValue(); 415221345Sdim PhysReg += "::"; 416224145Sdim PhysReg += Target.getRegBank().getReg(OpLeafRec)->getName(); 417221345Sdim return PhysReg; 418221345Sdim} 419221345Sdim 420221345Sdimvoid FastISelMap::collectPatterns(CodeGenDAGPatterns &CGP) { 421193323Sed const CodeGenTarget &Target = CGP.getTargetInfo(); 422193323Sed 423193323Sed // Determine the target's namespace name. 424193323Sed InstNS = Target.getInstNamespace() + "::"; 425193323Sed assert(InstNS.size() > 2 && "Can't determine target-specific namespace!"); 426193323Sed 427193323Sed // Scan through all the patterns and record the simple ones. 428193323Sed for (CodeGenDAGPatterns::ptm_iterator I = CGP.ptm_begin(), 429193323Sed E = CGP.ptm_end(); I != E; ++I) { 430193323Sed const PatternToMatch &Pattern = *I; 431193323Sed 432193323Sed // For now, just look at Instructions, so that we don't have to worry 433193323Sed // about emitting multiple instructions for a pattern. 434193323Sed TreePatternNode *Dst = Pattern.getDstPattern(); 435193323Sed if (Dst->isLeaf()) continue; 436193323Sed Record *Op = Dst->getOperator(); 437193323Sed if (!Op->isSubClassOf("Instruction")) 438193323Sed continue; 439205407Srdivacky CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(Op); 440221345Sdim if (II.Operands.empty()) 441193323Sed continue; 442218893Sdim 443193323Sed // For now, ignore multi-instruction patterns. 444193323Sed bool MultiInsts = false; 445193323Sed for (unsigned i = 0, e = Dst->getNumChildren(); i != e; ++i) { 446193323Sed TreePatternNode *ChildOp = Dst->getChild(i); 447193323Sed if (ChildOp->isLeaf()) 448193323Sed continue; 449193323Sed if (ChildOp->getOperator()->isSubClassOf("Instruction")) { 450193323Sed MultiInsts = true; 451193323Sed break; 452193323Sed } 453193323Sed } 454193323Sed if (MultiInsts) 455193323Sed continue; 456193323Sed 457193323Sed // For now, ignore instructions where the first operand is not an 458193323Sed // output register. 459193323Sed const CodeGenRegisterClass *DstRC = 0; 460208599Srdivacky std::string SubRegNo; 461193323Sed if (Op->getName() != "EXTRACT_SUBREG") { 462218893Sdim Record *Op0Rec = II.Operands[0].Rec; 463224145Sdim if (Op0Rec->isSubClassOf("RegisterOperand")) 464224145Sdim Op0Rec = Op0Rec->getValueAsDef("RegClass"); 465193323Sed if (!Op0Rec->isSubClassOf("RegisterClass")) 466193323Sed continue; 467193323Sed DstRC = &Target.getRegisterClass(Op0Rec); 468193323Sed if (!DstRC) 469193323Sed continue; 470193323Sed } else { 471212904Sdim // If this isn't a leaf, then continue since the register classes are 472212904Sdim // a bit too complicated for now. 473212904Sdim if (!Dst->getChild(1)->isLeaf()) continue; 474218893Sdim 475243830Sdim DefInit *SR = dyn_cast<DefInit>(Dst->getChild(1)->getLeafValue()); 476208599Srdivacky if (SR) 477208599Srdivacky SubRegNo = getQualifiedName(SR->getDef()); 478208599Srdivacky else 479208599Srdivacky SubRegNo = Dst->getChild(1)->getLeafValue()->getAsString(); 480193323Sed } 481193323Sed 482193323Sed // Inspect the pattern. 483193323Sed TreePatternNode *InstPatNode = Pattern.getSrcPattern(); 484193323Sed if (!InstPatNode) continue; 485193323Sed if (InstPatNode->isLeaf()) continue; 486193323Sed 487206083Srdivacky // Ignore multiple result nodes for now. 488206083Srdivacky if (InstPatNode->getNumTypes() > 1) continue; 489218893Sdim 490193323Sed Record *InstPatOp = InstPatNode->getOperator(); 491193323Sed std::string OpcodeName = getOpcodeName(InstPatOp, CGP); 492205407Srdivacky MVT::SimpleValueType RetVT = MVT::isVoid; 493205407Srdivacky if (InstPatNode->getNumTypes()) RetVT = InstPatNode->getType(0); 494193323Sed MVT::SimpleValueType VT = RetVT; 495205407Srdivacky if (InstPatNode->getNumChildren()) { 496205407Srdivacky assert(InstPatNode->getChild(0)->getNumTypes() == 1); 497205407Srdivacky VT = InstPatNode->getChild(0)->getType(0); 498205407Srdivacky } 499193323Sed 500193323Sed // For now, filter out any instructions with predicates. 501193323Sed if (!InstPatNode->getPredicateFns().empty()) 502193323Sed continue; 503193323Sed 504193323Sed // Check all the operands. 505193323Sed OperandsSignature Operands; 506221345Sdim if (!Operands.initialize(InstPatNode, Target, VT, ImmediatePredicates)) 507193323Sed continue; 508218893Sdim 509193323Sed std::vector<std::string>* PhysRegInputs = new std::vector<std::string>(); 510221345Sdim if (InstPatNode->getOperator()->getName() == "imm" || 511226633Sdim InstPatNode->getOperator()->getName() == "fpimm") 512193323Sed PhysRegInputs->push_back(""); 513221345Sdim else { 514221345Sdim // Compute the PhysRegs used by the given pattern, and check that 515221345Sdim // the mapping from the src to dst patterns is simple. 516221345Sdim bool FoundNonSimplePattern = false; 517221345Sdim unsigned DstIndex = 0; 518193323Sed for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) { 519221345Sdim std::string PhysReg = PhyRegForNode(InstPatNode->getChild(i), Target); 520221345Sdim if (PhysReg.empty()) { 521221345Sdim if (DstIndex >= Dst->getNumChildren() || 522221345Sdim Dst->getChild(DstIndex)->getName() != 523221345Sdim InstPatNode->getChild(i)->getName()) { 524221345Sdim FoundNonSimplePattern = true; 525221345Sdim break; 526193323Sed } 527221345Sdim ++DstIndex; 528193323Sed } 529218893Sdim 530193323Sed PhysRegInputs->push_back(PhysReg); 531193323Sed } 532193323Sed 533221345Sdim if (Op->getName() != "EXTRACT_SUBREG" && DstIndex < Dst->getNumChildren()) 534221345Sdim FoundNonSimplePattern = true; 535221345Sdim 536221345Sdim if (FoundNonSimplePattern) 537221345Sdim continue; 538221345Sdim } 539221345Sdim 540193323Sed // Get the predicate that guards this pattern. 541193323Sed std::string PredicateCheck = Pattern.getPredicateCheck(); 542193323Sed 543193323Sed // Ok, we found a pattern that we can handle. Remember it. 544193323Sed InstructionMemo Memo = { 545193323Sed Pattern.getDstPattern()->getOperator()->getName(), 546193323Sed DstRC, 547193323Sed SubRegNo, 548193323Sed PhysRegInputs 549193323Sed }; 550221345Sdim 551221345Sdim if (SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck)) 552243830Sdim PrintFatalError(Pattern.getSrcRecord()->getLoc(), 553221345Sdim "Duplicate record in FastISel table!"); 554218893Sdim 555193323Sed SimplePatterns[Operands][OpcodeName][VT][RetVT][PredicateCheck] = Memo; 556221345Sdim 557221345Sdim // If any of the operands were immediates with predicates on them, strip 558221345Sdim // them down to a signature that doesn't have predicates so that we can 559221345Sdim // associate them with the stripped predicate version. 560221345Sdim if (Operands.hasAnyImmediateCodes()) { 561221345Sdim SignaturesWithConstantForms[Operands.getWithoutImmCodes()] 562221345Sdim .push_back(Operands); 563221345Sdim } 564193323Sed } 565193323Sed} 566193323Sed 567221345Sdimvoid FastISelMap::printImmediatePredicates(raw_ostream &OS) { 568221345Sdim if (ImmediatePredicates.begin() == ImmediatePredicates.end()) 569221345Sdim return; 570221345Sdim 571221345Sdim OS << "\n// FastEmit Immediate Predicate functions.\n"; 572221345Sdim for (ImmPredicateSet::iterator I = ImmediatePredicates.begin(), 573221345Sdim E = ImmediatePredicates.end(); I != E; ++I) { 574221345Sdim OS << "static bool " << I->getFnName() << "(int64_t Imm) {\n"; 575221345Sdim OS << I->getImmediatePredicateCode() << "\n}\n"; 576221345Sdim } 577221345Sdim 578221345Sdim OS << "\n\n"; 579221345Sdim} 580221345Sdim 581221345Sdim 582221345Sdimvoid FastISelMap::printFunctionDefinitions(raw_ostream &OS) { 583193323Sed // Now emit code for all the patterns that we collected. 584193323Sed for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(), 585193323Sed OE = SimplePatterns.end(); OI != OE; ++OI) { 586193323Sed const OperandsSignature &Operands = OI->first; 587193323Sed const OpcodeTypeRetPredMap &OTM = OI->second; 588193323Sed 589193323Sed for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end(); 590193323Sed I != E; ++I) { 591193323Sed const std::string &Opcode = I->first; 592193323Sed const TypeRetPredMap &TM = I->second; 593193323Sed 594193323Sed OS << "// FastEmit functions for " << Opcode << ".\n"; 595193323Sed OS << "\n"; 596193323Sed 597193323Sed // Emit one function for each opcode,type pair. 598193323Sed for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end(); 599193323Sed TI != TE; ++TI) { 600193323Sed MVT::SimpleValueType VT = TI->first; 601193323Sed const RetPredMap &RM = TI->second; 602193323Sed if (RM.size() != 1) { 603193323Sed for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end(); 604193323Sed RI != RE; ++RI) { 605193323Sed MVT::SimpleValueType RetVT = RI->first; 606193323Sed const PredMap &PM = RI->second; 607193323Sed bool HasPred = false; 608193323Sed 609193323Sed OS << "unsigned FastEmit_" 610193323Sed << getLegalCName(Opcode) 611193323Sed << "_" << getLegalCName(getName(VT)) 612193323Sed << "_" << getLegalCName(getName(RetVT)) << "_"; 613221345Sdim Operands.PrintManglingSuffix(OS, ImmediatePredicates); 614193323Sed OS << "("; 615193323Sed Operands.PrintParameters(OS); 616193323Sed OS << ") {\n"; 617193323Sed 618193323Sed // Emit code for each possible instruction. There may be 619193323Sed // multiple if there are subtarget concerns. 620193323Sed for (PredMap::const_iterator PI = PM.begin(), PE = PM.end(); 621193323Sed PI != PE; ++PI) { 622193323Sed std::string PredicateCheck = PI->first; 623193323Sed const InstructionMemo &Memo = PI->second; 624218893Sdim 625193323Sed if (PredicateCheck.empty()) { 626193323Sed assert(!HasPred && 627193323Sed "Multiple instructions match, at least one has " 628193323Sed "a predicate and at least one doesn't!"); 629193323Sed } else { 630193323Sed OS << " if (" + PredicateCheck + ") {\n"; 631193323Sed OS << " "; 632193323Sed HasPred = true; 633193323Sed } 634218893Sdim 635193323Sed for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) { 636193323Sed if ((*Memo.PhysRegs)[i] != "") 637210299Sed OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, " 638210299Sed << "TII.get(TargetOpcode::COPY), " 639210299Sed << (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n"; 640193323Sed } 641218893Sdim 642193323Sed OS << " return FastEmitInst_"; 643208599Srdivacky if (Memo.SubRegNo.empty()) { 644221345Sdim Operands.PrintManglingSuffix(OS, *Memo.PhysRegs, 645221345Sdim ImmediatePredicates, true); 646193323Sed OS << "(" << InstNS << Memo.Name << ", "; 647239462Sdim OS << "&" << InstNS << Memo.RC->getName() << "RegClass"; 648193323Sed if (!Operands.empty()) 649193323Sed OS << ", "; 650193323Sed Operands.PrintArguments(OS, *Memo.PhysRegs); 651193323Sed OS << ");\n"; 652193323Sed } else { 653193323Sed OS << "extractsubreg(" << getName(RetVT); 654221345Sdim OS << ", Op0, Op0IsKill, " << Memo.SubRegNo << ");\n"; 655193323Sed } 656218893Sdim 657193323Sed if (HasPred) 658193323Sed OS << " }\n"; 659218893Sdim 660193323Sed } 661193323Sed // Return 0 if none of the predicates were satisfied. 662193323Sed if (HasPred) 663193323Sed OS << " return 0;\n"; 664193323Sed OS << "}\n"; 665193323Sed OS << "\n"; 666193323Sed } 667218893Sdim 668193323Sed // Emit one function for the type that demultiplexes on return type. 669193323Sed OS << "unsigned FastEmit_" 670193323Sed << getLegalCName(Opcode) << "_" 671193323Sed << getLegalCName(getName(VT)) << "_"; 672221345Sdim Operands.PrintManglingSuffix(OS, ImmediatePredicates); 673198090Srdivacky OS << "(MVT RetVT"; 674193323Sed if (!Operands.empty()) 675193323Sed OS << ", "; 676193323Sed Operands.PrintParameters(OS); 677198090Srdivacky OS << ") {\nswitch (RetVT.SimpleTy) {\n"; 678193323Sed for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end(); 679193323Sed RI != RE; ++RI) { 680193323Sed MVT::SimpleValueType RetVT = RI->first; 681193323Sed OS << " case " << getName(RetVT) << ": return FastEmit_" 682193323Sed << getLegalCName(Opcode) << "_" << getLegalCName(getName(VT)) 683193323Sed << "_" << getLegalCName(getName(RetVT)) << "_"; 684221345Sdim Operands.PrintManglingSuffix(OS, ImmediatePredicates); 685193323Sed OS << "("; 686193323Sed Operands.PrintArguments(OS); 687193323Sed OS << ");\n"; 688193323Sed } 689193323Sed OS << " default: return 0;\n}\n}\n\n"; 690218893Sdim 691193323Sed } else { 692193323Sed // Non-variadic return type. 693193323Sed OS << "unsigned FastEmit_" 694193323Sed << getLegalCName(Opcode) << "_" 695193323Sed << getLegalCName(getName(VT)) << "_"; 696221345Sdim Operands.PrintManglingSuffix(OS, ImmediatePredicates); 697198090Srdivacky OS << "(MVT RetVT"; 698193323Sed if (!Operands.empty()) 699193323Sed OS << ", "; 700193323Sed Operands.PrintParameters(OS); 701193323Sed OS << ") {\n"; 702218893Sdim 703198090Srdivacky OS << " if (RetVT.SimpleTy != " << getName(RM.begin()->first) 704193323Sed << ")\n return 0;\n"; 705218893Sdim 706193323Sed const PredMap &PM = RM.begin()->second; 707193323Sed bool HasPred = false; 708218893Sdim 709193323Sed // Emit code for each possible instruction. There may be 710193323Sed // multiple if there are subtarget concerns. 711193323Sed for (PredMap::const_iterator PI = PM.begin(), PE = PM.end(); PI != PE; 712193323Sed ++PI) { 713193323Sed std::string PredicateCheck = PI->first; 714193323Sed const InstructionMemo &Memo = PI->second; 715193323Sed 716193323Sed if (PredicateCheck.empty()) { 717193323Sed assert(!HasPred && 718193323Sed "Multiple instructions match, at least one has " 719193323Sed "a predicate and at least one doesn't!"); 720193323Sed } else { 721193323Sed OS << " if (" + PredicateCheck + ") {\n"; 722193323Sed OS << " "; 723193323Sed HasPred = true; 724193323Sed } 725218893Sdim 726210299Sed for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) { 727210299Sed if ((*Memo.PhysRegs)[i] != "") 728210299Sed OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, " 729210299Sed << "TII.get(TargetOpcode::COPY), " 730210299Sed << (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n"; 731210299Sed } 732218893Sdim 733193323Sed OS << " return FastEmitInst_"; 734218893Sdim 735208599Srdivacky if (Memo.SubRegNo.empty()) { 736221345Sdim Operands.PrintManglingSuffix(OS, *Memo.PhysRegs, 737221345Sdim ImmediatePredicates, true); 738193323Sed OS << "(" << InstNS << Memo.Name << ", "; 739239462Sdim OS << "&" << InstNS << Memo.RC->getName() << "RegClass"; 740193323Sed if (!Operands.empty()) 741193323Sed OS << ", "; 742193323Sed Operands.PrintArguments(OS, *Memo.PhysRegs); 743193323Sed OS << ");\n"; 744193323Sed } else { 745208599Srdivacky OS << "extractsubreg(RetVT, Op0, Op0IsKill, "; 746208599Srdivacky OS << Memo.SubRegNo; 747193323Sed OS << ");\n"; 748193323Sed } 749218893Sdim 750193323Sed if (HasPred) 751193323Sed OS << " }\n"; 752193323Sed } 753218893Sdim 754193323Sed // Return 0 if none of the predicates were satisfied. 755193323Sed if (HasPred) 756193323Sed OS << " return 0;\n"; 757193323Sed OS << "}\n"; 758193323Sed OS << "\n"; 759193323Sed } 760193323Sed } 761193323Sed 762193323Sed // Emit one function for the opcode that demultiplexes based on the type. 763193323Sed OS << "unsigned FastEmit_" 764193323Sed << getLegalCName(Opcode) << "_"; 765221345Sdim Operands.PrintManglingSuffix(OS, ImmediatePredicates); 766198090Srdivacky OS << "(MVT VT, MVT RetVT"; 767193323Sed if (!Operands.empty()) 768193323Sed OS << ", "; 769193323Sed Operands.PrintParameters(OS); 770193323Sed OS << ") {\n"; 771198090Srdivacky OS << " switch (VT.SimpleTy) {\n"; 772193323Sed for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end(); 773193323Sed TI != TE; ++TI) { 774193323Sed MVT::SimpleValueType VT = TI->first; 775193323Sed std::string TypeName = getName(VT); 776193323Sed OS << " case " << TypeName << ": return FastEmit_" 777193323Sed << getLegalCName(Opcode) << "_" << getLegalCName(TypeName) << "_"; 778221345Sdim Operands.PrintManglingSuffix(OS, ImmediatePredicates); 779193323Sed OS << "(RetVT"; 780193323Sed if (!Operands.empty()) 781193323Sed OS << ", "; 782193323Sed Operands.PrintArguments(OS); 783193323Sed OS << ");\n"; 784193323Sed } 785193323Sed OS << " default: return 0;\n"; 786193323Sed OS << " }\n"; 787193323Sed OS << "}\n"; 788193323Sed OS << "\n"; 789193323Sed } 790193323Sed 791193323Sed OS << "// Top-level FastEmit function.\n"; 792193323Sed OS << "\n"; 793193323Sed 794193323Sed // Emit one function for the operand signature that demultiplexes based 795193323Sed // on opcode and type. 796193323Sed OS << "unsigned FastEmit_"; 797221345Sdim Operands.PrintManglingSuffix(OS, ImmediatePredicates); 798202375Srdivacky OS << "(MVT VT, MVT RetVT, unsigned Opcode"; 799193323Sed if (!Operands.empty()) 800193323Sed OS << ", "; 801193323Sed Operands.PrintParameters(OS); 802193323Sed OS << ") {\n"; 803221345Sdim 804221345Sdim // If there are any forms of this signature available that operand on 805221345Sdim // constrained forms of the immediate (e.g. 32-bit sext immediate in a 806221345Sdim // 64-bit operand), check them first. 807221345Sdim 808221345Sdim std::map<OperandsSignature, std::vector<OperandsSignature> >::iterator MI 809221345Sdim = SignaturesWithConstantForms.find(Operands); 810221345Sdim if (MI != SignaturesWithConstantForms.end()) { 811221345Sdim // Unique any duplicates out of the list. 812221345Sdim std::sort(MI->second.begin(), MI->second.end()); 813221345Sdim MI->second.erase(std::unique(MI->second.begin(), MI->second.end()), 814221345Sdim MI->second.end()); 815221345Sdim 816221345Sdim // Check each in order it was seen. It would be nice to have a good 817221345Sdim // relative ordering between them, but we're not going for optimality 818221345Sdim // here. 819221345Sdim for (unsigned i = 0, e = MI->second.size(); i != e; ++i) { 820221345Sdim OS << " if ("; 821221345Sdim MI->second[i].emitImmediatePredicate(OS, ImmediatePredicates); 822221345Sdim OS << ")\n if (unsigned Reg = FastEmit_"; 823221345Sdim MI->second[i].PrintManglingSuffix(OS, ImmediatePredicates); 824221345Sdim OS << "(VT, RetVT, Opcode"; 825221345Sdim if (!MI->second[i].empty()) 826221345Sdim OS << ", "; 827221345Sdim MI->second[i].PrintArguments(OS); 828221345Sdim OS << "))\n return Reg;\n\n"; 829221345Sdim } 830221345Sdim 831221345Sdim // Done with this, remove it. 832221345Sdim SignaturesWithConstantForms.erase(MI); 833221345Sdim } 834221345Sdim 835193323Sed OS << " switch (Opcode) {\n"; 836193323Sed for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end(); 837193323Sed I != E; ++I) { 838193323Sed const std::string &Opcode = I->first; 839193323Sed 840193323Sed OS << " case " << Opcode << ": return FastEmit_" 841193323Sed << getLegalCName(Opcode) << "_"; 842221345Sdim Operands.PrintManglingSuffix(OS, ImmediatePredicates); 843193323Sed OS << "(VT, RetVT"; 844193323Sed if (!Operands.empty()) 845193323Sed OS << ", "; 846193323Sed Operands.PrintArguments(OS); 847193323Sed OS << ");\n"; 848193323Sed } 849193323Sed OS << " default: return 0;\n"; 850193323Sed OS << " }\n"; 851193323Sed OS << "}\n"; 852193323Sed OS << "\n"; 853193323Sed } 854221345Sdim 855221345Sdim // TODO: SignaturesWithConstantForms should be empty here. 856193323Sed} 857193323Sed 858239462Sdimnamespace llvm { 859239462Sdim 860239462Sdimvoid EmitFastISel(RecordKeeper &RK, raw_ostream &OS) { 861239462Sdim CodeGenDAGPatterns CGP(RK); 862193323Sed const CodeGenTarget &Target = CGP.getTargetInfo(); 863239462Sdim emitSourceFileHeader("\"Fast\" Instruction Selector for the " + 864239462Sdim Target.getName() + " target", OS); 865193323Sed 866193323Sed // Determine the target's namespace name. 867193323Sed std::string InstNS = Target.getInstNamespace() + "::"; 868193323Sed assert(InstNS.size() > 2 && "Can't determine target-specific namespace!"); 869193323Sed 870193323Sed FastISelMap F(InstNS); 871221345Sdim F.collectPatterns(CGP); 872221345Sdim F.printImmediatePredicates(OS); 873221345Sdim F.printFunctionDefinitions(OS); 874193323Sed} 875193323Sed 876239462Sdim} // End llvm namespace 877