LegalizeVectorOps.cpp revision 198090
1//===-- LegalizeVectorOps.cpp - Implement SelectionDAG::LegalizeVectors ---===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::LegalizeVectors method. 11// 12// The vector legalizer looks for vector operations which might need to be 13// scalarized and legalizes them. This is a separate step from Legalize because 14// scalarizing can introduce illegal types. For example, suppose we have an 15// ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition 16// on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the 17// operation, which introduces nodes with the illegal type i64 which must be 18// expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC; 19// the operation must be unrolled, which introduces nodes with the illegal 20// type i8 which must be promoted. 21// 22// This does not legalize vector manipulations like ISD::BUILD_VECTOR, 23// or operations that happen to take a vector which are custom-lowered; 24// the legalization for such operations never produces nodes 25// with illegal types, so it's okay to put off legalizing them until 26// SelectionDAG::Legalize runs. 27// 28//===----------------------------------------------------------------------===// 29 30#include "llvm/CodeGen/SelectionDAG.h" 31#include "llvm/Target/TargetLowering.h" 32using namespace llvm; 33 34namespace { 35class VectorLegalizer { 36 SelectionDAG& DAG; 37 TargetLowering& TLI; 38 bool Changed; // Keep track of whether anything changed 39 40 /// LegalizedNodes - For nodes that are of legal width, and that have more 41 /// than one use, this map indicates what regularized operand to use. This 42 /// allows us to avoid legalizing the same thing more than once. 43 DenseMap<SDValue, SDValue> LegalizedNodes; 44 45 // Adds a node to the translation cache 46 void AddLegalizedOperand(SDValue From, SDValue To) { 47 LegalizedNodes.insert(std::make_pair(From, To)); 48 // If someone requests legalization of the new node, return itself. 49 if (From != To) 50 LegalizedNodes.insert(std::make_pair(To, To)); 51 } 52 53 // Legalizes the given node 54 SDValue LegalizeOp(SDValue Op); 55 // Assuming the node is legal, "legalize" the results 56 SDValue TranslateLegalizeResults(SDValue Op, SDValue Result); 57 // Implements unrolling a generic vector operation, i.e. turning it into 58 // scalar operations. 59 SDValue UnrollVectorOp(SDValue Op); 60 // Implements unrolling a VSETCC. 61 SDValue UnrollVSETCC(SDValue Op); 62 // Implements expansion for FNEG; falls back to UnrollVectorOp if FSUB 63 // isn't legal. 64 SDValue ExpandFNEG(SDValue Op); 65 // Implements vector promotion; this is essentially just bitcasting the 66 // operands to a different type and bitcasting the result back to the 67 // original type. 68 SDValue PromoteVectorOp(SDValue Op); 69 70 public: 71 bool Run(); 72 VectorLegalizer(SelectionDAG& dag) : 73 DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {} 74}; 75 76bool VectorLegalizer::Run() { 77 // The legalize process is inherently a bottom-up recursive process (users 78 // legalize their uses before themselves). Given infinite stack space, we 79 // could just start legalizing on the root and traverse the whole graph. In 80 // practice however, this causes us to run out of stack space on large basic 81 // blocks. To avoid this problem, compute an ordering of the nodes where each 82 // node is only legalized after all of its operands are legalized. 83 DAG.AssignTopologicalOrder(); 84 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 85 E = prior(DAG.allnodes_end()); I != next(E); ++I) 86 LegalizeOp(SDValue(I, 0)); 87 88 // Finally, it's possible the root changed. Get the new root. 89 SDValue OldRoot = DAG.getRoot(); 90 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 91 DAG.setRoot(LegalizedNodes[OldRoot]); 92 93 LegalizedNodes.clear(); 94 95 // Remove dead nodes now. 96 DAG.RemoveDeadNodes(); 97 98 return Changed; 99} 100 101SDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDValue Result) { 102 // Generic legalization: just pass the operand through. 103 for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i) 104 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 105 return Result.getValue(Op.getResNo()); 106} 107 108SDValue VectorLegalizer::LegalizeOp(SDValue Op) { 109 // Note that LegalizeOp may be reentered even from single-use nodes, which 110 // means that we always must cache transformed nodes. 111 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 112 if (I != LegalizedNodes.end()) return I->second; 113 114 SDNode* Node = Op.getNode(); 115 116 // Legalize the operands 117 SmallVector<SDValue, 8> Ops; 118 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 119 Ops.push_back(LegalizeOp(Node->getOperand(i))); 120 121 SDValue Result = 122 DAG.UpdateNodeOperands(Op.getValue(0), Ops.data(), Ops.size()); 123 124 bool HasVectorValue = false; 125 for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end(); 126 J != E; 127 ++J) 128 HasVectorValue |= J->isVector(); 129 if (!HasVectorValue) 130 return TranslateLegalizeResults(Op, Result); 131 132 EVT QueryType; 133 switch (Op.getOpcode()) { 134 default: 135 return TranslateLegalizeResults(Op, Result); 136 case ISD::ADD: 137 case ISD::SUB: 138 case ISD::MUL: 139 case ISD::SDIV: 140 case ISD::UDIV: 141 case ISD::SREM: 142 case ISD::UREM: 143 case ISD::FADD: 144 case ISD::FSUB: 145 case ISD::FMUL: 146 case ISD::FDIV: 147 case ISD::FREM: 148 case ISD::AND: 149 case ISD::OR: 150 case ISD::XOR: 151 case ISD::SHL: 152 case ISD::SRA: 153 case ISD::SRL: 154 case ISD::ROTL: 155 case ISD::ROTR: 156 case ISD::CTTZ: 157 case ISD::CTLZ: 158 case ISD::CTPOP: 159 case ISD::SELECT: 160 case ISD::SELECT_CC: 161 case ISD::VSETCC: 162 case ISD::ZERO_EXTEND: 163 case ISD::ANY_EXTEND: 164 case ISD::TRUNCATE: 165 case ISD::SIGN_EXTEND: 166 case ISD::FP_TO_SINT: 167 case ISD::FP_TO_UINT: 168 case ISD::FNEG: 169 case ISD::FABS: 170 case ISD::FSQRT: 171 case ISD::FSIN: 172 case ISD::FCOS: 173 case ISD::FPOWI: 174 case ISD::FPOW: 175 case ISD::FLOG: 176 case ISD::FLOG2: 177 case ISD::FLOG10: 178 case ISD::FEXP: 179 case ISD::FEXP2: 180 case ISD::FCEIL: 181 case ISD::FTRUNC: 182 case ISD::FRINT: 183 case ISD::FNEARBYINT: 184 case ISD::FFLOOR: 185 QueryType = Node->getValueType(0); 186 break; 187 case ISD::SINT_TO_FP: 188 case ISD::UINT_TO_FP: 189 QueryType = Node->getOperand(0).getValueType(); 190 break; 191 } 192 193 switch (TLI.getOperationAction(Node->getOpcode(), QueryType)) { 194 case TargetLowering::Promote: 195 // "Promote" the operation by bitcasting 196 Result = PromoteVectorOp(Op); 197 Changed = true; 198 break; 199 case TargetLowering::Legal: break; 200 case TargetLowering::Custom: { 201 SDValue Tmp1 = TLI.LowerOperation(Op, DAG); 202 if (Tmp1.getNode()) { 203 Result = Tmp1; 204 break; 205 } 206 // FALL THROUGH 207 } 208 case TargetLowering::Expand: 209 if (Node->getOpcode() == ISD::FNEG) 210 Result = ExpandFNEG(Op); 211 else if (Node->getOpcode() == ISD::VSETCC) 212 Result = UnrollVSETCC(Op); 213 else 214 Result = UnrollVectorOp(Op); 215 break; 216 } 217 218 // Make sure that the generated code is itself legal. 219 if (Result != Op) { 220 Result = LegalizeOp(Result); 221 Changed = true; 222 } 223 224 // Note that LegalizeOp may be reentered even from single-use nodes, which 225 // means that we always must cache transformed nodes. 226 AddLegalizedOperand(Op, Result); 227 return Result; 228} 229 230SDValue VectorLegalizer::PromoteVectorOp(SDValue Op) { 231 // Vector "promotion" is basically just bitcasting and doing the operation 232 // in a different type. For example, x86 promotes ISD::AND on v2i32 to 233 // v1i64. 234 EVT VT = Op.getValueType(); 235 assert(Op.getNode()->getNumValues() == 1 && 236 "Can't promote a vector with multiple results!"); 237 EVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT); 238 DebugLoc dl = Op.getDebugLoc(); 239 SmallVector<SDValue, 4> Operands(Op.getNumOperands()); 240 241 for (unsigned j = 0; j != Op.getNumOperands(); ++j) { 242 if (Op.getOperand(j).getValueType().isVector()) 243 Operands[j] = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Op.getOperand(j)); 244 else 245 Operands[j] = Op.getOperand(j); 246 } 247 248 Op = DAG.getNode(Op.getOpcode(), dl, NVT, &Operands[0], Operands.size()); 249 250 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Op); 251} 252 253SDValue VectorLegalizer::ExpandFNEG(SDValue Op) { 254 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) { 255 SDValue Zero = DAG.getConstantFP(-0.0, Op.getValueType()); 256 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 257 Zero, Op.getOperand(0)); 258 } 259 return UnrollVectorOp(Op); 260} 261 262SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) { 263 EVT VT = Op.getValueType(); 264 unsigned NumElems = VT.getVectorNumElements(); 265 EVT EltVT = VT.getVectorElementType(); 266 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1), CC = Op.getOperand(2); 267 EVT TmpEltVT = LHS.getValueType().getVectorElementType(); 268 DebugLoc dl = Op.getDebugLoc(); 269 SmallVector<SDValue, 8> Ops(NumElems); 270 for (unsigned i = 0; i < NumElems; ++i) { 271 SDValue LHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS, 272 DAG.getIntPtrConstant(i)); 273 SDValue RHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS, 274 DAG.getIntPtrConstant(i)); 275 Ops[i] = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(TmpEltVT), 276 LHSElem, RHSElem, CC); 277 Ops[i] = DAG.getNode(ISD::SELECT, dl, EltVT, Ops[i], 278 DAG.getConstant(APInt::getAllOnesValue 279 (EltVT.getSizeInBits()), EltVT), 280 DAG.getConstant(0, EltVT)); 281 } 282 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElems); 283} 284 285/// UnrollVectorOp - We know that the given vector has a legal type, however 286/// the operation it performs is not legal, and the target has requested that 287/// the operation be expanded. "Unroll" the vector, splitting out the scalars 288/// and operating on each element individually. 289SDValue VectorLegalizer::UnrollVectorOp(SDValue Op) { 290 EVT VT = Op.getValueType(); 291 assert(Op.getNode()->getNumValues() == 1 && 292 "Can't unroll a vector with multiple results!"); 293 unsigned NE = VT.getVectorNumElements(); 294 EVT EltVT = VT.getVectorElementType(); 295 DebugLoc dl = Op.getDebugLoc(); 296 297 SmallVector<SDValue, 8> Scalars; 298 SmallVector<SDValue, 4> Operands(Op.getNumOperands()); 299 for (unsigned i = 0; i != NE; ++i) { 300 for (unsigned j = 0; j != Op.getNumOperands(); ++j) { 301 SDValue Operand = Op.getOperand(j); 302 EVT OperandVT = Operand.getValueType(); 303 if (OperandVT.isVector()) { 304 // A vector operand; extract a single element. 305 EVT OperandEltVT = OperandVT.getVectorElementType(); 306 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 307 OperandEltVT, 308 Operand, 309 DAG.getConstant(i, MVT::i32)); 310 } else { 311 // A scalar operand; just use it as is. 312 Operands[j] = Operand; 313 } 314 } 315 316 switch (Op.getOpcode()) { 317 default: 318 Scalars.push_back(DAG.getNode(Op.getOpcode(), dl, EltVT, 319 &Operands[0], Operands.size())); 320 break; 321 case ISD::SHL: 322 case ISD::SRA: 323 case ISD::SRL: 324 case ISD::ROTL: 325 case ISD::ROTR: 326 Scalars.push_back(DAG.getNode(Op.getOpcode(), dl, EltVT, Operands[0], 327 DAG.getShiftAmountOperand(Operands[1]))); 328 break; 329 } 330 } 331 332 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Scalars[0], Scalars.size()); 333} 334 335} 336 337bool SelectionDAG::LegalizeVectors() { 338 return VectorLegalizer(*this).Run(); 339} 340