LegalizeDAG.cpp revision 199481
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/CodeGen/MachineModuleInfo.h" 19#include "llvm/CodeGen/DwarfWriter.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/CodeGen/PseudoSourceValue.h" 22#include "llvm/Target/TargetFrameInfo.h" 23#include "llvm/Target/TargetLowering.h" 24#include "llvm/Target/TargetData.h" 25#include "llvm/Target/TargetMachine.h" 26#include "llvm/Target/TargetOptions.h" 27#include "llvm/Target/TargetSubtarget.h" 28#include "llvm/CallingConv.h" 29#include "llvm/Constants.h" 30#include "llvm/DerivedTypes.h" 31#include "llvm/Function.h" 32#include "llvm/GlobalVariable.h" 33#include "llvm/LLVMContext.h" 34#include "llvm/Support/CommandLine.h" 35#include "llvm/Support/ErrorHandling.h" 36#include "llvm/Support/MathExtras.h" 37#include "llvm/Support/raw_ostream.h" 38#include "llvm/ADT/DenseMap.h" 39#include "llvm/ADT/SmallVector.h" 40#include "llvm/ADT/SmallPtrSet.h" 41#include <map> 42using namespace llvm; 43 44//===----------------------------------------------------------------------===// 45/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 46/// hacks on it until the target machine can handle it. This involves 47/// eliminating value sizes the machine cannot handle (promoting small sizes to 48/// large sizes or splitting up large values into small values) as well as 49/// eliminating operations the machine cannot handle. 50/// 51/// This code also does a small amount of optimization and recognition of idioms 52/// as part of its processing. For example, if a target does not support a 53/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 54/// will attempt merge setcc and brc instructions into brcc's. 55/// 56namespace { 57class SelectionDAGLegalize { 58 TargetLowering &TLI; 59 SelectionDAG &DAG; 60 CodeGenOpt::Level OptLevel; 61 62 // Libcall insertion helpers. 63 64 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 65 /// legalized. We use this to ensure that calls are properly serialized 66 /// against each other, including inserted libcalls. 67 SDValue LastCALLSEQ_END; 68 69 /// IsLegalizingCall - This member is used *only* for purposes of providing 70 /// helpful assertions that a libcall isn't created while another call is 71 /// being legalized (which could lead to non-serialized call sequences). 72 bool IsLegalizingCall; 73 74 enum LegalizeAction { 75 Legal, // The target natively supports this operation. 76 Promote, // This operation should be executed in a larger type. 77 Expand // Try to expand this to other ops, otherwise use a libcall. 78 }; 79 80 /// ValueTypeActions - This is a bitvector that contains two bits for each 81 /// value type, where the two bits correspond to the LegalizeAction enum. 82 /// This can be queried with "getTypeAction(VT)". 83 TargetLowering::ValueTypeActionImpl ValueTypeActions; 84 85 /// LegalizedNodes - For nodes that are of legal width, and that have more 86 /// than one use, this map indicates what regularized operand to use. This 87 /// allows us to avoid legalizing the same thing more than once. 88 DenseMap<SDValue, SDValue> LegalizedNodes; 89 90 void AddLegalizedOperand(SDValue From, SDValue To) { 91 LegalizedNodes.insert(std::make_pair(From, To)); 92 // If someone requests legalization of the new node, return itself. 93 if (From != To) 94 LegalizedNodes.insert(std::make_pair(To, To)); 95 } 96 97public: 98 SelectionDAGLegalize(SelectionDAG &DAG, CodeGenOpt::Level ol); 99 100 /// getTypeAction - Return how we should legalize values of this type, either 101 /// it is already legal or we need to expand it into multiple registers of 102 /// smaller integer type, or we need to promote it to a larger type. 103 LegalizeAction getTypeAction(EVT VT) const { 104 return 105 (LegalizeAction)ValueTypeActions.getTypeAction(*DAG.getContext(), VT); 106 } 107 108 /// isTypeLegal - Return true if this type is legal on this target. 109 /// 110 bool isTypeLegal(EVT VT) const { 111 return getTypeAction(VT) == Legal; 112 } 113 114 void LegalizeDAG(); 115 116private: 117 /// LegalizeOp - We know that the specified value has a legal type. 118 /// Recursively ensure that the operands have legal types, then return the 119 /// result. 120 SDValue LegalizeOp(SDValue O); 121 122 SDValue OptimizeFloatStore(StoreSDNode *ST); 123 124 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 125 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 126 /// is necessary to spill the vector being inserted into to memory, perform 127 /// the insert there, and then read the result back. 128 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, 129 SDValue Idx, DebugLoc dl); 130 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, 131 SDValue Idx, DebugLoc dl); 132 133 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 134 /// performs the same shuffe in terms of order or result bytes, but on a type 135 /// whose vector element type is narrower than the original shuffle type. 136 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 137 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl, 138 SDValue N1, SDValue N2, 139 SmallVectorImpl<int> &Mask) const; 140 141 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 142 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 143 144 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, 145 DebugLoc dl); 146 147 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned); 148 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32, 149 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80, 150 RTLIB::Libcall Call_PPCF128); 151 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned, 152 RTLIB::Libcall Call_I8, 153 RTLIB::Libcall Call_I16, 154 RTLIB::Libcall Call_I32, 155 RTLIB::Libcall Call_I64, 156 RTLIB::Libcall Call_I128); 157 158 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl); 159 SDValue ExpandBUILD_VECTOR(SDNode *Node); 160 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node); 161 SDValue ExpandDBG_STOPPOINT(SDNode *Node); 162 void ExpandDYNAMIC_STACKALLOC(SDNode *Node, 163 SmallVectorImpl<SDValue> &Results); 164 SDValue ExpandFCOPYSIGN(SDNode *Node); 165 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT, 166 DebugLoc dl); 167 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned, 168 DebugLoc dl); 169 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned, 170 DebugLoc dl); 171 172 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl); 173 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl); 174 175 SDValue ExpandExtractFromVectorThroughStack(SDValue Op); 176 SDValue ExpandVectorBuildThroughStack(SDNode* Node); 177 178 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results); 179 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results); 180}; 181} 182 183/// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 184/// performs the same shuffe in terms of order or result bytes, but on a type 185/// whose vector element type is narrower than the original shuffle type. 186/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 187SDValue 188SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl, 189 SDValue N1, SDValue N2, 190 SmallVectorImpl<int> &Mask) const { 191 EVT EltVT = NVT.getVectorElementType(); 192 unsigned NumMaskElts = VT.getVectorNumElements(); 193 unsigned NumDestElts = NVT.getVectorNumElements(); 194 unsigned NumEltsGrowth = NumDestElts / NumMaskElts; 195 196 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 197 198 if (NumEltsGrowth == 1) 199 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]); 200 201 SmallVector<int, 8> NewMask; 202 for (unsigned i = 0; i != NumMaskElts; ++i) { 203 int Idx = Mask[i]; 204 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 205 if (Idx < 0) 206 NewMask.push_back(-1); 207 else 208 NewMask.push_back(Idx * NumEltsGrowth + j); 209 } 210 } 211 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?"); 212 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?"); 213 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]); 214} 215 216SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag, 217 CodeGenOpt::Level ol) 218 : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol), 219 ValueTypeActions(TLI.getValueTypeActions()) { 220 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 221 "Too many value types for ValueTypeActions to hold!"); 222} 223 224void SelectionDAGLegalize::LegalizeDAG() { 225 LastCALLSEQ_END = DAG.getEntryNode(); 226 IsLegalizingCall = false; 227 228 // The legalize process is inherently a bottom-up recursive process (users 229 // legalize their uses before themselves). Given infinite stack space, we 230 // could just start legalizing on the root and traverse the whole graph. In 231 // practice however, this causes us to run out of stack space on large basic 232 // blocks. To avoid this problem, compute an ordering of the nodes where each 233 // node is only legalized after all of its operands are legalized. 234 DAG.AssignTopologicalOrder(); 235 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 236 E = prior(DAG.allnodes_end()); I != next(E); ++I) 237 LegalizeOp(SDValue(I, 0)); 238 239 // Finally, it's possible the root changed. Get the new root. 240 SDValue OldRoot = DAG.getRoot(); 241 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 242 DAG.setRoot(LegalizedNodes[OldRoot]); 243 244 LegalizedNodes.clear(); 245 246 // Remove dead nodes now. 247 DAG.RemoveDeadNodes(); 248} 249 250 251/// FindCallEndFromCallStart - Given a chained node that is part of a call 252/// sequence, find the CALLSEQ_END node that terminates the call sequence. 253static SDNode *FindCallEndFromCallStart(SDNode *Node) { 254 if (Node->getOpcode() == ISD::CALLSEQ_END) 255 return Node; 256 if (Node->use_empty()) 257 return 0; // No CallSeqEnd 258 259 // The chain is usually at the end. 260 SDValue TheChain(Node, Node->getNumValues()-1); 261 if (TheChain.getValueType() != MVT::Other) { 262 // Sometimes it's at the beginning. 263 TheChain = SDValue(Node, 0); 264 if (TheChain.getValueType() != MVT::Other) { 265 // Otherwise, hunt for it. 266 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 267 if (Node->getValueType(i) == MVT::Other) { 268 TheChain = SDValue(Node, i); 269 break; 270 } 271 272 // Otherwise, we walked into a node without a chain. 273 if (TheChain.getValueType() != MVT::Other) 274 return 0; 275 } 276 } 277 278 for (SDNode::use_iterator UI = Node->use_begin(), 279 E = Node->use_end(); UI != E; ++UI) { 280 281 // Make sure to only follow users of our token chain. 282 SDNode *User = *UI; 283 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 284 if (User->getOperand(i) == TheChain) 285 if (SDNode *Result = FindCallEndFromCallStart(User)) 286 return Result; 287 } 288 return 0; 289} 290 291/// FindCallStartFromCallEnd - Given a chained node that is part of a call 292/// sequence, find the CALLSEQ_START node that initiates the call sequence. 293static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 294 assert(Node && "Didn't find callseq_start for a call??"); 295 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 296 297 assert(Node->getOperand(0).getValueType() == MVT::Other && 298 "Node doesn't have a token chain argument!"); 299 return FindCallStartFromCallEnd(Node->getOperand(0).getNode()); 300} 301 302/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 303/// see if any uses can reach Dest. If no dest operands can get to dest, 304/// legalize them, legalize ourself, and return false, otherwise, return true. 305/// 306/// Keep track of the nodes we fine that actually do lead to Dest in 307/// NodesLeadingTo. This avoids retraversing them exponential number of times. 308/// 309bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 310 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 311 if (N == Dest) return true; // N certainly leads to Dest :) 312 313 // If we've already processed this node and it does lead to Dest, there is no 314 // need to reprocess it. 315 if (NodesLeadingTo.count(N)) return true; 316 317 // If the first result of this node has been already legalized, then it cannot 318 // reach N. 319 if (LegalizedNodes.count(SDValue(N, 0))) return false; 320 321 // Okay, this node has not already been legalized. Check and legalize all 322 // operands. If none lead to Dest, then we can legalize this node. 323 bool OperandsLeadToDest = false; 324 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 325 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 326 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo); 327 328 if (OperandsLeadToDest) { 329 NodesLeadingTo.insert(N); 330 return true; 331 } 332 333 // Okay, this node looks safe, legalize it and return false. 334 LegalizeOp(SDValue(N, 0)); 335 return false; 336} 337 338/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 339/// a load from the constant pool. 340static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 341 SelectionDAG &DAG, const TargetLowering &TLI) { 342 bool Extend = false; 343 DebugLoc dl = CFP->getDebugLoc(); 344 345 // If a FP immediate is precise when represented as a float and if the 346 // target can do an extending load from float to double, we put it into 347 // the constant pool as a float, even if it's is statically typed as a 348 // double. This shrinks FP constants and canonicalizes them for targets where 349 // an FP extending load is the same cost as a normal load (such as on the x87 350 // fp stack or PPC FP unit). 351 EVT VT = CFP->getValueType(0); 352 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue()); 353 if (!UseCP) { 354 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion"); 355 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), 356 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 357 } 358 359 EVT OrigVT = VT; 360 EVT SVT = VT; 361 while (SVT != MVT::f32) { 362 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1); 363 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) && 364 // Only do this if the target has a native EXTLOAD instruction from 365 // smaller type. 366 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) && 367 TLI.ShouldShrinkFPConstant(OrigVT)) { 368 const Type *SType = SVT.getTypeForEVT(*DAG.getContext()); 369 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); 370 VT = SVT; 371 Extend = true; 372 } 373 } 374 375 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 376 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 377 if (Extend) 378 return DAG.getExtLoad(ISD::EXTLOAD, dl, 379 OrigVT, DAG.getEntryNode(), 380 CPIdx, PseudoSourceValue::getConstantPool(), 381 0, VT, false, Alignment); 382 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx, 383 PseudoSourceValue::getConstantPool(), 0, false, Alignment); 384} 385 386/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 387static 388SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 389 const TargetLowering &TLI) { 390 SDValue Chain = ST->getChain(); 391 SDValue Ptr = ST->getBasePtr(); 392 SDValue Val = ST->getValue(); 393 EVT VT = Val.getValueType(); 394 int Alignment = ST->getAlignment(); 395 int SVOffset = ST->getSrcValueOffset(); 396 DebugLoc dl = ST->getDebugLoc(); 397 if (ST->getMemoryVT().isFloatingPoint() || 398 ST->getMemoryVT().isVector()) { 399 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 400 if (TLI.isTypeLegal(intVT)) { 401 // Expand to a bitconvert of the value to the integer type of the 402 // same size, then a (misaligned) int store. 403 // FIXME: Does not handle truncating floating point stores! 404 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val); 405 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(), 406 SVOffset, ST->isVolatile(), Alignment); 407 } else { 408 // Do a (aligned) store to a stack slot, then copy from the stack slot 409 // to the final destination using (unaligned) integer loads and stores. 410 EVT StoredVT = ST->getMemoryVT(); 411 EVT RegVT = 412 TLI.getRegisterType(*DAG.getContext(), EVT::getIntegerVT(*DAG.getContext(), StoredVT.getSizeInBits())); 413 unsigned StoredBytes = StoredVT.getSizeInBits() / 8; 414 unsigned RegBytes = RegVT.getSizeInBits() / 8; 415 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; 416 417 // Make sure the stack slot is also aligned for the register type. 418 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); 419 420 // Perform the original store, only redirected to the stack slot. 421 SDValue Store = DAG.getTruncStore(Chain, dl, 422 Val, StackPtr, NULL, 0, StoredVT); 423 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 424 SmallVector<SDValue, 8> Stores; 425 unsigned Offset = 0; 426 427 // Do all but one copies using the full register width. 428 for (unsigned i = 1; i < NumRegs; i++) { 429 // Load one integer register's worth from the stack slot. 430 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0); 431 // Store it to the final location. Remember the store. 432 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr, 433 ST->getSrcValue(), SVOffset + Offset, 434 ST->isVolatile(), 435 MinAlign(ST->getAlignment(), Offset))); 436 // Increment the pointers. 437 Offset += RegBytes; 438 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 439 Increment); 440 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 441 } 442 443 // The last store may be partial. Do a truncating store. On big-endian 444 // machines this requires an extending load from the stack slot to ensure 445 // that the bits are in the right place. 446 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 8 * (StoredBytes - Offset)); 447 448 // Load from the stack slot. 449 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, 450 NULL, 0, MemVT); 451 452 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr, 453 ST->getSrcValue(), SVOffset + Offset, 454 MemVT, ST->isVolatile(), 455 MinAlign(ST->getAlignment(), Offset))); 456 // The order of the stores doesn't matter - say it with a TokenFactor. 457 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 458 Stores.size()); 459 } 460 } 461 assert(ST->getMemoryVT().isInteger() && 462 !ST->getMemoryVT().isVector() && 463 "Unaligned store of unknown type."); 464 // Get the half-size VT 465 EVT NewStoredVT = 466 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT().SimpleTy - 1); 467 int NumBits = NewStoredVT.getSizeInBits(); 468 int IncrementSize = NumBits / 8; 469 470 // Divide the stored value in two parts. 471 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 472 SDValue Lo = Val; 473 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); 474 475 // Store the two parts 476 SDValue Store1, Store2; 477 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr, 478 ST->getSrcValue(), SVOffset, NewStoredVT, 479 ST->isVolatile(), Alignment); 480 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 481 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 482 Alignment = MinAlign(Alignment, IncrementSize); 483 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr, 484 ST->getSrcValue(), SVOffset + IncrementSize, 485 NewStoredVT, ST->isVolatile(), Alignment); 486 487 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); 488} 489 490/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 491static 492SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 493 const TargetLowering &TLI) { 494 int SVOffset = LD->getSrcValueOffset(); 495 SDValue Chain = LD->getChain(); 496 SDValue Ptr = LD->getBasePtr(); 497 EVT VT = LD->getValueType(0); 498 EVT LoadedVT = LD->getMemoryVT(); 499 DebugLoc dl = LD->getDebugLoc(); 500 if (VT.isFloatingPoint() || VT.isVector()) { 501 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits()); 502 if (TLI.isTypeLegal(intVT)) { 503 // Expand to a (misaligned) integer load of the same size, 504 // then bitconvert to floating point or vector. 505 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(), 506 SVOffset, LD->isVolatile(), 507 LD->getAlignment()); 508 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad); 509 if (VT.isFloatingPoint() && LoadedVT != VT) 510 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result); 511 512 SDValue Ops[] = { Result, Chain }; 513 return DAG.getMergeValues(Ops, 2, dl); 514 } else { 515 // Copy the value to a (aligned) stack slot using (unaligned) integer 516 // loads and stores, then do a (aligned) load from the stack slot. 517 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT); 518 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8; 519 unsigned RegBytes = RegVT.getSizeInBits() / 8; 520 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; 521 522 // Make sure the stack slot is also aligned for the register type. 523 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); 524 525 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 526 SmallVector<SDValue, 8> Stores; 527 SDValue StackPtr = StackBase; 528 unsigned Offset = 0; 529 530 // Do all but one copies using the full register width. 531 for (unsigned i = 1; i < NumRegs; i++) { 532 // Load one integer register's worth from the original location. 533 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(), 534 SVOffset + Offset, LD->isVolatile(), 535 MinAlign(LD->getAlignment(), Offset)); 536 // Follow the load with a store to the stack slot. Remember the store. 537 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr, 538 NULL, 0)); 539 // Increment the pointers. 540 Offset += RegBytes; 541 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 542 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 543 Increment); 544 } 545 546 // The last copy may be partial. Do an extending load. 547 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 8 * (LoadedBytes - Offset)); 548 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, 549 LD->getSrcValue(), SVOffset + Offset, 550 MemVT, LD->isVolatile(), 551 MinAlign(LD->getAlignment(), Offset)); 552 // Follow the load with a store to the stack slot. Remember the store. 553 // On big-endian machines this requires a truncating store to ensure 554 // that the bits end up in the right place. 555 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr, 556 NULL, 0, MemVT)); 557 558 // The order of the stores doesn't matter - say it with a TokenFactor. 559 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 560 Stores.size()); 561 562 // Finally, perform the original load only redirected to the stack slot. 563 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase, 564 NULL, 0, LoadedVT); 565 566 // Callers expect a MERGE_VALUES node. 567 SDValue Ops[] = { Load, TF }; 568 return DAG.getMergeValues(Ops, 2, dl); 569 } 570 } 571 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && 572 "Unaligned load of unsupported type."); 573 574 // Compute the new VT that is half the size of the old one. This is an 575 // integer MVT. 576 unsigned NumBits = LoadedVT.getSizeInBits(); 577 EVT NewLoadedVT; 578 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2); 579 NumBits >>= 1; 580 581 unsigned Alignment = LD->getAlignment(); 582 unsigned IncrementSize = NumBits / 8; 583 ISD::LoadExtType HiExtType = LD->getExtensionType(); 584 585 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 586 if (HiExtType == ISD::NON_EXTLOAD) 587 HiExtType = ISD::ZEXTLOAD; 588 589 // Load the value in two parts 590 SDValue Lo, Hi; 591 if (TLI.isLittleEndian()) { 592 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(), 593 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 594 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 595 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 596 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(), 597 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 598 MinAlign(Alignment, IncrementSize)); 599 } else { 600 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(), 601 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 602 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 603 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 604 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(), 605 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 606 MinAlign(Alignment, IncrementSize)); 607 } 608 609 // aggregate the two parts 610 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 611 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); 612 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo); 613 614 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 615 Hi.getValue(1)); 616 617 SDValue Ops[] = { Result, TF }; 618 return DAG.getMergeValues(Ops, 2, dl); 619} 620 621/// PerformInsertVectorEltInMemory - Some target cannot handle a variable 622/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 623/// is necessary to spill the vector being inserted into to memory, perform 624/// the insert there, and then read the result back. 625SDValue SelectionDAGLegalize:: 626PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx, 627 DebugLoc dl) { 628 SDValue Tmp1 = Vec; 629 SDValue Tmp2 = Val; 630 SDValue Tmp3 = Idx; 631 632 // If the target doesn't support this, we have to spill the input vector 633 // to a temporary stack slot, update the element, then reload it. This is 634 // badness. We could also load the value into a vector register (either 635 // with a "move to register" or "extload into register" instruction, then 636 // permute it into place, if the idx is a constant and if the idx is 637 // supported by the target. 638 EVT VT = Tmp1.getValueType(); 639 EVT EltVT = VT.getVectorElementType(); 640 EVT IdxVT = Tmp3.getValueType(); 641 EVT PtrVT = TLI.getPointerTy(); 642 SDValue StackPtr = DAG.CreateStackTemporary(VT); 643 644 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); 645 646 // Store the vector. 647 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr, 648 PseudoSourceValue::getFixedStack(SPFI), 0); 649 650 // Truncate or zero extend offset to target pointer type. 651 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 652 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3); 653 // Add the offset to the index. 654 unsigned EltSize = EltVT.getSizeInBits()/8; 655 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 656 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr); 657 // Store the scalar value. 658 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, 659 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT); 660 // Load the updated vector. 661 return DAG.getLoad(VT, dl, Ch, StackPtr, 662 PseudoSourceValue::getFixedStack(SPFI), 0); 663} 664 665 666SDValue SelectionDAGLegalize:: 667ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) { 668 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) { 669 // SCALAR_TO_VECTOR requires that the type of the value being inserted 670 // match the element type of the vector being created, except for 671 // integers in which case the inserted value can be over width. 672 EVT EltVT = Vec.getValueType().getVectorElementType(); 673 if (Val.getValueType() == EltVT || 674 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) { 675 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 676 Vec.getValueType(), Val); 677 678 unsigned NumElts = Vec.getValueType().getVectorNumElements(); 679 // We generate a shuffle of InVec and ScVec, so the shuffle mask 680 // should be 0,1,2,3,4,5... with the appropriate element replaced with 681 // elt 0 of the RHS. 682 SmallVector<int, 8> ShufOps; 683 for (unsigned i = 0; i != NumElts; ++i) 684 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts); 685 686 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec, 687 &ShufOps[0]); 688 } 689 } 690 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl); 691} 692 693SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) { 694 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 695 // FIXME: We shouldn't do this for TargetConstantFP's. 696 // FIXME: move this to the DAG Combiner! Note that we can't regress due 697 // to phase ordering between legalized code and the dag combiner. This 698 // probably means that we need to integrate dag combiner and legalizer 699 // together. 700 // We generally can't do this one for long doubles. 701 SDValue Tmp1 = ST->getChain(); 702 SDValue Tmp2 = ST->getBasePtr(); 703 SDValue Tmp3; 704 int SVOffset = ST->getSrcValueOffset(); 705 unsigned Alignment = ST->getAlignment(); 706 bool isVolatile = ST->isVolatile(); 707 DebugLoc dl = ST->getDebugLoc(); 708 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 709 if (CFP->getValueType(0) == MVT::f32 && 710 getTypeAction(MVT::i32) == Legal) { 711 Tmp3 = DAG.getConstant(CFP->getValueAPF(). 712 bitcastToAPInt().zextOrTrunc(32), 713 MVT::i32); 714 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 715 SVOffset, isVolatile, Alignment); 716 } else if (CFP->getValueType(0) == MVT::f64) { 717 // If this target supports 64-bit registers, do a single 64-bit store. 718 if (getTypeAction(MVT::i64) == Legal) { 719 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 720 zextOrTrunc(64), MVT::i64); 721 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 722 SVOffset, isVolatile, Alignment); 723 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) { 724 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 725 // stores. If the target supports neither 32- nor 64-bits, this 726 // xform is certainly not worth it. 727 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt(); 728 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32); 729 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); 730 if (TLI.isBigEndian()) std::swap(Lo, Hi); 731 732 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(), 733 SVOffset, isVolatile, Alignment); 734 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 735 DAG.getIntPtrConstant(4)); 736 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 737 isVolatile, MinAlign(Alignment, 4U)); 738 739 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 740 } 741 } 742 } 743 return SDValue(); 744} 745 746/// LegalizeOp - We know that the specified value has a legal type, and 747/// that its operands are legal. Now ensure that the operation itself 748/// is legal, recursively ensuring that the operands' operations remain 749/// legal. 750SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { 751 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 752 return Op; 753 754 SDNode *Node = Op.getNode(); 755 DebugLoc dl = Node->getDebugLoc(); 756 757 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 758 assert(getTypeAction(Node->getValueType(i)) == Legal && 759 "Unexpected illegal type!"); 760 761 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 762 assert((isTypeLegal(Node->getOperand(i).getValueType()) || 763 Node->getOperand(i).getOpcode() == ISD::TargetConstant) && 764 "Unexpected illegal type!"); 765 766 // Note that LegalizeOp may be reentered even from single-use nodes, which 767 // means that we always must cache transformed nodes. 768 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 769 if (I != LegalizedNodes.end()) return I->second; 770 771 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 772 SDValue Result = Op; 773 bool isCustom = false; 774 775 // Figure out the correct action; the way to query this varies by opcode 776 TargetLowering::LegalizeAction Action; 777 bool SimpleFinishLegalizing = true; 778 switch (Node->getOpcode()) { 779 case ISD::INTRINSIC_W_CHAIN: 780 case ISD::INTRINSIC_WO_CHAIN: 781 case ISD::INTRINSIC_VOID: 782 case ISD::VAARG: 783 case ISD::STACKSAVE: 784 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other); 785 break; 786 case ISD::SINT_TO_FP: 787 case ISD::UINT_TO_FP: 788 case ISD::EXTRACT_VECTOR_ELT: 789 Action = TLI.getOperationAction(Node->getOpcode(), 790 Node->getOperand(0).getValueType()); 791 break; 792 case ISD::FP_ROUND_INREG: 793 case ISD::SIGN_EXTEND_INREG: { 794 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT(); 795 Action = TLI.getOperationAction(Node->getOpcode(), InnerType); 796 break; 797 } 798 case ISD::SELECT_CC: 799 case ISD::SETCC: 800 case ISD::BR_CC: { 801 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 : 802 Node->getOpcode() == ISD::SETCC ? 2 : 1; 803 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0; 804 EVT OpVT = Node->getOperand(CompareOperand).getValueType(); 805 ISD::CondCode CCCode = 806 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get(); 807 Action = TLI.getCondCodeAction(CCCode, OpVT); 808 if (Action == TargetLowering::Legal) { 809 if (Node->getOpcode() == ISD::SELECT_CC) 810 Action = TLI.getOperationAction(Node->getOpcode(), 811 Node->getValueType(0)); 812 else 813 Action = TLI.getOperationAction(Node->getOpcode(), OpVT); 814 } 815 break; 816 } 817 case ISD::LOAD: 818 case ISD::STORE: 819 // FIXME: Model these properly. LOAD and STORE are complicated, and 820 // STORE expects the unlegalized operand in some cases. 821 SimpleFinishLegalizing = false; 822 break; 823 case ISD::CALLSEQ_START: 824 case ISD::CALLSEQ_END: 825 // FIXME: This shouldn't be necessary. These nodes have special properties 826 // dealing with the recursive nature of legalization. Removing this 827 // special case should be done as part of making LegalizeDAG non-recursive. 828 SimpleFinishLegalizing = false; 829 break; 830 case ISD::EXTRACT_ELEMENT: 831 case ISD::FLT_ROUNDS_: 832 case ISD::SADDO: 833 case ISD::SSUBO: 834 case ISD::UADDO: 835 case ISD::USUBO: 836 case ISD::SMULO: 837 case ISD::UMULO: 838 case ISD::FPOWI: 839 case ISD::MERGE_VALUES: 840 case ISD::EH_RETURN: 841 case ISD::FRAME_TO_ARGS_OFFSET: 842 // These operations lie about being legal: when they claim to be legal, 843 // they should actually be expanded. 844 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 845 if (Action == TargetLowering::Legal) 846 Action = TargetLowering::Expand; 847 break; 848 case ISD::TRAMPOLINE: 849 case ISD::FRAMEADDR: 850 case ISD::RETURNADDR: 851 // These operations lie about being legal: when they claim to be legal, 852 // they should actually be custom-lowered. 853 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 854 if (Action == TargetLowering::Legal) 855 Action = TargetLowering::Custom; 856 break; 857 case ISD::BUILD_VECTOR: 858 // A weird case: legalization for BUILD_VECTOR never legalizes the 859 // operands! 860 // FIXME: This really sucks... changing it isn't semantically incorrect, 861 // but it massively pessimizes the code for floating-point BUILD_VECTORs 862 // because ConstantFP operands get legalized into constant pool loads 863 // before the BUILD_VECTOR code can see them. It doesn't usually bite, 864 // though, because BUILD_VECTORS usually get lowered into other nodes 865 // which get legalized properly. 866 SimpleFinishLegalizing = false; 867 break; 868 default: 869 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 870 Action = TargetLowering::Legal; 871 } else { 872 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 873 } 874 break; 875 } 876 877 if (SimpleFinishLegalizing) { 878 SmallVector<SDValue, 8> Ops, ResultVals; 879 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 880 Ops.push_back(LegalizeOp(Node->getOperand(i))); 881 switch (Node->getOpcode()) { 882 default: break; 883 case ISD::BR: 884 case ISD::BRIND: 885 case ISD::BR_JT: 886 case ISD::BR_CC: 887 case ISD::BRCOND: 888 // Branches tweak the chain to include LastCALLSEQ_END 889 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0], 890 LastCALLSEQ_END); 891 Ops[0] = LegalizeOp(Ops[0]); 892 LastCALLSEQ_END = DAG.getEntryNode(); 893 break; 894 case ISD::SHL: 895 case ISD::SRL: 896 case ISD::SRA: 897 case ISD::ROTL: 898 case ISD::ROTR: 899 // Legalizing shifts/rotates requires adjusting the shift amount 900 // to the appropriate width. 901 if (!Ops[1].getValueType().isVector()) 902 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[1])); 903 break; 904 case ISD::SRL_PARTS: 905 case ISD::SRA_PARTS: 906 case ISD::SHL_PARTS: 907 // Legalizing shifts/rotates requires adjusting the shift amount 908 // to the appropriate width. 909 if (!Ops[2].getValueType().isVector()) 910 Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[2])); 911 break; 912 } 913 914 Result = DAG.UpdateNodeOperands(Result.getValue(0), Ops.data(), 915 Ops.size()); 916 switch (Action) { 917 case TargetLowering::Legal: 918 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 919 ResultVals.push_back(Result.getValue(i)); 920 break; 921 case TargetLowering::Custom: 922 // FIXME: The handling for custom lowering with multiple results is 923 // a complete mess. 924 Tmp1 = TLI.LowerOperation(Result, DAG); 925 if (Tmp1.getNode()) { 926 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 927 if (e == 1) 928 ResultVals.push_back(Tmp1); 929 else 930 ResultVals.push_back(Tmp1.getValue(i)); 931 } 932 break; 933 } 934 935 // FALL THROUGH 936 case TargetLowering::Expand: 937 ExpandNode(Result.getNode(), ResultVals); 938 break; 939 case TargetLowering::Promote: 940 PromoteNode(Result.getNode(), ResultVals); 941 break; 942 } 943 if (!ResultVals.empty()) { 944 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) { 945 if (ResultVals[i] != SDValue(Node, i)) 946 ResultVals[i] = LegalizeOp(ResultVals[i]); 947 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]); 948 } 949 return ResultVals[Op.getResNo()]; 950 } 951 } 952 953 switch (Node->getOpcode()) { 954 default: 955#ifndef NDEBUG 956 errs() << "NODE: "; 957 Node->dump(&DAG); 958 errs() << "\n"; 959#endif 960 llvm_unreachable("Do not know how to legalize this operator!"); 961 962 case ISD::BUILD_VECTOR: 963 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 964 default: llvm_unreachable("This action is not supported yet!"); 965 case TargetLowering::Custom: 966 Tmp3 = TLI.LowerOperation(Result, DAG); 967 if (Tmp3.getNode()) { 968 Result = Tmp3; 969 break; 970 } 971 // FALLTHROUGH 972 case TargetLowering::Expand: 973 Result = ExpandBUILD_VECTOR(Result.getNode()); 974 break; 975 } 976 break; 977 case ISD::CALLSEQ_START: { 978 SDNode *CallEnd = FindCallEndFromCallStart(Node); 979 980 // Recursively Legalize all of the inputs of the call end that do not lead 981 // to this call start. This ensures that any libcalls that need be inserted 982 // are inserted *before* the CALLSEQ_START. 983 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 984 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 985 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node, 986 NodesLeadingTo); 987 } 988 989 // Now that we legalized all of the inputs (which may have inserted 990 // libcalls) create the new CALLSEQ_START node. 991 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 992 993 // Merge in the last call, to ensure that this call start after the last 994 // call ended. 995 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 996 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 997 Tmp1, LastCALLSEQ_END); 998 Tmp1 = LegalizeOp(Tmp1); 999 } 1000 1001 // Do not try to legalize the target-specific arguments (#1+). 1002 if (Tmp1 != Node->getOperand(0)) { 1003 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1004 Ops[0] = Tmp1; 1005 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1006 } 1007 1008 // Remember that the CALLSEQ_START is legalized. 1009 AddLegalizedOperand(Op.getValue(0), Result); 1010 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1011 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1012 1013 // Now that the callseq_start and all of the non-call nodes above this call 1014 // sequence have been legalized, legalize the call itself. During this 1015 // process, no libcalls can/will be inserted, guaranteeing that no calls 1016 // can overlap. 1017 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1018 // Note that we are selecting this call! 1019 LastCALLSEQ_END = SDValue(CallEnd, 0); 1020 IsLegalizingCall = true; 1021 1022 // Legalize the call, starting from the CALLSEQ_END. 1023 LegalizeOp(LastCALLSEQ_END); 1024 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1025 return Result; 1026 } 1027 case ISD::CALLSEQ_END: 1028 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1029 // will cause this node to be legalized as well as handling libcalls right. 1030 if (LastCALLSEQ_END.getNode() != Node) { 1031 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0)); 1032 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 1033 assert(I != LegalizedNodes.end() && 1034 "Legalizing the call start should have legalized this node!"); 1035 return I->second; 1036 } 1037 1038 // Otherwise, the call start has been legalized and everything is going 1039 // according to plan. Just legalize ourselves normally here. 1040 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1041 // Do not try to legalize the target-specific arguments (#1+), except for 1042 // an optional flag input. 1043 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1044 if (Tmp1 != Node->getOperand(0)) { 1045 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1046 Ops[0] = Tmp1; 1047 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1048 } 1049 } else { 1050 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1051 if (Tmp1 != Node->getOperand(0) || 1052 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1053 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1054 Ops[0] = Tmp1; 1055 Ops.back() = Tmp2; 1056 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1057 } 1058 } 1059 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1060 // This finishes up call legalization. 1061 IsLegalizingCall = false; 1062 1063 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1064 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1065 if (Node->getNumValues() == 2) 1066 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1067 return Result.getValue(Op.getResNo()); 1068 case ISD::LOAD: { 1069 LoadSDNode *LD = cast<LoadSDNode>(Node); 1070 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1071 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1072 1073 ISD::LoadExtType ExtType = LD->getExtensionType(); 1074 if (ExtType == ISD::NON_EXTLOAD) { 1075 EVT VT = Node->getValueType(0); 1076 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1077 Tmp3 = Result.getValue(0); 1078 Tmp4 = Result.getValue(1); 1079 1080 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1081 default: llvm_unreachable("This action is not supported yet!"); 1082 case TargetLowering::Legal: 1083 // If this is an unaligned load and the target doesn't support it, 1084 // expand it. 1085 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { 1086 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1087 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 1088 if (LD->getAlignment() < ABIAlignment){ 1089 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), 1090 DAG, TLI); 1091 Tmp3 = Result.getOperand(0); 1092 Tmp4 = Result.getOperand(1); 1093 Tmp3 = LegalizeOp(Tmp3); 1094 Tmp4 = LegalizeOp(Tmp4); 1095 } 1096 } 1097 break; 1098 case TargetLowering::Custom: 1099 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1100 if (Tmp1.getNode()) { 1101 Tmp3 = LegalizeOp(Tmp1); 1102 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1103 } 1104 break; 1105 case TargetLowering::Promote: { 1106 // Only promote a load of vector type to another. 1107 assert(VT.isVector() && "Cannot promote this load!"); 1108 // Change base type to a different vector type. 1109 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1110 1111 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(), 1112 LD->getSrcValueOffset(), 1113 LD->isVolatile(), LD->getAlignment()); 1114 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1)); 1115 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1116 break; 1117 } 1118 } 1119 // Since loads produce two values, make sure to remember that we 1120 // legalized both of them. 1121 AddLegalizedOperand(SDValue(Node, 0), Tmp3); 1122 AddLegalizedOperand(SDValue(Node, 1), Tmp4); 1123 return Op.getResNo() ? Tmp4 : Tmp3; 1124 } else { 1125 EVT SrcVT = LD->getMemoryVT(); 1126 unsigned SrcWidth = SrcVT.getSizeInBits(); 1127 int SVOffset = LD->getSrcValueOffset(); 1128 unsigned Alignment = LD->getAlignment(); 1129 bool isVolatile = LD->isVolatile(); 1130 1131 if (SrcWidth != SrcVT.getStoreSizeInBits() && 1132 // Some targets pretend to have an i1 loading operation, and actually 1133 // load an i8. This trick is correct for ZEXTLOAD because the top 7 1134 // bits are guaranteed to be zero; it helps the optimizers understand 1135 // that these bits are zero. It is also useful for EXTLOAD, since it 1136 // tells the optimizers that those bits are undefined. It would be 1137 // nice to have an effective generic way of getting these benefits... 1138 // Until such a way is found, don't insist on promoting i1 here. 1139 (SrcVT != MVT::i1 || 1140 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 1141 // Promote to a byte-sized load if not loading an integral number of 1142 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 1143 unsigned NewWidth = SrcVT.getStoreSizeInBits(); 1144 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth); 1145 SDValue Ch; 1146 1147 // The extra bits are guaranteed to be zero, since we stored them that 1148 // way. A zext load from NVT thus automatically gives zext from SrcVT. 1149 1150 ISD::LoadExtType NewExtType = 1151 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 1152 1153 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0), 1154 Tmp1, Tmp2, LD->getSrcValue(), SVOffset, 1155 NVT, isVolatile, Alignment); 1156 1157 Ch = Result.getValue(1); // The chain. 1158 1159 if (ExtType == ISD::SEXTLOAD) 1160 // Having the top bits zero doesn't help when sign extending. 1161 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1162 Result.getValueType(), 1163 Result, DAG.getValueType(SrcVT)); 1164 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 1165 // All the top bits are guaranteed to be zero - inform the optimizers. 1166 Result = DAG.getNode(ISD::AssertZext, dl, 1167 Result.getValueType(), Result, 1168 DAG.getValueType(SrcVT)); 1169 1170 Tmp1 = LegalizeOp(Result); 1171 Tmp2 = LegalizeOp(Ch); 1172 } else if (SrcWidth & (SrcWidth - 1)) { 1173 // If not loading a power-of-2 number of bits, expand as two loads. 1174 assert(SrcVT.isExtended() && !SrcVT.isVector() && 1175 "Unsupported extload!"); 1176 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 1177 assert(RoundWidth < SrcWidth); 1178 unsigned ExtraWidth = SrcWidth - RoundWidth; 1179 assert(ExtraWidth < RoundWidth); 1180 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1181 "Load size not an integral number of bytes!"); 1182 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth); 1183 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); 1184 SDValue Lo, Hi, Ch; 1185 unsigned IncrementSize; 1186 1187 if (TLI.isLittleEndian()) { 1188 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 1189 // Load the bottom RoundWidth bits. 1190 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, 1191 Node->getValueType(0), Tmp1, Tmp2, 1192 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 1193 Alignment); 1194 1195 // Load the remaining ExtraWidth bits. 1196 IncrementSize = RoundWidth / 8; 1197 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1198 DAG.getIntPtrConstant(IncrementSize)); 1199 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, 1200 LD->getSrcValue(), SVOffset + IncrementSize, 1201 ExtraVT, isVolatile, 1202 MinAlign(Alignment, IncrementSize)); 1203 1204 // Build a factor node to remember that this load is independent of the 1205 // other one. 1206 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1207 Hi.getValue(1)); 1208 1209 // Move the top bits to the right place. 1210 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1211 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 1212 1213 // Join the hi and lo parts. 1214 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1215 } else { 1216 // Big endian - avoid unaligned loads. 1217 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 1218 // Load the top RoundWidth bits. 1219 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, 1220 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 1221 Alignment); 1222 1223 // Load the remaining ExtraWidth bits. 1224 IncrementSize = RoundWidth / 8; 1225 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1226 DAG.getIntPtrConstant(IncrementSize)); 1227 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, 1228 Node->getValueType(0), Tmp1, Tmp2, 1229 LD->getSrcValue(), SVOffset + IncrementSize, 1230 ExtraVT, isVolatile, 1231 MinAlign(Alignment, IncrementSize)); 1232 1233 // Build a factor node to remember that this load is independent of the 1234 // other one. 1235 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1236 Hi.getValue(1)); 1237 1238 // Move the top bits to the right place. 1239 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1240 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 1241 1242 // Join the hi and lo parts. 1243 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1244 } 1245 1246 Tmp1 = LegalizeOp(Result); 1247 Tmp2 = LegalizeOp(Ch); 1248 } else { 1249 switch (TLI.getLoadExtAction(ExtType, SrcVT)) { 1250 default: llvm_unreachable("This action is not supported yet!"); 1251 case TargetLowering::Custom: 1252 isCustom = true; 1253 // FALLTHROUGH 1254 case TargetLowering::Legal: 1255 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1256 Tmp1 = Result.getValue(0); 1257 Tmp2 = Result.getValue(1); 1258 1259 if (isCustom) { 1260 Tmp3 = TLI.LowerOperation(Result, DAG); 1261 if (Tmp3.getNode()) { 1262 Tmp1 = LegalizeOp(Tmp3); 1263 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1264 } 1265 } else { 1266 // If this is an unaligned load and the target doesn't support it, 1267 // expand it. 1268 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { 1269 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1270 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 1271 if (LD->getAlignment() < ABIAlignment){ 1272 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), 1273 DAG, TLI); 1274 Tmp1 = Result.getOperand(0); 1275 Tmp2 = Result.getOperand(1); 1276 Tmp1 = LegalizeOp(Tmp1); 1277 Tmp2 = LegalizeOp(Tmp2); 1278 } 1279 } 1280 } 1281 break; 1282 case TargetLowering::Expand: 1283 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 1284 // f128 = EXTLOAD {f32,f64} too 1285 if ((SrcVT == MVT::f32 && (Node->getValueType(0) == MVT::f64 || 1286 Node->getValueType(0) == MVT::f128)) || 1287 (SrcVT == MVT::f64 && Node->getValueType(0) == MVT::f128)) { 1288 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(), 1289 LD->getSrcValueOffset(), 1290 LD->isVolatile(), LD->getAlignment()); 1291 Result = DAG.getNode(ISD::FP_EXTEND, dl, 1292 Node->getValueType(0), Load); 1293 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 1294 Tmp2 = LegalizeOp(Load.getValue(1)); 1295 break; 1296 } 1297 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 1298 // Turn the unsupported load into an EXTLOAD followed by an explicit 1299 // zero/sign extend inreg. 1300 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0), 1301 Tmp1, Tmp2, LD->getSrcValue(), 1302 LD->getSrcValueOffset(), SrcVT, 1303 LD->isVolatile(), LD->getAlignment()); 1304 SDValue ValRes; 1305 if (ExtType == ISD::SEXTLOAD) 1306 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1307 Result.getValueType(), 1308 Result, DAG.getValueType(SrcVT)); 1309 else 1310 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT); 1311 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 1312 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 1313 break; 1314 } 1315 } 1316 1317 // Since loads produce two values, make sure to remember that we legalized 1318 // both of them. 1319 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 1320 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 1321 return Op.getResNo() ? Tmp2 : Tmp1; 1322 } 1323 } 1324 case ISD::STORE: { 1325 StoreSDNode *ST = cast<StoreSDNode>(Node); 1326 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 1327 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 1328 int SVOffset = ST->getSrcValueOffset(); 1329 unsigned Alignment = ST->getAlignment(); 1330 bool isVolatile = ST->isVolatile(); 1331 1332 if (!ST->isTruncatingStore()) { 1333 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) { 1334 Result = SDValue(OptStore, 0); 1335 break; 1336 } 1337 1338 { 1339 Tmp3 = LegalizeOp(ST->getValue()); 1340 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1341 ST->getOffset()); 1342 1343 EVT VT = Tmp3.getValueType(); 1344 switch (TLI.getOperationAction(ISD::STORE, VT)) { 1345 default: llvm_unreachable("This action is not supported yet!"); 1346 case TargetLowering::Legal: 1347 // If this is an unaligned store and the target doesn't support it, 1348 // expand it. 1349 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 1350 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1351 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 1352 if (ST->getAlignment() < ABIAlignment) 1353 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), 1354 DAG, TLI); 1355 } 1356 break; 1357 case TargetLowering::Custom: 1358 Tmp1 = TLI.LowerOperation(Result, DAG); 1359 if (Tmp1.getNode()) Result = Tmp1; 1360 break; 1361 case TargetLowering::Promote: 1362 assert(VT.isVector() && "Unknown legal promote case!"); 1363 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl, 1364 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 1365 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, 1366 ST->getSrcValue(), SVOffset, isVolatile, 1367 Alignment); 1368 break; 1369 } 1370 break; 1371 } 1372 } else { 1373 Tmp3 = LegalizeOp(ST->getValue()); 1374 1375 EVT StVT = ST->getMemoryVT(); 1376 unsigned StWidth = StVT.getSizeInBits(); 1377 1378 if (StWidth != StVT.getStoreSizeInBits()) { 1379 // Promote to a byte-sized store with upper bits zero if not 1380 // storing an integral number of bytes. For example, promote 1381 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 1382 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), StVT.getStoreSizeInBits()); 1383 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT); 1384 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1385 SVOffset, NVT, isVolatile, Alignment); 1386 } else if (StWidth & (StWidth - 1)) { 1387 // If not storing a power-of-2 number of bits, expand as two stores. 1388 assert(StVT.isExtended() && !StVT.isVector() && 1389 "Unsupported truncstore!"); 1390 unsigned RoundWidth = 1 << Log2_32(StWidth); 1391 assert(RoundWidth < StWidth); 1392 unsigned ExtraWidth = StWidth - RoundWidth; 1393 assert(ExtraWidth < RoundWidth); 1394 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1395 "Store size not an integral number of bytes!"); 1396 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth); 1397 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); 1398 SDValue Lo, Hi; 1399 unsigned IncrementSize; 1400 1401 if (TLI.isLittleEndian()) { 1402 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 1403 // Store the bottom RoundWidth bits. 1404 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1405 SVOffset, RoundVT, 1406 isVolatile, Alignment); 1407 1408 // Store the remaining ExtraWidth bits. 1409 IncrementSize = RoundWidth / 8; 1410 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1411 DAG.getIntPtrConstant(IncrementSize)); 1412 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1413 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 1414 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), 1415 SVOffset + IncrementSize, ExtraVT, isVolatile, 1416 MinAlign(Alignment, IncrementSize)); 1417 } else { 1418 // Big endian - avoid unaligned stores. 1419 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 1420 // Store the top RoundWidth bits. 1421 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1422 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 1423 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), 1424 SVOffset, RoundVT, isVolatile, Alignment); 1425 1426 // Store the remaining ExtraWidth bits. 1427 IncrementSize = RoundWidth / 8; 1428 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1429 DAG.getIntPtrConstant(IncrementSize)); 1430 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1431 SVOffset + IncrementSize, ExtraVT, isVolatile, 1432 MinAlign(Alignment, IncrementSize)); 1433 } 1434 1435 // The order of the stores doesn't matter. 1436 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 1437 } else { 1438 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 1439 Tmp2 != ST->getBasePtr()) 1440 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1441 ST->getOffset()); 1442 1443 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 1444 default: llvm_unreachable("This action is not supported yet!"); 1445 case TargetLowering::Legal: 1446 // If this is an unaligned store and the target doesn't support it, 1447 // expand it. 1448 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 1449 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1450 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 1451 if (ST->getAlignment() < ABIAlignment) 1452 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), 1453 DAG, TLI); 1454 } 1455 break; 1456 case TargetLowering::Custom: 1457 Result = TLI.LowerOperation(Result, DAG); 1458 break; 1459 case Expand: 1460 // TRUNCSTORE:i16 i32 -> STORE i16 1461 assert(isTypeLegal(StVT) && "Do not know how to expand this store!"); 1462 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3); 1463 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1464 SVOffset, isVolatile, Alignment); 1465 break; 1466 } 1467 } 1468 } 1469 break; 1470 } 1471 } 1472 assert(Result.getValueType() == Op.getValueType() && 1473 "Bad legalization!"); 1474 1475 // Make sure that the generated code is itself legal. 1476 if (Result != Op) 1477 Result = LegalizeOp(Result); 1478 1479 // Note that LegalizeOp may be reentered even from single-use nodes, which 1480 // means that we always must cache transformed nodes. 1481 AddLegalizedOperand(Op, Result); 1482 return Result; 1483} 1484 1485SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) { 1486 SDValue Vec = Op.getOperand(0); 1487 SDValue Idx = Op.getOperand(1); 1488 DebugLoc dl = Op.getDebugLoc(); 1489 // Store the value to a temporary stack slot, then LOAD the returned part. 1490 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 1491 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0); 1492 1493 // Add the offset to the index. 1494 unsigned EltSize = 1495 Vec.getValueType().getVectorElementType().getSizeInBits()/8; 1496 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx, 1497 DAG.getConstant(EltSize, Idx.getValueType())); 1498 1499 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 1500 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx); 1501 else 1502 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); 1503 1504 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr); 1505 1506 if (Op.getValueType().isVector()) 1507 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0); 1508 else 1509 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr, 1510 NULL, 0, Vec.getValueType().getVectorElementType()); 1511} 1512 1513SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) { 1514 // We can't handle this case efficiently. Allocate a sufficiently 1515 // aligned object on the stack, store each element into it, then load 1516 // the result as a vector. 1517 // Create the stack frame object. 1518 EVT VT = Node->getValueType(0); 1519 EVT OpVT = Node->getOperand(0).getValueType(); 1520 DebugLoc dl = Node->getDebugLoc(); 1521 SDValue FIPtr = DAG.CreateStackTemporary(VT); 1522 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex(); 1523 const Value *SV = PseudoSourceValue::getFixedStack(FI); 1524 1525 // Emit a store of each element to the stack slot. 1526 SmallVector<SDValue, 8> Stores; 1527 unsigned TypeByteSize = OpVT.getSizeInBits() / 8; 1528 // Store (in the right endianness) the elements to memory. 1529 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1530 // Ignore undef elements. 1531 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 1532 1533 unsigned Offset = TypeByteSize*i; 1534 1535 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 1536 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx); 1537 1538 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(i), 1539 Idx, SV, Offset)); 1540 } 1541 1542 SDValue StoreChain; 1543 if (!Stores.empty()) // Not all undef elements? 1544 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1545 &Stores[0], Stores.size()); 1546 else 1547 StoreChain = DAG.getEntryNode(); 1548 1549 // Result is a load from the stack slot. 1550 return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0); 1551} 1552 1553SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) { 1554 DebugLoc dl = Node->getDebugLoc(); 1555 SDValue Tmp1 = Node->getOperand(0); 1556 SDValue Tmp2 = Node->getOperand(1); 1557 assert((Tmp2.getValueType() == MVT::f32 || 1558 Tmp2.getValueType() == MVT::f64) && 1559 "Ugly special-cased code!"); 1560 // Get the sign bit of the RHS. 1561 SDValue SignBit; 1562 EVT IVT = Tmp2.getValueType() == MVT::f64 ? MVT::i64 : MVT::i32; 1563 if (isTypeLegal(IVT)) { 1564 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2); 1565 } else { 1566 assert(isTypeLegal(TLI.getPointerTy()) && 1567 (TLI.getPointerTy() == MVT::i32 || 1568 TLI.getPointerTy() == MVT::i64) && 1569 "Legal type for load?!"); 1570 SDValue StackPtr = DAG.CreateStackTemporary(Tmp2.getValueType()); 1571 SDValue StorePtr = StackPtr, LoadPtr = StackPtr; 1572 SDValue Ch = 1573 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StorePtr, NULL, 0); 1574 if (Tmp2.getValueType() == MVT::f64 && TLI.isLittleEndian()) 1575 LoadPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), 1576 LoadPtr, DAG.getIntPtrConstant(4)); 1577 SignBit = DAG.getExtLoad(ISD::SEXTLOAD, dl, TLI.getPointerTy(), 1578 Ch, LoadPtr, NULL, 0, MVT::i32); 1579 } 1580 SignBit = 1581 DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()), 1582 SignBit, DAG.getConstant(0, SignBit.getValueType()), 1583 ISD::SETLT); 1584 // Get the absolute value of the result. 1585 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1); 1586 // Select between the nabs and abs value based on the sign bit of 1587 // the input. 1588 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit, 1589 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal), 1590 AbsVal); 1591} 1592 1593SDValue SelectionDAGLegalize::ExpandDBG_STOPPOINT(SDNode* Node) { 1594 DebugLoc dl = Node->getDebugLoc(); 1595 DwarfWriter *DW = DAG.getDwarfWriter(); 1596 bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC, 1597 MVT::Other); 1598 bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other); 1599 1600 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node); 1601 MDNode *CU_Node = DSP->getCompileUnit(); 1602 if (DW && (useDEBUG_LOC || useLABEL)) { 1603 1604 unsigned Line = DSP->getLine(); 1605 unsigned Col = DSP->getColumn(); 1606 1607 if (OptLevel == CodeGenOpt::None) { 1608 // A bit self-referential to have DebugLoc on Debug_Loc nodes, but it 1609 // won't hurt anything. 1610 if (useDEBUG_LOC) { 1611 return DAG.getNode(ISD::DEBUG_LOC, dl, MVT::Other, Node->getOperand(0), 1612 DAG.getConstant(Line, MVT::i32), 1613 DAG.getConstant(Col, MVT::i32), 1614 DAG.getSrcValue(CU_Node)); 1615 } else { 1616 unsigned ID = DW->RecordSourceLine(Line, Col, CU_Node); 1617 return DAG.getLabel(ISD::DBG_LABEL, dl, Node->getOperand(0), ID); 1618 } 1619 } 1620 } 1621 return Node->getOperand(0); 1622} 1623 1624void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node, 1625 SmallVectorImpl<SDValue> &Results) { 1626 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1627 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1628 " not tell us which reg is the stack pointer!"); 1629 DebugLoc dl = Node->getDebugLoc(); 1630 EVT VT = Node->getValueType(0); 1631 SDValue Tmp1 = SDValue(Node, 0); 1632 SDValue Tmp2 = SDValue(Node, 1); 1633 SDValue Tmp3 = Node->getOperand(2); 1634 SDValue Chain = Tmp1.getOperand(0); 1635 1636 // Chain the dynamic stack allocation so that it doesn't modify the stack 1637 // pointer when other instructions are using the stack. 1638 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); 1639 1640 SDValue Size = Tmp2.getOperand(1); 1641 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); 1642 Chain = SP.getValue(1); 1643 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue(); 1644 unsigned StackAlign = 1645 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1646 if (Align > StackAlign) 1647 SP = DAG.getNode(ISD::AND, dl, VT, SP, 1648 DAG.getConstant(-(uint64_t)Align, VT)); 1649 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value 1650 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain 1651 1652 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true), 1653 DAG.getIntPtrConstant(0, true), SDValue()); 1654 1655 Results.push_back(Tmp1); 1656 Results.push_back(Tmp2); 1657} 1658 1659/// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and 1660/// condition code CC on the current target. This routine expands SETCC with 1661/// illegal condition code into AND / OR of multiple SETCC values. 1662void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT, 1663 SDValue &LHS, SDValue &RHS, 1664 SDValue &CC, 1665 DebugLoc dl) { 1666 EVT OpVT = LHS.getValueType(); 1667 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 1668 switch (TLI.getCondCodeAction(CCCode, OpVT)) { 1669 default: llvm_unreachable("Unknown condition code action!"); 1670 case TargetLowering::Legal: 1671 // Nothing to do. 1672 break; 1673 case TargetLowering::Expand: { 1674 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID; 1675 unsigned Opc = 0; 1676 switch (CCCode) { 1677 default: llvm_unreachable("Don't know how to expand this condition!"); 1678 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break; 1679 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1680 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1681 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1682 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1683 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1684 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1685 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1686 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1687 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1688 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1689 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1690 // FIXME: Implement more expansions. 1691 } 1692 1693 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1); 1694 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2); 1695 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2); 1696 RHS = SDValue(); 1697 CC = SDValue(); 1698 break; 1699 } 1700 } 1701} 1702 1703/// EmitStackConvert - Emit a store/load combination to the stack. This stores 1704/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 1705/// a load from the stack slot to DestVT, extending it if needed. 1706/// The resultant code need not be legal. 1707SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, 1708 EVT SlotVT, 1709 EVT DestVT, 1710 DebugLoc dl) { 1711 // Create the stack frame object. 1712 unsigned SrcAlign = 1713 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType(). 1714 getTypeForEVT(*DAG.getContext())); 1715 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign); 1716 1717 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 1718 int SPFI = StackPtrFI->getIndex(); 1719 const Value *SV = PseudoSourceValue::getFixedStack(SPFI); 1720 1721 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); 1722 unsigned SlotSize = SlotVT.getSizeInBits(); 1723 unsigned DestSize = DestVT.getSizeInBits(); 1724 unsigned DestAlign = 1725 TLI.getTargetData()->getPrefTypeAlignment(DestVT.getTypeForEVT(*DAG.getContext())); 1726 1727 // Emit a store to the stack slot. Use a truncstore if the input value is 1728 // later than DestVT. 1729 SDValue Store; 1730 1731 if (SrcSize > SlotSize) 1732 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1733 SV, 0, SlotVT, false, SrcAlign); 1734 else { 1735 assert(SrcSize == SlotSize && "Invalid store"); 1736 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1737 SV, 0, false, SrcAlign); 1738 } 1739 1740 // Result is a load from the stack slot. 1741 if (SlotSize == DestSize) 1742 return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, DestAlign); 1743 1744 assert(SlotSize < DestSize && "Unknown extension!"); 1745 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, SV, 0, SlotVT, 1746 false, DestAlign); 1747} 1748 1749SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 1750 DebugLoc dl = Node->getDebugLoc(); 1751 // Create a vector sized/aligned stack slot, store the value to element #0, 1752 // then load the whole vector back out. 1753 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 1754 1755 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 1756 int SPFI = StackPtrFI->getIndex(); 1757 1758 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0), 1759 StackPtr, 1760 PseudoSourceValue::getFixedStack(SPFI), 0, 1761 Node->getValueType(0).getVectorElementType()); 1762 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr, 1763 PseudoSourceValue::getFixedStack(SPFI), 0); 1764} 1765 1766 1767/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 1768/// support the operation, but do support the resultant vector type. 1769SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 1770 unsigned NumElems = Node->getNumOperands(); 1771 SDValue Value1, Value2; 1772 DebugLoc dl = Node->getDebugLoc(); 1773 EVT VT = Node->getValueType(0); 1774 EVT OpVT = Node->getOperand(0).getValueType(); 1775 EVT EltVT = VT.getVectorElementType(); 1776 1777 // If the only non-undef value is the low element, turn this into a 1778 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 1779 bool isOnlyLowElement = true; 1780 bool MoreThanTwoValues = false; 1781 bool isConstant = true; 1782 for (unsigned i = 0; i < NumElems; ++i) { 1783 SDValue V = Node->getOperand(i); 1784 if (V.getOpcode() == ISD::UNDEF) 1785 continue; 1786 if (i > 0) 1787 isOnlyLowElement = false; 1788 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V)) 1789 isConstant = false; 1790 1791 if (!Value1.getNode()) { 1792 Value1 = V; 1793 } else if (!Value2.getNode()) { 1794 if (V != Value1) 1795 Value2 = V; 1796 } else if (V != Value1 && V != Value2) { 1797 MoreThanTwoValues = true; 1798 } 1799 } 1800 1801 if (!Value1.getNode()) 1802 return DAG.getUNDEF(VT); 1803 1804 if (isOnlyLowElement) 1805 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0)); 1806 1807 // If all elements are constants, create a load from the constant pool. 1808 if (isConstant) { 1809 std::vector<Constant*> CV; 1810 for (unsigned i = 0, e = NumElems; i != e; ++i) { 1811 if (ConstantFPSDNode *V = 1812 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 1813 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue())); 1814 } else if (ConstantSDNode *V = 1815 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 1816 if (OpVT==EltVT) 1817 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue())); 1818 else { 1819 // If OpVT and EltVT don't match, EltVT is not legal and the 1820 // element values have been promoted/truncated earlier. Undo this; 1821 // we don't want a v16i8 to become a v16i32 for example. 1822 const ConstantInt *CI = V->getConstantIntValue(); 1823 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()), 1824 CI->getZExtValue())); 1825 } 1826 } else { 1827 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 1828 const Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext()); 1829 CV.push_back(UndefValue::get(OpNTy)); 1830 } 1831 } 1832 Constant *CP = ConstantVector::get(CV); 1833 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 1834 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 1835 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 1836 PseudoSourceValue::getConstantPool(), 0, 1837 false, Alignment); 1838 } 1839 1840 if (!MoreThanTwoValues) { 1841 SmallVector<int, 8> ShuffleVec(NumElems, -1); 1842 for (unsigned i = 0; i < NumElems; ++i) { 1843 SDValue V = Node->getOperand(i); 1844 if (V.getOpcode() == ISD::UNDEF) 1845 continue; 1846 ShuffleVec[i] = V == Value1 ? 0 : NumElems; 1847 } 1848 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) { 1849 // Get the splatted value into the low element of a vector register. 1850 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1); 1851 SDValue Vec2; 1852 if (Value2.getNode()) 1853 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2); 1854 else 1855 Vec2 = DAG.getUNDEF(VT); 1856 1857 // Return shuffle(LowValVec, undef, <0,0,0,0>) 1858 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data()); 1859 } 1860 } 1861 1862 // Otherwise, we can't handle this case efficiently. 1863 return ExpandVectorBuildThroughStack(Node); 1864} 1865 1866// ExpandLibCall - Expand a node into a call to a libcall. If the result value 1867// does not fit into a register, return the lo part and set the hi part to the 1868// by-reg argument. If it does fit into a single register, return the result 1869// and leave the Hi part unset. 1870SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, 1871 bool isSigned) { 1872 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 1873 // The input chain to this libcall is the entry node of the function. 1874 // Legalizing the call will automatically add the previous call to the 1875 // dependence. 1876 SDValue InChain = DAG.getEntryNode(); 1877 1878 TargetLowering::ArgListTy Args; 1879 TargetLowering::ArgListEntry Entry; 1880 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1881 EVT ArgVT = Node->getOperand(i).getValueType(); 1882 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 1883 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 1884 Entry.isSExt = isSigned; 1885 Entry.isZExt = !isSigned; 1886 Args.push_back(Entry); 1887 } 1888 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 1889 TLI.getPointerTy()); 1890 1891 // Splice the libcall in wherever FindInputOutputChains tells us to. 1892 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext()); 1893 std::pair<SDValue, SDValue> CallInfo = 1894 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 1895 0, TLI.getLibcallCallingConv(LC), false, 1896 /*isReturnValueUsed=*/true, 1897 Callee, Args, DAG, 1898 Node->getDebugLoc()); 1899 1900 // Legalize the call sequence, starting with the chain. This will advance 1901 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 1902 // was added by LowerCallTo (guaranteeing proper serialization of calls). 1903 LegalizeOp(CallInfo.second); 1904 return CallInfo.first; 1905} 1906 1907SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node, 1908 RTLIB::Libcall Call_F32, 1909 RTLIB::Libcall Call_F64, 1910 RTLIB::Libcall Call_F80, 1911 RTLIB::Libcall Call_PPCF128) { 1912 RTLIB::Libcall LC; 1913 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 1914 default: llvm_unreachable("Unexpected request for libcall!"); 1915 case MVT::f32: LC = Call_F32; break; 1916 case MVT::f64: LC = Call_F64; break; 1917 case MVT::f80: LC = Call_F80; break; 1918 case MVT::ppcf128: LC = Call_PPCF128; break; 1919 } 1920 return ExpandLibCall(LC, Node, false); 1921} 1922 1923SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned, 1924 RTLIB::Libcall Call_I8, 1925 RTLIB::Libcall Call_I16, 1926 RTLIB::Libcall Call_I32, 1927 RTLIB::Libcall Call_I64, 1928 RTLIB::Libcall Call_I128) { 1929 RTLIB::Libcall LC; 1930 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 1931 default: llvm_unreachable("Unexpected request for libcall!"); 1932 case MVT::i8: LC = Call_I8; break; 1933 case MVT::i16: LC = Call_I16; break; 1934 case MVT::i32: LC = Call_I32; break; 1935 case MVT::i64: LC = Call_I64; break; 1936 case MVT::i128: LC = Call_I128; break; 1937 } 1938 return ExpandLibCall(LC, Node, isSigned); 1939} 1940 1941/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 1942/// INT_TO_FP operation of the specified operand when the target requests that 1943/// we expand it. At this point, we know that the result and operand types are 1944/// legal for the target. 1945SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 1946 SDValue Op0, 1947 EVT DestVT, 1948 DebugLoc dl) { 1949 if (Op0.getValueType() == MVT::i32) { 1950 // simple 32-bit [signed|unsigned] integer to float/double expansion 1951 1952 // Get the stack frame index of a 8 byte buffer. 1953 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64); 1954 1955 // word offset constant for Hi/Lo address computation 1956 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 1957 // set up Hi and Lo (into buffer) address based on endian 1958 SDValue Hi = StackSlot; 1959 SDValue Lo = DAG.getNode(ISD::ADD, dl, 1960 TLI.getPointerTy(), StackSlot, WordOff); 1961 if (TLI.isLittleEndian()) 1962 std::swap(Hi, Lo); 1963 1964 // if signed map to unsigned space 1965 SDValue Op0Mapped; 1966 if (isSigned) { 1967 // constant used to invert sign bit (signed to unsigned mapping) 1968 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32); 1969 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit); 1970 } else { 1971 Op0Mapped = Op0; 1972 } 1973 // store the lo of the constructed double - based on integer input 1974 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, 1975 Op0Mapped, Lo, NULL, 0); 1976 // initial hi portion of constructed double 1977 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 1978 // store the hi of the constructed double - biased exponent 1979 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0); 1980 // load the constructed double 1981 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0); 1982 // FP constant to bias correct the final result 1983 SDValue Bias = DAG.getConstantFP(isSigned ? 1984 BitsToDouble(0x4330000080000000ULL) : 1985 BitsToDouble(0x4330000000000000ULL), 1986 MVT::f64); 1987 // subtract the bias 1988 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias); 1989 // final result 1990 SDValue Result; 1991 // handle final rounding 1992 if (DestVT == MVT::f64) { 1993 // do nothing 1994 Result = Sub; 1995 } else if (DestVT.bitsLT(MVT::f64)) { 1996 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 1997 DAG.getIntPtrConstant(0)); 1998 } else if (DestVT.bitsGT(MVT::f64)) { 1999 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 2000 } 2001 return Result; 2002 } 2003 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 2004 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); 2005 2006 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()), 2007 Op0, DAG.getConstant(0, Op0.getValueType()), 2008 ISD::SETLT); 2009 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 2010 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), 2011 SignSet, Four, Zero); 2012 2013 // If the sign bit of the integer is set, the large number will be treated 2014 // as a negative number. To counteract this, the dynamic code adds an 2015 // offset depending on the data type. 2016 uint64_t FF; 2017 switch (Op0.getValueType().getSimpleVT().SimpleTy) { 2018 default: llvm_unreachable("Unsupported integer type!"); 2019 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 2020 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 2021 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 2022 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 2023 } 2024 if (TLI.isLittleEndian()) FF <<= 32; 2025 Constant *FudgeFactor = ConstantInt::get( 2026 Type::getInt64Ty(*DAG.getContext()), FF); 2027 2028 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 2029 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 2030 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset); 2031 Alignment = std::min(Alignment, 4u); 2032 SDValue FudgeInReg; 2033 if (DestVT == MVT::f32) 2034 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx, 2035 PseudoSourceValue::getConstantPool(), 0, 2036 false, Alignment); 2037 else { 2038 FudgeInReg = 2039 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, 2040 DAG.getEntryNode(), CPIdx, 2041 PseudoSourceValue::getConstantPool(), 0, 2042 MVT::f32, false, Alignment)); 2043 } 2044 2045 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg); 2046} 2047 2048/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 2049/// *INT_TO_FP operation of the specified operand when the target requests that 2050/// we promote it. At this point, we know that the result and operand types are 2051/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 2052/// operation that takes a larger input. 2053SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, 2054 EVT DestVT, 2055 bool isSigned, 2056 DebugLoc dl) { 2057 // First step, figure out the appropriate *INT_TO_FP operation to use. 2058 EVT NewInTy = LegalOp.getValueType(); 2059 2060 unsigned OpToUse = 0; 2061 2062 // Scan for the appropriate larger type to use. 2063 while (1) { 2064 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1); 2065 assert(NewInTy.isInteger() && "Ran out of possibilities!"); 2066 2067 // If the target supports SINT_TO_FP of this type, use it. 2068 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) { 2069 OpToUse = ISD::SINT_TO_FP; 2070 break; 2071 } 2072 if (isSigned) continue; 2073 2074 // If the target supports UINT_TO_FP of this type, use it. 2075 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) { 2076 OpToUse = ISD::UINT_TO_FP; 2077 break; 2078 } 2079 2080 // Otherwise, try a larger type. 2081 } 2082 2083 // Okay, we found the operation and type to use. Zero extend our input to the 2084 // desired type then run the operation on it. 2085 return DAG.getNode(OpToUse, dl, DestVT, 2086 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 2087 dl, NewInTy, LegalOp)); 2088} 2089 2090/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 2091/// FP_TO_*INT operation of the specified operand when the target requests that 2092/// we promote it. At this point, we know that the result and operand types are 2093/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 2094/// operation that returns a larger result. 2095SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, 2096 EVT DestVT, 2097 bool isSigned, 2098 DebugLoc dl) { 2099 // First step, figure out the appropriate FP_TO*INT operation to use. 2100 EVT NewOutTy = DestVT; 2101 2102 unsigned OpToUse = 0; 2103 2104 // Scan for the appropriate larger type to use. 2105 while (1) { 2106 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1); 2107 assert(NewOutTy.isInteger() && "Ran out of possibilities!"); 2108 2109 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) { 2110 OpToUse = ISD::FP_TO_SINT; 2111 break; 2112 } 2113 2114 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) { 2115 OpToUse = ISD::FP_TO_UINT; 2116 break; 2117 } 2118 2119 // Otherwise, try a larger type. 2120 } 2121 2122 2123 // Okay, we found the operation and type to use. 2124 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp); 2125 2126 // Truncate the result of the extended FP_TO_*INT operation to the desired 2127 // size. 2128 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation); 2129} 2130 2131/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 2132/// 2133SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) { 2134 EVT VT = Op.getValueType(); 2135 EVT SHVT = TLI.getShiftAmountTy(); 2136 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 2137 switch (VT.getSimpleVT().SimpleTy) { 2138 default: llvm_unreachable("Unhandled Expand type in BSWAP!"); 2139 case MVT::i16: 2140 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2141 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2142 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 2143 case MVT::i32: 2144 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2145 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2146 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2147 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2148 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 2149 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 2150 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2151 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2152 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2153 case MVT::i64: 2154 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2155 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2156 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2157 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2158 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2159 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2160 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2161 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2162 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 2163 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 2164 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 2165 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 2166 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 2167 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 2168 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7); 2169 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5); 2170 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2171 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2172 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6); 2173 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2174 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4); 2175 } 2176} 2177 2178/// ExpandBitCount - Expand the specified bitcount instruction into operations. 2179/// 2180SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op, 2181 DebugLoc dl) { 2182 switch (Opc) { 2183 default: llvm_unreachable("Cannot expand this yet!"); 2184 case ISD::CTPOP: { 2185 static const uint64_t mask[6] = { 2186 0x5555555555555555ULL, 0x3333333333333333ULL, 2187 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 2188 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 2189 }; 2190 EVT VT = Op.getValueType(); 2191 EVT ShVT = TLI.getShiftAmountTy(); 2192 unsigned len = VT.getSizeInBits(); 2193 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2194 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 2195 unsigned EltSize = VT.isVector() ? 2196 VT.getVectorElementType().getSizeInBits() : len; 2197 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT); 2198 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2199 Op = DAG.getNode(ISD::ADD, dl, VT, 2200 DAG.getNode(ISD::AND, dl, VT, Op, Tmp2), 2201 DAG.getNode(ISD::AND, dl, VT, 2202 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3), 2203 Tmp2)); 2204 } 2205 return Op; 2206 } 2207 case ISD::CTLZ: { 2208 // for now, we do this: 2209 // x = x | (x >> 1); 2210 // x = x | (x >> 2); 2211 // ... 2212 // x = x | (x >>16); 2213 // x = x | (x >>32); // for 64-bit input 2214 // return popcount(~x); 2215 // 2216 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 2217 EVT VT = Op.getValueType(); 2218 EVT ShVT = TLI.getShiftAmountTy(); 2219 unsigned len = VT.getSizeInBits(); 2220 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2221 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2222 Op = DAG.getNode(ISD::OR, dl, VT, Op, 2223 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3)); 2224 } 2225 Op = DAG.getNOT(dl, Op, VT); 2226 return DAG.getNode(ISD::CTPOP, dl, VT, Op); 2227 } 2228 case ISD::CTTZ: { 2229 // for now, we use: { return popcount(~x & (x - 1)); } 2230 // unless the target has ctlz but not ctpop, in which case we use: 2231 // { return 32 - nlz(~x & (x-1)); } 2232 // see also http://www.hackersdelight.org/HDcode/ntz.cc 2233 EVT VT = Op.getValueType(); 2234 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT, 2235 DAG.getNOT(dl, Op, VT), 2236 DAG.getNode(ISD::SUB, dl, VT, Op, 2237 DAG.getConstant(1, VT))); 2238 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 2239 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) && 2240 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) 2241 return DAG.getNode(ISD::SUB, dl, VT, 2242 DAG.getConstant(VT.getSizeInBits(), VT), 2243 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3)); 2244 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3); 2245 } 2246 } 2247} 2248 2249void SelectionDAGLegalize::ExpandNode(SDNode *Node, 2250 SmallVectorImpl<SDValue> &Results) { 2251 DebugLoc dl = Node->getDebugLoc(); 2252 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 2253 switch (Node->getOpcode()) { 2254 case ISD::CTPOP: 2255 case ISD::CTLZ: 2256 case ISD::CTTZ: 2257 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl); 2258 Results.push_back(Tmp1); 2259 break; 2260 case ISD::BSWAP: 2261 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl)); 2262 break; 2263 case ISD::FRAMEADDR: 2264 case ISD::RETURNADDR: 2265 case ISD::FRAME_TO_ARGS_OFFSET: 2266 Results.push_back(DAG.getConstant(0, Node->getValueType(0))); 2267 break; 2268 case ISD::FLT_ROUNDS_: 2269 Results.push_back(DAG.getConstant(1, Node->getValueType(0))); 2270 break; 2271 case ISD::EH_RETURN: 2272 case ISD::DBG_LABEL: 2273 case ISD::EH_LABEL: 2274 case ISD::PREFETCH: 2275 case ISD::MEMBARRIER: 2276 case ISD::VAEND: 2277 Results.push_back(Node->getOperand(0)); 2278 break; 2279 case ISD::DBG_STOPPOINT: 2280 Results.push_back(ExpandDBG_STOPPOINT(Node)); 2281 break; 2282 case ISD::DYNAMIC_STACKALLOC: 2283 ExpandDYNAMIC_STACKALLOC(Node, Results); 2284 break; 2285 case ISD::MERGE_VALUES: 2286 for (unsigned i = 0; i < Node->getNumValues(); i++) 2287 Results.push_back(Node->getOperand(i)); 2288 break; 2289 case ISD::UNDEF: { 2290 EVT VT = Node->getValueType(0); 2291 if (VT.isInteger()) 2292 Results.push_back(DAG.getConstant(0, VT)); 2293 else if (VT.isFloatingPoint()) 2294 Results.push_back(DAG.getConstantFP(0, VT)); 2295 else 2296 llvm_unreachable("Unknown value type!"); 2297 break; 2298 } 2299 case ISD::TRAP: { 2300 // If this operation is not supported, lower it to 'abort()' call 2301 TargetLowering::ArgListTy Args; 2302 std::pair<SDValue, SDValue> CallResult = 2303 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()), 2304 false, false, false, false, 0, CallingConv::C, false, 2305 /*isReturnValueUsed=*/true, 2306 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 2307 Args, DAG, dl); 2308 Results.push_back(CallResult.second); 2309 break; 2310 } 2311 case ISD::FP_ROUND: 2312 case ISD::BIT_CONVERT: 2313 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 2314 Node->getValueType(0), dl); 2315 Results.push_back(Tmp1); 2316 break; 2317 case ISD::FP_EXTEND: 2318 Tmp1 = EmitStackConvert(Node->getOperand(0), 2319 Node->getOperand(0).getValueType(), 2320 Node->getValueType(0), dl); 2321 Results.push_back(Tmp1); 2322 break; 2323 case ISD::SIGN_EXTEND_INREG: { 2324 // NOTE: we could fall back on load/store here too for targets without 2325 // SAR. However, it is doubtful that any exist. 2326 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2327 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() - 2328 ExtraVT.getSizeInBits(); 2329 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 2330 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0), 2331 Node->getOperand(0), ShiftCst); 2332 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst); 2333 Results.push_back(Tmp1); 2334 break; 2335 } 2336 case ISD::FP_ROUND_INREG: { 2337 // The only way we can lower this is to turn it into a TRUNCSTORE, 2338 // EXTLOAD pair, targetting a temporary location (a stack slot). 2339 2340 // NOTE: there is a choice here between constantly creating new stack 2341 // slots and always reusing the same one. We currently always create 2342 // new ones, as reuse may inhibit scheduling. 2343 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2344 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT, 2345 Node->getValueType(0), dl); 2346 Results.push_back(Tmp1); 2347 break; 2348 } 2349 case ISD::SINT_TO_FP: 2350 case ISD::UINT_TO_FP: 2351 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP, 2352 Node->getOperand(0), Node->getValueType(0), dl); 2353 Results.push_back(Tmp1); 2354 break; 2355 case ISD::FP_TO_UINT: { 2356 SDValue True, False; 2357 EVT VT = Node->getOperand(0).getValueType(); 2358 EVT NVT = Node->getValueType(0); 2359 const uint64_t zero[] = {0, 0}; 2360 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero)); 2361 APInt x = APInt::getSignBit(NVT.getSizeInBits()); 2362 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); 2363 Tmp1 = DAG.getConstantFP(apf, VT); 2364 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), 2365 Node->getOperand(0), 2366 Tmp1, ISD::SETLT); 2367 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0)); 2368 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, 2369 DAG.getNode(ISD::FSUB, dl, VT, 2370 Node->getOperand(0), Tmp1)); 2371 False = DAG.getNode(ISD::XOR, dl, NVT, False, 2372 DAG.getConstant(x, NVT)); 2373 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False); 2374 Results.push_back(Tmp1); 2375 break; 2376 } 2377 case ISD::VAARG: { 2378 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 2379 EVT VT = Node->getValueType(0); 2380 Tmp1 = Node->getOperand(0); 2381 Tmp2 = Node->getOperand(1); 2382 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0); 2383 // Increment the pointer, VAList, to the next vaarg 2384 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, 2385 DAG.getConstant(TLI.getTargetData()-> 2386 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())), 2387 TLI.getPointerTy())); 2388 // Store the incremented VAList to the legalized pointer 2389 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0); 2390 // Load the actual argument out of the pointer VAList 2391 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0)); 2392 Results.push_back(Results[0].getValue(1)); 2393 break; 2394 } 2395 case ISD::VACOPY: { 2396 // This defaults to loading a pointer from the input and storing it to the 2397 // output, returning the chain. 2398 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 2399 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 2400 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0), 2401 Node->getOperand(2), VS, 0); 2402 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), VD, 0); 2403 Results.push_back(Tmp1); 2404 break; 2405 } 2406 case ISD::EXTRACT_VECTOR_ELT: 2407 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1) 2408 // This must be an access of the only element. Return it. 2409 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), 2410 Node->getOperand(0)); 2411 else 2412 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0)); 2413 Results.push_back(Tmp1); 2414 break; 2415 case ISD::EXTRACT_SUBVECTOR: 2416 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0))); 2417 break; 2418 case ISD::CONCAT_VECTORS: { 2419 Results.push_back(ExpandVectorBuildThroughStack(Node)); 2420 break; 2421 } 2422 case ISD::SCALAR_TO_VECTOR: 2423 Results.push_back(ExpandSCALAR_TO_VECTOR(Node)); 2424 break; 2425 case ISD::INSERT_VECTOR_ELT: 2426 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0), 2427 Node->getOperand(1), 2428 Node->getOperand(2), dl)); 2429 break; 2430 case ISD::VECTOR_SHUFFLE: { 2431 SmallVector<int, 8> Mask; 2432 cast<ShuffleVectorSDNode>(Node)->getMask(Mask); 2433 2434 EVT VT = Node->getValueType(0); 2435 EVT EltVT = VT.getVectorElementType(); 2436 unsigned NumElems = VT.getVectorNumElements(); 2437 SmallVector<SDValue, 8> Ops; 2438 for (unsigned i = 0; i != NumElems; ++i) { 2439 if (Mask[i] < 0) { 2440 Ops.push_back(DAG.getUNDEF(EltVT)); 2441 continue; 2442 } 2443 unsigned Idx = Mask[i]; 2444 if (Idx < NumElems) 2445 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 2446 Node->getOperand(0), 2447 DAG.getIntPtrConstant(Idx))); 2448 else 2449 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 2450 Node->getOperand(1), 2451 DAG.getIntPtrConstant(Idx - NumElems))); 2452 } 2453 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size()); 2454 Results.push_back(Tmp1); 2455 break; 2456 } 2457 case ISD::EXTRACT_ELEMENT: { 2458 EVT OpTy = Node->getOperand(0).getValueType(); 2459 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { 2460 // 1 -> Hi 2461 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0), 2462 DAG.getConstant(OpTy.getSizeInBits()/2, 2463 TLI.getShiftAmountTy())); 2464 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1); 2465 } else { 2466 // 0 -> Lo 2467 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), 2468 Node->getOperand(0)); 2469 } 2470 Results.push_back(Tmp1); 2471 break; 2472 } 2473 case ISD::STACKSAVE: 2474 // Expand to CopyFromReg if the target set 2475 // StackPointerRegisterToSaveRestore. 2476 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2477 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP, 2478 Node->getValueType(0))); 2479 Results.push_back(Results[0].getValue(1)); 2480 } else { 2481 Results.push_back(DAG.getUNDEF(Node->getValueType(0))); 2482 Results.push_back(Node->getOperand(0)); 2483 } 2484 break; 2485 case ISD::STACKRESTORE: 2486 // Expand to CopyToReg if the target set 2487 // StackPointerRegisterToSaveRestore. 2488 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2489 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP, 2490 Node->getOperand(1))); 2491 } else { 2492 Results.push_back(Node->getOperand(0)); 2493 } 2494 break; 2495 case ISD::FCOPYSIGN: 2496 Results.push_back(ExpandFCOPYSIGN(Node)); 2497 break; 2498 case ISD::FNEG: 2499 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 2500 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 2501 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1, 2502 Node->getOperand(0)); 2503 Results.push_back(Tmp1); 2504 break; 2505 case ISD::FABS: { 2506 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 2507 EVT VT = Node->getValueType(0); 2508 Tmp1 = Node->getOperand(0); 2509 Tmp2 = DAG.getConstantFP(0.0, VT); 2510 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), 2511 Tmp1, Tmp2, ISD::SETUGT); 2512 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1); 2513 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3); 2514 Results.push_back(Tmp1); 2515 break; 2516 } 2517 case ISD::FSQRT: 2518 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 2519 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128)); 2520 break; 2521 case ISD::FSIN: 2522 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64, 2523 RTLIB::SIN_F80, RTLIB::SIN_PPCF128)); 2524 break; 2525 case ISD::FCOS: 2526 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64, 2527 RTLIB::COS_F80, RTLIB::COS_PPCF128)); 2528 break; 2529 case ISD::FLOG: 2530 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64, 2531 RTLIB::LOG_F80, RTLIB::LOG_PPCF128)); 2532 break; 2533 case ISD::FLOG2: 2534 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64, 2535 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128)); 2536 break; 2537 case ISD::FLOG10: 2538 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64, 2539 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128)); 2540 break; 2541 case ISD::FEXP: 2542 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64, 2543 RTLIB::EXP_F80, RTLIB::EXP_PPCF128)); 2544 break; 2545 case ISD::FEXP2: 2546 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64, 2547 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128)); 2548 break; 2549 case ISD::FTRUNC: 2550 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64, 2551 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128)); 2552 break; 2553 case ISD::FFLOOR: 2554 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64, 2555 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128)); 2556 break; 2557 case ISD::FCEIL: 2558 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64, 2559 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128)); 2560 break; 2561 case ISD::FRINT: 2562 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64, 2563 RTLIB::RINT_F80, RTLIB::RINT_PPCF128)); 2564 break; 2565 case ISD::FNEARBYINT: 2566 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32, 2567 RTLIB::NEARBYINT_F64, 2568 RTLIB::NEARBYINT_F80, 2569 RTLIB::NEARBYINT_PPCF128)); 2570 break; 2571 case ISD::FPOWI: 2572 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64, 2573 RTLIB::POWI_F80, RTLIB::POWI_PPCF128)); 2574 break; 2575 case ISD::FPOW: 2576 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64, 2577 RTLIB::POW_F80, RTLIB::POW_PPCF128)); 2578 break; 2579 case ISD::FDIV: 2580 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64, 2581 RTLIB::DIV_F80, RTLIB::DIV_PPCF128)); 2582 break; 2583 case ISD::FREM: 2584 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64, 2585 RTLIB::REM_F80, RTLIB::REM_PPCF128)); 2586 break; 2587 case ISD::ConstantFP: { 2588 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 2589 // Check to see if this FP immediate is already legal. 2590 // If this is a legal constant, turn it into a TargetConstantFP node. 2591 if (TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0))) 2592 Results.push_back(SDValue(Node, 0)); 2593 else 2594 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI)); 2595 break; 2596 } 2597 case ISD::EHSELECTION: { 2598 unsigned Reg = TLI.getExceptionSelectorRegister(); 2599 assert(Reg && "Can't expand to unknown register!"); 2600 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg, 2601 Node->getValueType(0))); 2602 Results.push_back(Results[0].getValue(1)); 2603 break; 2604 } 2605 case ISD::EXCEPTIONADDR: { 2606 unsigned Reg = TLI.getExceptionAddressRegister(); 2607 assert(Reg && "Can't expand to unknown register!"); 2608 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg, 2609 Node->getValueType(0))); 2610 Results.push_back(Results[0].getValue(1)); 2611 break; 2612 } 2613 case ISD::SUB: { 2614 EVT VT = Node->getValueType(0); 2615 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) && 2616 TLI.isOperationLegalOrCustom(ISD::XOR, VT) && 2617 "Don't know how to expand this subtraction!"); 2618 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1), 2619 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT)); 2620 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT)); 2621 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1)); 2622 break; 2623 } 2624 case ISD::UREM: 2625 case ISD::SREM: { 2626 EVT VT = Node->getValueType(0); 2627 SDVTList VTs = DAG.getVTList(VT, VT); 2628 bool isSigned = Node->getOpcode() == ISD::SREM; 2629 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV; 2630 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 2631 Tmp2 = Node->getOperand(0); 2632 Tmp3 = Node->getOperand(1); 2633 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) { 2634 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1); 2635 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) { 2636 // X % Y -> X-X/Y*Y 2637 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3); 2638 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3); 2639 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1); 2640 } else if (isSigned) { 2641 Tmp1 = ExpandIntLibCall(Node, true, 2642 RTLIB::SREM_I8, 2643 RTLIB::SREM_I16, RTLIB::SREM_I32, 2644 RTLIB::SREM_I64, RTLIB::SREM_I128); 2645 } else { 2646 Tmp1 = ExpandIntLibCall(Node, false, 2647 RTLIB::UREM_I8, 2648 RTLIB::UREM_I16, RTLIB::UREM_I32, 2649 RTLIB::UREM_I64, RTLIB::UREM_I128); 2650 } 2651 Results.push_back(Tmp1); 2652 break; 2653 } 2654 case ISD::UDIV: 2655 case ISD::SDIV: { 2656 bool isSigned = Node->getOpcode() == ISD::SDIV; 2657 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 2658 EVT VT = Node->getValueType(0); 2659 SDVTList VTs = DAG.getVTList(VT, VT); 2660 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) 2661 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0), 2662 Node->getOperand(1)); 2663 else if (isSigned) 2664 Tmp1 = ExpandIntLibCall(Node, true, 2665 RTLIB::SDIV_I8, 2666 RTLIB::SDIV_I16, RTLIB::SDIV_I32, 2667 RTLIB::SDIV_I64, RTLIB::SDIV_I128); 2668 else 2669 Tmp1 = ExpandIntLibCall(Node, false, 2670 RTLIB::UDIV_I8, 2671 RTLIB::UDIV_I16, RTLIB::UDIV_I32, 2672 RTLIB::UDIV_I64, RTLIB::UDIV_I128); 2673 Results.push_back(Tmp1); 2674 break; 2675 } 2676 case ISD::MULHU: 2677 case ISD::MULHS: { 2678 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : 2679 ISD::SMUL_LOHI; 2680 EVT VT = Node->getValueType(0); 2681 SDVTList VTs = DAG.getVTList(VT, VT); 2682 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) && 2683 "If this wasn't legal, it shouldn't have been created!"); 2684 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0), 2685 Node->getOperand(1)); 2686 Results.push_back(Tmp1.getValue(1)); 2687 break; 2688 } 2689 case ISD::MUL: { 2690 EVT VT = Node->getValueType(0); 2691 SDVTList VTs = DAG.getVTList(VT, VT); 2692 // See if multiply or divide can be lowered using two-result operations. 2693 // We just need the low half of the multiply; try both the signed 2694 // and unsigned forms. If the target supports both SMUL_LOHI and 2695 // UMUL_LOHI, form a preference by checking which forms of plain 2696 // MULH it supports. 2697 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT); 2698 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT); 2699 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT); 2700 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT); 2701 unsigned OpToUse = 0; 2702 if (HasSMUL_LOHI && !HasMULHS) { 2703 OpToUse = ISD::SMUL_LOHI; 2704 } else if (HasUMUL_LOHI && !HasMULHU) { 2705 OpToUse = ISD::UMUL_LOHI; 2706 } else if (HasSMUL_LOHI) { 2707 OpToUse = ISD::SMUL_LOHI; 2708 } else if (HasUMUL_LOHI) { 2709 OpToUse = ISD::UMUL_LOHI; 2710 } 2711 if (OpToUse) { 2712 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0), 2713 Node->getOperand(1))); 2714 break; 2715 } 2716 Tmp1 = ExpandIntLibCall(Node, false, 2717 RTLIB::MUL_I8, 2718 RTLIB::MUL_I16, RTLIB::MUL_I32, 2719 RTLIB::MUL_I64, RTLIB::MUL_I128); 2720 Results.push_back(Tmp1); 2721 break; 2722 } 2723 case ISD::SADDO: 2724 case ISD::SSUBO: { 2725 SDValue LHS = Node->getOperand(0); 2726 SDValue RHS = Node->getOperand(1); 2727 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ? 2728 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 2729 LHS, RHS); 2730 Results.push_back(Sum); 2731 EVT OType = Node->getValueType(1); 2732 2733 SDValue Zero = DAG.getConstant(0, LHS.getValueType()); 2734 2735 // LHSSign -> LHS >= 0 2736 // RHSSign -> RHS >= 0 2737 // SumSign -> Sum >= 0 2738 // 2739 // Add: 2740 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign) 2741 // Sub: 2742 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign) 2743 // 2744 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); 2745 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); 2746 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign, 2747 Node->getOpcode() == ISD::SADDO ? 2748 ISD::SETEQ : ISD::SETNE); 2749 2750 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE); 2751 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); 2752 2753 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE); 2754 Results.push_back(Cmp); 2755 break; 2756 } 2757 case ISD::UADDO: 2758 case ISD::USUBO: { 2759 SDValue LHS = Node->getOperand(0); 2760 SDValue RHS = Node->getOperand(1); 2761 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ? 2762 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 2763 LHS, RHS); 2764 Results.push_back(Sum); 2765 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS, 2766 Node->getOpcode () == ISD::UADDO ? 2767 ISD::SETULT : ISD::SETUGT)); 2768 break; 2769 } 2770 case ISD::UMULO: 2771 case ISD::SMULO: { 2772 EVT VT = Node->getValueType(0); 2773 SDValue LHS = Node->getOperand(0); 2774 SDValue RHS = Node->getOperand(1); 2775 SDValue BottomHalf; 2776 SDValue TopHalf; 2777 static unsigned Ops[2][3] = 2778 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND }, 2779 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }}; 2780 bool isSigned = Node->getOpcode() == ISD::SMULO; 2781 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) { 2782 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS); 2783 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS); 2784 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) { 2785 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS, 2786 RHS); 2787 TopHalf = BottomHalf.getValue(1); 2788 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2))) { 2789 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2); 2790 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS); 2791 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS); 2792 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS); 2793 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 2794 DAG.getIntPtrConstant(0)); 2795 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 2796 DAG.getIntPtrConstant(1)); 2797 } else { 2798 // FIXME: We should be able to fall back to a libcall with an illegal 2799 // type in some cases cases. 2800 // Also, we can fall back to a division in some cases, but that's a big 2801 // performance hit in the general case. 2802 llvm_unreachable("Don't know how to expand this operation yet!"); 2803 } 2804 if (isSigned) { 2805 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, TLI.getShiftAmountTy()); 2806 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1); 2807 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1, 2808 ISD::SETNE); 2809 } else { 2810 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, 2811 DAG.getConstant(0, VT), ISD::SETNE); 2812 } 2813 Results.push_back(BottomHalf); 2814 Results.push_back(TopHalf); 2815 break; 2816 } 2817 case ISD::BUILD_PAIR: { 2818 EVT PairTy = Node->getValueType(0); 2819 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0)); 2820 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1)); 2821 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2, 2822 DAG.getConstant(PairTy.getSizeInBits()/2, 2823 TLI.getShiftAmountTy())); 2824 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2)); 2825 break; 2826 } 2827 case ISD::SELECT: 2828 Tmp1 = Node->getOperand(0); 2829 Tmp2 = Node->getOperand(1); 2830 Tmp3 = Node->getOperand(2); 2831 if (Tmp1.getOpcode() == ISD::SETCC) { 2832 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1), 2833 Tmp2, Tmp3, 2834 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2835 } else { 2836 Tmp1 = DAG.getSelectCC(dl, Tmp1, 2837 DAG.getConstant(0, Tmp1.getValueType()), 2838 Tmp2, Tmp3, ISD::SETNE); 2839 } 2840 Results.push_back(Tmp1); 2841 break; 2842 case ISD::BR_JT: { 2843 SDValue Chain = Node->getOperand(0); 2844 SDValue Table = Node->getOperand(1); 2845 SDValue Index = Node->getOperand(2); 2846 2847 EVT PTy = TLI.getPointerTy(); 2848 MachineFunction &MF = DAG.getMachineFunction(); 2849 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); 2850 Index= DAG.getNode(ISD::MUL, dl, PTy, 2851 Index, DAG.getConstant(EntrySize, PTy)); 2852 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); 2853 2854 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8); 2855 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr, 2856 PseudoSourceValue::getJumpTable(), 0, MemVT); 2857 Addr = LD; 2858 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2859 // For PIC, the sequence is: 2860 // BRIND(load(Jumptable + index) + RelocBase) 2861 // RelocBase can be JumpTable, GOT or some sort of global base. 2862 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, 2863 TLI.getPICJumpTableRelocBase(Table, DAG)); 2864 } 2865 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr); 2866 Results.push_back(Tmp1); 2867 break; 2868 } 2869 case ISD::BRCOND: 2870 // Expand brcond's setcc into its constituent parts and create a BR_CC 2871 // Node. 2872 Tmp1 = Node->getOperand(0); 2873 Tmp2 = Node->getOperand(1); 2874 if (Tmp2.getOpcode() == ISD::SETCC) { 2875 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, 2876 Tmp1, Tmp2.getOperand(2), 2877 Tmp2.getOperand(0), Tmp2.getOperand(1), 2878 Node->getOperand(2)); 2879 } else { 2880 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1, 2881 DAG.getCondCode(ISD::SETNE), Tmp2, 2882 DAG.getConstant(0, Tmp2.getValueType()), 2883 Node->getOperand(2)); 2884 } 2885 Results.push_back(Tmp1); 2886 break; 2887 case ISD::SETCC: { 2888 Tmp1 = Node->getOperand(0); 2889 Tmp2 = Node->getOperand(1); 2890 Tmp3 = Node->getOperand(2); 2891 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl); 2892 2893 // If we expanded the SETCC into an AND/OR, return the new node 2894 if (Tmp2.getNode() == 0) { 2895 Results.push_back(Tmp1); 2896 break; 2897 } 2898 2899 // Otherwise, SETCC for the given comparison type must be completely 2900 // illegal; expand it into a SELECT_CC. 2901 EVT VT = Node->getValueType(0); 2902 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2, 2903 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3); 2904 Results.push_back(Tmp1); 2905 break; 2906 } 2907 case ISD::SELECT_CC: { 2908 Tmp1 = Node->getOperand(0); // LHS 2909 Tmp2 = Node->getOperand(1); // RHS 2910 Tmp3 = Node->getOperand(2); // True 2911 Tmp4 = Node->getOperand(3); // False 2912 SDValue CC = Node->getOperand(4); 2913 2914 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()), 2915 Tmp1, Tmp2, CC, dl); 2916 2917 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!"); 2918 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 2919 CC = DAG.getCondCode(ISD::SETNE); 2920 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2, 2921 Tmp3, Tmp4, CC); 2922 Results.push_back(Tmp1); 2923 break; 2924 } 2925 case ISD::BR_CC: { 2926 Tmp1 = Node->getOperand(0); // Chain 2927 Tmp2 = Node->getOperand(2); // LHS 2928 Tmp3 = Node->getOperand(3); // RHS 2929 Tmp4 = Node->getOperand(1); // CC 2930 2931 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()), 2932 Tmp2, Tmp3, Tmp4, dl); 2933 LastCALLSEQ_END = DAG.getEntryNode(); 2934 2935 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!"); 2936 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 2937 Tmp4 = DAG.getCondCode(ISD::SETNE); 2938 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2, 2939 Tmp3, Node->getOperand(4)); 2940 Results.push_back(Tmp1); 2941 break; 2942 } 2943 case ISD::GLOBAL_OFFSET_TABLE: 2944 case ISD::GlobalAddress: 2945 case ISD::GlobalTLSAddress: 2946 case ISD::ExternalSymbol: 2947 case ISD::ConstantPool: 2948 case ISD::JumpTable: 2949 case ISD::INTRINSIC_W_CHAIN: 2950 case ISD::INTRINSIC_WO_CHAIN: 2951 case ISD::INTRINSIC_VOID: 2952 // FIXME: Custom lowering for these operations shouldn't return null! 2953 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 2954 Results.push_back(SDValue(Node, i)); 2955 break; 2956 } 2957} 2958void SelectionDAGLegalize::PromoteNode(SDNode *Node, 2959 SmallVectorImpl<SDValue> &Results) { 2960 EVT OVT = Node->getValueType(0); 2961 if (Node->getOpcode() == ISD::UINT_TO_FP || 2962 Node->getOpcode() == ISD::SINT_TO_FP || 2963 Node->getOpcode() == ISD::SETCC) { 2964 OVT = Node->getOperand(0).getValueType(); 2965 } 2966 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2967 DebugLoc dl = Node->getDebugLoc(); 2968 SDValue Tmp1, Tmp2, Tmp3; 2969 switch (Node->getOpcode()) { 2970 case ISD::CTTZ: 2971 case ISD::CTLZ: 2972 case ISD::CTPOP: 2973 // Zero extend the argument. 2974 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 2975 // Perform the larger operation. 2976 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); 2977 if (Node->getOpcode() == ISD::CTTZ) { 2978 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 2979 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), 2980 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT), 2981 ISD::SETEQ); 2982 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, 2983 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1); 2984 } else if (Node->getOpcode() == ISD::CTLZ) { 2985 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 2986 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1, 2987 DAG.getConstant(NVT.getSizeInBits() - 2988 OVT.getSizeInBits(), NVT)); 2989 } 2990 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1)); 2991 break; 2992 case ISD::BSWAP: { 2993 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 2994 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1); 2995 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1); 2996 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, 2997 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 2998 Results.push_back(Tmp1); 2999 break; 3000 } 3001 case ISD::FP_TO_UINT: 3002 case ISD::FP_TO_SINT: 3003 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0), 3004 Node->getOpcode() == ISD::FP_TO_SINT, dl); 3005 Results.push_back(Tmp1); 3006 break; 3007 case ISD::UINT_TO_FP: 3008 case ISD::SINT_TO_FP: 3009 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0), 3010 Node->getOpcode() == ISD::SINT_TO_FP, dl); 3011 Results.push_back(Tmp1); 3012 break; 3013 case ISD::AND: 3014 case ISD::OR: 3015 case ISD::XOR: { 3016 unsigned ExtOp, TruncOp; 3017 if (OVT.isVector()) { 3018 ExtOp = ISD::BIT_CONVERT; 3019 TruncOp = ISD::BIT_CONVERT; 3020 } else if (OVT.isInteger()) { 3021 ExtOp = ISD::ANY_EXTEND; 3022 TruncOp = ISD::TRUNCATE; 3023 } else { 3024 llvm_report_error("Cannot promote logic operation"); 3025 } 3026 // Promote each of the values to the new type. 3027 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); 3028 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3029 // Perform the larger operation, then convert back 3030 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 3031 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1)); 3032 break; 3033 } 3034 case ISD::SELECT: { 3035 unsigned ExtOp, TruncOp; 3036 if (Node->getValueType(0).isVector()) { 3037 ExtOp = ISD::BIT_CONVERT; 3038 TruncOp = ISD::BIT_CONVERT; 3039 } else if (Node->getValueType(0).isInteger()) { 3040 ExtOp = ISD::ANY_EXTEND; 3041 TruncOp = ISD::TRUNCATE; 3042 } else { 3043 ExtOp = ISD::FP_EXTEND; 3044 TruncOp = ISD::FP_ROUND; 3045 } 3046 Tmp1 = Node->getOperand(0); 3047 // Promote each of the values to the new type. 3048 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3049 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2)); 3050 // Perform the larger operation, then round down. 3051 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3); 3052 if (TruncOp != ISD::FP_ROUND) 3053 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1); 3054 else 3055 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1, 3056 DAG.getIntPtrConstant(0)); 3057 Results.push_back(Tmp1); 3058 break; 3059 } 3060 case ISD::VECTOR_SHUFFLE: { 3061 SmallVector<int, 8> Mask; 3062 cast<ShuffleVectorSDNode>(Node)->getMask(Mask); 3063 3064 // Cast the two input vectors. 3065 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0)); 3066 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1)); 3067 3068 // Convert the shuffle mask to the right # elements. 3069 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask); 3070 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1); 3071 Results.push_back(Tmp1); 3072 break; 3073 } 3074 case ISD::SETCC: { 3075 unsigned ExtOp = ISD::FP_EXTEND; 3076 if (NVT.isInteger()) { 3077 ISD::CondCode CCCode = 3078 cast<CondCodeSDNode>(Node->getOperand(2))->get(); 3079 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 3080 } 3081 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); 3082 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3083 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), 3084 Tmp1, Tmp2, Node->getOperand(2))); 3085 break; 3086 } 3087 } 3088} 3089 3090// SelectionDAG::Legalize - This is the entry point for the file. 3091// 3092void SelectionDAG::Legalize(bool TypesNeedLegalizing, 3093 CodeGenOpt::Level OptLevel) { 3094 /// run - This is the main entry point to this class. 3095 /// 3096 SelectionDAGLegalize(*this, OptLevel).LegalizeDAG(); 3097} 3098 3099