1198090Srdivacky//===---- InstrEmitter.h - Emit MachineInstrs for the SelectionDAG class ---==// 2198090Srdivacky// 3198090Srdivacky// The LLVM Compiler Infrastructure 4198090Srdivacky// 5198090Srdivacky// This file is distributed under the University of Illinois Open Source 6198090Srdivacky// License. See LICENSE.TXT for details. 7198090Srdivacky// 8198090Srdivacky//===----------------------------------------------------------------------===// 9198090Srdivacky// 10198090Srdivacky// This declares the Emit routines for the SelectionDAG class, which creates 11198090Srdivacky// MachineInstrs based on the decisions of the SelectionDAG instruction 12198090Srdivacky// selection. 13198090Srdivacky// 14198090Srdivacky//===----------------------------------------------------------------------===// 15198090Srdivacky 16198090Srdivacky#ifndef INSTREMITTER_H 17198090Srdivacky#define INSTREMITTER_H 18198090Srdivacky 19249423Sdim#include "llvm/ADT/DenseMap.h" 20249423Sdim#include "llvm/CodeGen/MachineBasicBlock.h" 21198090Srdivacky#include "llvm/CodeGen/SelectionDAG.h" 22198090Srdivacky 23198090Srdivackynamespace llvm { 24198090Srdivacky 25249423Sdimclass MachineInstrBuilder; 26224145Sdimclass MCInstrDesc; 27204792Srdivackyclass SDDbgValue; 28198090Srdivacky 29198090Srdivackyclass InstrEmitter { 30198090Srdivacky MachineFunction *MF; 31198090Srdivacky MachineRegisterInfo *MRI; 32198090Srdivacky const TargetMachine *TM; 33198090Srdivacky const TargetInstrInfo *TII; 34198090Srdivacky const TargetRegisterInfo *TRI; 35198090Srdivacky const TargetLowering *TLI; 36198090Srdivacky 37198090Srdivacky MachineBasicBlock *MBB; 38198090Srdivacky MachineBasicBlock::iterator InsertPos; 39198090Srdivacky 40198090Srdivacky /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an 41198090Srdivacky /// implicit physical register output. 42198090Srdivacky void EmitCopyFromReg(SDNode *Node, unsigned ResNo, 43198090Srdivacky bool IsClone, bool IsCloned, 44198090Srdivacky unsigned SrcReg, 45198090Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap); 46198090Srdivacky 47198090Srdivacky /// getDstOfCopyToRegUse - If the only use of the specified result number of 48198090Srdivacky /// node is a CopyToReg, return its destination register. Return 0 otherwise. 49198090Srdivacky unsigned getDstOfOnlyCopyToRegUse(SDNode *Node, 50198090Srdivacky unsigned ResNo) const; 51198090Srdivacky 52249423Sdim void CreateVirtualRegisters(SDNode *Node, 53249423Sdim MachineInstrBuilder &MIB, 54224145Sdim const MCInstrDesc &II, 55198090Srdivacky bool IsClone, bool IsCloned, 56198090Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap); 57198090Srdivacky 58198090Srdivacky /// getVR - Return the virtual register corresponding to the specified result 59198090Srdivacky /// of the specified node. 60198090Srdivacky unsigned getVR(SDValue Op, 61198090Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap); 62198090Srdivacky 63198090Srdivacky /// AddRegisterOperand - Add the specified register as an operand to the 64198090Srdivacky /// specified machine instr. Insert register copies if the register is 65198090Srdivacky /// not in the required register class. 66249423Sdim void AddRegisterOperand(MachineInstrBuilder &MIB, 67249423Sdim SDValue Op, 68198090Srdivacky unsigned IIOpNum, 69224145Sdim const MCInstrDesc *II, 70206083Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap, 71208599Srdivacky bool IsDebug, bool IsClone, bool IsCloned); 72198090Srdivacky 73198090Srdivacky /// AddOperand - Add the specified operand to the specified machine instr. II 74198090Srdivacky /// specifies the instruction information for the node, and IIOpNum is the 75198090Srdivacky /// operand number (in the II) that we are adding. IIOpNum and II are used for 76198090Srdivacky /// assertions only. 77249423Sdim void AddOperand(MachineInstrBuilder &MIB, 78249423Sdim SDValue Op, 79198090Srdivacky unsigned IIOpNum, 80224145Sdim const MCInstrDesc *II, 81206083Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap, 82208599Srdivacky bool IsDebug, bool IsClone, bool IsCloned); 83198090Srdivacky 84226633Sdim /// ConstrainForSubReg - Try to constrain VReg to a register class that 85226633Sdim /// supports SubIdx sub-registers. Emit a copy if that isn't possible. 86226633Sdim /// Return the virtual register to use. 87226633Sdim unsigned ConstrainForSubReg(unsigned VReg, unsigned SubIdx, 88249423Sdim MVT VT, DebugLoc DL); 89226633Sdim 90198090Srdivacky /// EmitSubregNode - Generate machine code for subreg nodes. 91198090Srdivacky /// 92208599Srdivacky void EmitSubregNode(SDNode *Node, DenseMap<SDValue, unsigned> &VRBaseMap, 93208599Srdivacky bool IsClone, bool IsCloned); 94198090Srdivacky 95198090Srdivacky /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes. 96198090Srdivacky /// COPY_TO_REGCLASS is just a normal copy, except that the destination 97198090Srdivacky /// register is constrained to be in a particular register class. 98198090Srdivacky /// 99198090Srdivacky void EmitCopyToRegClassNode(SDNode *Node, 100198090Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap); 101198090Srdivacky 102207618Srdivacky /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes. 103207618Srdivacky /// 104208599Srdivacky void EmitRegSequence(SDNode *Node, DenseMap<SDValue, unsigned> &VRBaseMap, 105208599Srdivacky bool IsClone, bool IsCloned); 106198090Srdivackypublic: 107198090Srdivacky /// CountResults - The results of target nodes have register or immediate 108198090Srdivacky /// operands first, then an optional chain, and optional flag operands 109198090Srdivacky /// (which do not go into the machine instrs.) 110198090Srdivacky static unsigned CountResults(SDNode *Node); 111198090Srdivacky 112206083Srdivacky /// EmitDbgValue - Generate machine instruction for a dbg_value node. 113206083Srdivacky /// 114206083Srdivacky MachineInstr *EmitDbgValue(SDDbgValue *SD, 115207618Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap); 116204792Srdivacky 117199481Srdivacky /// EmitNode - Generate machine code for a node and needed dependencies. 118198090Srdivacky /// 119198090Srdivacky void EmitNode(SDNode *Node, bool IsClone, bool IsCloned, 120207618Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap) { 121206083Srdivacky if (Node->isMachineOpcode()) 122207618Srdivacky EmitMachineNode(Node, IsClone, IsCloned, VRBaseMap); 123206083Srdivacky else 124206083Srdivacky EmitSpecialNode(Node, IsClone, IsCloned, VRBaseMap); 125206083Srdivacky } 126198090Srdivacky 127198090Srdivacky /// getBlock - Return the current basic block. 128198090Srdivacky MachineBasicBlock *getBlock() { return MBB; } 129198090Srdivacky 130198090Srdivacky /// getInsertPos - Return the current insertion position. 131198090Srdivacky MachineBasicBlock::iterator getInsertPos() { return InsertPos; } 132198090Srdivacky 133198090Srdivacky /// InstrEmitter - Construct an InstrEmitter and set it to start inserting 134198090Srdivacky /// at the given position in the given block. 135198090Srdivacky InstrEmitter(MachineBasicBlock *mbb, MachineBasicBlock::iterator insertpos); 136206083Srdivacky 137206083Srdivackyprivate: 138206083Srdivacky void EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned, 139207618Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap); 140206083Srdivacky void EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned, 141206083Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap); 142198090Srdivacky}; 143198090Srdivacky 144198090Srdivacky} 145198090Srdivacky 146198090Srdivacky#endif 147