1198090Srdivacky//==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==// 2198090Srdivacky// 3198090Srdivacky// The LLVM Compiler Infrastructure 4198090Srdivacky// 5198090Srdivacky// This file is distributed under the University of Illinois Open Source 6198090Srdivacky// License. See LICENSE.TXT for details. 7198090Srdivacky// 8198090Srdivacky//===----------------------------------------------------------------------===// 9198090Srdivacky// 10198090Srdivacky// This implements the Emit routines for the SelectionDAG class, which creates 11198090Srdivacky// MachineInstrs based on the decisions of the SelectionDAG instruction 12198090Srdivacky// selection. 13198090Srdivacky// 14198090Srdivacky//===----------------------------------------------------------------------===// 15198090Srdivacky 16198090Srdivacky#define DEBUG_TYPE "instr-emitter" 17198090Srdivacky#include "InstrEmitter.h" 18205218Srdivacky#include "SDNodeDbgValue.h" 19249423Sdim#include "llvm/ADT/Statistic.h" 20198090Srdivacky#include "llvm/CodeGen/MachineConstantPool.h" 21198090Srdivacky#include "llvm/CodeGen/MachineFunction.h" 22198090Srdivacky#include "llvm/CodeGen/MachineInstrBuilder.h" 23198090Srdivacky#include "llvm/CodeGen/MachineRegisterInfo.h" 24249423Sdim#include "llvm/IR/DataLayout.h" 25198090Srdivacky#include "llvm/Support/Debug.h" 26198090Srdivacky#include "llvm/Support/ErrorHandling.h" 27198090Srdivacky#include "llvm/Support/MathExtras.h" 28249423Sdim#include "llvm/Target/TargetInstrInfo.h" 29249423Sdim#include "llvm/Target/TargetLowering.h" 30249423Sdim#include "llvm/Target/TargetMachine.h" 31198090Srdivackyusing namespace llvm; 32198090Srdivacky 33226633Sdim/// MinRCSize - Smallest register class we allow when constraining virtual 34226633Sdim/// registers. If satisfying all register class constraints would require 35226633Sdim/// using a smaller register class, emit a COPY to a new virtual register 36226633Sdim/// instead. 37226633Sdimconst unsigned MinRCSize = 4; 38226633Sdim 39198090Srdivacky/// CountResults - The results of target nodes have register or immediate 40218893Sdim/// operands first, then an optional chain, and optional glue operands (which do 41198090Srdivacky/// not go into the resulting MachineInstr). 42198090Srdivackyunsigned InstrEmitter::CountResults(SDNode *Node) { 43198090Srdivacky unsigned N = Node->getNumValues(); 44218893Sdim while (N && Node->getValueType(N - 1) == MVT::Glue) 45198090Srdivacky --N; 46198090Srdivacky if (N && Node->getValueType(N - 1) == MVT::Other) 47198090Srdivacky --N; // Skip over chain result. 48198090Srdivacky return N; 49198090Srdivacky} 50198090Srdivacky 51239462Sdim/// countOperands - The inputs to target nodes have any actual inputs first, 52218893Sdim/// followed by an optional chain operand, then an optional glue operand. 53198090Srdivacky/// Compute the number of actual operands that will go into the resulting 54198090Srdivacky/// MachineInstr. 55239462Sdim/// 56239462Sdim/// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding 57239462Sdim/// the chain and glue. These operands may be implicit on the machine instr. 58243830Sdimstatic unsigned countOperands(SDNode *Node, unsigned NumExpUses, 59243830Sdim unsigned &NumImpUses) { 60198090Srdivacky unsigned N = Node->getNumOperands(); 61218893Sdim while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue) 62198090Srdivacky --N; 63198090Srdivacky if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) 64198090Srdivacky --N; // Ignore chain if it exists. 65239462Sdim 66239462Sdim // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses. 67243830Sdim NumImpUses = N - NumExpUses; 68243830Sdim for (unsigned I = N; I > NumExpUses; --I) { 69239462Sdim if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1))) 70239462Sdim continue; 71239462Sdim if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1))) 72239462Sdim if (TargetRegisterInfo::isPhysicalRegister(RN->getReg())) 73239462Sdim continue; 74239462Sdim NumImpUses = N - I; 75239462Sdim break; 76239462Sdim } 77239462Sdim 78198090Srdivacky return N; 79198090Srdivacky} 80198090Srdivacky 81198090Srdivacky/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an 82198090Srdivacky/// implicit physical register output. 83198090Srdivackyvoid InstrEmitter:: 84198090SrdivackyEmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned, 85198090Srdivacky unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) { 86198090Srdivacky unsigned VRBase = 0; 87198090Srdivacky if (TargetRegisterInfo::isVirtualRegister(SrcReg)) { 88198090Srdivacky // Just use the input register directly! 89198090Srdivacky SDValue Op(Node, ResNo); 90198090Srdivacky if (IsClone) 91198090Srdivacky VRBaseMap.erase(Op); 92198090Srdivacky bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second; 93218893Sdim (void)isNew; // Silence compiler warning. 94198090Srdivacky assert(isNew && "Node emitted out of order - early"); 95198090Srdivacky return; 96198090Srdivacky } 97198090Srdivacky 98198090Srdivacky // If the node is only used by a CopyToReg and the dest reg is a vreg, use 99198090Srdivacky // the CopyToReg'd destination register instead of creating a new vreg. 100198090Srdivacky bool MatchReg = true; 101198090Srdivacky const TargetRegisterClass *UseRC = NULL; 102249423Sdim MVT VT = Node->getSimpleValueType(ResNo); 103224145Sdim 104224145Sdim // Stick to the preferred register classes for legal types. 105224145Sdim if (TLI->isTypeLegal(VT)) 106224145Sdim UseRC = TLI->getRegClassFor(VT); 107224145Sdim 108198090Srdivacky if (!IsClone && !IsCloned) 109198090Srdivacky for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 110198090Srdivacky UI != E; ++UI) { 111198090Srdivacky SDNode *User = *UI; 112198090Srdivacky bool Match = true; 113226633Sdim if (User->getOpcode() == ISD::CopyToReg && 114198090Srdivacky User->getOperand(2).getNode() == Node && 115198090Srdivacky User->getOperand(2).getResNo() == ResNo) { 116198090Srdivacky unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 117198090Srdivacky if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 118198090Srdivacky VRBase = DestReg; 119198090Srdivacky Match = false; 120198090Srdivacky } else if (DestReg != SrcReg) 121198090Srdivacky Match = false; 122198090Srdivacky } else { 123198090Srdivacky for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 124198090Srdivacky SDValue Op = User->getOperand(i); 125198090Srdivacky if (Op.getNode() != Node || Op.getResNo() != ResNo) 126198090Srdivacky continue; 127249423Sdim MVT VT = Node->getSimpleValueType(Op.getResNo()); 128218893Sdim if (VT == MVT::Other || VT == MVT::Glue) 129198090Srdivacky continue; 130198090Srdivacky Match = false; 131198090Srdivacky if (User->isMachineOpcode()) { 132224145Sdim const MCInstrDesc &II = TII->get(User->getMachineOpcode()); 133198090Srdivacky const TargetRegisterClass *RC = 0; 134239462Sdim if (i+II.getNumDefs() < II.getNumOperands()) { 135239462Sdim RC = TRI->getAllocatableClass( 136239462Sdim TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF)); 137239462Sdim } 138198090Srdivacky if (!UseRC) 139198090Srdivacky UseRC = RC; 140198090Srdivacky else if (RC) { 141226633Sdim const TargetRegisterClass *ComRC = 142226633Sdim TRI->getCommonSubClass(UseRC, RC); 143198090Srdivacky // If multiple uses expect disjoint register classes, we emit 144198090Srdivacky // copies in AddRegisterOperand. 145198090Srdivacky if (ComRC) 146198090Srdivacky UseRC = ComRC; 147198090Srdivacky } 148198090Srdivacky } 149198090Srdivacky } 150198090Srdivacky } 151198090Srdivacky MatchReg &= Match; 152198090Srdivacky if (VRBase) 153198090Srdivacky break; 154198090Srdivacky } 155198090Srdivacky 156198090Srdivacky const TargetRegisterClass *SrcRC = 0, *DstRC = 0; 157210299Sed SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT); 158224145Sdim 159198090Srdivacky // Figure out the register class to create for the destreg. 160198090Srdivacky if (VRBase) { 161198090Srdivacky DstRC = MRI->getRegClass(VRBase); 162198090Srdivacky } else if (UseRC) { 163198090Srdivacky assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!"); 164198090Srdivacky DstRC = UseRC; 165198090Srdivacky } else { 166198090Srdivacky DstRC = TLI->getRegClassFor(VT); 167198090Srdivacky } 168226633Sdim 169198090Srdivacky // If all uses are reading from the src physical register and copying the 170198090Srdivacky // register is either impossible or very expensive, then don't create a copy. 171198090Srdivacky if (MatchReg && SrcRC->getCopyCost() < 0) { 172198090Srdivacky VRBase = SrcReg; 173198090Srdivacky } else { 174198090Srdivacky // Create the reg, emit the copy. 175198090Srdivacky VRBase = MRI->createVirtualRegister(DstRC); 176210299Sed BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 177210299Sed VRBase).addReg(SrcReg); 178198090Srdivacky } 179198090Srdivacky 180198090Srdivacky SDValue Op(Node, ResNo); 181198090Srdivacky if (IsClone) 182198090Srdivacky VRBaseMap.erase(Op); 183198090Srdivacky bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 184218893Sdim (void)isNew; // Silence compiler warning. 185198090Srdivacky assert(isNew && "Node emitted out of order - early"); 186198090Srdivacky} 187198090Srdivacky 188198090Srdivacky/// getDstOfCopyToRegUse - If the only use of the specified result number of 189198090Srdivacky/// node is a CopyToReg, return its destination register. Return 0 otherwise. 190198090Srdivackyunsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node, 191198090Srdivacky unsigned ResNo) const { 192198090Srdivacky if (!Node->hasOneUse()) 193198090Srdivacky return 0; 194198090Srdivacky 195198090Srdivacky SDNode *User = *Node->use_begin(); 196226633Sdim if (User->getOpcode() == ISD::CopyToReg && 197198090Srdivacky User->getOperand(2).getNode() == Node && 198198090Srdivacky User->getOperand(2).getResNo() == ResNo) { 199198090Srdivacky unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 200198090Srdivacky if (TargetRegisterInfo::isVirtualRegister(Reg)) 201198090Srdivacky return Reg; 202198090Srdivacky } 203198090Srdivacky return 0; 204198090Srdivacky} 205198090Srdivacky 206249423Sdimvoid InstrEmitter::CreateVirtualRegisters(SDNode *Node, 207249423Sdim MachineInstrBuilder &MIB, 208224145Sdim const MCInstrDesc &II, 209198090Srdivacky bool IsClone, bool IsCloned, 210198090Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap) { 211203954Srdivacky assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && 212198090Srdivacky "IMPLICIT_DEF should have been handled as a special case elsewhere!"); 213198090Srdivacky 214198090Srdivacky for (unsigned i = 0; i < II.getNumDefs(); ++i) { 215198090Srdivacky // If the specific node value is only used by a CopyToReg and the dest reg 216198090Srdivacky // is a vreg in the same register class, use the CopyToReg'd destination 217198090Srdivacky // register instead of creating a new vreg. 218198090Srdivacky unsigned VRBase = 0; 219239462Sdim const TargetRegisterClass *RC = 220239462Sdim TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); 221198090Srdivacky if (II.OpInfo[i].isOptionalDef()) { 222198090Srdivacky // Optional def must be a physical register. 223198090Srdivacky unsigned NumResults = CountResults(Node); 224198090Srdivacky VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg(); 225198090Srdivacky assert(TargetRegisterInfo::isPhysicalRegister(VRBase)); 226249423Sdim MIB.addReg(VRBase, RegState::Define); 227198090Srdivacky } 228198090Srdivacky 229198090Srdivacky if (!VRBase && !IsClone && !IsCloned) 230198090Srdivacky for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 231198090Srdivacky UI != E; ++UI) { 232198090Srdivacky SDNode *User = *UI; 233226633Sdim if (User->getOpcode() == ISD::CopyToReg && 234198090Srdivacky User->getOperand(2).getNode() == Node && 235198090Srdivacky User->getOperand(2).getResNo() == i) { 236198090Srdivacky unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 237198090Srdivacky if (TargetRegisterInfo::isVirtualRegister(Reg)) { 238198090Srdivacky const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); 239198090Srdivacky if (RegRC == RC) { 240198090Srdivacky VRBase = Reg; 241249423Sdim MIB.addReg(VRBase, RegState::Define); 242198090Srdivacky break; 243198090Srdivacky } 244198090Srdivacky } 245198090Srdivacky } 246198090Srdivacky } 247198090Srdivacky 248198090Srdivacky // Create the result registers for this node and add the result regs to 249198090Srdivacky // the machine instruction. 250198090Srdivacky if (VRBase == 0) { 251198090Srdivacky assert(RC && "Isn't a register operand!"); 252198090Srdivacky VRBase = MRI->createVirtualRegister(RC); 253249423Sdim MIB.addReg(VRBase, RegState::Define); 254198090Srdivacky } 255198090Srdivacky 256198090Srdivacky SDValue Op(Node, i); 257198090Srdivacky if (IsClone) 258198090Srdivacky VRBaseMap.erase(Op); 259198090Srdivacky bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 260218893Sdim (void)isNew; // Silence compiler warning. 261198090Srdivacky assert(isNew && "Node emitted out of order - early"); 262198090Srdivacky } 263198090Srdivacky} 264198090Srdivacky 265198090Srdivacky/// getVR - Return the virtual register corresponding to the specified result 266198090Srdivacky/// of the specified node. 267198090Srdivackyunsigned InstrEmitter::getVR(SDValue Op, 268198090Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap) { 269198090Srdivacky if (Op.isMachineOpcode() && 270203954Srdivacky Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { 271198090Srdivacky // Add an IMPLICIT_DEF instruction before every use. 272198090Srdivacky unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); 273224145Sdim // IMPLICIT_DEF can produce any type of result so its MCInstrDesc 274198090Srdivacky // does not include operand register class info. 275198090Srdivacky if (!VReg) { 276249423Sdim const TargetRegisterClass *RC = 277249423Sdim TLI->getRegClassFor(Op.getSimpleValueType()); 278198090Srdivacky VReg = MRI->createVirtualRegister(RC); 279198090Srdivacky } 280210299Sed BuildMI(*MBB, InsertPos, Op.getDebugLoc(), 281203954Srdivacky TII->get(TargetOpcode::IMPLICIT_DEF), VReg); 282198090Srdivacky return VReg; 283198090Srdivacky } 284198090Srdivacky 285198090Srdivacky DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 286198090Srdivacky assert(I != VRBaseMap.end() && "Node emitted out of order - late"); 287198090Srdivacky return I->second; 288198090Srdivacky} 289198090Srdivacky 290198090Srdivacky 291198090Srdivacky/// AddRegisterOperand - Add the specified register as an operand to the 292198090Srdivacky/// specified machine instr. Insert register copies if the register is 293198090Srdivacky/// not in the required register class. 294198090Srdivackyvoid 295249423SdimInstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB, 296249423Sdim SDValue Op, 297198090Srdivacky unsigned IIOpNum, 298224145Sdim const MCInstrDesc *II, 299206083Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap, 300208599Srdivacky bool IsDebug, bool IsClone, bool IsCloned) { 301198090Srdivacky assert(Op.getValueType() != MVT::Other && 302218893Sdim Op.getValueType() != MVT::Glue && 303218893Sdim "Chain and glue operands should occur at end of operand list!"); 304198090Srdivacky // Get/emit the operand. 305198090Srdivacky unsigned VReg = getVR(Op, VRBaseMap); 306198090Srdivacky assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); 307198090Srdivacky 308249423Sdim const MCInstrDesc &MCID = MIB->getDesc(); 309224145Sdim bool isOptDef = IIOpNum < MCID.getNumOperands() && 310224145Sdim MCID.OpInfo[IIOpNum].isOptionalDef(); 311198090Srdivacky 312198090Srdivacky // If the instruction requires a register in a different class, create 313226633Sdim // a new virtual register and copy the value into it, but first attempt to 314226633Sdim // shrink VReg's register class within reason. For example, if VReg == GR32 315226633Sdim // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP. 316198090Srdivacky if (II) { 317198090Srdivacky const TargetRegisterClass *DstRC = 0; 318198090Srdivacky if (IIOpNum < II->getNumOperands()) 319239462Sdim DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF)); 320226633Sdim if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) { 321198090Srdivacky unsigned NewVReg = MRI->createVirtualRegister(DstRC); 322210299Sed BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(), 323210299Sed TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); 324198090Srdivacky VReg = NewVReg; 325198090Srdivacky } 326198090Srdivacky } 327198090Srdivacky 328207618Srdivacky // If this value has only one use, that use is a kill. This is a 329208599Srdivacky // conservative approximation. InstrEmitter does trivial coalescing 330208599Srdivacky // with CopyFromReg nodes, so don't emit kill flags for them. 331208599Srdivacky // Avoid kill flags on Schedule cloned nodes, since there will be 332208599Srdivacky // multiple uses. 333208599Srdivacky // Tied operands are never killed, so we need to check that. And that 334208599Srdivacky // means we need to determine the index of the operand. 335208599Srdivacky bool isKill = Op.hasOneUse() && 336208599Srdivacky Op.getNode()->getOpcode() != ISD::CopyFromReg && 337208599Srdivacky !IsDebug && 338208599Srdivacky !(IsClone || IsCloned); 339208599Srdivacky if (isKill) { 340249423Sdim unsigned Idx = MIB->getNumOperands(); 341208599Srdivacky while (Idx > 0 && 342249423Sdim MIB->getOperand(Idx-1).isReg() && 343249423Sdim MIB->getOperand(Idx-1).isImplicit()) 344208599Srdivacky --Idx; 345249423Sdim bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1; 346208599Srdivacky if (isTied) 347208599Srdivacky isKill = false; 348208599Srdivacky } 349207618Srdivacky 350249423Sdim MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) | 351249423Sdim getDebugRegState(IsDebug)); 352198090Srdivacky} 353198090Srdivacky 354198090Srdivacky/// AddOperand - Add the specified operand to the specified machine instr. II 355198090Srdivacky/// specifies the instruction information for the node, and IIOpNum is the 356239462Sdim/// operand number (in the II) that we are adding. 357249423Sdimvoid InstrEmitter::AddOperand(MachineInstrBuilder &MIB, 358249423Sdim SDValue Op, 359198090Srdivacky unsigned IIOpNum, 360224145Sdim const MCInstrDesc *II, 361206083Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap, 362208599Srdivacky bool IsDebug, bool IsClone, bool IsCloned) { 363198090Srdivacky if (Op.isMachineOpcode()) { 364249423Sdim AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap, 365208599Srdivacky IsDebug, IsClone, IsCloned); 366198090Srdivacky } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 367249423Sdim MIB.addImm(C->getSExtValue()); 368198090Srdivacky } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) { 369249423Sdim MIB.addFPImm(F->getConstantFPValue()); 370198090Srdivacky } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) { 371239462Sdim // Turn additional physreg operands into implicit uses on non-variadic 372239462Sdim // instructions. This is used by call and return instructions passing 373239462Sdim // arguments in registers. 374239462Sdim bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic()); 375249423Sdim MIB.addReg(R->getReg(), getImplRegState(Imp)); 376234353Sdim } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) { 377249423Sdim MIB.addRegMask(RM->getRegMask()); 378198090Srdivacky } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) { 379249423Sdim MIB.addGlobalAddress(TGA->getGlobal(), TGA->getOffset(), 380249423Sdim TGA->getTargetFlags()); 381198090Srdivacky } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) { 382249423Sdim MIB.addMBB(BBNode->getBasicBlock()); 383198090Srdivacky } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) { 384249423Sdim MIB.addFrameIndex(FI->getIndex()); 385198090Srdivacky } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) { 386249423Sdim MIB.addJumpTableIndex(JT->getIndex(), JT->getTargetFlags()); 387198090Srdivacky } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) { 388198090Srdivacky int Offset = CP->getOffset(); 389198090Srdivacky unsigned Align = CP->getAlignment(); 390226633Sdim Type *Type = CP->getType(); 391198090Srdivacky // MachineConstantPool wants an explicit alignment. 392198090Srdivacky if (Align == 0) { 393243830Sdim Align = TM->getDataLayout()->getPrefTypeAlignment(Type); 394198090Srdivacky if (Align == 0) { 395198090Srdivacky // Alignment of vector types. FIXME! 396243830Sdim Align = TM->getDataLayout()->getTypeAllocSize(Type); 397198090Srdivacky } 398198090Srdivacky } 399226633Sdim 400198090Srdivacky unsigned Idx; 401198090Srdivacky MachineConstantPool *MCP = MF->getConstantPool(); 402198090Srdivacky if (CP->isMachineConstantPoolEntry()) 403198090Srdivacky Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align); 404198090Srdivacky else 405198090Srdivacky Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align); 406249423Sdim MIB.addConstantPoolIndex(Idx, Offset, CP->getTargetFlags()); 407198090Srdivacky } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) { 408249423Sdim MIB.addExternalSymbol(ES->getSymbol(), ES->getTargetFlags()); 409198892Srdivacky } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) { 410249423Sdim MIB.addBlockAddress(BA->getBlockAddress(), 411249423Sdim BA->getOffset(), 412249423Sdim BA->getTargetFlags()); 413239462Sdim } else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Op)) { 414249423Sdim MIB.addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags()); 415198090Srdivacky } else { 416198090Srdivacky assert(Op.getValueType() != MVT::Other && 417218893Sdim Op.getValueType() != MVT::Glue && 418218893Sdim "Chain and glue operands should occur at end of operand list!"); 419249423Sdim AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap, 420208599Srdivacky IsDebug, IsClone, IsCloned); 421198090Srdivacky } 422198090Srdivacky} 423198090Srdivacky 424226633Sdimunsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx, 425249423Sdim MVT VT, DebugLoc DL) { 426226633Sdim const TargetRegisterClass *VRC = MRI->getRegClass(VReg); 427226633Sdim const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); 428226633Sdim 429226633Sdim // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg 430226633Sdim // within reason. 431226633Sdim if (RC && RC != VRC) 432226633Sdim RC = MRI->constrainRegClass(VReg, RC, MinRCSize); 433226633Sdim 434226633Sdim // VReg has been adjusted. It can be used with SubIdx operands now. 435226633Sdim if (RC) 436226633Sdim return VReg; 437226633Sdim 438226633Sdim // VReg couldn't be reasonably constrained. Emit a COPY to a new virtual 439226633Sdim // register instead. 440226633Sdim RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx); 441226633Sdim assert(RC && "No legal register class for VT supports that SubIdx"); 442226633Sdim unsigned NewReg = MRI->createVirtualRegister(RC); 443226633Sdim BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg) 444226633Sdim .addReg(VReg); 445226633Sdim return NewReg; 446198090Srdivacky} 447198090Srdivacky 448198090Srdivacky/// EmitSubregNode - Generate machine code for subreg nodes. 449198090Srdivacky/// 450226633Sdimvoid InstrEmitter::EmitSubregNode(SDNode *Node, 451208599Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap, 452208599Srdivacky bool IsClone, bool IsCloned) { 453198090Srdivacky unsigned VRBase = 0; 454198090Srdivacky unsigned Opc = Node->getMachineOpcode(); 455226633Sdim 456198090Srdivacky // If the node is only used by a CopyToReg and the dest reg is a vreg, use 457198090Srdivacky // the CopyToReg'd destination register instead of creating a new vreg. 458198090Srdivacky for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 459198090Srdivacky UI != E; ++UI) { 460198090Srdivacky SDNode *User = *UI; 461226633Sdim if (User->getOpcode() == ISD::CopyToReg && 462198090Srdivacky User->getOperand(2).getNode() == Node) { 463198090Srdivacky unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 464198090Srdivacky if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 465198090Srdivacky VRBase = DestReg; 466198090Srdivacky break; 467198090Srdivacky } 468198090Srdivacky } 469198090Srdivacky } 470226633Sdim 471203954Srdivacky if (Opc == TargetOpcode::EXTRACT_SUBREG) { 472226633Sdim // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub. There are no 473226633Sdim // constraints on the %dst register, COPY can target all legal register 474226633Sdim // classes. 475198090Srdivacky unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 476249423Sdim const TargetRegisterClass *TRC = 477249423Sdim TLI->getRegClassFor(Node->getSimpleValueType(0)); 478198090Srdivacky 479198090Srdivacky unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 480218893Sdim MachineInstr *DefMI = MRI->getVRegDef(VReg); 481218893Sdim unsigned SrcReg, DstReg, DefSubIdx; 482218893Sdim if (DefMI && 483218893Sdim TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) && 484239462Sdim SubIdx == DefSubIdx && 485239462Sdim TRC == MRI->getRegClass(SrcReg)) { 486218893Sdim // Optimize these: 487218893Sdim // r1025 = s/zext r1024, 4 488218893Sdim // r1026 = extract_subreg r1025, 4 489218893Sdim // to a copy 490218893Sdim // r1026 = copy r1024 491218893Sdim VRBase = MRI->createVirtualRegister(TRC); 492218893Sdim BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 493218893Sdim TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg); 494239462Sdim MRI->clearKillFlags(SrcReg); 495218893Sdim } else { 496226633Sdim // VReg may not support a SubIdx sub-register, and we may need to 497226633Sdim // constrain its register class or issue a COPY to a compatible register 498226633Sdim // class. 499226633Sdim VReg = ConstrainForSubReg(VReg, SubIdx, 500249423Sdim Node->getOperand(0).getSimpleValueType(), 501226633Sdim Node->getDebugLoc()); 502198090Srdivacky 503226633Sdim // Create the destreg if it is missing. 504226633Sdim if (VRBase == 0) 505226633Sdim VRBase = MRI->createVirtualRegister(TRC); 506198090Srdivacky 507218893Sdim // Create the extract_subreg machine instruction. 508226633Sdim BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 509226633Sdim TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx); 510218893Sdim } 511203954Srdivacky } else if (Opc == TargetOpcode::INSERT_SUBREG || 512203954Srdivacky Opc == TargetOpcode::SUBREG_TO_REG) { 513198090Srdivacky SDValue N0 = Node->getOperand(0); 514198090Srdivacky SDValue N1 = Node->getOperand(1); 515198090Srdivacky SDValue N2 = Node->getOperand(2); 516198090Srdivacky unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); 517198090Srdivacky 518226633Sdim // Figure out the register class to create for the destreg. It should be 519226633Sdim // the largest legal register class supporting SubIdx sub-registers. 520226633Sdim // RegisterCoalescer will constrain it further if it decides to eliminate 521226633Sdim // the INSERT_SUBREG instruction. 522226633Sdim // 523226633Sdim // %dst = INSERT_SUBREG %src, %sub, SubIdx 524226633Sdim // 525226633Sdim // is lowered by TwoAddressInstructionPass to: 526226633Sdim // 527226633Sdim // %dst = COPY %src 528226633Sdim // %dst:SubIdx = COPY %sub 529226633Sdim // 530226633Sdim // There is no constraint on the %src register class. 531226633Sdim // 532249423Sdim const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getSimpleValueType(0)); 533226633Sdim SRC = TRI->getSubClassWithSubReg(SRC, SubIdx); 534226633Sdim assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG"); 535226633Sdim 536226633Sdim if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase))) 537198090Srdivacky VRBase = MRI->createVirtualRegister(SRC); 538198090Srdivacky 539198090Srdivacky // Create the insert_subreg or subreg_to_reg machine instruction. 540249423Sdim MachineInstrBuilder MIB = 541249423Sdim BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase); 542226633Sdim 543198090Srdivacky // If creating a subreg_to_reg, then the first input operand 544198090Srdivacky // is an implicit value immediate, otherwise it's a register 545203954Srdivacky if (Opc == TargetOpcode::SUBREG_TO_REG) { 546198090Srdivacky const ConstantSDNode *SD = cast<ConstantSDNode>(N0); 547249423Sdim MIB.addImm(SD->getZExtValue()); 548198090Srdivacky } else 549249423Sdim AddOperand(MIB, N0, 0, 0, VRBaseMap, /*IsDebug=*/false, 550208599Srdivacky IsClone, IsCloned); 551198090Srdivacky // Add the subregster being inserted 552249423Sdim AddOperand(MIB, N1, 0, 0, VRBaseMap, /*IsDebug=*/false, 553208599Srdivacky IsClone, IsCloned); 554249423Sdim MIB.addImm(SubIdx); 555249423Sdim MBB->insert(InsertPos, MIB); 556198090Srdivacky } else 557198090Srdivacky llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg"); 558226633Sdim 559198090Srdivacky SDValue Op(Node, 0); 560198090Srdivacky bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 561218893Sdim (void)isNew; // Silence compiler warning. 562198090Srdivacky assert(isNew && "Node emitted out of order - early"); 563198090Srdivacky} 564198090Srdivacky 565198090Srdivacky/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes. 566198090Srdivacky/// COPY_TO_REGCLASS is just a normal copy, except that the destination 567198090Srdivacky/// register is constrained to be in a particular register class. 568198090Srdivacky/// 569198090Srdivackyvoid 570198090SrdivackyInstrEmitter::EmitCopyToRegClassNode(SDNode *Node, 571198090Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap) { 572198090Srdivacky unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 573198090Srdivacky 574210299Sed // Create the new VReg in the destination class and emit a copy. 575198090Srdivacky unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 576239462Sdim const TargetRegisterClass *DstRC = 577239462Sdim TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx)); 578198090Srdivacky unsigned NewVReg = MRI->createVirtualRegister(DstRC); 579210299Sed BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 580210299Sed NewVReg).addReg(VReg); 581198090Srdivacky 582198090Srdivacky SDValue Op(Node, 0); 583198090Srdivacky bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; 584218893Sdim (void)isNew; // Silence compiler warning. 585198090Srdivacky assert(isNew && "Node emitted out of order - early"); 586198090Srdivacky} 587198090Srdivacky 588207618Srdivacky/// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes. 589207618Srdivacky/// 590207618Srdivackyvoid InstrEmitter::EmitRegSequence(SDNode *Node, 591208599Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap, 592208599Srdivacky bool IsClone, bool IsCloned) { 593224145Sdim unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue(); 594224145Sdim const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx); 595239462Sdim unsigned NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC)); 596249423Sdim const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE); 597249423Sdim MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg); 598207618Srdivacky unsigned NumOps = Node->getNumOperands(); 599224145Sdim assert((NumOps & 1) == 1 && 600224145Sdim "REG_SEQUENCE must have an odd number of operands!"); 601224145Sdim for (unsigned i = 1; i != NumOps; ++i) { 602207618Srdivacky SDValue Op = Node->getOperand(i); 603224145Sdim if ((i & 1) == 0) { 604234353Sdim RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1)); 605234353Sdim // Skip physical registers as they don't have a vreg to get and we'll 606234353Sdim // insert copies for them in TwoAddressInstructionPass anyway. 607234353Sdim if (!R || !TargetRegisterInfo::isPhysicalRegister(R->getReg())) { 608234353Sdim unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue(); 609234353Sdim unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap); 610234353Sdim const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); 611234353Sdim const TargetRegisterClass *SRC = 612208599Srdivacky TRI->getMatchingSuperRegClass(RC, TRC, SubIdx); 613234353Sdim if (SRC && SRC != RC) { 614234353Sdim MRI->setRegClass(NewVReg, SRC); 615234353Sdim RC = SRC; 616234353Sdim } 617208599Srdivacky } 618207618Srdivacky } 619249423Sdim AddOperand(MIB, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false, 620208599Srdivacky IsClone, IsCloned); 621207618Srdivacky } 622207618Srdivacky 623249423Sdim MBB->insert(InsertPos, MIB); 624207618Srdivacky SDValue Op(Node, 0); 625207618Srdivacky bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; 626218893Sdim (void)isNew; // Silence compiler warning. 627207618Srdivacky assert(isNew && "Node emitted out of order - early"); 628207618Srdivacky} 629207618Srdivacky 630206083Srdivacky/// EmitDbgValue - Generate machine instruction for a dbg_value node. 631206083Srdivacky/// 632207618SrdivackyMachineInstr * 633207618SrdivackyInstrEmitter::EmitDbgValue(SDDbgValue *SD, 634207618Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap) { 635206083Srdivacky uint64_t Offset = SD->getOffset(); 636206083Srdivacky MDNode* MDPtr = SD->getMDPtr(); 637206083Srdivacky DebugLoc DL = SD->getDebugLoc(); 638204792Srdivacky 639207618Srdivacky if (SD->getKind() == SDDbgValue::FRAMEIX) { 640207618Srdivacky // Stack address; this needs to be lowered in target-dependent fashion. 641207618Srdivacky // EmitTargetCodeForFrameDebugValue is responsible for allocation. 642207618Srdivacky unsigned FrameIx = SD->getFrameIx(); 643207618Srdivacky return TII->emitFrameIndexDebugValue(*MF, FrameIx, Offset, MDPtr, DL); 644207618Srdivacky } 645207618Srdivacky // Otherwise, we're going to create an instruction here. 646224145Sdim const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE); 647206083Srdivacky MachineInstrBuilder MIB = BuildMI(*MF, DL, II); 648206083Srdivacky if (SD->getKind() == SDDbgValue::SDNODE) { 649207618Srdivacky SDNode *Node = SD->getSDNode(); 650207618Srdivacky SDValue Op = SDValue(Node, SD->getResNo()); 651207618Srdivacky // It's possible we replaced this SDNode with other(s) and therefore 652207618Srdivacky // didn't generate code for it. It's better to catch these cases where 653207618Srdivacky // they happen and transfer the debug info, but trying to guarantee that 654207618Srdivacky // in all cases would be very fragile; this is a safeguard for any 655207618Srdivacky // that were missed. 656207618Srdivacky DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 657207618Srdivacky if (I==VRBaseMap.end()) 658207618Srdivacky MIB.addReg(0U); // undef 659207618Srdivacky else 660249423Sdim AddOperand(MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap, 661208599Srdivacky /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false); 662206083Srdivacky } else if (SD->getKind() == SDDbgValue::CONST) { 663207618Srdivacky const Value *V = SD->getConst(); 664207618Srdivacky if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 665224145Sdim if (CI->getBitWidth() > 64) 666224145Sdim MIB.addCImm(CI); 667208599Srdivacky else 668208599Srdivacky MIB.addImm(CI->getSExtValue()); 669207618Srdivacky } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 670206083Srdivacky MIB.addFPImm(CF); 671205218Srdivacky } else { 672205218Srdivacky // Could be an Undef. In any case insert an Undef so we can see what we 673205218Srdivacky // dropped. 674206083Srdivacky MIB.addReg(0U); 675205218Srdivacky } 676204792Srdivacky } else { 677204792Srdivacky // Insert an Undef so we can see what we dropped. 678206083Srdivacky MIB.addReg(0U); 679204792Srdivacky } 680206083Srdivacky 681206083Srdivacky MIB.addImm(Offset).addMetadata(MDPtr); 682206083Srdivacky return &*MIB; 683204792Srdivacky} 684204792Srdivacky 685206083Srdivacky/// EmitMachineNode - Generate machine code for a target-specific node and 686206083Srdivacky/// needed dependencies. 687198090Srdivacky/// 688206083Srdivackyvoid InstrEmitter:: 689206083SrdivackyEmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned, 690207618Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap) { 691206083Srdivacky unsigned Opc = Node->getMachineOpcode(); 692226633Sdim 693206083Srdivacky // Handle subreg insert/extract specially 694226633Sdim if (Opc == TargetOpcode::EXTRACT_SUBREG || 695206083Srdivacky Opc == TargetOpcode::INSERT_SUBREG || 696206083Srdivacky Opc == TargetOpcode::SUBREG_TO_REG) { 697208599Srdivacky EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned); 698206083Srdivacky return; 699206083Srdivacky } 700198090Srdivacky 701206083Srdivacky // Handle COPY_TO_REGCLASS specially. 702206083Srdivacky if (Opc == TargetOpcode::COPY_TO_REGCLASS) { 703206083Srdivacky EmitCopyToRegClassNode(Node, VRBaseMap); 704206083Srdivacky return; 705206083Srdivacky } 706198090Srdivacky 707207618Srdivacky // Handle REG_SEQUENCE specially. 708207618Srdivacky if (Opc == TargetOpcode::REG_SEQUENCE) { 709208599Srdivacky EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned); 710207618Srdivacky return; 711207618Srdivacky } 712207618Srdivacky 713206083Srdivacky if (Opc == TargetOpcode::IMPLICIT_DEF) 714206083Srdivacky // We want a unique VR for each IMPLICIT_DEF use. 715206083Srdivacky return; 716226633Sdim 717224145Sdim const MCInstrDesc &II = TII->get(Opc); 718206083Srdivacky unsigned NumResults = CountResults(Node); 719239462Sdim unsigned NumImpUses = 0; 720243830Sdim unsigned NodeOperands = 721243830Sdim countOperands(Node, II.getNumOperands() - II.getNumDefs(), NumImpUses); 722206083Srdivacky bool HasPhysRegOuts = NumResults > II.getNumDefs() && II.getImplicitDefs()!=0; 723198090Srdivacky#ifndef NDEBUG 724206083Srdivacky unsigned NumMIOperands = NodeOperands + NumResults; 725206083Srdivacky if (II.isVariadic()) 726206083Srdivacky assert(NumMIOperands >= II.getNumOperands() && 727206083Srdivacky "Too few operands for a variadic node!"); 728206083Srdivacky else 729206083Srdivacky assert(NumMIOperands >= II.getNumOperands() && 730239462Sdim NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() + 731239462Sdim NumImpUses && 732206083Srdivacky "#operands for dag node doesn't match .td file!"); 733198090Srdivacky#endif 734198090Srdivacky 735206083Srdivacky // Create the new machine instruction. 736249423Sdim MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II); 737210299Sed 738206083Srdivacky // Add result register values for things that are defined by this 739206083Srdivacky // instruction. 740206083Srdivacky if (NumResults) 741249423Sdim CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap); 742226633Sdim 743206083Srdivacky // Emit all of the actual operands of this instruction, adding them to the 744206083Srdivacky // instruction as appropriate. 745206083Srdivacky bool HasOptPRefs = II.getNumDefs() > NumResults; 746206083Srdivacky assert((!HasOptPRefs || !HasPhysRegOuts) && 747206083Srdivacky "Unable to cope with optional defs and phys regs defs!"); 748206083Srdivacky unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0; 749206083Srdivacky for (unsigned i = NumSkip; i != NodeOperands; ++i) 750249423Sdim AddOperand(MIB, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II, 751208599Srdivacky VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned); 752198090Srdivacky 753206083Srdivacky // Transfer all of the memory reference descriptions of this instruction. 754249423Sdim MIB.setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(), 755206083Srdivacky cast<MachineSDNode>(Node)->memoperands_end()); 756198090Srdivacky 757210299Sed // Insert the instruction into position in the block. This needs to 758210299Sed // happen before any custom inserter hook is called so that the 759210299Sed // hook knows where in the block to insert the replacement code. 760249423Sdim MBB->insert(InsertPos, MIB); 761210299Sed 762234353Sdim // The MachineInstr may also define physregs instead of virtregs. These 763234353Sdim // physreg values can reach other instructions in different ways: 764234353Sdim // 765234353Sdim // 1. When there is a use of a Node value beyond the explicitly defined 766234353Sdim // virtual registers, we emit a CopyFromReg for one of the implicitly 767234353Sdim // defined physregs. This only happens when HasPhysRegOuts is true. 768234353Sdim // 769234353Sdim // 2. A CopyFromReg reading a physreg may be glued to this instruction. 770234353Sdim // 771234353Sdim // 3. A glued instruction may implicitly use a physreg. 772234353Sdim // 773234353Sdim // 4. A glued instruction may use a RegisterSDNode operand. 774234353Sdim // 775234353Sdim // Collect all the used physreg defs, and make sure that any unused physreg 776234353Sdim // defs are marked as dead. 777234353Sdim SmallVector<unsigned, 8> UsedRegs; 778234353Sdim 779218893Sdim // Additional results must be physical register defs. 780206083Srdivacky if (HasPhysRegOuts) { 781206083Srdivacky for (unsigned i = II.getNumDefs(); i < NumResults; ++i) { 782206083Srdivacky unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()]; 783234353Sdim if (!Node->hasAnyUseOfValue(i)) 784234353Sdim continue; 785234353Sdim // This implicitly defined physreg has a use. 786234353Sdim UsedRegs.push_back(Reg); 787234353Sdim EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap); 788198090Srdivacky } 789198090Srdivacky } 790226633Sdim 791234353Sdim // Scan the glue chain for any used physregs. 792234353Sdim if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) { 793234353Sdim for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) { 794234353Sdim if (F->getOpcode() == ISD::CopyFromReg) { 795234353Sdim UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg()); 796234353Sdim continue; 797234353Sdim } else if (F->getOpcode() == ISD::CopyToReg) { 798234353Sdim // Skip CopyToReg nodes that are internal to the glue chain. 799234353Sdim continue; 800234353Sdim } 801234353Sdim // Collect declared implicit uses. 802234353Sdim const MCInstrDesc &MCID = TII->get(F->getMachineOpcode()); 803234353Sdim UsedRegs.append(MCID.getImplicitUses(), 804234353Sdim MCID.getImplicitUses() + MCID.getNumImplicitUses()); 805234353Sdim // In addition to declared implicit uses, we must also check for 806234353Sdim // direct RegisterSDNode operands. 807234353Sdim for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i) 808234353Sdim if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) { 809234353Sdim unsigned Reg = R->getReg(); 810234353Sdim if (TargetRegisterInfo::isPhysicalRegister(Reg)) 811234353Sdim UsedRegs.push_back(Reg); 812234353Sdim } 813206083Srdivacky } 814234353Sdim } 815226633Sdim 816234353Sdim // Finally mark unused registers as dead. 817234353Sdim if (!UsedRegs.empty() || II.getImplicitDefs()) 818249423Sdim MIB->setPhysRegsDeadExcept(UsedRegs, *TRI); 819234353Sdim 820226633Sdim // Run post-isel target hook to adjust this instruction if needed. 821226633Sdim#ifdef NDEBUG 822226633Sdim if (II.hasPostISelHook()) 823226633Sdim#endif 824249423Sdim TLI->AdjustInstrPostInstrSelection(MIB, Node); 825206083Srdivacky} 826198090Srdivacky 827206083Srdivacky/// EmitSpecialNode - Generate machine code for a target-independent node and 828206083Srdivacky/// needed dependencies. 829206083Srdivackyvoid InstrEmitter:: 830206083SrdivackyEmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned, 831206083Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap) { 832198090Srdivacky switch (Node->getOpcode()) { 833198090Srdivacky default: 834198090Srdivacky#ifndef NDEBUG 835198090Srdivacky Node->dump(); 836198090Srdivacky#endif 837198090Srdivacky llvm_unreachable("This target-independent node should have been selected!"); 838198090Srdivacky case ISD::EntryToken: 839198090Srdivacky llvm_unreachable("EntryToken should have been excluded from the schedule!"); 840198090Srdivacky case ISD::MERGE_VALUES: 841198090Srdivacky case ISD::TokenFactor: // fall thru 842198090Srdivacky break; 843198090Srdivacky case ISD::CopyToReg: { 844198090Srdivacky unsigned SrcReg; 845198090Srdivacky SDValue SrcVal = Node->getOperand(2); 846198090Srdivacky if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal)) 847198090Srdivacky SrcReg = R->getReg(); 848198090Srdivacky else 849198090Srdivacky SrcReg = getVR(SrcVal, VRBaseMap); 850226633Sdim 851198090Srdivacky unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 852198090Srdivacky if (SrcReg == DestReg) // Coalesced away the copy? Ignore. 853198090Srdivacky break; 854198090Srdivacky 855210299Sed BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 856210299Sed DestReg).addReg(SrcReg); 857198090Srdivacky break; 858198090Srdivacky } 859198090Srdivacky case ISD::CopyFromReg: { 860198090Srdivacky unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 861198090Srdivacky EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap); 862198090Srdivacky break; 863198090Srdivacky } 864205218Srdivacky case ISD::EH_LABEL: { 865205218Srdivacky MCSymbol *S = cast<EHLabelSDNode>(Node)->getLabel(); 866205218Srdivacky BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 867205218Srdivacky TII->get(TargetOpcode::EH_LABEL)).addSym(S); 868205218Srdivacky break; 869205218Srdivacky } 870226633Sdim 871243830Sdim case ISD::LIFETIME_START: 872243830Sdim case ISD::LIFETIME_END: { 873243830Sdim unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START) ? 874243830Sdim TargetOpcode::LIFETIME_START : TargetOpcode::LIFETIME_END; 875243830Sdim 876243830Sdim FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Node->getOperand(1)); 877243830Sdim BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp)) 878243830Sdim .addFrameIndex(FI->getIndex()); 879243830Sdim break; 880243830Sdim } 881243830Sdim 882198090Srdivacky case ISD::INLINEASM: { 883198090Srdivacky unsigned NumOps = Node->getNumOperands(); 884218893Sdim if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue) 885218893Sdim --NumOps; // Ignore the glue operand. 886226633Sdim 887198090Srdivacky // Create the inline asm machine instruction. 888249423Sdim MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), 889249423Sdim TII->get(TargetOpcode::INLINEASM)); 890198090Srdivacky 891198090Srdivacky // Add the asm string as an external symbol operand. 892207618Srdivacky SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString); 893207618Srdivacky const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol(); 894249423Sdim MIB.addExternalSymbol(AsmStr); 895226633Sdim 896243830Sdim // Add the HasSideEffect, isAlignStack, AsmDialect, MayLoad and MayStore 897243830Sdim // bits. 898218893Sdim int64_t ExtraInfo = 899218893Sdim cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))-> 900210299Sed getZExtValue(); 901249423Sdim MIB.addImm(ExtraInfo); 902210299Sed 903243830Sdim // Remember to operand index of the group flags. 904243830Sdim SmallVector<unsigned, 8> GroupIdx; 905243830Sdim 906198090Srdivacky // Add all of the operand registers to the instruction. 907207618Srdivacky for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) { 908198090Srdivacky unsigned Flags = 909198090Srdivacky cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue(); 910243830Sdim const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); 911226633Sdim 912249423Sdim GroupIdx.push_back(MIB->getNumOperands()); 913249423Sdim MIB.addImm(Flags); 914198090Srdivacky ++i; // Skip the ID value. 915226633Sdim 916207618Srdivacky switch (InlineAsm::getKind(Flags)) { 917198090Srdivacky default: llvm_unreachable("Bad flags!"); 918207618Srdivacky case InlineAsm::Kind_RegDef: 919243830Sdim for (unsigned j = 0; j != NumVals; ++j, ++i) { 920198090Srdivacky unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 921210299Sed // FIXME: Add dead flags for physical and virtual registers defined. 922210299Sed // For now, mark physical register defs as implicit to help fast 923210299Sed // regalloc. This makes inline asm look a lot like calls. 924249423Sdim MIB.addReg(Reg, RegState::Define | 925249423Sdim getImplRegState(TargetRegisterInfo::isPhysicalRegister(Reg))); 926198090Srdivacky } 927198090Srdivacky break; 928207618Srdivacky case InlineAsm::Kind_RegDefEarlyClobber: 929224145Sdim case InlineAsm::Kind_Clobber: 930243830Sdim for (unsigned j = 0; j != NumVals; ++j, ++i) { 931198090Srdivacky unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 932249423Sdim MIB.addReg(Reg, RegState::Define | RegState::EarlyClobber | 933249423Sdim getImplRegState(TargetRegisterInfo::isPhysicalRegister(Reg))); 934198090Srdivacky } 935198090Srdivacky break; 936207618Srdivacky case InlineAsm::Kind_RegUse: // Use of register. 937207618Srdivacky case InlineAsm::Kind_Imm: // Immediate. 938207618Srdivacky case InlineAsm::Kind_Mem: // Addressing mode. 939198090Srdivacky // The addressing mode has been selected, just add all of the 940198090Srdivacky // operands to the machine instruction. 941243830Sdim for (unsigned j = 0; j != NumVals; ++j, ++i) 942249423Sdim AddOperand(MIB, Node->getOperand(i), 0, 0, VRBaseMap, 943208599Srdivacky /*IsDebug=*/false, IsClone, IsCloned); 944243830Sdim 945243830Sdim // Manually set isTied bits. 946243830Sdim if (InlineAsm::getKind(Flags) == InlineAsm::Kind_RegUse) { 947243830Sdim unsigned DefGroup = 0; 948243830Sdim if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) { 949243830Sdim unsigned DefIdx = GroupIdx[DefGroup] + 1; 950243830Sdim unsigned UseIdx = GroupIdx.back() + 1; 951243830Sdim for (unsigned j = 0; j != NumVals; ++j) 952249423Sdim MIB->tieOperands(DefIdx + j, UseIdx + j); 953243830Sdim } 954243830Sdim } 955198090Srdivacky break; 956198090Srdivacky } 957198090Srdivacky } 958226633Sdim 959207618Srdivacky // Get the mdnode from the asm if it exists and add it to the instruction. 960207618Srdivacky SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode); 961207618Srdivacky const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD(); 962207618Srdivacky if (MD) 963249423Sdim MIB.addMetadata(MD); 964226633Sdim 965249423Sdim MBB->insert(InsertPos, MIB); 966198090Srdivacky break; 967198090Srdivacky } 968198090Srdivacky } 969198090Srdivacky} 970198090Srdivacky 971198090Srdivacky/// InstrEmitter - Construct an InstrEmitter and set it to start inserting 972198090Srdivacky/// at the given position in the given block. 973198090SrdivackyInstrEmitter::InstrEmitter(MachineBasicBlock *mbb, 974198090Srdivacky MachineBasicBlock::iterator insertpos) 975198090Srdivacky : MF(mbb->getParent()), 976198090Srdivacky MRI(&MF->getRegInfo()), 977198090Srdivacky TM(&MF->getTarget()), 978198090Srdivacky TII(TM->getInstrInfo()), 979198090Srdivacky TRI(TM->getRegisterInfo()), 980198090Srdivacky TLI(TM->getTargetLowering()), 981198090Srdivacky MBB(mbb), InsertPos(insertpos) { 982198090Srdivacky} 983