1193323Sed//=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file describes an abstract interface used to get information about a 11193323Sed// target machines register file. This information is used for a variety of 12193323Sed// purposed, especially register allocation. 13193323Sed// 14193323Sed//===----------------------------------------------------------------------===// 15193323Sed 16193323Sed#ifndef LLVM_TARGET_TARGETREGISTERINFO_H 17193323Sed#define LLVM_TARGET_TARGETREGISTERINFO_H 18193323Sed 19249423Sdim#include "llvm/ADT/ArrayRef.h" 20193323Sed#include "llvm/CodeGen/MachineBasicBlock.h" 21193323Sed#include "llvm/CodeGen/ValueTypes.h" 22249423Sdim#include "llvm/IR/CallingConv.h" 23249423Sdim#include "llvm/MC/MCRegisterInfo.h" 24193323Sed#include <cassert> 25193323Sed#include <functional> 26193323Sed 27193323Sednamespace llvm { 28193323Sed 29193323Sedclass BitVector; 30193323Sedclass MachineFunction; 31193323Sedclass RegScavenger; 32208599Srdivackytemplate<class T> class SmallVectorImpl; 33249423Sdimclass VirtRegMap; 34218893Sdimclass raw_ostream; 35193323Sed 36193323Sedclass TargetRegisterClass { 37193323Sedpublic: 38249423Sdim typedef const MCPhysReg* iterator; 39249423Sdim typedef const MCPhysReg* const_iterator; 40234353Sdim typedef const MVT::SimpleValueType* vt_iterator; 41193323Sed typedef const TargetRegisterClass* const * sc_iterator; 42234353Sdim 43234353Sdim // Instance variables filled by tablegen, do not use! 44226633Sdim const MCRegisterClass *MC; 45193323Sed const vt_iterator VTs; 46239462Sdim const uint32_t *SubClassMask; 47239462Sdim const uint16_t *SuperRegIndices; 48193323Sed const sc_iterator SuperClasses; 49249423Sdim ArrayRef<MCPhysReg> (*OrderFunc)(const MachineFunction&); 50226633Sdim 51193323Sed /// getID() - Return the register class ID number. 52193323Sed /// 53226633Sdim unsigned getID() const { return MC->getID(); } 54193323Sed 55193323Sed /// getName() - Return the register class name for debugging. 56193323Sed /// 57226633Sdim const char *getName() const { return MC->getName(); } 58193323Sed 59193323Sed /// begin/end - Return all of the registers in this class. 60193323Sed /// 61226633Sdim iterator begin() const { return MC->begin(); } 62226633Sdim iterator end() const { return MC->end(); } 63193323Sed 64193323Sed /// getNumRegs - Return the number of registers in this class. 65193323Sed /// 66226633Sdim unsigned getNumRegs() const { return MC->getNumRegs(); } 67193323Sed 68193323Sed /// getRegister - Return the specified register in the class. 69193323Sed /// 70193323Sed unsigned getRegister(unsigned i) const { 71226633Sdim return MC->getRegister(i); 72193323Sed } 73193323Sed 74193323Sed /// contains - Return true if the specified register is included in this 75207618Srdivacky /// register class. This does not include virtual registers. 76193323Sed bool contains(unsigned Reg) const { 77226633Sdim return MC->contains(Reg); 78193323Sed } 79193323Sed 80210299Sed /// contains - Return true if both registers are in this class. 81210299Sed bool contains(unsigned Reg1, unsigned Reg2) const { 82226633Sdim return MC->contains(Reg1, Reg2); 83210299Sed } 84210299Sed 85226633Sdim /// getSize - Return the size of the register in bytes, which is also the size 86226633Sdim /// of a stack slot allocated to hold a spilled copy of this register. 87226633Sdim unsigned getSize() const { return MC->getSize(); } 88226633Sdim 89226633Sdim /// getAlignment - Return the minimum required alignment for a register of 90226633Sdim /// this class. 91226633Sdim unsigned getAlignment() const { return MC->getAlignment(); } 92226633Sdim 93226633Sdim /// getCopyCost - Return the cost of copying a value between two registers in 94226633Sdim /// this class. A negative number means the register class is very expensive 95226633Sdim /// to copy e.g. status flag register classes. 96226633Sdim int getCopyCost() const { return MC->getCopyCost(); } 97226633Sdim 98226633Sdim /// isAllocatable - Return true if this register class may be used to create 99226633Sdim /// virtual registers. 100226633Sdim bool isAllocatable() const { return MC->isAllocatable(); } 101226633Sdim 102193323Sed /// hasType - return true if this TargetRegisterClass has the ValueType vt. 103193323Sed /// 104198090Srdivacky bool hasType(EVT vt) const { 105218893Sdim for(int i = 0; VTs[i] != MVT::Other; ++i) 106234353Sdim if (EVT(VTs[i]) == vt) 107193323Sed return true; 108193323Sed return false; 109193323Sed } 110198090Srdivacky 111193323Sed /// vt_begin / vt_end - Loop over all of the value types that can be 112193323Sed /// represented by values in this register class. 113193323Sed vt_iterator vt_begin() const { 114193323Sed return VTs; 115193323Sed } 116193323Sed 117193323Sed vt_iterator vt_end() const { 118193323Sed vt_iterator I = VTs; 119218893Sdim while (*I != MVT::Other) ++I; 120193323Sed return I; 121193323Sed } 122193323Sed 123203954Srdivacky /// hasSubClass - return true if the specified TargetRegisterClass 124226633Sdim /// is a proper sub-class of this TargetRegisterClass. 125226633Sdim bool hasSubClass(const TargetRegisterClass *RC) const { 126226633Sdim return RC != this && hasSubClassEq(RC); 127193323Sed } 128193323Sed 129226633Sdim /// hasSubClassEq - Returns true if RC is a sub-class of or equal to this 130223017Sdim /// class. 131223017Sdim bool hasSubClassEq(const TargetRegisterClass *RC) const { 132226633Sdim unsigned ID = RC->getID(); 133226633Sdim return (SubClassMask[ID / 32] >> (ID % 32)) & 1; 134223017Sdim } 135223017Sdim 136193323Sed /// hasSuperClass - return true if the specified TargetRegisterClass is a 137226633Sdim /// proper super-class of this TargetRegisterClass. 138226633Sdim bool hasSuperClass(const TargetRegisterClass *RC) const { 139226633Sdim return RC->hasSubClass(this); 140193323Sed } 141193323Sed 142226633Sdim /// hasSuperClassEq - Returns true if RC is a super-class of or equal to this 143223017Sdim /// class. 144223017Sdim bool hasSuperClassEq(const TargetRegisterClass *RC) const { 145226633Sdim return RC->hasSubClassEq(this); 146223017Sdim } 147223017Sdim 148226633Sdim /// getSubClassMask - Returns a bit vector of subclasses, including this one. 149226633Sdim /// The vector is indexed by class IDs, see hasSubClassEq() above for how to 150226633Sdim /// use it. 151234353Sdim const uint32_t *getSubClassMask() const { 152226633Sdim return SubClassMask; 153193323Sed } 154198090Srdivacky 155239462Sdim /// getSuperRegIndices - Returns a 0-terminated list of sub-register indices 156239462Sdim /// that project some super-register class into this register class. The list 157239462Sdim /// has an entry for each Idx such that: 158239462Sdim /// 159239462Sdim /// There exists SuperRC where: 160239462Sdim /// For all Reg in SuperRC: 161239462Sdim /// this->contains(Reg:Idx) 162239462Sdim /// 163239462Sdim const uint16_t *getSuperRegIndices() const { 164239462Sdim return SuperRegIndices; 165239462Sdim } 166239462Sdim 167226633Sdim /// getSuperClasses - Returns a NULL terminated list of super-classes. The 168226633Sdim /// classes are ordered by ID which is also a topological ordering from large 169226633Sdim /// to small classes. The list does NOT include the current class. 170226633Sdim sc_iterator getSuperClasses() const { 171226633Sdim return SuperClasses; 172193323Sed } 173193323Sed 174193323Sed /// isASubClass - return true if this TargetRegisterClass is a subset 175193323Sed /// class of at least one other TargetRegisterClass. 176193323Sed bool isASubClass() const { 177193323Sed return SuperClasses[0] != 0; 178193323Sed } 179198090Srdivacky 180224145Sdim /// getRawAllocationOrder - Returns the preferred order for allocating 181224145Sdim /// registers from this register class in MF. The raw order comes directly 182224145Sdim /// from the .td file and may include reserved registers that are not 183224145Sdim /// allocatable. Register allocators should also make sure to allocate 184224145Sdim /// callee-saved registers only after all the volatiles are used. The 185224145Sdim /// RegisterClassInfo class provides filtered allocation orders with 186224145Sdim /// callee-saved registers moved to the end. 187193323Sed /// 188224145Sdim /// The MachineFunction argument can be used to tune the allocatable 189224145Sdim /// registers based on the characteristics of the function, subtarget, or 190224145Sdim /// other criteria. 191193323Sed /// 192224145Sdim /// By default, this method returns all registers in the class. 193218893Sdim /// 194249423Sdim ArrayRef<MCPhysReg> getRawAllocationOrder(const MachineFunction &MF) const { 195234353Sdim return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs()); 196193323Sed } 197193323Sed}; 198193323Sed 199224145Sdim/// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about 200224145Sdim/// registers. These are used by codegen, not by MC. 201224145Sdimstruct TargetRegisterInfoDesc { 202224145Sdim unsigned CostPerUse; // Extra cost of instructions using register. 203224145Sdim bool inAllocatableClass; // Register belongs to an allocatable regclass. 204224145Sdim}; 205193323Sed 206234353Sdim/// Each TargetRegisterClass has a per register weight, and weight 207234353Sdim/// limit which must be less than the limits of its pressure sets. 208234353Sdimstruct RegClassWeight { 209234982Sdim unsigned RegWeight; 210234353Sdim unsigned WeightLimit; 211234353Sdim}; 212234353Sdim 213193323Sed/// TargetRegisterInfo base class - We assume that the target defines a static 214193323Sed/// array of TargetRegisterDesc objects that represent all of the machine 215193323Sed/// registers that the target has. As such, we simply have to track a pointer 216193323Sed/// to this array so that we can turn register number into a register 217193323Sed/// descriptor. 218193323Sed/// 219224145Sdimclass TargetRegisterInfo : public MCRegisterInfo { 220193323Sedpublic: 221193323Sed typedef const TargetRegisterClass * const * regclass_iterator; 222193323Sedprivate: 223224145Sdim const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen 224208599Srdivacky const char *const *SubRegIndexNames; // Names of subreg indexes. 225243830Sdim // Pointer to array of lane masks, one per sub-reg index. 226243830Sdim const unsigned *SubRegIndexLaneMasks; 227243830Sdim 228193323Sed regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses 229193323Sed 230193323Sedprotected: 231224145Sdim TargetRegisterInfo(const TargetRegisterInfoDesc *ID, 232193323Sed regclass_iterator RegClassBegin, 233193323Sed regclass_iterator RegClassEnd, 234243830Sdim const char *const *SRINames, 235243830Sdim const unsigned *SRILaneMasks); 236193323Sed virtual ~TargetRegisterInfo(); 237193323Sedpublic: 238193323Sed 239218893Sdim // Register numbers can represent physical registers, virtual registers, and 240218893Sdim // sometimes stack slots. The unsigned values are divided into these ranges: 241218893Sdim // 242218893Sdim // 0 Not a register, can be used as a sentinel. 243218893Sdim // [1;2^30) Physical registers assigned by TableGen. 244218893Sdim // [2^30;2^31) Stack slots. (Rarely used.) 245218893Sdim // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo. 246218893Sdim // 247218893Sdim // Further sentinels can be allocated from the small negative integers. 248218893Sdim // DenseMapInfo<unsigned> uses -1u and -2u. 249193323Sed 250218893Sdim /// isStackSlot - Sometimes it is useful the be able to store a non-negative 251218893Sdim /// frame index in a variable that normally holds a register. isStackSlot() 252218893Sdim /// returns true if Reg is in the range used for stack slots. 253218893Sdim /// 254218893Sdim /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack 255218893Sdim /// slots, so if a variable may contains a stack slot, always check 256218893Sdim /// isStackSlot() first. 257218893Sdim /// 258218893Sdim static bool isStackSlot(unsigned Reg) { 259218893Sdim return int(Reg) >= (1 << 30); 260218893Sdim } 261193323Sed 262218893Sdim /// stackSlot2Index - Compute the frame index from a register value 263218893Sdim /// representing a stack slot. 264218893Sdim static int stackSlot2Index(unsigned Reg) { 265218893Sdim assert(isStackSlot(Reg) && "Not a stack slot"); 266218893Sdim return int(Reg - (1u << 30)); 267218893Sdim } 268218893Sdim 269218893Sdim /// index2StackSlot - Convert a non-negative frame index to a stack slot 270218893Sdim /// register value. 271218893Sdim static unsigned index2StackSlot(int FI) { 272218893Sdim assert(FI >= 0 && "Cannot hold a negative frame index."); 273218893Sdim return FI + (1u << 30); 274218893Sdim } 275218893Sdim 276193323Sed /// isPhysicalRegister - Return true if the specified register number is in 277193323Sed /// the physical register namespace. 278193323Sed static bool isPhysicalRegister(unsigned Reg) { 279218893Sdim assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); 280218893Sdim return int(Reg) > 0; 281193323Sed } 282193323Sed 283193323Sed /// isVirtualRegister - Return true if the specified register number is in 284193323Sed /// the virtual register namespace. 285193323Sed static bool isVirtualRegister(unsigned Reg) { 286218893Sdim assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); 287218893Sdim return int(Reg) < 0; 288193323Sed } 289193323Sed 290218893Sdim /// virtReg2Index - Convert a virtual register number to a 0-based index. 291218893Sdim /// The first virtual register in a function will get the index 0. 292218893Sdim static unsigned virtReg2Index(unsigned Reg) { 293218893Sdim assert(isVirtualRegister(Reg) && "Not a virtual register"); 294223017Sdim return Reg & ~(1u << 31); 295218893Sdim } 296218893Sdim 297218893Sdim /// index2VirtReg - Convert a 0-based index to a virtual register number. 298218893Sdim /// This is the inverse operation of VirtReg2IndexFunctor below. 299218893Sdim static unsigned index2VirtReg(unsigned Index) { 300223017Sdim return Index | (1u << 31); 301218893Sdim } 302218893Sdim 303210299Sed /// getMinimalPhysRegClass - Returns the Register Class of a physical 304210299Sed /// register of the given type, picking the most sub register class of 305210299Sed /// the right type that contains this physreg. 306210299Sed const TargetRegisterClass * 307210299Sed getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const; 308193323Sed 309239462Sdim /// getAllocatableClass - Return the maximal subclass of the given register 310239462Sdim /// class that is alloctable, or NULL. 311239462Sdim const TargetRegisterClass * 312239462Sdim getAllocatableClass(const TargetRegisterClass *RC) const; 313239462Sdim 314193323Sed /// getAllocatableSet - Returns a bitset indexed by register number 315193323Sed /// indicating if a register is allocatable or not. If a register class is 316193323Sed /// specified, returns the subset for the class. 317198090Srdivacky BitVector getAllocatableSet(const MachineFunction &MF, 318193323Sed const TargetRegisterClass *RC = NULL) const; 319193323Sed 320221345Sdim /// getCostPerUse - Return the additional cost of using this register instead 321221345Sdim /// of other registers in its class. 322221345Sdim unsigned getCostPerUse(unsigned RegNo) const { 323224145Sdim return InfoDesc[RegNo].CostPerUse; 324221345Sdim } 325221345Sdim 326224145Sdim /// isInAllocatableClass - Return true if the register is in the allocation 327224145Sdim /// of any register class. 328224145Sdim bool isInAllocatableClass(unsigned RegNo) const { 329224145Sdim return InfoDesc[RegNo].inAllocatableClass; 330193323Sed } 331193323Sed 332208599Srdivacky /// getSubRegIndexName - Return the human-readable symbolic target-specific 333208599Srdivacky /// name for the specified SubRegIndex. 334208599Srdivacky const char *getSubRegIndexName(unsigned SubIdx) const { 335243830Sdim assert(SubIdx && SubIdx < getNumSubRegIndices() && 336243830Sdim "This is not a subregister index"); 337208599Srdivacky return SubRegIndexNames[SubIdx-1]; 338208599Srdivacky } 339208599Srdivacky 340243830Sdim /// getSubRegIndexLaneMask - Return a bitmask representing the parts of a 341243830Sdim /// register that are covered by SubIdx. 342243830Sdim /// 343243830Sdim /// Lane masks for sub-register indices are similar to register units for 344243830Sdim /// physical registers. The individual bits in a lane mask can't be assigned 345243830Sdim /// any specific meaning. They can be used to check if two sub-register 346243830Sdim /// indices overlap. 347243830Sdim /// 348243830Sdim /// If the target has a register such that: 349243830Sdim /// 350243830Sdim /// getSubReg(Reg, A) overlaps getSubReg(Reg, B) 351243830Sdim /// 352243830Sdim /// then: 353243830Sdim /// 354243830Sdim /// getSubRegIndexLaneMask(A) & getSubRegIndexLaneMask(B) != 0 355243830Sdim /// 356243830Sdim /// The converse is not necessarily true. If two lane masks have a common 357243830Sdim /// bit, the corresponding sub-registers may not overlap, but it can be 358243830Sdim /// assumed that they usually will. 359243830Sdim unsigned getSubRegIndexLaneMask(unsigned SubIdx) const { 360243830Sdim // SubIdx == 0 is allowed, it has the lane mask ~0u. 361243830Sdim assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index"); 362243830Sdim return SubRegIndexLaneMasks[SubIdx]; 363243830Sdim } 364243830Sdim 365198090Srdivacky /// regsOverlap - Returns true if the two registers are equal or alias each 366198090Srdivacky /// other. The registers may be virtual register. 367198090Srdivacky bool regsOverlap(unsigned regA, unsigned regB) const { 368224145Sdim if (regA == regB) return true; 369198090Srdivacky if (isVirtualRegister(regA) || isVirtualRegister(regB)) 370198090Srdivacky return false; 371239462Sdim 372239462Sdim // Regunits are numerically ordered. Find a common unit. 373239462Sdim MCRegUnitIterator RUA(regA, this); 374239462Sdim MCRegUnitIterator RUB(regB, this); 375239462Sdim do { 376239462Sdim if (*RUA == *RUB) return true; 377239462Sdim if (*RUA < *RUB) ++RUA; 378239462Sdim else ++RUB; 379239462Sdim } while (RUA.isValid() && RUB.isValid()); 380193323Sed return false; 381193323Sed } 382193323Sed 383239462Sdim /// hasRegUnit - Returns true if Reg contains RegUnit. 384239462Sdim bool hasRegUnit(unsigned Reg, unsigned RegUnit) const { 385239462Sdim for (MCRegUnitIterator Units(Reg, this); Units.isValid(); ++Units) 386239462Sdim if (*Units == RegUnit) 387239462Sdim return true; 388239462Sdim return false; 389239462Sdim } 390239462Sdim 391193323Sed /// getCalleeSavedRegs - Return a null-terminated list of all of the 392193323Sed /// callee saved registers on this target. The register should be in the 393193323Sed /// order of desired callee-save stack frame offset. The first register is 394234353Sdim /// closest to the incoming stack pointer if stack grows down, and vice versa. 395234353Sdim /// 396249423Sdim virtual const MCPhysReg* getCalleeSavedRegs(const MachineFunction *MF = 0) 397193323Sed const = 0; 398193323Sed 399234353Sdim /// getCallPreservedMask - Return a mask of call-preserved registers for the 400234353Sdim /// given calling convention on the current sub-target. The mask should 401234353Sdim /// include all call-preserved aliases. This is used by the register 402234353Sdim /// allocator to determine which registers can be live across a call. 403234353Sdim /// 404234353Sdim /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries. 405234353Sdim /// A set bit indicates that all bits of the corresponding register are 406234353Sdim /// preserved across the function call. The bit mask is expected to be 407234353Sdim /// sub-register complete, i.e. if A is preserved, so are all its 408234353Sdim /// sub-registers. 409234353Sdim /// 410234353Sdim /// Bits are numbered from the LSB, so the bit for physical register Reg can 411234353Sdim /// be found as (Mask[Reg / 32] >> Reg % 32) & 1. 412234353Sdim /// 413234353Sdim /// A NULL pointer means that no register mask will be used, and call 414234353Sdim /// instructions should use implicit-def operands to indicate call clobbered 415234353Sdim /// registers. 416234353Sdim /// 417234353Sdim virtual const uint32_t *getCallPreservedMask(CallingConv::ID) const { 418234353Sdim // The default mask clobbers everything. All targets should override. 419234353Sdim return 0; 420234353Sdim } 421193323Sed 422193323Sed /// getReservedRegs - Returns a bitset indexed by physical register number 423193323Sed /// indicating if a register is a special register that has particular uses 424193323Sed /// and should be considered unavailable at all times, e.g. SP, RA. This is 425193323Sed /// used by register scavenger to determine what registers are free. 426193323Sed virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0; 427193323Sed 428193323Sed /// getMatchingSuperReg - Return a super-register of the specified register 429193323Sed /// Reg so its sub-register of index SubIdx is Reg. 430198090Srdivacky unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 431193323Sed const TargetRegisterClass *RC) const { 432234353Sdim return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC); 433193323Sed } 434193323Sed 435198090Srdivacky /// getMatchingSuperRegClass - Return a subclass of the specified register 436198090Srdivacky /// class A so that each register in it has a sub-register of the 437198090Srdivacky /// specified sub-register index which is in the specified register class B. 438234353Sdim /// 439234353Sdim /// TableGen will synthesize missing A sub-classes. 440198090Srdivacky virtual const TargetRegisterClass * 441198090Srdivacky getMatchingSuperRegClass(const TargetRegisterClass *A, 442239462Sdim const TargetRegisterClass *B, unsigned Idx) const; 443198090Srdivacky 444226633Sdim /// getSubClassWithSubReg - Returns the largest legal sub-class of RC that 445226633Sdim /// supports the sub-register index Idx. 446226633Sdim /// If no such sub-class exists, return NULL. 447226633Sdim /// If all registers in RC already have an Idx sub-register, return RC. 448226633Sdim /// 449226633Sdim /// TableGen generates a version of this function that is good enough in most 450226633Sdim /// cases. Targets can override if they have constraints that TableGen 451226633Sdim /// doesn't understand. For example, the x86 sub_8bit sub-register index is 452226633Sdim /// supported by the full GR32 register class in 64-bit mode, but only by the 453226633Sdim /// GR32_ABCD regiister class in 32-bit mode. 454226633Sdim /// 455234353Sdim /// TableGen will synthesize missing RC sub-classes. 456226633Sdim virtual const TargetRegisterClass * 457239462Sdim getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const { 458239462Sdim assert(Idx == 0 && "Target has no sub-registers"); 459239462Sdim return RC; 460239462Sdim } 461226633Sdim 462210299Sed /// composeSubRegIndices - Return the subregister index you get from composing 463210299Sed /// two subregister indices. 464210299Sed /// 465243830Sdim /// The special null sub-register index composes as the identity. 466243830Sdim /// 467210299Sed /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b) 468210299Sed /// returns c. Note that composeSubRegIndices does not tell you about illegal 469210299Sed /// compositions. If R does not have a subreg a, or R:a does not have a subreg 470210299Sed /// b, composeSubRegIndices doesn't tell you. 471210299Sed /// 472210299Sed /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has 473210299Sed /// ssub_0:S0 - ssub_3:S3 subregs. 474210299Sed /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2. 475210299Sed /// 476243830Sdim unsigned composeSubRegIndices(unsigned a, unsigned b) const { 477243830Sdim if (!a) return b; 478243830Sdim if (!b) return a; 479243830Sdim return composeSubRegIndicesImpl(a, b); 480210299Sed } 481210299Sed 482243830Sdimprotected: 483243830Sdim /// Overridden by TableGen in targets that have sub-registers. 484243830Sdim virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const { 485243830Sdim llvm_unreachable("Target has no sub-registers"); 486243830Sdim } 487243830Sdim 488243830Sdimpublic: 489239462Sdim /// getCommonSuperRegClass - Find a common super-register class if it exists. 490239462Sdim /// 491239462Sdim /// Find a register class, SuperRC and two sub-register indices, PreA and 492239462Sdim /// PreB, such that: 493239462Sdim /// 494239462Sdim /// 1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and 495239462Sdim /// 496239462Sdim /// 2. For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and 497239462Sdim /// 498239462Sdim /// 3. SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()). 499239462Sdim /// 500239462Sdim /// SuperRC will be chosen such that no super-class of SuperRC satisfies the 501239462Sdim /// requirements, and there is no register class with a smaller spill size 502239462Sdim /// that satisfies the requirements. 503239462Sdim /// 504239462Sdim /// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead. 505239462Sdim /// 506239462Sdim /// Either of the PreA and PreB sub-register indices may be returned as 0. In 507239462Sdim /// that case, the returned register class will be a sub-class of the 508239462Sdim /// corresponding argument register class. 509239462Sdim /// 510239462Sdim /// The function returns NULL if no register class can be found. 511239462Sdim /// 512239462Sdim const TargetRegisterClass* 513239462Sdim getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, 514239462Sdim const TargetRegisterClass *RCB, unsigned SubB, 515239462Sdim unsigned &PreA, unsigned &PreB) const; 516239462Sdim 517193323Sed //===--------------------------------------------------------------------===// 518193323Sed // Register Class Information 519193323Sed // 520193323Sed 521193323Sed /// Register class iterators 522193323Sed /// 523193323Sed regclass_iterator regclass_begin() const { return RegClassBegin; } 524193323Sed regclass_iterator regclass_end() const { return RegClassEnd; } 525193323Sed 526193323Sed unsigned getNumRegClasses() const { 527193323Sed return (unsigned)(regclass_end()-regclass_begin()); 528193323Sed } 529198090Srdivacky 530193323Sed /// getRegClass - Returns the register class associated with the enumeration 531224145Sdim /// value. See class MCOperandInfo. 532193323Sed const TargetRegisterClass *getRegClass(unsigned i) const { 533210299Sed assert(i < getNumRegClasses() && "Register Class ID out of range"); 534210299Sed return RegClassBegin[i]; 535193323Sed } 536193323Sed 537226633Sdim /// getCommonSubClass - find the largest common subclass of A and B. Return 538226633Sdim /// NULL if there is no common subclass. 539226633Sdim const TargetRegisterClass * 540226633Sdim getCommonSubClass(const TargetRegisterClass *A, 541226633Sdim const TargetRegisterClass *B) const; 542226633Sdim 543193323Sed /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 544198090Srdivacky /// values. If a target supports multiple different pointer register classes, 545198090Srdivacky /// kind specifies which one is indicated. 546239462Sdim virtual const TargetRegisterClass * 547239462Sdim getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const { 548234353Sdim llvm_unreachable("Target didn't implement getPointerRegClass!"); 549193323Sed } 550193323Sed 551193323Sed /// getCrossCopyRegClass - Returns a legal register class to copy a register 552221345Sdim /// in the specified class to or from. If it is possible to copy the register 553221345Sdim /// directly without using a cross register class copy, return the specified 554221345Sdim /// RC. Returns NULL if it is not possible to copy between a two registers of 555221345Sdim /// the specified class. 556193323Sed virtual const TargetRegisterClass * 557193323Sed getCrossCopyRegClass(const TargetRegisterClass *RC) const { 558221345Sdim return RC; 559193323Sed } 560193323Sed 561221345Sdim /// getLargestLegalSuperClass - Returns the largest super class of RC that is 562221345Sdim /// legal to use in the current sub-target and has the same spill size. 563221345Sdim /// The returned register class can be used to create virtual registers which 564221345Sdim /// means that all its registers can be copied and spilled. 565221345Sdim virtual const TargetRegisterClass* 566221345Sdim getLargestLegalSuperClass(const TargetRegisterClass *RC) const { 567221345Sdim /// The default implementation is very conservative and doesn't allow the 568221345Sdim /// register allocator to inflate register classes. 569221345Sdim return RC; 570221345Sdim } 571221345Sdim 572221345Sdim /// getRegPressureLimit - Return the register pressure "high water mark" for 573221345Sdim /// the specific register class. The scheduler is in high register pressure 574221345Sdim /// mode (for the specific register class) if it goes over the limit. 575234353Sdim /// 576234353Sdim /// Note: this is the old register pressure model that relies on a manually 577234353Sdim /// specified representative register class per value type. 578221345Sdim virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, 579221345Sdim MachineFunction &MF) const { 580221345Sdim return 0; 581221345Sdim } 582221345Sdim 583249423Sdim /// Get the weight in units of pressure for this register class. 584234353Sdim virtual const RegClassWeight &getRegClassWeight( 585234353Sdim const TargetRegisterClass *RC) const = 0; 586234353Sdim 587249423Sdim /// Get the weight in units of pressure for this register unit. 588249423Sdim virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0; 589249423Sdim 590234353Sdim /// Get the number of dimensions of register pressure. 591234353Sdim virtual unsigned getNumRegPressureSets() const = 0; 592234353Sdim 593239462Sdim /// Get the name of this register unit pressure set. 594239462Sdim virtual const char *getRegPressureSetName(unsigned Idx) const = 0; 595239462Sdim 596234353Sdim /// Get the register unit pressure limit for this dimension. 597234353Sdim /// This limit must be adjusted dynamically for reserved registers. 598234353Sdim virtual unsigned getRegPressureSetLimit(unsigned Idx) const = 0; 599234353Sdim 600234353Sdim /// Get the dimensions of register pressure impacted by this register class. 601234353Sdim /// Returns a -1 terminated array of pressure set IDs. 602234353Sdim virtual const int *getRegClassPressureSets( 603234353Sdim const TargetRegisterClass *RC) const = 0; 604234353Sdim 605249423Sdim /// Get the dimensions of register pressure impacted by this register unit. 606249423Sdim /// Returns a -1 terminated array of pressure set IDs. 607249423Sdim virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0; 608249423Sdim 609249423Sdim /// Get a list of 'hint' registers that the register allocator should try 610249423Sdim /// first when allocating a physical register for the virtual register 611249423Sdim /// VirtReg. These registers are effectively moved to the front of the 612249423Sdim /// allocation order. 613224145Sdim /// 614249423Sdim /// The Order argument is the allocation order for VirtReg's register class 615249423Sdim /// as returned from RegisterClassInfo::getOrder(). The hint registers must 616249423Sdim /// come from Order, and they must not be reserved. 617249423Sdim /// 618249423Sdim /// The default implementation of this function can resolve 619249423Sdim /// target-independent hints provided to MRI::setRegAllocationHint with 620249423Sdim /// HintType == 0. Targets that override this function should defer to the 621249423Sdim /// default implementation if they have no reason to change the allocation 622249423Sdim /// order for VirtReg. There may be target-independent hints. 623249423Sdim virtual void getRegAllocationHints(unsigned VirtReg, 624249423Sdim ArrayRef<MCPhysReg> Order, 625249423Sdim SmallVectorImpl<MCPhysReg> &Hints, 626249423Sdim const MachineFunction &MF, 627249423Sdim const VirtRegMap *VRM = 0) const; 628194612Sed 629221345Sdim /// avoidWriteAfterWrite - Return true if the register allocator should avoid 630221345Sdim /// writing a register from RC in two consecutive instructions. 631221345Sdim /// This can avoid pipeline stalls on certain architectures. 632221345Sdim /// It does cause increased register pressure, though. 633221345Sdim virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const { 634221345Sdim return false; 635221345Sdim } 636221345Sdim 637194612Sed /// UpdateRegAllocHint - A callback to allow target a chance to update 638194612Sed /// register allocation hints when a register is "changed" (e.g. coalesced) 639194612Sed /// to another register. e.g. On ARM, some virtual registers should target 640194612Sed /// register pairs, if one of pair is coalesced to another register, the 641194612Sed /// allocation hint of the other half of the pair should be changed to point 642194612Sed /// to the new register. 643194612Sed virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 644194612Sed MachineFunction &MF) const { 645194612Sed // Do nothing. 646194612Sed } 647194612Sed 648193323Sed /// requiresRegisterScavenging - returns true if the target requires (and can 649193323Sed /// make use of) the register scavenger. 650193323Sed virtual bool requiresRegisterScavenging(const MachineFunction &MF) const { 651193323Sed return false; 652193323Sed } 653198090Srdivacky 654221345Sdim /// useFPForScavengingIndex - returns true if the target wants to use 655221345Sdim /// frame pointer based accesses to spill to the scavenger emergency spill 656221345Sdim /// slot. 657221345Sdim virtual bool useFPForScavengingIndex(const MachineFunction &MF) const { 658221345Sdim return true; 659221345Sdim } 660221345Sdim 661198090Srdivacky /// requiresFrameIndexScavenging - returns true if the target requires post 662198090Srdivacky /// PEI scavenging of registers for materializing frame index constants. 663198090Srdivacky virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const { 664198090Srdivacky return false; 665198090Srdivacky } 666198090Srdivacky 667212904Sdim /// requiresVirtualBaseRegisters - Returns true if the target wants the 668212904Sdim /// LocalStackAllocation pass to be run and virtual base registers 669212904Sdim /// used for more efficient stack access. 670212904Sdim virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const { 671212904Sdim return false; 672212904Sdim } 673212904Sdim 674198090Srdivacky /// hasReservedSpillSlot - Return true if target has reserved a spill slot in 675198090Srdivacky /// the stack frame of the given function for the specified register. e.g. On 676198090Srdivacky /// x86, if the frame register is required, the first fixed stack object is 677198090Srdivacky /// reserved as its spill slot. This tells PEI not to create a new stack frame 678198090Srdivacky /// object for the given register. It should be called only after 679198090Srdivacky /// processFunctionBeforeCalleeSavedScan(). 680212904Sdim virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, 681198090Srdivacky int &FrameIdx) const { 682198090Srdivacky return false; 683198090Srdivacky } 684198090Srdivacky 685239462Sdim /// trackLivenessAfterRegAlloc - returns true if the live-ins should be tracked 686239462Sdim /// after register allocation. 687239462Sdim virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const { 688239462Sdim return false; 689239462Sdim } 690239462Sdim 691198090Srdivacky /// needsStackRealignment - true if storage within the function requires the 692198090Srdivacky /// stack pointer to be aligned more than the normal calling convention calls 693198090Srdivacky /// for. 694193323Sed virtual bool needsStackRealignment(const MachineFunction &MF) const { 695193323Sed return false; 696193323Sed } 697193323Sed 698212904Sdim /// getFrameIndexInstrOffset - Get the offset from the referenced frame 699218893Sdim /// index in the instruction, if there is one. 700212904Sdim virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI, 701212904Sdim int Idx) const { 702212904Sdim return 0; 703212904Sdim } 704212904Sdim 705212904Sdim /// needsFrameBaseReg - Returns true if the instruction's frame index 706212904Sdim /// reference would be better served by a base register other than FP 707212904Sdim /// or SP. Used by LocalStackFrameAllocation to determine which frame index 708212904Sdim /// references it should create new base registers for. 709212904Sdim virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 710212904Sdim return false; 711212904Sdim } 712212904Sdim 713212904Sdim /// materializeFrameBaseRegister - Insert defining instruction(s) for 714212904Sdim /// BaseReg to be a pointer to FrameIdx before insertion point I. 715218893Sdim virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB, 716212904Sdim unsigned BaseReg, int FrameIdx, 717212904Sdim int64_t Offset) const { 718234353Sdim llvm_unreachable("materializeFrameBaseRegister does not exist on this " 719234353Sdim "target"); 720212904Sdim } 721212904Sdim 722212904Sdim /// resolveFrameIndex - Resolve a frame index operand of an instruction 723212904Sdim /// to reference the indicated base register plus offset instead. 724212904Sdim virtual void resolveFrameIndex(MachineBasicBlock::iterator I, 725212904Sdim unsigned BaseReg, int64_t Offset) const { 726234353Sdim llvm_unreachable("resolveFrameIndex does not exist on this target"); 727212904Sdim } 728212904Sdim 729212904Sdim /// isFrameOffsetLegal - Determine whether a given offset immediate is 730212904Sdim /// encodable to resolve a frame index. 731212904Sdim virtual bool isFrameOffsetLegal(const MachineInstr *MI, 732212904Sdim int64_t Offset) const { 733234353Sdim llvm_unreachable("isFrameOffsetLegal does not exist on this target"); 734212904Sdim } 735212904Sdim 736193323Sed 737198396Srdivacky /// saveScavengerRegister - Spill the register so it can be used by the 738198396Srdivacky /// register scavenger. Return true if the register was spilled, false 739198396Srdivacky /// otherwise. If this function does not spill the register, the scavenger 740198090Srdivacky /// will instead spill it to the emergency spill slot. 741198090Srdivacky /// 742198090Srdivacky virtual bool saveScavengerRegister(MachineBasicBlock &MBB, 743198090Srdivacky MachineBasicBlock::iterator I, 744198396Srdivacky MachineBasicBlock::iterator &UseMI, 745198090Srdivacky const TargetRegisterClass *RC, 746199989Srdivacky unsigned Reg) const { 747199989Srdivacky return false; 748199989Srdivacky } 749198090Srdivacky 750193323Sed /// eliminateFrameIndex - This method must be overriden to eliminate abstract 751193323Sed /// frame indices from instructions which may use them. The instruction 752193323Sed /// referenced by the iterator contains an MO_FrameIndex operand which must be 753193323Sed /// eliminated by this method. This method may modify or replace the 754202375Srdivacky /// specified instruction, as long as it keeps the iterator pointing at the 755249423Sdim /// finished product. SPAdj is the SP adjustment due to call frame setup 756249423Sdim /// instruction. FIOperandNum is the FI operand number. 757212904Sdim virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, 758249423Sdim int SPAdj, unsigned FIOperandNum, 759249423Sdim RegScavenger *RS = NULL) const = 0; 760193323Sed 761193323Sed //===--------------------------------------------------------------------===// 762193323Sed /// Debug information queries. 763198090Srdivacky 764193323Sed /// getFrameRegister - This method should return the register used as a base 765193323Sed /// for values allocated in the current stack frame. 766199481Srdivacky virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0; 767193323Sed 768224145Sdim /// getCompactUnwindRegNum - This function maps the register to the number for 769224145Sdim /// compact unwind encoding. Return -1 if the register isn't valid. 770224145Sdim virtual int getCompactUnwindRegNum(unsigned, bool) const { 771224145Sdim return -1; 772224145Sdim } 773193323Sed}; 774193323Sed 775193323Sed 776239462Sdim//===----------------------------------------------------------------------===// 777239462Sdim// SuperRegClassIterator 778239462Sdim//===----------------------------------------------------------------------===// 779239462Sdim// 780239462Sdim// Iterate over the possible super-registers for a given register class. The 781239462Sdim// iterator will visit a list of pairs (Idx, Mask) corresponding to the 782239462Sdim// possible classes of super-registers. 783239462Sdim// 784239462Sdim// Each bit mask will have at least one set bit, and each set bit in Mask 785239462Sdim// corresponds to a SuperRC such that: 786239462Sdim// 787239462Sdim// For all Reg in SuperRC: Reg:Idx is in RC. 788239462Sdim// 789239462Sdim// The iterator can include (O, RC->getSubClassMask()) as the first entry which 790239462Sdim// also satisfies the above requirement, assuming Reg:0 == Reg. 791239462Sdim// 792239462Sdimclass SuperRegClassIterator { 793239462Sdim const unsigned RCMaskWords; 794239462Sdim unsigned SubReg; 795239462Sdim const uint16_t *Idx; 796239462Sdim const uint32_t *Mask; 797239462Sdim 798239462Sdimpublic: 799239462Sdim /// Create a SuperRegClassIterator that visits all the super-register classes 800239462Sdim /// of RC. When IncludeSelf is set, also include the (0, sub-classes) entry. 801239462Sdim SuperRegClassIterator(const TargetRegisterClass *RC, 802239462Sdim const TargetRegisterInfo *TRI, 803239462Sdim bool IncludeSelf = false) 804239462Sdim : RCMaskWords((TRI->getNumRegClasses() + 31) / 32), 805239462Sdim SubReg(0), 806239462Sdim Idx(RC->getSuperRegIndices()), 807239462Sdim Mask(RC->getSubClassMask()) { 808239462Sdim if (!IncludeSelf) 809239462Sdim ++*this; 810239462Sdim } 811239462Sdim 812239462Sdim /// Returns true if this iterator is still pointing at a valid entry. 813239462Sdim bool isValid() const { return Idx; } 814239462Sdim 815239462Sdim /// Returns the current sub-register index. 816239462Sdim unsigned getSubReg() const { return SubReg; } 817239462Sdim 818239462Sdim /// Returns the bit mask if register classes that getSubReg() projects into 819239462Sdim /// RC. 820239462Sdim const uint32_t *getMask() const { return Mask; } 821239462Sdim 822239462Sdim /// Advance iterator to the next entry. 823239462Sdim void operator++() { 824239462Sdim assert(isValid() && "Cannot move iterator past end."); 825239462Sdim Mask += RCMaskWords; 826239462Sdim SubReg = *Idx++; 827239462Sdim if (!SubReg) 828239462Sdim Idx = 0; 829239462Sdim } 830239462Sdim}; 831239462Sdim 832193323Sed// This is useful when building IndexedMaps keyed on virtual registers 833198090Srdivackystruct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> { 834193323Sed unsigned operator()(unsigned Reg) const { 835218893Sdim return TargetRegisterInfo::virtReg2Index(Reg); 836193323Sed } 837193323Sed}; 838193323Sed 839218893Sdim/// PrintReg - Helper class for printing registers on a raw_ostream. 840218893Sdim/// Prints virtual and physical registers with or without a TRI instance. 841218893Sdim/// 842218893Sdim/// The format is: 843218893Sdim/// %noreg - NoRegister 844218893Sdim/// %vreg5 - a virtual register. 845218893Sdim/// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI). 846218893Sdim/// %EAX - a physical register 847218893Sdim/// %physreg17 - a physical register when no TRI instance given. 848218893Sdim/// 849218893Sdim/// Usage: OS << PrintReg(Reg, TRI) << '\n'; 850218893Sdim/// 851218893Sdimclass PrintReg { 852218893Sdim const TargetRegisterInfo *TRI; 853218893Sdim unsigned Reg; 854218893Sdim unsigned SubIdx; 855218893Sdimpublic: 856249423Sdim explicit PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0, 857249423Sdim unsigned subidx = 0) 858218893Sdim : TRI(tri), Reg(reg), SubIdx(subidx) {} 859218893Sdim void print(raw_ostream&) const; 860218893Sdim}; 861218893Sdim 862218893Sdimstatic inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) { 863218893Sdim PR.print(OS); 864218893Sdim return OS; 865218893Sdim} 866218893Sdim 867239462Sdim/// PrintRegUnit - Helper class for printing register units on a raw_ostream. 868239462Sdim/// 869239462Sdim/// Register units are named after their root registers: 870239462Sdim/// 871239462Sdim/// AL - Single root. 872239462Sdim/// FP0~ST7 - Dual roots. 873239462Sdim/// 874239462Sdim/// Usage: OS << PrintRegUnit(Unit, TRI) << '\n'; 875239462Sdim/// 876239462Sdimclass PrintRegUnit { 877239462Sdim const TargetRegisterInfo *TRI; 878239462Sdim unsigned Unit; 879239462Sdimpublic: 880239462Sdim PrintRegUnit(unsigned unit, const TargetRegisterInfo *tri) 881239462Sdim : TRI(tri), Unit(unit) {} 882239462Sdim void print(raw_ostream&) const; 883239462Sdim}; 884239462Sdim 885239462Sdimstatic inline raw_ostream &operator<<(raw_ostream &OS, const PrintRegUnit &PR) { 886239462Sdim PR.print(OS); 887239462Sdim return OS; 888239462Sdim} 889239462Sdim 890193323Sed} // End llvm namespace 891193323Sed 892193323Sed#endif 893