1115462Sdes;; Scheduling description for IBM RS64 processors.
2115462Sdes;;   Copyright (C) 2003, 2004 Free Software Foundation, Inc.
3115462Sdes;;
4115462Sdes;; This file is part of GCC.
5115462Sdes
6115462Sdes;; GCC is free software; you can redistribute it and/or modify it
7115462Sdes;; under the terms of the GNU General Public License as published
8115462Sdes;; by the Free Software Foundation; either version 2, or (at your
9115462Sdes;; option) any later version.
10115462Sdes
11115462Sdes;; GCC is distributed in the hope that it will be useful, but WITHOUT
12115462Sdes;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13115462Sdes;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
14115462Sdes;; License for more details.
15115462Sdes
16115462Sdes;; You should have received a copy of the GNU General Public License
17115462Sdes;; along with GCC; see the file COPYING.  If not, write to the
18115462Sdes;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
19115462Sdes;; MA 02110-1301, USA.
20115462Sdes
21115462Sdes(define_automaton "rs64,rs64fp")
22115462Sdes(define_cpu_unit "iu_rs64" "rs64")
23115462Sdes(define_cpu_unit "mciu_rs64" "rs64")
24115462Sdes(define_cpu_unit "fpu_rs64" "rs64fp")
25115462Sdes(define_cpu_unit "lsu_rs64,bpu_rs64" "rs64")
26115462Sdes
27115462Sdes;; RS64a 64-bit IU, LSU, FPU, BPU
28115462Sdes
29115462Sdes(define_insn_reservation "rs64a-load" 2
30115462Sdes  (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u")
31115462Sdes       (eq_attr "cpu" "rs64a"))
32115462Sdes  "lsu_rs64")
33115462Sdes
34115462Sdes(define_insn_reservation "rs64a-store" 2
35115462Sdes  (and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u")
36115462Sdes       (eq_attr "cpu" "rs64a"))
37115462Sdes  "lsu_rs64")
38115462Sdes
39115462Sdes(define_insn_reservation "rs64a-fpload" 3
40115462Sdes  (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
41115462Sdes       (eq_attr "cpu" "rs64a"))
42115462Sdes  "lsu_rs64")
43115462Sdes
44115462Sdes(define_insn_reservation "rs64a-llsc" 2
45115462Sdes  (and (eq_attr "type" "load_l,store_c")
46115462Sdes       (eq_attr "cpu" "rs64a"))
47115462Sdes  "lsu_rs64")
48115462Sdes
49115462Sdes(define_insn_reservation "rs64a-integer" 1
50115462Sdes  (and (eq_attr "type" "integer,insert_word")
51115462Sdes       (eq_attr "cpu" "rs64a"))
52115462Sdes  "iu_rs64")
53115462Sdes
54115462Sdes(define_insn_reservation "rs64a-two" 1
55115462Sdes  (and (eq_attr "type" "two")
56115462Sdes       (eq_attr "cpu" "rs64a"))
57115462Sdes  "iu_rs64,iu_rs64")
58115462Sdes
59115462Sdes(define_insn_reservation "rs64a-three" 1
60115462Sdes  (and (eq_attr "type" "three")
61115462Sdes       (eq_attr "cpu" "rs64a"))
62115462Sdes  "iu_rs64,iu_rs64,iu_rs64")
63115462Sdes
64115462Sdes(define_insn_reservation "rs64a-imul" 20
65131608Sru  (and (eq_attr "type" "imul,imul_compare")
66115462Sdes       (eq_attr "cpu" "rs64a"))
67115462Sdes  "mciu_rs64*13")
68115462Sdes
69131608Sru(define_insn_reservation "rs64a-imul2" 12
70115462Sdes  (and (eq_attr "type" "imul2")
71115462Sdes       (eq_attr "cpu" "rs64a"))
72115462Sdes  "mciu_rs64*5")
73115462Sdes
74115462Sdes(define_insn_reservation "rs64a-imul3" 8
75115462Sdes  (and (eq_attr "type" "imul3")
76115462Sdes       (eq_attr "cpu" "rs64a"))
77115462Sdes  "mciu_rs64*2")
78115462Sdes
79115462Sdes(define_insn_reservation "rs64a-lmul" 34
80115462Sdes  (and (eq_attr "type" "lmul,lmul_compare")
81115462Sdes       (eq_attr "cpu" "rs64a"))
82115462Sdes  "mciu_rs64*34")
83115462Sdes
84115462Sdes(define_insn_reservation "rs64a-idiv" 66
85131594Sru  (and (eq_attr "type" "idiv")
86115462Sdes       (eq_attr "cpu" "rs64a"))
87115462Sdes  "mciu_rs64*66")
88115462Sdes
89115462Sdes(define_insn_reservation "rs64a-ldiv" 66
90115462Sdes  (and (eq_attr "type" "ldiv")
91115462Sdes       (eq_attr "cpu" "rs64a"))
92115462Sdes  "mciu_rs64*66")
93115462Sdes
94115462Sdes(define_insn_reservation "rs64a-compare" 3
95115462Sdes  (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare")
96131504Sru       (eq_attr "cpu" "rs64a"))
97115462Sdes  "iu_rs64,nothing,bpu_rs64")
98115462Sdes
99(define_insn_reservation "rs64a-fpcompare" 5
100  (and (eq_attr "type" "fpcompare")
101       (eq_attr "cpu" "rs64a"))
102  "mciu_rs64,fpu_rs64,bpu_rs64")
103
104(define_insn_reservation "rs64a-fp" 4
105  (and (eq_attr "type" "fp,dmul")
106       (eq_attr "cpu" "rs64a"))
107  "mciu_rs64,fpu_rs64")
108
109(define_insn_reservation "rs64a-sdiv" 31
110  (and (eq_attr "type" "sdiv,ddiv")
111       (eq_attr "cpu" "rs64a"))
112  "mciu_rs64,fpu_rs64*31")
113
114(define_insn_reservation "rs64a-sqrt" 49
115  (and (eq_attr "type" "ssqrt,dsqrt")
116       (eq_attr "cpu" "rs64a"))
117  "mciu_rs64,fpu_rs64*49")
118
119(define_insn_reservation "rs64a-mfcr" 2
120  (and (eq_attr "type" "mfcr")
121       (eq_attr "cpu" "rs64a"))
122  "lsu_rs64")
123
124(define_insn_reservation "rs64a-mtcr" 3
125  (and (eq_attr "type" "mtcr")
126       (eq_attr "cpu" "rs64a"))
127  "lsu_rs64")
128
129(define_insn_reservation "rs64a-mtjmpr" 3
130  (and (eq_attr "type" "mtjmpr")
131       (eq_attr "cpu" "rs64a"))
132  "lsu_rs64")
133
134(define_insn_reservation "rs64a-mfjmpr" 2
135  (and (eq_attr "type" "mfjmpr")
136       (eq_attr "cpu" "rs64a"))
137  "lsu_rs64")
138
139(define_insn_reservation "rs64a-jmpreg" 1
140  (and (eq_attr "type" "jmpreg,branch,cr_logical,delayed_cr")
141       (eq_attr "cpu" "rs64a"))
142  "bpu_rs64")
143
144(define_insn_reservation "rs64a-isync" 6
145  (and (eq_attr "type" "isync")
146       (eq_attr "cpu" "rs64a"))
147  "bpu_rs64")
148
149(define_insn_reservation "rs64a-sync" 1
150  (and (eq_attr "type" "sync")
151       (eq_attr "cpu" "rs64a"))
152  "lsu_rs64")
153
154