1132718Skan;; Scheduling description for PowerPC 604, PowerPC 604e, PowerPC 620, 2132718Skan;; and PowerPC 630 processors. 3169689Skan;; Copyright (C) 2003, 2004 Free Software Foundation, Inc. 4132718Skan;; 5132718Skan;; This file is part of GCC. 6132718Skan 7132718Skan;; GCC is free software; you can redistribute it and/or modify it 8132718Skan;; under the terms of the GNU General Public License as published 9132718Skan;; by the Free Software Foundation; either version 2, or (at your 10132718Skan;; option) any later version. 11132718Skan 12132718Skan;; GCC is distributed in the hope that it will be useful, but WITHOUT 13132718Skan;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14132718Skan;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15132718Skan;; License for more details. 16132718Skan 17132718Skan;; You should have received a copy of the GNU General Public License 18132718Skan;; along with GCC; see the file COPYING. If not, write to the 19169689Skan;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, 20169689Skan;; MA 02110-1301, USA. 21132718Skan 22132718Skan(define_automaton "ppc6xx,ppc6xxfp,ppc6xxfp2") 23132718Skan(define_cpu_unit "iu1_6xx,iu2_6xx,mciu_6xx" "ppc6xx") 24132718Skan(define_cpu_unit "fpu_6xx" "ppc6xxfp") 25132718Skan(define_cpu_unit "fpu1_6xx,fpu2_6xx" "ppc6xxfp2") 26132718Skan(define_cpu_unit "lsu_6xx,bpu_6xx,cru_6xx" "ppc6xx") 27132718Skan 28132718Skan;; PPC604 32-bit 2xSCIU, MCIU, LSU, FPU, BPU 29132718Skan;; PPC604e 32-bit 2xSCIU, MCIU, LSU, FPU, BPU, CRU 30132718Skan;; MCIU used for imul/idiv and moves from/to spr 31132718Skan;; LSU 2 stage pipelined 32132718Skan;; FPU 3 stage pipelined 33132718Skan;; Max issue 4 insns/clock cycle 34132718Skan 35132718Skan;; PPC604e is PPC604 with larger caches and a CRU. In the 604 36132718Skan;; the CR logical operations are handled in the BPU. 37132718Skan;; In the 604e, the CRU shares bus with BPU so only one condition 38132718Skan;; register or branch insn can be issued per clock. Not modelled. 39132718Skan 40132718Skan;; PPC620 64-bit 2xSCIU, MCIU, LSU, FPU, BPU, CRU 41132718Skan;; PPC630 64-bit 2xSCIU, MCIU, LSU, 2xFPU, BPU, CRU 42132718Skan;; Max issue 4 insns/clock cycle 43132718Skan;; Out-of-order execution, in-order completion 44132718Skan 45132718Skan;; No following instruction can dispatch in the same cycle as a branch 46132718Skan;; instruction. Not modelled. This is no problem if RCSP is not 47132718Skan;; enabled since the scheduler stops a schedule when it gets to a branch. 48132718Skan 49132718Skan;; Four insns can be dispatched per cycle. 50132718Skan 51132718Skan(define_insn_reservation "ppc604-load" 2 52132718Skan (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u") 53132718Skan (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) 54132718Skan "lsu_6xx") 55132718Skan 56132718Skan(define_insn_reservation "ppc604-fpload" 3 57132718Skan (and (eq_attr "type" "fpload,fpload_ux,fpload_u") 58132718Skan (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) 59132718Skan "lsu_6xx") 60132718Skan 61169689Skan(define_insn_reservation "ppc604-store" 3 62132718Skan (and (eq_attr "type" "store,fpstore,store_ux,store_u,fpstore_ux,fpstore_u") 63132718Skan (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) 64132718Skan "lsu_6xx") 65132718Skan 66169689Skan(define_insn_reservation "ppc604-llsc" 3 67169689Skan (and (eq_attr "type" "load_l,store_c") 68169689Skan (eq_attr "cpu" "ppc604,ppc604e")) 69169689Skan "lsu_6xx") 70169689Skan 71169689Skan(define_insn_reservation "ppc630-llsc" 4 72169689Skan (and (eq_attr "type" "load_l,store_c") 73169689Skan (eq_attr "cpu" "ppc620,ppc630")) 74169689Skan "lsu_6xx") 75169689Skan 76132718Skan(define_insn_reservation "ppc604-integer" 1 77132718Skan (and (eq_attr "type" "integer,insert_word") 78132718Skan (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) 79132718Skan "iu1_6xx|iu2_6xx") 80132718Skan 81169689Skan(define_insn_reservation "ppc604-two" 1 82169689Skan (and (eq_attr "type" "two") 83169689Skan (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) 84169689Skan "iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx") 85169689Skan 86169689Skan(define_insn_reservation "ppc604-three" 1 87169689Skan (and (eq_attr "type" "three") 88169689Skan (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) 89169689Skan "iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx") 90169689Skan 91132718Skan(define_insn_reservation "ppc604-imul" 4 92132718Skan (and (eq_attr "type" "imul,imul2,imul3,imul_compare") 93132718Skan (eq_attr "cpu" "ppc604")) 94132718Skan "mciu_6xx*2") 95132718Skan 96132718Skan(define_insn_reservation "ppc604e-imul" 2 97132718Skan (and (eq_attr "type" "imul,imul2,imul3,imul_compare") 98132718Skan (eq_attr "cpu" "ppc604e")) 99132718Skan "mciu_6xx") 100132718Skan 101132718Skan(define_insn_reservation "ppc620-imul" 5 102132718Skan (and (eq_attr "type" "imul,imul_compare") 103132718Skan (eq_attr "cpu" "ppc620,ppc630")) 104132718Skan "mciu_6xx*3") 105132718Skan 106132718Skan(define_insn_reservation "ppc620-imul2" 4 107132718Skan (and (eq_attr "type" "imul2") 108132718Skan (eq_attr "cpu" "ppc620,ppc630")) 109132718Skan "mciu_6xx*3") 110132718Skan 111132718Skan(define_insn_reservation "ppc620-imul3" 3 112132718Skan (and (eq_attr "type" "imul3") 113132718Skan (eq_attr "cpu" "ppc620,ppc630")) 114132718Skan "mciu_6xx*3") 115132718Skan 116132718Skan(define_insn_reservation "ppc620-lmul" 7 117132718Skan (and (eq_attr "type" "lmul,lmul_compare") 118132718Skan (eq_attr "cpu" "ppc620,ppc630")) 119132718Skan "mciu_6xx*5") 120132718Skan 121132718Skan(define_insn_reservation "ppc604-idiv" 20 122132718Skan (and (eq_attr "type" "idiv") 123132718Skan (eq_attr "cpu" "ppc604,ppc604e")) 124132718Skan "mciu_6xx*19") 125132718Skan 126132718Skan(define_insn_reservation "ppc620-idiv" 37 127132718Skan (and (eq_attr "type" "idiv") 128132718Skan (eq_attr "cpu" "ppc620")) 129132718Skan "mciu_6xx*36") 130132718Skan 131132718Skan(define_insn_reservation "ppc630-idiv" 21 132132718Skan (and (eq_attr "type" "idiv") 133132718Skan (eq_attr "cpu" "ppc630")) 134132718Skan "mciu_6xx*20") 135132718Skan 136132718Skan(define_insn_reservation "ppc620-ldiv" 37 137132718Skan (and (eq_attr "type" "ldiv") 138132718Skan (eq_attr "cpu" "ppc620,ppc630")) 139132718Skan "mciu_6xx*36") 140132718Skan 141132718Skan(define_insn_reservation "ppc604-compare" 3 142132718Skan (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare") 143132718Skan (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) 144132718Skan "(iu1_6xx|iu2_6xx)") 145132718Skan 146132718Skan; FPU PPC604{,e},PPC620 147132718Skan(define_insn_reservation "ppc604-fpcompare" 5 148132718Skan (and (eq_attr "type" "fpcompare") 149132718Skan (eq_attr "cpu" "ppc604,ppc604e,ppc620")) 150132718Skan "fpu_6xx") 151132718Skan 152132718Skan(define_insn_reservation "ppc604-fp" 3 153132718Skan (and (eq_attr "type" "fp") 154132718Skan (eq_attr "cpu" "ppc604,ppc604e,ppc620")) 155132718Skan "fpu_6xx") 156132718Skan 157132718Skan(define_insn_reservation "ppc604-dmul" 3 158132718Skan (and (eq_attr "type" "dmul") 159132718Skan (eq_attr "cpu" "ppc604,ppc604e,ppc620")) 160132718Skan "fpu_6xx") 161132718Skan 162132718Skan; Divides are not pipelined 163132718Skan(define_insn_reservation "ppc604-sdiv" 18 164132718Skan (and (eq_attr "type" "sdiv") 165132718Skan (eq_attr "cpu" "ppc604,ppc604e,ppc620")) 166132718Skan "fpu_6xx*18") 167132718Skan 168132718Skan(define_insn_reservation "ppc604-ddiv" 32 169132718Skan (and (eq_attr "type" "ddiv") 170132718Skan (eq_attr "cpu" "ppc604,ppc604e,ppc620")) 171132718Skan "fpu_6xx*32") 172132718Skan 173132718Skan(define_insn_reservation "ppc620-ssqrt" 31 174132718Skan (and (eq_attr "type" "ssqrt") 175132718Skan (eq_attr "cpu" "ppc620")) 176132718Skan "fpu_6xx*31") 177132718Skan 178132718Skan(define_insn_reservation "ppc620-dsqrt" 31 179132718Skan (and (eq_attr "type" "dsqrt") 180132718Skan (eq_attr "cpu" "ppc620")) 181132718Skan "fpu_6xx*31") 182132718Skan 183132718Skan 184132718Skan; 2xFPU PPC630 185132718Skan(define_insn_reservation "ppc630-fpcompare" 5 186132718Skan (and (eq_attr "type" "fpcompare") 187132718Skan (eq_attr "cpu" "ppc630")) 188132718Skan "fpu1_6xx|fpu2_6xx") 189132718Skan 190132718Skan(define_insn_reservation "ppc630-fp" 3 191132718Skan (and (eq_attr "type" "fp,dmul") 192132718Skan (eq_attr "cpu" "ppc630")) 193132718Skan "fpu1_6xx|fpu2_6xx") 194132718Skan 195132718Skan(define_insn_reservation "ppc630-sdiv" 17 196132718Skan (and (eq_attr "type" "sdiv") 197132718Skan (eq_attr "cpu" "ppc630")) 198132718Skan "fpu1_6xx*17|fpu2_6xx*17") 199132718Skan 200132718Skan(define_insn_reservation "ppc630-ddiv" 21 201132718Skan (and (eq_attr "type" "ddiv") 202132718Skan (eq_attr "cpu" "ppc630")) 203132718Skan "fpu1_6xx*21|fpu2_6xx*21") 204132718Skan 205132718Skan(define_insn_reservation "ppc630-ssqrt" 18 206132718Skan (and (eq_attr "type" "ssqrt") 207132718Skan (eq_attr "cpu" "ppc630")) 208132718Skan "fpu1_6xx*18|fpu2_6xx*18") 209132718Skan 210132718Skan(define_insn_reservation "ppc630-dsqrt" 25 211132718Skan (and (eq_attr "type" "dsqrt") 212132718Skan (eq_attr "cpu" "ppc630")) 213132718Skan "fpu1_6xx*25|fpu2_6xx*25") 214132718Skan 215132718Skan(define_insn_reservation "ppc604-mfcr" 3 216132718Skan (and (eq_attr "type" "mfcr") 217132718Skan (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) 218132718Skan "mciu_6xx") 219132718Skan 220132718Skan(define_insn_reservation "ppc604-mtcr" 2 221132718Skan (and (eq_attr "type" "mtcr") 222132718Skan (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) 223132718Skan "iu1_6xx|iu2_6xx") 224132718Skan 225132718Skan(define_insn_reservation "ppc604-crlogical" 2 226132718Skan (and (eq_attr "type" "cr_logical,delayed_cr") 227132718Skan (eq_attr "cpu" "ppc604")) 228132718Skan "bpu_6xx") 229132718Skan 230132718Skan(define_insn_reservation "ppc604e-crlogical" 2 231132718Skan (and (eq_attr "type" "cr_logical,delayed_cr") 232132718Skan (eq_attr "cpu" "ppc604e,ppc620,ppc630")) 233132718Skan "cru_6xx") 234132718Skan 235132718Skan(define_insn_reservation "ppc604-mtjmpr" 2 236132718Skan (and (eq_attr "type" "mtjmpr") 237132718Skan (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) 238132718Skan "mciu_6xx") 239132718Skan 240132718Skan(define_insn_reservation "ppc604-mfjmpr" 3 241132718Skan (and (eq_attr "type" "mfjmpr") 242132718Skan (eq_attr "cpu" "ppc604,ppc604e,ppc620")) 243132718Skan "mciu_6xx") 244132718Skan 245132718Skan(define_insn_reservation "ppc630-mfjmpr" 2 246132718Skan (and (eq_attr "type" "mfjmpr") 247132718Skan (eq_attr "cpu" "ppc630")) 248132718Skan "mciu_6xx") 249132718Skan 250132718Skan(define_insn_reservation "ppc604-jmpreg" 1 251132718Skan (and (eq_attr "type" "jmpreg,branch") 252132718Skan (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) 253132718Skan "bpu_6xx") 254132718Skan 255169689Skan(define_insn_reservation "ppc604-isync" 0 256169689Skan (and (eq_attr "type" "isync") 257169689Skan (eq_attr "cpu" "ppc604,ppc604e")) 258169689Skan "bpu_6xx") 259169689Skan 260169689Skan(define_insn_reservation "ppc630-isync" 6 261169689Skan (and (eq_attr "type" "isync") 262169689Skan (eq_attr "cpu" "ppc620,ppc630")) 263169689Skan "bpu_6xx") 264169689Skan 265169689Skan(define_insn_reservation "ppc604-sync" 35 266169689Skan (and (eq_attr "type" "sync") 267169689Skan (eq_attr "cpu" "ppc604,ppc604e")) 268169689Skan "lsu_6xx") 269169689Skan 270169689Skan(define_insn_reservation "ppc630-sync" 26 271169689Skan (and (eq_attr "type" "sync") 272169689Skan (eq_attr "cpu" "ppc620,ppc630")) 273169689Skan "lsu_6xx") 274169689Skan 275