1132718Skan;; Scheduling description for PowerPC 603 processor. 2169689Skan;; Copyright (C) 2003, 2004 Free Software Foundation, Inc. 3132718Skan;; 4132718Skan;; This file is part of GCC. 5132718Skan 6132718Skan;; GCC is free software; you can redistribute it and/or modify it 7132718Skan;; under the terms of the GNU General Public License as published 8132718Skan;; by the Free Software Foundation; either version 2, or (at your 9132718Skan;; option) any later version. 10132718Skan 11132718Skan;; GCC is distributed in the hope that it will be useful, but WITHOUT 12132718Skan;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13132718Skan;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14132718Skan;; License for more details. 15132718Skan 16132718Skan;; You should have received a copy of the GNU General Public License 17132718Skan;; along with GCC; see the file COPYING. If not, write to the 18169689Skan;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, 19169689Skan;; MA 02110-1301, USA. 20132718Skan 21132718Skan(define_automaton "ppc603,ppc603fp") 22132718Skan(define_cpu_unit "iu_603" "ppc603") 23132718Skan(define_cpu_unit "fpu_603" "ppc603fp") 24132718Skan(define_cpu_unit "lsu_603,bpu_603,sru_603" "ppc603") 25132718Skan 26132718Skan;; PPC603/PPC603e 32-bit IU, LSU, FPU, BPU, SRU 27132718Skan;; Max issue 3 insns/clock cycle (includes 1 branch) 28132718Skan 29132718Skan;; Branches go straight to the BPU. All other insns are handled 30132718Skan;; by a dispatch unit which can issue a max of 2 insns per cycle. 31132718Skan 32132718Skan;; The PPC603e user's manual recommends that to reduce branch mispredictions, 33132718Skan;; the insn that sets CR bits should be separated from the branch insn 34132718Skan;; that evaluates them; separation by more than 9 insns ensures that the CR 35132718Skan;; bits will be immediately available for execution. 36132718Skan;; This could be artificially achieved by exaggerating the latency of 37132718Skan;; compare insns but at the expense of a poorer schedule. 38132718Skan 39132718Skan;; CR insns get executed in the SRU. Not modelled. 40132718Skan 41132718Skan(define_insn_reservation "ppc603-load" 2 42169689Skan (and (eq_attr "type" "load,load_ext,load_ux,load_u,load_l") 43132718Skan (eq_attr "cpu" "ppc603")) 44132718Skan "lsu_603") 45132718Skan 46169689Skan(define_insn_reservation "ppc603-store" 2 47132718Skan (and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u") 48132718Skan (eq_attr "cpu" "ppc603")) 49169689Skan "lsu_603*2") 50132718Skan 51132718Skan(define_insn_reservation "ppc603-fpload" 2 52132718Skan (and (eq_attr "type" "fpload,fpload_ux,fpload_u") 53132718Skan (eq_attr "cpu" "ppc603")) 54132718Skan "lsu_603") 55132718Skan 56169689Skan(define_insn_reservation "ppc603-storec" 8 57169689Skan (and (eq_attr "type" "store_c") 58169689Skan (eq_attr "cpu" "ppc603")) 59169689Skan "lsu_603") 60169689Skan 61132718Skan(define_insn_reservation "ppc603-integer" 1 62132718Skan (and (eq_attr "type" "integer,insert_word") 63132718Skan (eq_attr "cpu" "ppc603")) 64132718Skan "iu_603") 65132718Skan 66169689Skan(define_insn_reservation "ppc603-two" 1 67169689Skan (and (eq_attr "type" "two") 68169689Skan (eq_attr "cpu" "ppc603")) 69169689Skan "iu_603,iu_603") 70169689Skan 71169689Skan(define_insn_reservation "ppc603-three" 1 72169689Skan (and (eq_attr "type" "three") 73169689Skan (eq_attr "cpu" "ppc603")) 74169689Skan "iu_603,iu_603,iu_603") 75169689Skan 76132718Skan; This takes 2 or 3 cycles 77132718Skan(define_insn_reservation "ppc603-imul" 3 78132718Skan (and (eq_attr "type" "imul,imul_compare") 79132718Skan (eq_attr "cpu" "ppc603")) 80132718Skan "iu_603*2") 81132718Skan 82132718Skan(define_insn_reservation "ppc603-imul2" 2 83132718Skan (and (eq_attr "type" "imul2,imul3") 84132718Skan (eq_attr "cpu" "ppc603")) 85132718Skan "iu_603*2") 86132718Skan 87132718Skan(define_insn_reservation "ppc603-idiv" 37 88132718Skan (and (eq_attr "type" "idiv") 89132718Skan (eq_attr "cpu" "ppc603")) 90132718Skan "iu_603*37") 91132718Skan 92132718Skan(define_insn_reservation "ppc603-compare" 3 93132718Skan (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare") 94132718Skan (eq_attr "cpu" "ppc603")) 95132718Skan "iu_603,nothing,bpu_603") 96132718Skan 97132718Skan(define_insn_reservation "ppc603-fpcompare" 3 98132718Skan (and (eq_attr "type" "fpcompare") 99132718Skan (eq_attr "cpu" "ppc603")) 100132718Skan "(fpu_603+iu_603*2),bpu_603") 101132718Skan 102132718Skan(define_insn_reservation "ppc603-fp" 3 103132718Skan (and (eq_attr "type" "fp") 104132718Skan (eq_attr "cpu" "ppc603")) 105132718Skan "fpu_603") 106132718Skan 107132718Skan(define_insn_reservation "ppc603-dmul" 4 108132718Skan (and (eq_attr "type" "dmul") 109132718Skan (eq_attr "cpu" "ppc603")) 110132718Skan "fpu_603*2") 111132718Skan 112132718Skan; Divides are not pipelined 113132718Skan(define_insn_reservation "ppc603-sdiv" 18 114132718Skan (and (eq_attr "type" "sdiv") 115132718Skan (eq_attr "cpu" "ppc603")) 116132718Skan "fpu_603*18") 117132718Skan 118132718Skan(define_insn_reservation "ppc603-ddiv" 33 119132718Skan (and (eq_attr "type" "ddiv") 120132718Skan (eq_attr "cpu" "ppc603")) 121132718Skan "fpu_603*33") 122132718Skan 123132718Skan(define_insn_reservation "ppc603-crlogical" 2 124132718Skan (and (eq_attr "type" "cr_logical,delayed_cr,mfcr,mtcr") 125132718Skan (eq_attr "cpu" "ppc603")) 126132718Skan "sru_603") 127132718Skan 128132718Skan(define_insn_reservation "ppc603-mtjmpr" 4 129132718Skan (and (eq_attr "type" "mtjmpr") 130132718Skan (eq_attr "cpu" "ppc603")) 131132718Skan "sru_603") 132132718Skan 133132718Skan(define_insn_reservation "ppc603-mfjmpr" 2 134169689Skan (and (eq_attr "type" "mfjmpr,isync,sync") 135132718Skan (eq_attr "cpu" "ppc603")) 136132718Skan "sru_603") 137132718Skan 138132718Skan(define_insn_reservation "ppc603-jmpreg" 1 139132718Skan (and (eq_attr "type" "jmpreg,branch") 140132718Skan (eq_attr "cpu" "ppc603")) 141132718Skan "bpu_603") 142132718Skan 143