tc-i386.h revision 94546
1/* tc-i386.h -- Header file for tc-i386.c 2 Copyright 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 3 2001 4 Free Software Foundation, Inc. 5 6 This file is part of GAS, the GNU Assembler. 7 8 GAS is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 2, or (at your option) 11 any later version. 12 13 GAS is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GAS; see the file COPYING. If not, write to the Free 20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 21 02111-1307, USA. */ 22 23 24/* $FreeBSD: head/contrib/binutils/gas/config/tc-i386.h 94546 2002-04-12 19:54:03Z obrien $ */ 25 26 27#ifndef TC_I386 28#define TC_I386 1 29 30#ifdef ANSI_PROTOTYPES 31struct fix; 32#endif 33 34#define TARGET_BYTES_BIG_ENDIAN 0 35 36#ifdef TE_LYNX 37#define TARGET_FORMAT "coff-i386-lynx" 38#endif 39 40#ifdef BFD_ASSEMBLER 41/* This is used to determine relocation types in tc-i386.c. The first 42 parameter is the current relocation type, the second one is the desired 43 type. The idea is that if the original type is already some kind of PIC 44 relocation, we leave it alone, otherwise we give it the desired type */ 45 46#define tc_fix_adjustable(X) tc_i386_fix_adjustable(X) 47extern int tc_i386_fix_adjustable PARAMS ((struct fix *)); 48 49#if (defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) || defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)) && !defined (TE_PE) 50/* This arranges for gas/write.c to not apply a relocation if 51 tc_fix_adjustable() says it is not adjustable. 52 The "! symbol_used_in_reloc_p" test is there specifically to cover 53 the case of non-global symbols in linkonce sections. It's the 54 generally correct thing to do though; If a reloc is going to be 55 emitted against a symbol then we don't want to adjust the fixup by 56 applying the reloc during assembly. The reloc will be applied by 57 the linker during final link. */ 58#define TC_FIX_ADJUSTABLE(fixP) \ 59 (! symbol_used_in_reloc_p ((fixP)->fx_addsy) && tc_fix_adjustable (fixP)) 60#endif 61 62/* This expression evaluates to false if the relocation is for a local object 63 for which we still want to do the relocation at runtime. True if we 64 are willing to perform this relocation while building the .o file. 65 This is only used for pcrel relocations, so GOTOFF does not need to be 66 checked here. I am not sure if some of the others are ever used with 67 pcrel, but it is easier to be safe than sorry. */ 68 69#define TC_RELOC_RTSYM_LOC_FIXUP(FIX) \ 70 ((FIX)->fx_r_type != BFD_RELOC_386_PLT32 \ 71 && (FIX)->fx_r_type != BFD_RELOC_386_GOT32 \ 72 && (FIX)->fx_r_type != BFD_RELOC_386_GOTPC \ 73 && ((FIX)->fx_addsy == NULL \ 74 || (! S_IS_EXTERNAL ((FIX)->fx_addsy) \ 75 && ! S_IS_WEAK ((FIX)->fx_addsy) \ 76 && S_IS_DEFINED ((FIX)->fx_addsy) \ 77 && ! S_IS_COMMON ((FIX)->fx_addsy)))) 78 79#define TARGET_ARCH bfd_arch_i386 80#define TARGET_MACH (i386_mach ()) 81extern unsigned long i386_mach PARAMS ((void)); 82 83#ifdef TE_FreeBSD 84#define AOUT_TARGET_FORMAT "a.out-i386-freebsd" 85#endif 86#ifdef TE_NetBSD 87#define AOUT_TARGET_FORMAT "a.out-i386-netbsd" 88#endif 89#ifdef TE_386BSD 90#define AOUT_TARGET_FORMAT "a.out-i386-bsd" 91#endif 92#ifdef TE_LINUX 93#define AOUT_TARGET_FORMAT "a.out-i386-linux" 94#endif 95#ifdef TE_Mach 96#define AOUT_TARGET_FORMAT "a.out-mach3" 97#endif 98#ifdef TE_DYNIX 99#define AOUT_TARGET_FORMAT "a.out-i386-dynix" 100#endif 101#ifndef AOUT_TARGET_FORMAT 102#define AOUT_TARGET_FORMAT "a.out-i386" 103#endif 104 105#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ 106 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) 107extern const char *i386_target_format PARAMS ((void)); 108#define TARGET_FORMAT i386_target_format () 109#else 110#ifdef OBJ_ELF 111#define TARGET_FORMAT "elf32-i386" 112#endif 113#ifdef OBJ_AOUT 114#define TARGET_FORMAT AOUT_TARGET_FORMAT 115#endif 116#endif 117 118#if (defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)) 119#define md_end i386_elf_emit_arch_note 120extern void i386_elf_emit_arch_note PARAMS ((void)); 121#endif 122 123#else /* ! BFD_ASSEMBLER */ 124 125/* COFF STUFF */ 126 127#define COFF_MAGIC I386MAGIC 128#define BFD_ARCH bfd_arch_i386 129#define COFF_FLAGS F_AR32WR 130#define TC_COUNT_RELOC(x) ((x)->fx_addsy || (x)->fx_r_type==7) 131#define TC_COFF_FIX2RTYPE(fixP) tc_coff_fix2rtype(fixP) 132extern short tc_coff_fix2rtype PARAMS ((struct fix *)); 133#define TC_COFF_SIZEMACHDEP(frag) tc_coff_sizemachdep (frag) 134extern int tc_coff_sizemachdep PARAMS ((fragS *frag)); 135 136#ifdef TE_GO32 137/* DJGPP now expects some sections to be 2**4 aligned. */ 138#define SUB_SEGMENT_ALIGN(SEG) \ 139 ((strcmp (obj_segment_name (SEG), ".text") == 0 \ 140 || strcmp (obj_segment_name (SEG), ".data") == 0 \ 141 || strcmp (obj_segment_name (SEG), ".bss") == 0 \ 142 || strncmp (obj_segment_name (SEG), ".gnu.linkonce.t", 15) == 0 \ 143 || strncmp (obj_segment_name (SEG), ".gnu.linkonce.d", 15) == 0 \ 144 || strncmp (obj_segment_name (SEG), ".gnu.linkonce.r", 15) == 0) \ 145 ? 4 \ 146 : 2) 147#else 148#define SUB_SEGMENT_ALIGN(SEG) 2 149#endif 150 151#define TC_RVA_RELOC 7 152/* Need this for PIC relocations */ 153#define NEED_FX_R_TYPE 154 155#ifdef TE_386BSD 156/* The BSDI linker apparently rejects objects with a machine type of 157 M_386 (100). */ 158#define AOUT_MACHTYPE 0 159#else 160#define AOUT_MACHTYPE 100 161#endif 162 163#undef REVERSE_SORT_RELOCS 164 165#endif /* ! BFD_ASSEMBLER */ 166 167#ifndef LEX_AT 168#define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) x86_cons (EXP, NBYTES) 169extern void x86_cons PARAMS ((expressionS *, int)); 170 171#define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) x86_cons_fix_new(FRAG, OFF, LEN, EXP) 172extern void x86_cons_fix_new 173 PARAMS ((fragS *, unsigned int, unsigned int, expressionS *)); 174#endif 175 176#define TC_FORCE_RELOCATION(fixp) tc_i386_force_relocation(fixp) 177extern int tc_i386_force_relocation PARAMS ((struct fix *)); 178 179#ifdef BFD_ASSEMBLER 180#define NO_RELOC BFD_RELOC_NONE 181#else 182#define NO_RELOC 0 183#endif 184#define tc_coff_symbol_emit_hook(a) ; /* not used */ 185 186#ifndef BFD_ASSEMBLER 187#ifndef OBJ_AOUT 188#ifndef TE_PE 189#ifndef TE_GO32 190/* Local labels starts with .L */ 191#define LOCAL_LABEL(name) (name[0] == '.' \ 192 && (name[1] == 'L' || name[1] == 'X' || name[1] == '.')) 193#endif 194#endif 195#endif 196#endif 197 198#define LOCAL_LABELS_FB 1 199 200#define tc_aout_pre_write_hook(x) {;} /* not used */ 201#define tc_crawl_symbol_chain(a) {;} /* not used */ 202#define tc_headers_hook(a) {;} /* not used */ 203 204extern const char extra_symbol_chars[]; 205#define tc_symbol_chars extra_symbol_chars 206 207#define MAX_OPERANDS 3 /* max operands per insn */ 208#define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp) */ 209#define MAX_MEMORY_OPERANDS 2 /* max memory refs per insn (string ops) */ 210 211/* Prefixes will be emitted in the order defined below. 212 WAIT_PREFIX must be the first prefix since FWAIT is really is an 213 instruction, and so must come before any prefixes. */ 214#define WAIT_PREFIX 0 215#define LOCKREP_PREFIX 1 216#define ADDR_PREFIX 2 217#define DATA_PREFIX 3 218#define SEG_PREFIX 4 219#define REX_PREFIX 5 /* must come last. */ 220#define MAX_PREFIXES 6 /* max prefixes per opcode */ 221 222/* we define the syntax here (modulo base,index,scale syntax) */ 223#define REGISTER_PREFIX '%' 224#define IMMEDIATE_PREFIX '$' 225#define ABSOLUTE_PREFIX '*' 226 227#define TWO_BYTE_OPCODE_ESCAPE 0x0f 228#define NOP_OPCODE (char) 0x90 229 230/* register numbers */ 231#define EBP_REG_NUM 5 232#define ESP_REG_NUM 4 233 234/* modrm_byte.regmem for twobyte escape */ 235#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM 236/* index_base_byte.index for no index register addressing */ 237#define NO_INDEX_REGISTER ESP_REG_NUM 238/* index_base_byte.base for no base register addressing */ 239#define NO_BASE_REGISTER EBP_REG_NUM 240#define NO_BASE_REGISTER_16 6 241 242/* these are the instruction mnemonic suffixes. */ 243#define WORD_MNEM_SUFFIX 'w' 244#define BYTE_MNEM_SUFFIX 'b' 245#define SHORT_MNEM_SUFFIX 's' 246#define LONG_MNEM_SUFFIX 'l' 247#define QWORD_MNEM_SUFFIX 'q' 248/* Intel Syntax */ 249#define LONG_DOUBLE_MNEM_SUFFIX 'x' 250 251/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */ 252#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */ 253#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG) 254 255#define END_OF_INSN '\0' 256 257/* Intel Syntax */ 258/* Values 0-4 map onto scale factor */ 259#define BYTE_PTR 0 260#define WORD_PTR 1 261#define DWORD_PTR 2 262#define QWORD_PTR 3 263#define XWORD_PTR 4 264#define SHORT 5 265#define OFFSET_FLAT 6 266#define FLAT 7 267#define NONE_FOUND 8 268 269typedef struct 270{ 271 /* instruction name sans width suffix ("mov" for movl insns) */ 272 char *name; 273 274 /* how many operands */ 275 unsigned int operands; 276 277 /* base_opcode is the fundamental opcode byte without optional 278 prefix(es). */ 279 unsigned int base_opcode; 280 281 /* extension_opcode is the 3 bit extension for group <n> insns. 282 This field is also used to store the 8-bit opcode suffix for the 283 AMD 3DNow! instructions. 284 If this template has no extension opcode (the usual case) use None */ 285 unsigned int extension_opcode; 286#define None 0xffff /* If no extension_opcode is possible. */ 287 288 /* cpu feature flags */ 289 unsigned int cpu_flags; 290#define Cpu086 0x1 /* Any old cpu will do, 0 does the same */ 291#define Cpu186 0x2 /* i186 or better required */ 292#define Cpu286 0x4 /* i286 or better required */ 293#define Cpu386 0x8 /* i386 or better required */ 294#define Cpu486 0x10 /* i486 or better required */ 295#define Cpu586 0x20 /* i585 or better required */ 296#define Cpu686 0x40 /* i686 or better required */ 297#define CpuP4 0x80 /* Pentium4 or better required */ 298#define CpuK6 0x100 /* AMD K6 or better required*/ 299#define CpuAthlon 0x200 /* AMD Athlon or better required*/ 300#define CpuSledgehammer 0x400 /* Sledgehammer or better required */ 301#define CpuMMX 0x800 /* MMX support required */ 302#define CpuSSE 0x1000 /* Streaming SIMD extensions required */ 303#define CpuSSE2 0x2000 /* Streaming SIMD extensions 2 required */ 304#define Cpu3dnow 0x4000 /* 3dnow! support required */ 305 306 /* These flags are set by gas depending on the flag_code. */ 307#define Cpu64 0x4000000 /* 64bit support required */ 308#define CpuNo64 0x8000000 /* Not supported in the 64bit mode */ 309 310 /* The default value for unknown CPUs - enable all features to avoid problems. */ 311#define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuSledgehammer|CpuMMX|CpuSSE|CpuSSE2|Cpu3dnow|CpuK6|CpuAthlon) 312 313 /* the bits in opcode_modifier are used to generate the final opcode from 314 the base_opcode. These bits also are used to detect alternate forms of 315 the same instruction */ 316 unsigned int opcode_modifier; 317 318 /* opcode_modifier bits: */ 319#define W 0x1 /* set if operands can be words or dwords 320 encoded the canonical way */ 321#define D 0x2 /* D = 0 if Reg --> Regmem; 322 D = 1 if Regmem --> Reg: MUST BE 0x2 */ 323#define Modrm 0x4 324#define FloatR 0x8 /* src/dest swap for floats: MUST BE 0x8 */ 325#define ShortForm 0x10 /* register is in low 3 bits of opcode */ 326#define FloatMF 0x20 /* FP insn memory format bit, sized by 0x4 */ 327#define Jump 0x40 /* special case for jump insns. */ 328#define JumpDword 0x80 /* call and jump */ 329#define JumpByte 0x100 /* loop and jecxz */ 330#define JumpInterSegment 0x200 /* special case for intersegment leaps/calls */ 331#define FloatD 0x400 /* direction for float insns: MUST BE 0x400 */ 332#define Seg2ShortForm 0x800 /* encoding of load segment reg insns */ 333#define Seg3ShortForm 0x1000 /* fs/gs segment register insns. */ 334#define Size16 0x2000 /* needs size prefix if in 32-bit mode */ 335#define Size32 0x4000 /* needs size prefix if in 16-bit mode */ 336#define Size64 0x8000 /* needs size prefix if in 16-bit mode */ 337#define IgnoreSize 0x10000 /* instruction ignores operand size prefix */ 338#define DefaultSize 0x20000 /* default insn size depends on mode */ 339#define No_bSuf 0x40000 /* b suffix on instruction illegal */ 340#define No_wSuf 0x80000 /* w suffix on instruction illegal */ 341#define No_lSuf 0x100000 /* l suffix on instruction illegal */ 342#define No_sSuf 0x200000 /* s suffix on instruction illegal */ 343#define No_qSuf 0x400000 /* q suffix on instruction illegal */ 344#define No_xSuf 0x800000 /* x suffix on instruction illegal */ 345#define FWait 0x1000000 /* instruction needs FWAIT */ 346#define IsString 0x2000000 /* quick test for string instructions */ 347#define regKludge 0x4000000 /* fake an extra reg operand for clr, imul */ 348#define IsPrefix 0x8000000 /* opcode is a prefix */ 349#define ImmExt 0x10000000 /* instruction has extension in 8 bit imm */ 350#define NoRex64 0x20000000 /* instruction don't need Rex64 prefix. */ 351#define Rex64 0x40000000 /* instruction require Rex64 prefix. */ 352#define Ugh 0x80000000 /* deprecated fp insn, gets a warning */ 353 354 /* operand_types[i] describes the type of operand i. This is made 355 by OR'ing together all of the possible type masks. (e.g. 356 'operand_types[i] = Reg|Imm' specifies that operand i can be 357 either a register or an immediate operand. */ 358 unsigned int operand_types[3]; 359 360 /* operand_types[i] bits */ 361 /* register */ 362#define Reg8 0x1 /* 8 bit reg */ 363#define Reg16 0x2 /* 16 bit reg */ 364#define Reg32 0x4 /* 32 bit reg */ 365#define Reg64 0x8 /* 64 bit reg */ 366 /* immediate */ 367#define Imm8 0x10 /* 8 bit immediate */ 368#define Imm8S 0x20 /* 8 bit immediate sign extended */ 369#define Imm16 0x40 /* 16 bit immediate */ 370#define Imm32 0x80 /* 32 bit immediate */ 371#define Imm32S 0x100 /* 32 bit immediate sign extended */ 372#define Imm64 0x200 /* 64 bit immediate */ 373#define Imm1 0x400 /* 1 bit immediate */ 374 /* memory */ 375#define BaseIndex 0x800 376 /* Disp8,16,32 are used in different ways, depending on the 377 instruction. For jumps, they specify the size of the PC relative 378 displacement, for baseindex type instructions, they specify the 379 size of the offset relative to the base register, and for memory 380 offset instructions such as `mov 1234,%al' they specify the size of 381 the offset relative to the segment base. */ 382#define Disp8 0x1000 /* 8 bit displacement */ 383#define Disp16 0x2000 /* 16 bit displacement */ 384#define Disp32 0x4000 /* 32 bit displacement */ 385#define Disp32S 0x8000 /* 32 bit signed displacement */ 386#define Disp64 0x10000 /* 64 bit displacement */ 387 /* specials */ 388#define InOutPortReg 0x20000 /* register to hold in/out port addr = dx */ 389#define ShiftCount 0x40000 /* register to hold shift cound = cl */ 390#define Control 0x80000 /* Control register */ 391#define Debug 0x100000 /* Debug register */ 392#define Test 0x200000 /* Test register */ 393#define FloatReg 0x400000 /* Float register */ 394#define FloatAcc 0x800000 /* Float stack top %st(0) */ 395#define SReg2 0x1000000 /* 2 bit segment register */ 396#define SReg3 0x2000000 /* 3 bit segment register */ 397#define Acc 0x4000000 /* Accumulator %al or %ax or %eax */ 398#define JumpAbsolute 0x8000000 399#define RegMMX 0x10000000 /* MMX register */ 400#define RegXMM 0x20000000 /* XMM registers in PIII */ 401#define EsSeg 0x40000000 /* String insn operand with fixed es segment */ 402 403 /* InvMem is for instructions with a modrm byte that only allow a 404 general register encoding in the i.tm.mode and i.tm.regmem fields, 405 eg. control reg moves. They really ought to support a memory form, 406 but don't, so we add an InvMem flag to the register operand to 407 indicate that it should be encoded in the i.tm.regmem field. */ 408#define InvMem 0x80000000 409 410#define Reg (Reg8|Reg16|Reg32|Reg64) /* gen'l register */ 411#define WordReg (Reg16|Reg32|Reg64) 412#define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc) 413#define Imm (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */ 414#define EncImm (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */ 415#define Disp (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */ 416#define AnyMem (Disp8|Disp16|Disp32|Disp32S|BaseIndex|InvMem) /* General memory */ 417 /* The following aliases are defined because the opcode table 418 carefully specifies the allowed memory types for each instruction. 419 At the moment we can only tell a memory reference size by the 420 instruction suffix, so there's not much point in defining Mem8, 421 Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use 422 the suffix directly to check memory operands. */ 423#define LLongMem AnyMem /* 64 bits (or more) */ 424#define LongMem AnyMem /* 32 bit memory ref */ 425#define ShortMem AnyMem /* 16 bit memory ref */ 426#define WordMem AnyMem /* 16 or 32 bit memory ref */ 427#define ByteMem AnyMem /* 8 bit memory ref */ 428} 429template; 430 431/* 432 'templates' is for grouping together 'template' structures for opcodes 433 of the same name. This is only used for storing the insns in the grand 434 ole hash table of insns. 435 The templates themselves start at START and range up to (but not including) 436 END. 437 */ 438typedef struct 439{ 440 const template *start; 441 const template *end; 442} 443templates; 444 445/* these are for register name --> number & type hash lookup */ 446typedef struct 447{ 448 char *reg_name; 449 unsigned int reg_type; 450 unsigned int reg_flags; 451#define RegRex 0x1 /* Extended register. */ 452#define RegRex64 0x2 /* Extended 8 bit register. */ 453 unsigned int reg_num; 454} 455reg_entry; 456 457typedef struct 458{ 459 char *seg_name; 460 unsigned int seg_prefix; 461} 462seg_entry; 463 464/* 386 operand encoding bytes: see 386 book for details of this. */ 465typedef struct 466{ 467 unsigned int regmem; /* codes register or memory operand */ 468 unsigned int reg; /* codes register operand (or extended opcode) */ 469 unsigned int mode; /* how to interpret regmem & reg */ 470} 471modrm_byte; 472 473/* x86-64 extension prefix. */ 474typedef int rex_byte; 475#define REX_OPCODE 0x40 476 477/* Indicates 64 bit operand size. */ 478#define REX_MODE64 8 479/* High extension to reg field of modrm byte. */ 480#define REX_EXTX 4 481/* High extension to SIB index field. */ 482#define REX_EXTY 2 483/* High extension to base field of modrm or SIB, or reg field of opcode. */ 484#define REX_EXTZ 1 485 486/* 386 opcode byte to code indirect addressing. */ 487typedef struct 488{ 489 unsigned base; 490 unsigned index; 491 unsigned scale; 492} 493sib_byte; 494 495/* x86 arch names and features */ 496typedef struct 497{ 498 const char *name; /* arch name */ 499 unsigned int flags; /* cpu feature flags */ 500} 501arch_entry; 502 503/* The name of the global offset table generated by the compiler. Allow 504 this to be overridden if need be. */ 505#ifndef GLOBAL_OFFSET_TABLE_NAME 506#define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_" 507#endif 508 509#ifdef BFD_ASSEMBLER 510void i386_validate_fix PARAMS ((struct fix *)); 511#define TC_VALIDATE_FIX(FIXP,SEGTYPE,SKIP) i386_validate_fix(FIXP) 512#endif 513 514#endif /* TC_I386 */ 515 516#define md_operand(x) 517 518extern const struct relax_type md_relax_table[]; 519#define TC_GENERIC_RELAX_TABLE md_relax_table 520 521#define md_do_align(n, fill, len, max, around) \ 522if ((n) && !need_pass_2 \ 523 && (!(fill) || ((char)*(fill) == (char)0x90 && (len) == 1)) \ 524 && subseg_text_p (now_seg)) \ 525 { \ 526 frag_align_code ((n), (max)); \ 527 goto around; \ 528 } 529 530#define MAX_MEM_FOR_RS_ALIGN_CODE 15 531 532extern void i386_align_code PARAMS ((fragS *, int)); 533 534#define HANDLE_ALIGN(fragP) \ 535if (fragP->fr_type == rs_align_code) \ 536 i386_align_code (fragP, (fragP->fr_next->fr_address \ 537 - fragP->fr_address \ 538 - fragP->fr_fix)); 539 540void i386_print_statistics PARAMS ((FILE *)); 541#define tc_print_statistics i386_print_statistics 542 543#define md_number_to_chars number_to_chars_littleendian 544 545#ifdef SCO_ELF 546#define tc_init_after_args() sco_id () 547extern void sco_id PARAMS ((void)); 548#endif 549 550#define DIFF_EXPR_OK /* foo-. gets turned into PC relative relocs */ 551