tc-i386.h revision 107491
1/* tc-i386.h -- Header file for tc-i386.c 2 Copyright 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 3 2001 4 Free Software Foundation, Inc. 5 6 This file is part of GAS, the GNU Assembler. 7 8 GAS is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 2, or (at your option) 11 any later version. 12 13 GAS is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GAS; see the file COPYING. If not, write to the Free 20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 21 02111-1307, USA. */ 22 23#ifndef TC_I386 24#define TC_I386 1 25 26#ifdef ANSI_PROTOTYPES 27struct fix; 28#endif 29 30#define TARGET_BYTES_BIG_ENDIAN 0 31 32#ifdef TE_LYNX 33#define TARGET_FORMAT "coff-i386-lynx" 34#endif 35 36#ifdef BFD_ASSEMBLER 37/* This is used to determine relocation types in tc-i386.c. The first 38 parameter is the current relocation type, the second one is the desired 39 type. The idea is that if the original type is already some kind of PIC 40 relocation, we leave it alone, otherwise we give it the desired type */ 41 42#define tc_fix_adjustable(X) tc_i386_fix_adjustable(X) 43extern int tc_i386_fix_adjustable PARAMS ((struct fix *)); 44 45#if (defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) || defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)) && !defined (TE_PE) 46/* This arranges for gas/write.c to not apply a relocation if 47 tc_fix_adjustable() says it is not adjustable. 48 The "! symbol_used_in_reloc_p" test is there specifically to cover 49 the case of non-global symbols in linkonce sections. It's the 50 generally correct thing to do though; If a reloc is going to be 51 emitted against a symbol then we don't want to adjust the fixup by 52 applying the reloc during assembly. The reloc will be applied by 53 the linker during final link. */ 54#define TC_FIX_ADJUSTABLE(fixP) \ 55 (! symbol_used_in_reloc_p ((fixP)->fx_addsy) && tc_fix_adjustable (fixP)) 56#endif 57 58/* This expression evaluates to false if the relocation is for a local object 59 for which we still want to do the relocation at runtime. True if we 60 are willing to perform this relocation while building the .o file. 61 This is only used for pcrel relocations, so GOTOFF does not need to be 62 checked here. I am not sure if some of the others are ever used with 63 pcrel, but it is easier to be safe than sorry. */ 64 65#define TC_RELOC_RTSYM_LOC_FIXUP(FIX) \ 66 ((FIX)->fx_r_type != BFD_RELOC_386_PLT32 \ 67 && (FIX)->fx_r_type != BFD_RELOC_386_GOT32 \ 68 && (FIX)->fx_r_type != BFD_RELOC_386_GOTPC \ 69 && ((FIX)->fx_addsy == NULL \ 70 || (! S_IS_EXTERNAL ((FIX)->fx_addsy) \ 71 && ! S_IS_WEAK ((FIX)->fx_addsy) \ 72 && S_IS_DEFINED ((FIX)->fx_addsy) \ 73 && ! S_IS_COMMON ((FIX)->fx_addsy)))) 74 75#define TARGET_ARCH bfd_arch_i386 76#define TARGET_MACH (i386_mach ()) 77extern unsigned long i386_mach PARAMS ((void)); 78 79#ifdef TE_FreeBSD 80#define AOUT_TARGET_FORMAT "a.out-i386-freebsd" 81#endif 82#ifdef TE_NetBSD 83#define AOUT_TARGET_FORMAT "a.out-i386-netbsd" 84#endif 85#ifdef TE_386BSD 86#define AOUT_TARGET_FORMAT "a.out-i386-bsd" 87#endif 88#ifdef TE_LINUX 89#define AOUT_TARGET_FORMAT "a.out-i386-linux" 90#endif 91#ifdef TE_Mach 92#define AOUT_TARGET_FORMAT "a.out-mach3" 93#endif 94#ifdef TE_DYNIX 95#define AOUT_TARGET_FORMAT "a.out-i386-dynix" 96#endif 97#ifndef AOUT_TARGET_FORMAT 98#define AOUT_TARGET_FORMAT "a.out-i386" 99#endif 100 101#ifdef TE_FreeBSD 102#define ELF_TARGET_FORMAT "elf32-i386-freebsd" 103#endif 104#ifndef ELF_TARGET_FORMAT 105#define ELF_TARGET_FORMAT "elf32-i386" 106#endif 107 108#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ 109 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) 110extern const char *i386_target_format PARAMS ((void)); 111#define TARGET_FORMAT i386_target_format () 112#else 113#ifdef OBJ_ELF 114#define TARGET_FORMAT ELF_TARGET_FORMAT 115#endif 116#ifdef OBJ_AOUT 117#define TARGET_FORMAT AOUT_TARGET_FORMAT 118#endif 119#endif 120 121#if (defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)) 122#define md_end i386_elf_emit_arch_note 123extern void i386_elf_emit_arch_note PARAMS ((void)); 124#endif 125 126#define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0 127 128#else /* ! BFD_ASSEMBLER */ 129 130/* COFF STUFF */ 131 132#define COFF_MAGIC I386MAGIC 133#define BFD_ARCH bfd_arch_i386 134#define COFF_FLAGS F_AR32WR 135#define TC_COUNT_RELOC(x) ((x)->fx_addsy || (x)->fx_r_type==7) 136#define TC_COFF_FIX2RTYPE(fixP) tc_coff_fix2rtype(fixP) 137extern short tc_coff_fix2rtype PARAMS ((struct fix *)); 138#define TC_COFF_SIZEMACHDEP(frag) tc_coff_sizemachdep (frag) 139extern int tc_coff_sizemachdep PARAMS ((fragS *frag)); 140 141#ifdef TE_GO32 142/* DJGPP now expects some sections to be 2**4 aligned. */ 143#define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) \ 144 ((strcmp (obj_segment_name (SEG), ".text") == 0 \ 145 || strcmp (obj_segment_name (SEG), ".data") == 0 \ 146 || strcmp (obj_segment_name (SEG), ".bss") == 0 \ 147 || strncmp (obj_segment_name (SEG), ".gnu.linkonce.t", 15) == 0 \ 148 || strncmp (obj_segment_name (SEG), ".gnu.linkonce.d", 15) == 0 \ 149 || strncmp (obj_segment_name (SEG), ".gnu.linkonce.r", 15) == 0) \ 150 ? 4 \ 151 : 2) 152#else 153#define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 2 154#endif 155 156#define TC_RVA_RELOC 7 157/* Need this for PIC relocations */ 158#define NEED_FX_R_TYPE 159 160#ifdef TE_386BSD 161/* The BSDI linker apparently rejects objects with a machine type of 162 M_386 (100). */ 163#define AOUT_MACHTYPE 0 164#else 165#define AOUT_MACHTYPE 100 166#endif 167 168#undef REVERSE_SORT_RELOCS 169 170#endif /* ! BFD_ASSEMBLER */ 171 172#ifndef LEX_AT 173#define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) x86_cons (EXP, NBYTES) 174extern void x86_cons PARAMS ((expressionS *, int)); 175 176#define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) x86_cons_fix_new(FRAG, OFF, LEN, EXP) 177extern void x86_cons_fix_new 178 PARAMS ((fragS *, unsigned int, unsigned int, expressionS *)); 179#endif 180 181#ifdef BFD_ASSEMBLER 182#define TC_FORCE_RELOCATION(FIXP) \ 183 ((FIXP)->fx_r_type == BFD_RELOC_VTABLE_INHERIT \ 184 || (FIXP)->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 185#else 186/* For COFF. */ 187#define TC_FORCE_RELOCATION(FIXP) \ 188 ((FIXP)->fx_r_type == 7) 189#endif 190 191#ifdef BFD_ASSEMBLER 192#define NO_RELOC BFD_RELOC_NONE 193#else 194#define NO_RELOC 0 195#endif 196#define tc_coff_symbol_emit_hook(a) ; /* not used */ 197 198#ifndef BFD_ASSEMBLER 199#ifndef OBJ_AOUT 200#ifndef TE_PE 201#ifndef TE_GO32 202/* Local labels starts with .L */ 203#define LOCAL_LABEL(name) (name[0] == '.' \ 204 && (name[1] == 'L' || name[1] == 'X' || name[1] == '.')) 205#endif 206#endif 207#endif 208#endif 209 210#define LOCAL_LABELS_FB 1 211 212#define tc_aout_pre_write_hook(x) {;} /* not used */ 213#define tc_crawl_symbol_chain(a) {;} /* not used */ 214#define tc_headers_hook(a) {;} /* not used */ 215 216extern const char extra_symbol_chars[]; 217#define tc_symbol_chars extra_symbol_chars 218 219#define MAX_OPERANDS 3 /* max operands per insn */ 220#define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp) */ 221#define MAX_MEMORY_OPERANDS 2 /* max memory refs per insn (string ops) */ 222 223/* Prefixes will be emitted in the order defined below. 224 WAIT_PREFIX must be the first prefix since FWAIT is really is an 225 instruction, and so must come before any prefixes. */ 226#define WAIT_PREFIX 0 227#define LOCKREP_PREFIX 1 228#define ADDR_PREFIX 2 229#define DATA_PREFIX 3 230#define SEG_PREFIX 4 231#define REX_PREFIX 5 /* must come last. */ 232#define MAX_PREFIXES 6 /* max prefixes per opcode */ 233 234/* we define the syntax here (modulo base,index,scale syntax) */ 235#define REGISTER_PREFIX '%' 236#define IMMEDIATE_PREFIX '$' 237#define ABSOLUTE_PREFIX '*' 238 239#define TWO_BYTE_OPCODE_ESCAPE 0x0f 240#define NOP_OPCODE (char) 0x90 241 242/* register numbers */ 243#define EBP_REG_NUM 5 244#define ESP_REG_NUM 4 245 246/* modrm_byte.regmem for twobyte escape */ 247#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM 248/* index_base_byte.index for no index register addressing */ 249#define NO_INDEX_REGISTER ESP_REG_NUM 250/* index_base_byte.base for no base register addressing */ 251#define NO_BASE_REGISTER EBP_REG_NUM 252#define NO_BASE_REGISTER_16 6 253 254/* these are the instruction mnemonic suffixes. */ 255#define WORD_MNEM_SUFFIX 'w' 256#define BYTE_MNEM_SUFFIX 'b' 257#define SHORT_MNEM_SUFFIX 's' 258#define LONG_MNEM_SUFFIX 'l' 259#define QWORD_MNEM_SUFFIX 'q' 260/* Intel Syntax */ 261#define LONG_DOUBLE_MNEM_SUFFIX 'x' 262 263/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */ 264#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */ 265#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG) 266 267#define END_OF_INSN '\0' 268 269/* Intel Syntax */ 270/* Values 0-4 map onto scale factor */ 271#define BYTE_PTR 0 272#define WORD_PTR 1 273#define DWORD_PTR 2 274#define QWORD_PTR 3 275#define XWORD_PTR 4 276#define SHORT 5 277#define OFFSET_FLAT 6 278#define FLAT 7 279#define NONE_FOUND 8 280 281typedef struct 282{ 283 /* instruction name sans width suffix ("mov" for movl insns) */ 284 char *name; 285 286 /* how many operands */ 287 unsigned int operands; 288 289 /* base_opcode is the fundamental opcode byte without optional 290 prefix(es). */ 291 unsigned int base_opcode; 292 293 /* extension_opcode is the 3 bit extension for group <n> insns. 294 This field is also used to store the 8-bit opcode suffix for the 295 AMD 3DNow! instructions. 296 If this template has no extension opcode (the usual case) use None */ 297 unsigned int extension_opcode; 298#define None 0xffff /* If no extension_opcode is possible. */ 299 300 /* cpu feature flags */ 301 unsigned int cpu_flags; 302#define Cpu086 0x1 /* Any old cpu will do, 0 does the same */ 303#define Cpu186 0x2 /* i186 or better required */ 304#define Cpu286 0x4 /* i286 or better required */ 305#define Cpu386 0x8 /* i386 or better required */ 306#define Cpu486 0x10 /* i486 or better required */ 307#define Cpu586 0x20 /* i585 or better required */ 308#define Cpu686 0x40 /* i686 or better required */ 309#define CpuP4 0x80 /* Pentium4 or better required */ 310#define CpuK6 0x100 /* AMD K6 or better required*/ 311#define CpuAthlon 0x200 /* AMD Athlon or better required*/ 312#define CpuSledgehammer 0x400 /* Sledgehammer or better required */ 313#define CpuMMX 0x800 /* MMX support required */ 314#define CpuSSE 0x1000 /* Streaming SIMD extensions required */ 315#define CpuSSE2 0x2000 /* Streaming SIMD extensions 2 required */ 316#define Cpu3dnow 0x4000 /* 3dnow! support required */ 317 318 /* These flags are set by gas depending on the flag_code. */ 319#define Cpu64 0x4000000 /* 64bit support required */ 320#define CpuNo64 0x8000000 /* Not supported in the 64bit mode */ 321 322 /* The default value for unknown CPUs - enable all features to avoid problems. */ 323#define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuSledgehammer|CpuMMX|CpuSSE|CpuSSE2|Cpu3dnow|CpuK6|CpuAthlon) 324 325 /* the bits in opcode_modifier are used to generate the final opcode from 326 the base_opcode. These bits also are used to detect alternate forms of 327 the same instruction */ 328 unsigned int opcode_modifier; 329 330 /* opcode_modifier bits: */ 331#define W 0x1 /* set if operands can be words or dwords 332 encoded the canonical way */ 333#define D 0x2 /* D = 0 if Reg --> Regmem; 334 D = 1 if Regmem --> Reg: MUST BE 0x2 */ 335#define Modrm 0x4 336#define FloatR 0x8 /* src/dest swap for floats: MUST BE 0x8 */ 337#define ShortForm 0x10 /* register is in low 3 bits of opcode */ 338#define FloatMF 0x20 /* FP insn memory format bit, sized by 0x4 */ 339#define Jump 0x40 /* special case for jump insns. */ 340#define JumpDword 0x80 /* call and jump */ 341#define JumpByte 0x100 /* loop and jecxz */ 342#define JumpInterSegment 0x200 /* special case for intersegment leaps/calls */ 343#define FloatD 0x400 /* direction for float insns: MUST BE 0x400 */ 344#define Seg2ShortForm 0x800 /* encoding of load segment reg insns */ 345#define Seg3ShortForm 0x1000 /* fs/gs segment register insns. */ 346#define Size16 0x2000 /* needs size prefix if in 32-bit mode */ 347#define Size32 0x4000 /* needs size prefix if in 16-bit mode */ 348#define Size64 0x8000 /* needs size prefix if in 16-bit mode */ 349#define IgnoreSize 0x10000 /* instruction ignores operand size prefix */ 350#define DefaultSize 0x20000 /* default insn size depends on mode */ 351#define No_bSuf 0x40000 /* b suffix on instruction illegal */ 352#define No_wSuf 0x80000 /* w suffix on instruction illegal */ 353#define No_lSuf 0x100000 /* l suffix on instruction illegal */ 354#define No_sSuf 0x200000 /* s suffix on instruction illegal */ 355#define No_qSuf 0x400000 /* q suffix on instruction illegal */ 356#define No_xSuf 0x800000 /* x suffix on instruction illegal */ 357#define FWait 0x1000000 /* instruction needs FWAIT */ 358#define IsString 0x2000000 /* quick test for string instructions */ 359#define regKludge 0x4000000 /* fake an extra reg operand for clr, imul */ 360#define IsPrefix 0x8000000 /* opcode is a prefix */ 361#define ImmExt 0x10000000 /* instruction has extension in 8 bit imm */ 362#define NoRex64 0x20000000 /* instruction don't need Rex64 prefix. */ 363#define Rex64 0x40000000 /* instruction require Rex64 prefix. */ 364#define Ugh 0x80000000 /* deprecated fp insn, gets a warning */ 365 366 /* operand_types[i] describes the type of operand i. This is made 367 by OR'ing together all of the possible type masks. (e.g. 368 'operand_types[i] = Reg|Imm' specifies that operand i can be 369 either a register or an immediate operand. */ 370 unsigned int operand_types[3]; 371 372 /* operand_types[i] bits */ 373 /* register */ 374#define Reg8 0x1 /* 8 bit reg */ 375#define Reg16 0x2 /* 16 bit reg */ 376#define Reg32 0x4 /* 32 bit reg */ 377#define Reg64 0x8 /* 64 bit reg */ 378 /* immediate */ 379#define Imm8 0x10 /* 8 bit immediate */ 380#define Imm8S 0x20 /* 8 bit immediate sign extended */ 381#define Imm16 0x40 /* 16 bit immediate */ 382#define Imm32 0x80 /* 32 bit immediate */ 383#define Imm32S 0x100 /* 32 bit immediate sign extended */ 384#define Imm64 0x200 /* 64 bit immediate */ 385#define Imm1 0x400 /* 1 bit immediate */ 386 /* memory */ 387#define BaseIndex 0x800 388 /* Disp8,16,32 are used in different ways, depending on the 389 instruction. For jumps, they specify the size of the PC relative 390 displacement, for baseindex type instructions, they specify the 391 size of the offset relative to the base register, and for memory 392 offset instructions such as `mov 1234,%al' they specify the size of 393 the offset relative to the segment base. */ 394#define Disp8 0x1000 /* 8 bit displacement */ 395#define Disp16 0x2000 /* 16 bit displacement */ 396#define Disp32 0x4000 /* 32 bit displacement */ 397#define Disp32S 0x8000 /* 32 bit signed displacement */ 398#define Disp64 0x10000 /* 64 bit displacement */ 399 /* specials */ 400#define InOutPortReg 0x20000 /* register to hold in/out port addr = dx */ 401#define ShiftCount 0x40000 /* register to hold shift cound = cl */ 402#define Control 0x80000 /* Control register */ 403#define Debug 0x100000 /* Debug register */ 404#define Test 0x200000 /* Test register */ 405#define FloatReg 0x400000 /* Float register */ 406#define FloatAcc 0x800000 /* Float stack top %st(0) */ 407#define SReg2 0x1000000 /* 2 bit segment register */ 408#define SReg3 0x2000000 /* 3 bit segment register */ 409#define Acc 0x4000000 /* Accumulator %al or %ax or %eax */ 410#define JumpAbsolute 0x8000000 411#define RegMMX 0x10000000 /* MMX register */ 412#define RegXMM 0x20000000 /* XMM registers in PIII */ 413#define EsSeg 0x40000000 /* String insn operand with fixed es segment */ 414 415 /* InvMem is for instructions with a modrm byte that only allow a 416 general register encoding in the i.tm.mode and i.tm.regmem fields, 417 eg. control reg moves. They really ought to support a memory form, 418 but don't, so we add an InvMem flag to the register operand to 419 indicate that it should be encoded in the i.tm.regmem field. */ 420#define InvMem 0x80000000 421 422#define Reg (Reg8|Reg16|Reg32|Reg64) /* gen'l register */ 423#define WordReg (Reg16|Reg32|Reg64) 424#define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc) 425#define Imm (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */ 426#define EncImm (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */ 427#define Disp (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */ 428#define AnyMem (Disp8|Disp16|Disp32|Disp32S|BaseIndex|InvMem) /* General memory */ 429 /* The following aliases are defined because the opcode table 430 carefully specifies the allowed memory types for each instruction. 431 At the moment we can only tell a memory reference size by the 432 instruction suffix, so there's not much point in defining Mem8, 433 Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use 434 the suffix directly to check memory operands. */ 435#define LLongMem AnyMem /* 64 bits (or more) */ 436#define LongMem AnyMem /* 32 bit memory ref */ 437#define ShortMem AnyMem /* 16 bit memory ref */ 438#define WordMem AnyMem /* 16 or 32 bit memory ref */ 439#define ByteMem AnyMem /* 8 bit memory ref */ 440} 441template; 442 443/* 444 'templates' is for grouping together 'template' structures for opcodes 445 of the same name. This is only used for storing the insns in the grand 446 ole hash table of insns. 447 The templates themselves start at START and range up to (but not including) 448 END. 449 */ 450typedef struct 451{ 452 const template *start; 453 const template *end; 454} 455templates; 456 457/* these are for register name --> number & type hash lookup */ 458typedef struct 459{ 460 char *reg_name; 461 unsigned int reg_type; 462 unsigned int reg_flags; 463#define RegRex 0x1 /* Extended register. */ 464#define RegRex64 0x2 /* Extended 8 bit register. */ 465 unsigned int reg_num; 466} 467reg_entry; 468 469typedef struct 470{ 471 char *seg_name; 472 unsigned int seg_prefix; 473} 474seg_entry; 475 476/* 386 operand encoding bytes: see 386 book for details of this. */ 477typedef struct 478{ 479 unsigned int regmem; /* codes register or memory operand */ 480 unsigned int reg; /* codes register operand (or extended opcode) */ 481 unsigned int mode; /* how to interpret regmem & reg */ 482} 483modrm_byte; 484 485/* x86-64 extension prefix. */ 486typedef int rex_byte; 487#define REX_OPCODE 0x40 488 489/* Indicates 64 bit operand size. */ 490#define REX_MODE64 8 491/* High extension to reg field of modrm byte. */ 492#define REX_EXTX 4 493/* High extension to SIB index field. */ 494#define REX_EXTY 2 495/* High extension to base field of modrm or SIB, or reg field of opcode. */ 496#define REX_EXTZ 1 497 498/* 386 opcode byte to code indirect addressing. */ 499typedef struct 500{ 501 unsigned base; 502 unsigned index; 503 unsigned scale; 504} 505sib_byte; 506 507/* x86 arch names and features */ 508typedef struct 509{ 510 const char *name; /* arch name */ 511 unsigned int flags; /* cpu feature flags */ 512} 513arch_entry; 514 515/* The name of the global offset table generated by the compiler. Allow 516 this to be overridden if need be. */ 517#ifndef GLOBAL_OFFSET_TABLE_NAME 518#define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_" 519#endif 520 521#ifdef BFD_ASSEMBLER 522void i386_validate_fix PARAMS ((struct fix *)); 523#define TC_VALIDATE_FIX(FIXP,SEGTYPE,SKIP) i386_validate_fix(FIXP) 524#endif 525 526#endif /* TC_I386 */ 527 528#define md_operand(x) 529 530extern const struct relax_type md_relax_table[]; 531#define TC_GENERIC_RELAX_TABLE md_relax_table 532 533#define md_do_align(n, fill, len, max, around) \ 534if ((n) && !need_pass_2 \ 535 && (!(fill) || ((char)*(fill) == (char)0x90 && (len) == 1)) \ 536 && subseg_text_p (now_seg)) \ 537 { \ 538 frag_align_code ((n), (max)); \ 539 goto around; \ 540 } 541 542#define MAX_MEM_FOR_RS_ALIGN_CODE 15 543 544extern void i386_align_code PARAMS ((fragS *, int)); 545 546#define HANDLE_ALIGN(fragP) \ 547if (fragP->fr_type == rs_align_code) \ 548 i386_align_code (fragP, (fragP->fr_next->fr_address \ 549 - fragP->fr_address \ 550 - fragP->fr_fix)); 551 552void i386_print_statistics PARAMS ((FILE *)); 553#define tc_print_statistics i386_print_statistics 554 555#define md_number_to_chars number_to_chars_littleendian 556 557#ifdef SCO_ELF 558#define tc_init_after_args() sco_id () 559extern void sco_id PARAMS ((void)); 560#endif 561 562#define DIFF_EXPR_OK /* foo-. gets turned into PC relative relocs */ 563