tc-i386.h revision 104848
1/* tc-i386.h -- Header file for tc-i386.c 2 Copyright 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 3 2001 4 Free Software Foundation, Inc. 5 6 This file is part of GAS, the GNU Assembler. 7 8 GAS is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 2, or (at your option) 11 any later version. 12 13 GAS is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GAS; see the file COPYING. If not, write to the Free 20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 21 02111-1307, USA. */ 22 23 24/* $FreeBSD: head/contrib/binutils/gas/config/tc-i386.h 104848 2002-10-11 06:18:04Z obrien $ */ 25 26 27#ifndef TC_I386 28#define TC_I386 1 29 30#ifdef ANSI_PROTOTYPES 31struct fix; 32#endif 33 34#define TARGET_BYTES_BIG_ENDIAN 0 35 36#ifdef TE_LYNX 37#define TARGET_FORMAT "coff-i386-lynx" 38#endif 39 40#ifdef BFD_ASSEMBLER 41/* This is used to determine relocation types in tc-i386.c. The first 42 parameter is the current relocation type, the second one is the desired 43 type. The idea is that if the original type is already some kind of PIC 44 relocation, we leave it alone, otherwise we give it the desired type */ 45 46#define tc_fix_adjustable(X) tc_i386_fix_adjustable(X) 47extern int tc_i386_fix_adjustable PARAMS ((struct fix *)); 48 49#if (defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) || defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)) && !defined (TE_PE) 50/* This arranges for gas/write.c to not apply a relocation if 51 tc_fix_adjustable() says it is not adjustable. 52 The "! symbol_used_in_reloc_p" test is there specifically to cover 53 the case of non-global symbols in linkonce sections. It's the 54 generally correct thing to do though; If a reloc is going to be 55 emitted against a symbol then we don't want to adjust the fixup by 56 applying the reloc during assembly. The reloc will be applied by 57 the linker during final link. */ 58#define TC_FIX_ADJUSTABLE(fixP) \ 59 (! symbol_used_in_reloc_p ((fixP)->fx_addsy) && tc_fix_adjustable (fixP)) 60#endif 61 62/* This expression evaluates to false if the relocation is for a local object 63 for which we still want to do the relocation at runtime. True if we 64 are willing to perform this relocation while building the .o file. 65 This is only used for pcrel relocations, so GOTOFF does not need to be 66 checked here. I am not sure if some of the others are ever used with 67 pcrel, but it is easier to be safe than sorry. */ 68 69#define TC_RELOC_RTSYM_LOC_FIXUP(FIX) \ 70 ((FIX)->fx_r_type != BFD_RELOC_386_PLT32 \ 71 && (FIX)->fx_r_type != BFD_RELOC_386_GOT32 \ 72 && (FIX)->fx_r_type != BFD_RELOC_386_GOTPC \ 73 && ((FIX)->fx_addsy == NULL \ 74 || (! S_IS_EXTERNAL ((FIX)->fx_addsy) \ 75 && ! S_IS_WEAK ((FIX)->fx_addsy) \ 76 && S_IS_DEFINED ((FIX)->fx_addsy) \ 77 && ! S_IS_COMMON ((FIX)->fx_addsy)))) 78 79#define TARGET_ARCH bfd_arch_i386 80#define TARGET_MACH (i386_mach ()) 81extern unsigned long i386_mach PARAMS ((void)); 82 83#ifdef TE_FreeBSD 84#define AOUT_TARGET_FORMAT "a.out-i386-freebsd" 85#endif 86#ifdef TE_NetBSD 87#define AOUT_TARGET_FORMAT "a.out-i386-netbsd" 88#endif 89#ifdef TE_386BSD 90#define AOUT_TARGET_FORMAT "a.out-i386-bsd" 91#endif 92#ifdef TE_LINUX 93#define AOUT_TARGET_FORMAT "a.out-i386-linux" 94#endif 95#ifdef TE_Mach 96#define AOUT_TARGET_FORMAT "a.out-mach3" 97#endif 98#ifdef TE_DYNIX 99#define AOUT_TARGET_FORMAT "a.out-i386-dynix" 100#endif 101#ifndef AOUT_TARGET_FORMAT 102#define AOUT_TARGET_FORMAT "a.out-i386" 103#endif 104 105#ifdef TE_FreeBSD 106#define ELF_TARGET_FORMAT "elf32-i386-freebsd" 107#endif 108#ifndef ELF_TARGET_FORMAT 109#define ELF_TARGET_FORMAT "elf32-i386" 110#endif 111 112#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ 113 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) 114extern const char *i386_target_format PARAMS ((void)); 115#define TARGET_FORMAT i386_target_format () 116#else 117#ifdef OBJ_ELF 118#define TARGET_FORMAT ELF_TARGET_FORMAT 119#endif 120#ifdef OBJ_AOUT 121#define TARGET_FORMAT AOUT_TARGET_FORMAT 122#endif 123#endif 124 125#if (defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)) 126#define md_end i386_elf_emit_arch_note 127extern void i386_elf_emit_arch_note PARAMS ((void)); 128#endif 129 130#define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0 131 132#else /* ! BFD_ASSEMBLER */ 133 134/* COFF STUFF */ 135 136#define COFF_MAGIC I386MAGIC 137#define BFD_ARCH bfd_arch_i386 138#define COFF_FLAGS F_AR32WR 139#define TC_COUNT_RELOC(x) ((x)->fx_addsy || (x)->fx_r_type==7) 140#define TC_COFF_FIX2RTYPE(fixP) tc_coff_fix2rtype(fixP) 141extern short tc_coff_fix2rtype PARAMS ((struct fix *)); 142#define TC_COFF_SIZEMACHDEP(frag) tc_coff_sizemachdep (frag) 143extern int tc_coff_sizemachdep PARAMS ((fragS *frag)); 144 145#ifdef TE_GO32 146/* DJGPP now expects some sections to be 2**4 aligned. */ 147#define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) \ 148 ((strcmp (obj_segment_name (SEG), ".text") == 0 \ 149 || strcmp (obj_segment_name (SEG), ".data") == 0 \ 150 || strcmp (obj_segment_name (SEG), ".bss") == 0 \ 151 || strncmp (obj_segment_name (SEG), ".gnu.linkonce.t", 15) == 0 \ 152 || strncmp (obj_segment_name (SEG), ".gnu.linkonce.d", 15) == 0 \ 153 || strncmp (obj_segment_name (SEG), ".gnu.linkonce.r", 15) == 0) \ 154 ? 4 \ 155 : 2) 156#else 157#define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 2 158#endif 159 160#define TC_RVA_RELOC 7 161/* Need this for PIC relocations */ 162#define NEED_FX_R_TYPE 163 164#ifdef TE_386BSD 165/* The BSDI linker apparently rejects objects with a machine type of 166 M_386 (100). */ 167#define AOUT_MACHTYPE 0 168#else 169#define AOUT_MACHTYPE 100 170#endif 171 172#undef REVERSE_SORT_RELOCS 173 174#endif /* ! BFD_ASSEMBLER */ 175 176#ifndef LEX_AT 177#define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) x86_cons (EXP, NBYTES) 178extern void x86_cons PARAMS ((expressionS *, int)); 179 180#define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) x86_cons_fix_new(FRAG, OFF, LEN, EXP) 181extern void x86_cons_fix_new 182 PARAMS ((fragS *, unsigned int, unsigned int, expressionS *)); 183#endif 184 185#ifdef BFD_ASSEMBLER 186#define TC_FORCE_RELOCATION(FIXP) \ 187 ((FIXP)->fx_r_type == BFD_RELOC_VTABLE_INHERIT \ 188 || (FIXP)->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 189#else 190/* For COFF. */ 191#define TC_FORCE_RELOCATION(FIXP) \ 192 ((FIXP)->fx_r_type == 7) 193#endif 194 195#ifdef BFD_ASSEMBLER 196#define NO_RELOC BFD_RELOC_NONE 197#else 198#define NO_RELOC 0 199#endif 200#define tc_coff_symbol_emit_hook(a) ; /* not used */ 201 202#ifndef BFD_ASSEMBLER 203#ifndef OBJ_AOUT 204#ifndef TE_PE 205#ifndef TE_GO32 206/* Local labels starts with .L */ 207#define LOCAL_LABEL(name) (name[0] == '.' \ 208 && (name[1] == 'L' || name[1] == 'X' || name[1] == '.')) 209#endif 210#endif 211#endif 212#endif 213 214#define LOCAL_LABELS_FB 1 215 216#define tc_aout_pre_write_hook(x) {;} /* not used */ 217#define tc_crawl_symbol_chain(a) {;} /* not used */ 218#define tc_headers_hook(a) {;} /* not used */ 219 220extern const char extra_symbol_chars[]; 221#define tc_symbol_chars extra_symbol_chars 222 223#define MAX_OPERANDS 3 /* max operands per insn */ 224#define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp) */ 225#define MAX_MEMORY_OPERANDS 2 /* max memory refs per insn (string ops) */ 226 227/* Prefixes will be emitted in the order defined below. 228 WAIT_PREFIX must be the first prefix since FWAIT is really is an 229 instruction, and so must come before any prefixes. */ 230#define WAIT_PREFIX 0 231#define LOCKREP_PREFIX 1 232#define ADDR_PREFIX 2 233#define DATA_PREFIX 3 234#define SEG_PREFIX 4 235#define REX_PREFIX 5 /* must come last. */ 236#define MAX_PREFIXES 6 /* max prefixes per opcode */ 237 238/* we define the syntax here (modulo base,index,scale syntax) */ 239#define REGISTER_PREFIX '%' 240#define IMMEDIATE_PREFIX '$' 241#define ABSOLUTE_PREFIX '*' 242 243#define TWO_BYTE_OPCODE_ESCAPE 0x0f 244#define NOP_OPCODE (char) 0x90 245 246/* register numbers */ 247#define EBP_REG_NUM 5 248#define ESP_REG_NUM 4 249 250/* modrm_byte.regmem for twobyte escape */ 251#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM 252/* index_base_byte.index for no index register addressing */ 253#define NO_INDEX_REGISTER ESP_REG_NUM 254/* index_base_byte.base for no base register addressing */ 255#define NO_BASE_REGISTER EBP_REG_NUM 256#define NO_BASE_REGISTER_16 6 257 258/* these are the instruction mnemonic suffixes. */ 259#define WORD_MNEM_SUFFIX 'w' 260#define BYTE_MNEM_SUFFIX 'b' 261#define SHORT_MNEM_SUFFIX 's' 262#define LONG_MNEM_SUFFIX 'l' 263#define QWORD_MNEM_SUFFIX 'q' 264/* Intel Syntax */ 265#define LONG_DOUBLE_MNEM_SUFFIX 'x' 266 267/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */ 268#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */ 269#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG) 270 271#define END_OF_INSN '\0' 272 273/* Intel Syntax */ 274/* Values 0-4 map onto scale factor */ 275#define BYTE_PTR 0 276#define WORD_PTR 1 277#define DWORD_PTR 2 278#define QWORD_PTR 3 279#define XWORD_PTR 4 280#define SHORT 5 281#define OFFSET_FLAT 6 282#define FLAT 7 283#define NONE_FOUND 8 284 285typedef struct 286{ 287 /* instruction name sans width suffix ("mov" for movl insns) */ 288 char *name; 289 290 /* how many operands */ 291 unsigned int operands; 292 293 /* base_opcode is the fundamental opcode byte without optional 294 prefix(es). */ 295 unsigned int base_opcode; 296 297 /* extension_opcode is the 3 bit extension for group <n> insns. 298 This field is also used to store the 8-bit opcode suffix for the 299 AMD 3DNow! instructions. 300 If this template has no extension opcode (the usual case) use None */ 301 unsigned int extension_opcode; 302#define None 0xffff /* If no extension_opcode is possible. */ 303 304 /* cpu feature flags */ 305 unsigned int cpu_flags; 306#define Cpu086 0x1 /* Any old cpu will do, 0 does the same */ 307#define Cpu186 0x2 /* i186 or better required */ 308#define Cpu286 0x4 /* i286 or better required */ 309#define Cpu386 0x8 /* i386 or better required */ 310#define Cpu486 0x10 /* i486 or better required */ 311#define Cpu586 0x20 /* i585 or better required */ 312#define Cpu686 0x40 /* i686 or better required */ 313#define CpuP4 0x80 /* Pentium4 or better required */ 314#define CpuK6 0x100 /* AMD K6 or better required*/ 315#define CpuAthlon 0x200 /* AMD Athlon or better required*/ 316#define CpuSledgehammer 0x400 /* Sledgehammer or better required */ 317#define CpuMMX 0x800 /* MMX support required */ 318#define CpuSSE 0x1000 /* Streaming SIMD extensions required */ 319#define CpuSSE2 0x2000 /* Streaming SIMD extensions 2 required */ 320#define Cpu3dnow 0x4000 /* 3dnow! support required */ 321 322 /* These flags are set by gas depending on the flag_code. */ 323#define Cpu64 0x4000000 /* 64bit support required */ 324#define CpuNo64 0x8000000 /* Not supported in the 64bit mode */ 325 326 /* The default value for unknown CPUs - enable all features to avoid problems. */ 327#define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuSledgehammer|CpuMMX|CpuSSE|CpuSSE2|Cpu3dnow|CpuK6|CpuAthlon) 328 329 /* the bits in opcode_modifier are used to generate the final opcode from 330 the base_opcode. These bits also are used to detect alternate forms of 331 the same instruction */ 332 unsigned int opcode_modifier; 333 334 /* opcode_modifier bits: */ 335#define W 0x1 /* set if operands can be words or dwords 336 encoded the canonical way */ 337#define D 0x2 /* D = 0 if Reg --> Regmem; 338 D = 1 if Regmem --> Reg: MUST BE 0x2 */ 339#define Modrm 0x4 340#define FloatR 0x8 /* src/dest swap for floats: MUST BE 0x8 */ 341#define ShortForm 0x10 /* register is in low 3 bits of opcode */ 342#define FloatMF 0x20 /* FP insn memory format bit, sized by 0x4 */ 343#define Jump 0x40 /* special case for jump insns. */ 344#define JumpDword 0x80 /* call and jump */ 345#define JumpByte 0x100 /* loop and jecxz */ 346#define JumpInterSegment 0x200 /* special case for intersegment leaps/calls */ 347#define FloatD 0x400 /* direction for float insns: MUST BE 0x400 */ 348#define Seg2ShortForm 0x800 /* encoding of load segment reg insns */ 349#define Seg3ShortForm 0x1000 /* fs/gs segment register insns. */ 350#define Size16 0x2000 /* needs size prefix if in 32-bit mode */ 351#define Size32 0x4000 /* needs size prefix if in 16-bit mode */ 352#define Size64 0x8000 /* needs size prefix if in 16-bit mode */ 353#define IgnoreSize 0x10000 /* instruction ignores operand size prefix */ 354#define DefaultSize 0x20000 /* default insn size depends on mode */ 355#define No_bSuf 0x40000 /* b suffix on instruction illegal */ 356#define No_wSuf 0x80000 /* w suffix on instruction illegal */ 357#define No_lSuf 0x100000 /* l suffix on instruction illegal */ 358#define No_sSuf 0x200000 /* s suffix on instruction illegal */ 359#define No_qSuf 0x400000 /* q suffix on instruction illegal */ 360#define No_xSuf 0x800000 /* x suffix on instruction illegal */ 361#define FWait 0x1000000 /* instruction needs FWAIT */ 362#define IsString 0x2000000 /* quick test for string instructions */ 363#define regKludge 0x4000000 /* fake an extra reg operand for clr, imul */ 364#define IsPrefix 0x8000000 /* opcode is a prefix */ 365#define ImmExt 0x10000000 /* instruction has extension in 8 bit imm */ 366#define NoRex64 0x20000000 /* instruction don't need Rex64 prefix. */ 367#define Rex64 0x40000000 /* instruction require Rex64 prefix. */ 368#define Ugh 0x80000000 /* deprecated fp insn, gets a warning */ 369 370 /* operand_types[i] describes the type of operand i. This is made 371 by OR'ing together all of the possible type masks. (e.g. 372 'operand_types[i] = Reg|Imm' specifies that operand i can be 373 either a register or an immediate operand. */ 374 unsigned int operand_types[3]; 375 376 /* operand_types[i] bits */ 377 /* register */ 378#define Reg8 0x1 /* 8 bit reg */ 379#define Reg16 0x2 /* 16 bit reg */ 380#define Reg32 0x4 /* 32 bit reg */ 381#define Reg64 0x8 /* 64 bit reg */ 382 /* immediate */ 383#define Imm8 0x10 /* 8 bit immediate */ 384#define Imm8S 0x20 /* 8 bit immediate sign extended */ 385#define Imm16 0x40 /* 16 bit immediate */ 386#define Imm32 0x80 /* 32 bit immediate */ 387#define Imm32S 0x100 /* 32 bit immediate sign extended */ 388#define Imm64 0x200 /* 64 bit immediate */ 389#define Imm1 0x400 /* 1 bit immediate */ 390 /* memory */ 391#define BaseIndex 0x800 392 /* Disp8,16,32 are used in different ways, depending on the 393 instruction. For jumps, they specify the size of the PC relative 394 displacement, for baseindex type instructions, they specify the 395 size of the offset relative to the base register, and for memory 396 offset instructions such as `mov 1234,%al' they specify the size of 397 the offset relative to the segment base. */ 398#define Disp8 0x1000 /* 8 bit displacement */ 399#define Disp16 0x2000 /* 16 bit displacement */ 400#define Disp32 0x4000 /* 32 bit displacement */ 401#define Disp32S 0x8000 /* 32 bit signed displacement */ 402#define Disp64 0x10000 /* 64 bit displacement */ 403 /* specials */ 404#define InOutPortReg 0x20000 /* register to hold in/out port addr = dx */ 405#define ShiftCount 0x40000 /* register to hold shift cound = cl */ 406#define Control 0x80000 /* Control register */ 407#define Debug 0x100000 /* Debug register */ 408#define Test 0x200000 /* Test register */ 409#define FloatReg 0x400000 /* Float register */ 410#define FloatAcc 0x800000 /* Float stack top %st(0) */ 411#define SReg2 0x1000000 /* 2 bit segment register */ 412#define SReg3 0x2000000 /* 3 bit segment register */ 413#define Acc 0x4000000 /* Accumulator %al or %ax or %eax */ 414#define JumpAbsolute 0x8000000 415#define RegMMX 0x10000000 /* MMX register */ 416#define RegXMM 0x20000000 /* XMM registers in PIII */ 417#define EsSeg 0x40000000 /* String insn operand with fixed es segment */ 418 419 /* InvMem is for instructions with a modrm byte that only allow a 420 general register encoding in the i.tm.mode and i.tm.regmem fields, 421 eg. control reg moves. They really ought to support a memory form, 422 but don't, so we add an InvMem flag to the register operand to 423 indicate that it should be encoded in the i.tm.regmem field. */ 424#define InvMem 0x80000000 425 426#define Reg (Reg8|Reg16|Reg32|Reg64) /* gen'l register */ 427#define WordReg (Reg16|Reg32|Reg64) 428#define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc) 429#define Imm (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */ 430#define EncImm (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */ 431#define Disp (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */ 432#define AnyMem (Disp8|Disp16|Disp32|Disp32S|BaseIndex|InvMem) /* General memory */ 433 /* The following aliases are defined because the opcode table 434 carefully specifies the allowed memory types for each instruction. 435 At the moment we can only tell a memory reference size by the 436 instruction suffix, so there's not much point in defining Mem8, 437 Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use 438 the suffix directly to check memory operands. */ 439#define LLongMem AnyMem /* 64 bits (or more) */ 440#define LongMem AnyMem /* 32 bit memory ref */ 441#define ShortMem AnyMem /* 16 bit memory ref */ 442#define WordMem AnyMem /* 16 or 32 bit memory ref */ 443#define ByteMem AnyMem /* 8 bit memory ref */ 444} 445template; 446 447/* 448 'templates' is for grouping together 'template' structures for opcodes 449 of the same name. This is only used for storing the insns in the grand 450 ole hash table of insns. 451 The templates themselves start at START and range up to (but not including) 452 END. 453 */ 454typedef struct 455{ 456 const template *start; 457 const template *end; 458} 459templates; 460 461/* these are for register name --> number & type hash lookup */ 462typedef struct 463{ 464 char *reg_name; 465 unsigned int reg_type; 466 unsigned int reg_flags; 467#define RegRex 0x1 /* Extended register. */ 468#define RegRex64 0x2 /* Extended 8 bit register. */ 469 unsigned int reg_num; 470} 471reg_entry; 472 473typedef struct 474{ 475 char *seg_name; 476 unsigned int seg_prefix; 477} 478seg_entry; 479 480/* 386 operand encoding bytes: see 386 book for details of this. */ 481typedef struct 482{ 483 unsigned int regmem; /* codes register or memory operand */ 484 unsigned int reg; /* codes register operand (or extended opcode) */ 485 unsigned int mode; /* how to interpret regmem & reg */ 486} 487modrm_byte; 488 489/* x86-64 extension prefix. */ 490typedef int rex_byte; 491#define REX_OPCODE 0x40 492 493/* Indicates 64 bit operand size. */ 494#define REX_MODE64 8 495/* High extension to reg field of modrm byte. */ 496#define REX_EXTX 4 497/* High extension to SIB index field. */ 498#define REX_EXTY 2 499/* High extension to base field of modrm or SIB, or reg field of opcode. */ 500#define REX_EXTZ 1 501 502/* 386 opcode byte to code indirect addressing. */ 503typedef struct 504{ 505 unsigned base; 506 unsigned index; 507 unsigned scale; 508} 509sib_byte; 510 511/* x86 arch names and features */ 512typedef struct 513{ 514 const char *name; /* arch name */ 515 unsigned int flags; /* cpu feature flags */ 516} 517arch_entry; 518 519/* The name of the global offset table generated by the compiler. Allow 520 this to be overridden if need be. */ 521#ifndef GLOBAL_OFFSET_TABLE_NAME 522#define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_" 523#endif 524 525#ifdef BFD_ASSEMBLER 526void i386_validate_fix PARAMS ((struct fix *)); 527#define TC_VALIDATE_FIX(FIXP,SEGTYPE,SKIP) i386_validate_fix(FIXP) 528#endif 529 530#endif /* TC_I386 */ 531 532#define md_operand(x) 533 534extern const struct relax_type md_relax_table[]; 535#define TC_GENERIC_RELAX_TABLE md_relax_table 536 537#define md_do_align(n, fill, len, max, around) \ 538if ((n) && !need_pass_2 \ 539 && (!(fill) || ((char)*(fill) == (char)0x90 && (len) == 1)) \ 540 && subseg_text_p (now_seg)) \ 541 { \ 542 frag_align_code ((n), (max)); \ 543 goto around; \ 544 } 545 546#define MAX_MEM_FOR_RS_ALIGN_CODE 15 547 548extern void i386_align_code PARAMS ((fragS *, int)); 549 550#define HANDLE_ALIGN(fragP) \ 551if (fragP->fr_type == rs_align_code) \ 552 i386_align_code (fragP, (fragP->fr_next->fr_address \ 553 - fragP->fr_address \ 554 - fragP->fr_fix)); 555 556void i386_print_statistics PARAMS ((FILE *)); 557#define tc_print_statistics i386_print_statistics 558 559#define md_number_to_chars number_to_chars_littleendian 560 561#ifdef SCO_ELF 562#define tc_init_after_args() sco_id () 563extern void sco_id PARAMS ((void)); 564#endif 565 566#define DIFF_EXPR_OK /* foo-. gets turned into PC relative relocs */ 567