pci_passthru.c revision 268887
1/*- 2 * Copyright (c) 2011 NetApp, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: stable/10/usr.sbin/bhyve/pci_passthru.c 268887 2014-07-19 20:13:01Z jhb $ 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: stable/10/usr.sbin/bhyve/pci_passthru.c 268887 2014-07-19 20:13:01Z jhb $"); 31 32#include <sys/param.h> 33#include <sys/types.h> 34#include <sys/pciio.h> 35#include <sys/ioctl.h> 36 37#include <dev/io/iodev.h> 38#include <dev/pci/pcireg.h> 39 40#include <machine/iodev.h> 41 42#include <stdio.h> 43#include <stdlib.h> 44#include <string.h> 45#include <errno.h> 46#include <fcntl.h> 47#include <unistd.h> 48 49#include <machine/vmm.h> 50#include <vmmapi.h> 51#include "pci_emul.h" 52#include "mem.h" 53 54#ifndef _PATH_DEVPCI 55#define _PATH_DEVPCI "/dev/pci" 56#endif 57 58#ifndef _PATH_DEVIO 59#define _PATH_DEVIO "/dev/io" 60#endif 61 62#define LEGACY_SUPPORT 1 63 64#define MSIX_TABLE_COUNT(ctrl) (((ctrl) & PCIM_MSIXCTRL_TABLE_SIZE) + 1) 65#define MSIX_CAPLEN 12 66 67static int pcifd = -1; 68static int iofd = -1; 69 70struct passthru_softc { 71 struct pci_devinst *psc_pi; 72 struct pcibar psc_bar[PCI_BARMAX + 1]; 73 struct { 74 int capoff; 75 int msgctrl; 76 int emulated; 77 } psc_msi; 78 struct { 79 int capoff; 80 } psc_msix; 81 struct pcisel psc_sel; 82}; 83 84static int 85msi_caplen(int msgctrl) 86{ 87 int len; 88 89 len = 10; /* minimum length of msi capability */ 90 91 if (msgctrl & PCIM_MSICTRL_64BIT) 92 len += 4; 93 94#if 0 95 /* 96 * Ignore the 'mask' and 'pending' bits in the MSI capability. 97 * We'll let the guest manipulate them directly. 98 */ 99 if (msgctrl & PCIM_MSICTRL_VECTOR) 100 len += 10; 101#endif 102 103 return (len); 104} 105 106static uint32_t 107read_config(const struct pcisel *sel, long reg, int width) 108{ 109 struct pci_io pi; 110 111 bzero(&pi, sizeof(pi)); 112 pi.pi_sel = *sel; 113 pi.pi_reg = reg; 114 pi.pi_width = width; 115 116 if (ioctl(pcifd, PCIOCREAD, &pi) < 0) 117 return (0); /* XXX */ 118 else 119 return (pi.pi_data); 120} 121 122static void 123write_config(const struct pcisel *sel, long reg, int width, uint32_t data) 124{ 125 struct pci_io pi; 126 127 bzero(&pi, sizeof(pi)); 128 pi.pi_sel = *sel; 129 pi.pi_reg = reg; 130 pi.pi_width = width; 131 pi.pi_data = data; 132 133 (void)ioctl(pcifd, PCIOCWRITE, &pi); /* XXX */ 134} 135 136#ifdef LEGACY_SUPPORT 137static int 138passthru_add_msicap(struct pci_devinst *pi, int msgnum, int nextptr) 139{ 140 int capoff, i; 141 struct msicap msicap; 142 u_char *capdata; 143 144 pci_populate_msicap(&msicap, msgnum, nextptr); 145 146 /* 147 * XXX 148 * Copy the msi capability structure in the last 16 bytes of the 149 * config space. This is wrong because it could shadow something 150 * useful to the device. 151 */ 152 capoff = 256 - roundup(sizeof(msicap), 4); 153 capdata = (u_char *)&msicap; 154 for (i = 0; i < sizeof(msicap); i++) 155 pci_set_cfgdata8(pi, capoff + i, capdata[i]); 156 157 return (capoff); 158} 159#endif /* LEGACY_SUPPORT */ 160 161static int 162cfginitmsi(struct passthru_softc *sc) 163{ 164 int i, ptr, capptr, cap, sts, caplen, table_size; 165 uint32_t u32; 166 struct pcisel sel; 167 struct pci_devinst *pi; 168 struct msixcap msixcap; 169 uint32_t *msixcap_ptr; 170 171 pi = sc->psc_pi; 172 sel = sc->psc_sel; 173 174 /* 175 * Parse the capabilities and cache the location of the MSI 176 * and MSI-X capabilities. 177 */ 178 sts = read_config(&sel, PCIR_STATUS, 2); 179 if (sts & PCIM_STATUS_CAPPRESENT) { 180 ptr = read_config(&sel, PCIR_CAP_PTR, 1); 181 while (ptr != 0 && ptr != 0xff) { 182 cap = read_config(&sel, ptr + PCICAP_ID, 1); 183 if (cap == PCIY_MSI) { 184 /* 185 * Copy the MSI capability into the config 186 * space of the emulated pci device 187 */ 188 sc->psc_msi.capoff = ptr; 189 sc->psc_msi.msgctrl = read_config(&sel, 190 ptr + 2, 2); 191 sc->psc_msi.emulated = 0; 192 caplen = msi_caplen(sc->psc_msi.msgctrl); 193 capptr = ptr; 194 while (caplen > 0) { 195 u32 = read_config(&sel, capptr, 4); 196 pci_set_cfgdata32(pi, capptr, u32); 197 caplen -= 4; 198 capptr += 4; 199 } 200 } else if (cap == PCIY_MSIX) { 201 /* 202 * Copy the MSI-X capability 203 */ 204 sc->psc_msix.capoff = ptr; 205 caplen = 12; 206 msixcap_ptr = (uint32_t*) &msixcap; 207 capptr = ptr; 208 while (caplen > 0) { 209 u32 = read_config(&sel, capptr, 4); 210 *msixcap_ptr = u32; 211 pci_set_cfgdata32(pi, capptr, u32); 212 caplen -= 4; 213 capptr += 4; 214 msixcap_ptr++; 215 } 216 } 217 ptr = read_config(&sel, ptr + PCICAP_NEXTPTR, 1); 218 } 219 } 220 221 if (sc->psc_msix.capoff != 0) { 222 pi->pi_msix.pba_bar = 223 msixcap.pba_info & PCIM_MSIX_BIR_MASK; 224 pi->pi_msix.pba_offset = 225 msixcap.pba_info & ~PCIM_MSIX_BIR_MASK; 226 pi->pi_msix.table_bar = 227 msixcap.table_info & PCIM_MSIX_BIR_MASK; 228 pi->pi_msix.table_offset = 229 msixcap.table_info & ~PCIM_MSIX_BIR_MASK; 230 pi->pi_msix.table_count = MSIX_TABLE_COUNT(msixcap.msgctrl); 231 pi->pi_msix.pba_size = PBA_SIZE(pi->pi_msix.table_count); 232 233 /* Allocate the emulated MSI-X table array */ 234 table_size = pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE; 235 pi->pi_msix.table = malloc(table_size); 236 bzero(pi->pi_msix.table, table_size); 237 238 /* Mask all table entries */ 239 for (i = 0; i < pi->pi_msix.table_count; i++) { 240 pi->pi_msix.table[i].vector_control |= 241 PCIM_MSIX_VCTRL_MASK; 242 } 243 } 244 245#ifdef LEGACY_SUPPORT 246 /* 247 * If the passthrough device does not support MSI then craft a 248 * MSI capability for it. We link the new MSI capability at the 249 * head of the list of capabilities. 250 */ 251 if ((sts & PCIM_STATUS_CAPPRESENT) != 0 && sc->psc_msi.capoff == 0) { 252 int origptr, msiptr; 253 origptr = read_config(&sel, PCIR_CAP_PTR, 1); 254 msiptr = passthru_add_msicap(pi, 1, origptr); 255 sc->psc_msi.capoff = msiptr; 256 sc->psc_msi.msgctrl = pci_get_cfgdata16(pi, msiptr + 2); 257 sc->psc_msi.emulated = 1; 258 pci_set_cfgdata8(pi, PCIR_CAP_PTR, msiptr); 259 } 260#endif 261 262 /* Make sure one of the capabilities is present */ 263 if (sc->psc_msi.capoff == 0 && sc->psc_msix.capoff == 0) 264 return (-1); 265 else 266 return (0); 267} 268 269static uint64_t 270msix_table_read(struct passthru_softc *sc, uint64_t offset, int size) 271{ 272 struct pci_devinst *pi; 273 struct msix_table_entry *entry; 274 uint8_t *src8; 275 uint16_t *src16; 276 uint32_t *src32; 277 uint64_t *src64; 278 uint64_t data; 279 size_t entry_offset; 280 int index; 281 282 pi = sc->psc_pi; 283 if (offset < pi->pi_msix.table_offset) 284 return (-1); 285 286 offset -= pi->pi_msix.table_offset; 287 index = offset / MSIX_TABLE_ENTRY_SIZE; 288 if (index >= pi->pi_msix.table_count) 289 return (-1); 290 291 entry = &pi->pi_msix.table[index]; 292 entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 293 294 switch(size) { 295 case 1: 296 src8 = (uint8_t *)((void *)entry + entry_offset); 297 data = *src8; 298 break; 299 case 2: 300 src16 = (uint16_t *)((void *)entry + entry_offset); 301 data = *src16; 302 break; 303 case 4: 304 src32 = (uint32_t *)((void *)entry + entry_offset); 305 data = *src32; 306 break; 307 case 8: 308 src64 = (uint64_t *)((void *)entry + entry_offset); 309 data = *src64; 310 break; 311 default: 312 return (-1); 313 } 314 315 return (data); 316} 317 318static void 319msix_table_write(struct vmctx *ctx, int vcpu, struct passthru_softc *sc, 320 uint64_t offset, int size, uint64_t data) 321{ 322 struct pci_devinst *pi; 323 struct msix_table_entry *entry; 324 uint32_t *dest; 325 size_t entry_offset; 326 uint32_t vector_control; 327 int error, index; 328 329 pi = sc->psc_pi; 330 if (offset < pi->pi_msix.table_offset) 331 return; 332 333 offset -= pi->pi_msix.table_offset; 334 index = offset / MSIX_TABLE_ENTRY_SIZE; 335 if (index >= pi->pi_msix.table_count) 336 return; 337 338 entry = &pi->pi_msix.table[index]; 339 entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 340 341 /* Only 4 byte naturally-aligned writes are supported */ 342 assert(size == 4); 343 assert(entry_offset % 4 == 0); 344 345 vector_control = entry->vector_control; 346 dest = (uint32_t *)((void *)entry + entry_offset); 347 *dest = data; 348 /* If MSI-X hasn't been enabled, do nothing */ 349 if (pi->pi_msix.enabled) { 350 /* If the entry is masked, don't set it up */ 351 if ((entry->vector_control & PCIM_MSIX_VCTRL_MASK) == 0 || 352 (vector_control & PCIM_MSIX_VCTRL_MASK) == 0) { 353 error = vm_setup_pptdev_msix(ctx, vcpu, 354 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev, 355 sc->psc_sel.pc_func, index, entry->addr, 356 entry->msg_data, entry->vector_control); 357 } 358 } 359} 360 361static int 362init_msix_table(struct vmctx *ctx, struct passthru_softc *sc, uint64_t base) 363{ 364 int b, s, f; 365 int error, idx; 366 size_t len, remaining; 367 uint32_t table_size, table_offset; 368 uint32_t pba_size, pba_offset; 369 vm_paddr_t start; 370 struct pci_devinst *pi = sc->psc_pi; 371 372 assert(pci_msix_table_bar(pi) >= 0 && pci_msix_pba_bar(pi) >= 0); 373 374 b = sc->psc_sel.pc_bus; 375 s = sc->psc_sel.pc_dev; 376 f = sc->psc_sel.pc_func; 377 378 /* 379 * If the MSI-X table BAR maps memory intended for 380 * other uses, it is at least assured that the table 381 * either resides in its own page within the region, 382 * or it resides in a page shared with only the PBA. 383 */ 384 table_offset = rounddown2(pi->pi_msix.table_offset, 4096); 385 386 table_size = pi->pi_msix.table_offset - table_offset; 387 table_size += pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE; 388 table_size = roundup2(table_size, 4096); 389 390 if (pi->pi_msix.pba_bar == pi->pi_msix.table_bar) { 391 pba_offset = pi->pi_msix.pba_offset; 392 pba_size = pi->pi_msix.pba_size; 393 if (pba_offset >= table_offset + table_size || 394 table_offset >= pba_offset + pba_size) { 395 /* 396 * The PBA can reside in the same BAR as the MSI-x 397 * tables as long as it does not overlap with any 398 * naturally aligned page occupied by the tables. 399 */ 400 } else { 401 /* Need to also emulate the PBA, not supported yet */ 402 printf("Unsupported MSI-X configuration: %d/%d/%d\n", 403 b, s, f); 404 return (-1); 405 } 406 } 407 408 idx = pi->pi_msix.table_bar; 409 start = pi->pi_bar[idx].addr; 410 remaining = pi->pi_bar[idx].size; 411 412 /* Map everything before the MSI-X table */ 413 if (table_offset > 0) { 414 len = table_offset; 415 error = vm_map_pptdev_mmio(ctx, b, s, f, start, len, base); 416 if (error) 417 return (error); 418 419 base += len; 420 start += len; 421 remaining -= len; 422 } 423 424 /* Skip the MSI-X table */ 425 base += table_size; 426 start += table_size; 427 remaining -= table_size; 428 429 /* Map everything beyond the end of the MSI-X table */ 430 if (remaining > 0) { 431 len = remaining; 432 error = vm_map_pptdev_mmio(ctx, b, s, f, start, len, base); 433 if (error) 434 return (error); 435 } 436 437 return (0); 438} 439 440static int 441cfginitbar(struct vmctx *ctx, struct passthru_softc *sc) 442{ 443 int i, error; 444 struct pci_devinst *pi; 445 struct pci_bar_io bar; 446 enum pcibar_type bartype; 447 uint64_t base, size; 448 449 pi = sc->psc_pi; 450 451 /* 452 * Initialize BAR registers 453 */ 454 for (i = 0; i <= PCI_BARMAX; i++) { 455 bzero(&bar, sizeof(bar)); 456 bar.pbi_sel = sc->psc_sel; 457 bar.pbi_reg = PCIR_BAR(i); 458 459 if (ioctl(pcifd, PCIOCGETBAR, &bar) < 0) 460 continue; 461 462 if (PCI_BAR_IO(bar.pbi_base)) { 463 bartype = PCIBAR_IO; 464 base = bar.pbi_base & PCIM_BAR_IO_BASE; 465 } else { 466 switch (bar.pbi_base & PCIM_BAR_MEM_TYPE) { 467 case PCIM_BAR_MEM_64: 468 bartype = PCIBAR_MEM64; 469 break; 470 default: 471 bartype = PCIBAR_MEM32; 472 break; 473 } 474 base = bar.pbi_base & PCIM_BAR_MEM_BASE; 475 } 476 size = bar.pbi_length; 477 478 if (bartype != PCIBAR_IO) { 479 if (((base | size) & PAGE_MASK) != 0) { 480 printf("passthru device %d/%d/%d BAR %d: " 481 "base %#lx or size %#lx not page aligned\n", 482 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev, 483 sc->psc_sel.pc_func, i, base, size); 484 return (-1); 485 } 486 } 487 488 /* Cache information about the "real" BAR */ 489 sc->psc_bar[i].type = bartype; 490 sc->psc_bar[i].size = size; 491 sc->psc_bar[i].addr = base; 492 493 /* Allocate the BAR in the guest I/O or MMIO space */ 494 error = pci_emul_alloc_pbar(pi, i, base, bartype, size); 495 if (error) 496 return (-1); 497 498 /* The MSI-X table needs special handling */ 499 if (i == pci_msix_table_bar(pi)) { 500 error = init_msix_table(ctx, sc, base); 501 if (error) 502 return (-1); 503 } else if (bartype != PCIBAR_IO) { 504 /* Map the physical BAR in the guest MMIO space */ 505 error = vm_map_pptdev_mmio(ctx, sc->psc_sel.pc_bus, 506 sc->psc_sel.pc_dev, sc->psc_sel.pc_func, 507 pi->pi_bar[i].addr, pi->pi_bar[i].size, base); 508 if (error) 509 return (-1); 510 } 511 512 /* 513 * 64-bit BAR takes up two slots so skip the next one. 514 */ 515 if (bartype == PCIBAR_MEM64) { 516 i++; 517 assert(i <= PCI_BARMAX); 518 sc->psc_bar[i].type = PCIBAR_MEMHI64; 519 } 520 } 521 return (0); 522} 523 524static int 525cfginit(struct vmctx *ctx, struct pci_devinst *pi, int bus, int slot, int func) 526{ 527 int error; 528 struct passthru_softc *sc; 529 530 error = 1; 531 sc = pi->pi_arg; 532 533 bzero(&sc->psc_sel, sizeof(struct pcisel)); 534 sc->psc_sel.pc_bus = bus; 535 sc->psc_sel.pc_dev = slot; 536 sc->psc_sel.pc_func = func; 537 538 if (cfginitmsi(sc) != 0) 539 goto done; 540 541 if (cfginitbar(ctx, sc) != 0) 542 goto done; 543 544 error = 0; /* success */ 545done: 546 return (error); 547} 548 549static int 550passthru_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts) 551{ 552 int bus, slot, func, error; 553 struct passthru_softc *sc; 554 555 sc = NULL; 556 error = 1; 557 558 if (pcifd < 0) { 559 pcifd = open(_PATH_DEVPCI, O_RDWR, 0); 560 if (pcifd < 0) 561 goto done; 562 } 563 564 if (iofd < 0) { 565 iofd = open(_PATH_DEVIO, O_RDWR, 0); 566 if (iofd < 0) 567 goto done; 568 } 569 570 if (opts == NULL || 571 sscanf(opts, "%d/%d/%d", &bus, &slot, &func) != 3) 572 goto done; 573 574 if (vm_assign_pptdev(ctx, bus, slot, func) != 0) 575 goto done; 576 577 sc = malloc(sizeof(struct passthru_softc)); 578 memset(sc, 0, sizeof(struct passthru_softc)); 579 580 pi->pi_arg = sc; 581 sc->psc_pi = pi; 582 583 /* initialize config space */ 584 if ((error = cfginit(ctx, pi, bus, slot, func)) != 0) 585 goto done; 586 587 error = 0; /* success */ 588done: 589 if (error) { 590 free(sc); 591 vm_unassign_pptdev(ctx, bus, slot, func); 592 } 593 return (error); 594} 595 596static int 597bar_access(int coff) 598{ 599 if (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1)) 600 return (1); 601 else 602 return (0); 603} 604 605static int 606msicap_access(struct passthru_softc *sc, int coff) 607{ 608 int caplen; 609 610 if (sc->psc_msi.capoff == 0) 611 return (0); 612 613 caplen = msi_caplen(sc->psc_msi.msgctrl); 614 615 if (coff >= sc->psc_msi.capoff && coff < sc->psc_msi.capoff + caplen) 616 return (1); 617 else 618 return (0); 619} 620 621static int 622msixcap_access(struct passthru_softc *sc, int coff) 623{ 624 if (sc->psc_msix.capoff == 0) 625 return (0); 626 627 return (coff >= sc->psc_msix.capoff && 628 coff < sc->psc_msix.capoff + MSIX_CAPLEN); 629} 630 631static int 632passthru_cfgread(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, 633 int coff, int bytes, uint32_t *rv) 634{ 635 struct passthru_softc *sc; 636 637 sc = pi->pi_arg; 638 639 /* 640 * PCI BARs and MSI capability is emulated. 641 */ 642 if (bar_access(coff) || msicap_access(sc, coff)) 643 return (-1); 644 645#ifdef LEGACY_SUPPORT 646 /* 647 * Emulate PCIR_CAP_PTR if this device does not support MSI capability 648 * natively. 649 */ 650 if (sc->psc_msi.emulated) { 651 if (coff >= PCIR_CAP_PTR && coff < PCIR_CAP_PTR + 4) 652 return (-1); 653 } 654#endif 655 656 /* Everything else just read from the device's config space */ 657 *rv = read_config(&sc->psc_sel, coff, bytes); 658 659 return (0); 660} 661 662static int 663passthru_cfgwrite(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, 664 int coff, int bytes, uint32_t val) 665{ 666 int error, msix_table_entries, i; 667 struct passthru_softc *sc; 668 669 sc = pi->pi_arg; 670 671 /* 672 * PCI BARs are emulated 673 */ 674 if (bar_access(coff)) 675 return (-1); 676 677 /* 678 * MSI capability is emulated 679 */ 680 if (msicap_access(sc, coff)) { 681 msicap_cfgwrite(pi, sc->psc_msi.capoff, coff, bytes, val); 682 683 error = vm_setup_pptdev_msi(ctx, vcpu, sc->psc_sel.pc_bus, 684 sc->psc_sel.pc_dev, sc->psc_sel.pc_func, 685 pi->pi_msi.addr, pi->pi_msi.msg_data, 686 pi->pi_msi.maxmsgnum); 687 if (error != 0) { 688 printf("vm_setup_pptdev_msi error %d\r\n", errno); 689 exit(1); 690 } 691 return (0); 692 } 693 694 if (msixcap_access(sc, coff)) { 695 msixcap_cfgwrite(pi, sc->psc_msix.capoff, coff, bytes, val); 696 if (pi->pi_msix.enabled) { 697 msix_table_entries = pi->pi_msix.table_count; 698 for (i = 0; i < msix_table_entries; i++) { 699 error = vm_setup_pptdev_msix(ctx, vcpu, 700 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev, 701 sc->psc_sel.pc_func, i, 702 pi->pi_msix.table[i].addr, 703 pi->pi_msix.table[i].msg_data, 704 pi->pi_msix.table[i].vector_control); 705 706 if (error) { 707 printf("vm_setup_pptdev_msix error " 708 "%d\r\n", errno); 709 exit(1); 710 } 711 } 712 } 713 return (0); 714 } 715 716#ifdef LEGACY_SUPPORT 717 /* 718 * If this device does not support MSI natively then we cannot let 719 * the guest disable legacy interrupts from the device. It is the 720 * legacy interrupt that is triggering the virtual MSI to the guest. 721 */ 722 if (sc->psc_msi.emulated && pci_msi_enabled(pi)) { 723 if (coff == PCIR_COMMAND && bytes == 2) 724 val &= ~PCIM_CMD_INTxDIS; 725 } 726#endif 727 728 write_config(&sc->psc_sel, coff, bytes, val); 729 730 return (0); 731} 732 733static void 734passthru_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 735 uint64_t offset, int size, uint64_t value) 736{ 737 struct passthru_softc *sc; 738 struct iodev_pio_req pio; 739 740 sc = pi->pi_arg; 741 742 if (baridx == pci_msix_table_bar(pi)) { 743 msix_table_write(ctx, vcpu, sc, offset, size, value); 744 } else { 745 assert(pi->pi_bar[baridx].type == PCIBAR_IO); 746 bzero(&pio, sizeof(struct iodev_pio_req)); 747 pio.access = IODEV_PIO_WRITE; 748 pio.port = sc->psc_bar[baridx].addr + offset; 749 pio.width = size; 750 pio.val = value; 751 752 (void)ioctl(iofd, IODEV_PIO, &pio); 753 } 754} 755 756static uint64_t 757passthru_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 758 uint64_t offset, int size) 759{ 760 struct passthru_softc *sc; 761 struct iodev_pio_req pio; 762 uint64_t val; 763 764 sc = pi->pi_arg; 765 766 if (baridx == pci_msix_table_bar(pi)) { 767 val = msix_table_read(sc, offset, size); 768 } else { 769 assert(pi->pi_bar[baridx].type == PCIBAR_IO); 770 bzero(&pio, sizeof(struct iodev_pio_req)); 771 pio.access = IODEV_PIO_READ; 772 pio.port = sc->psc_bar[baridx].addr + offset; 773 pio.width = size; 774 pio.val = 0; 775 776 (void)ioctl(iofd, IODEV_PIO, &pio); 777 778 val = pio.val; 779 } 780 781 return (val); 782} 783 784struct pci_devemu passthru = { 785 .pe_emu = "passthru", 786 .pe_init = passthru_init, 787 .pe_cfgwrite = passthru_cfgwrite, 788 .pe_cfgread = passthru_cfgread, 789 .pe_barwrite = passthru_write, 790 .pe_barread = passthru_read, 791}; 792PCI_EMUL_SET(passthru); 793