pci_emul.h revision 268887
1/*- 2 * Copyright (c) 2011 NetApp, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: stable/10/usr.sbin/bhyve/pci_emul.h 268887 2014-07-19 20:13:01Z jhb $ 27 */ 28 29#ifndef _PCI_EMUL_H_ 30#define _PCI_EMUL_H_ 31 32#include <sys/types.h> 33#include <sys/queue.h> 34#include <sys/kernel.h> 35#include <sys/_pthreadtypes.h> 36 37#include <dev/pci/pcireg.h> 38 39#include <assert.h> 40 41#define PCI_BARMAX PCIR_MAX_BAR_0 /* BAR registers in a Type 0 header */ 42 43struct vmctx; 44struct pci_devinst; 45struct memory_region; 46 47struct pci_devemu { 48 char *pe_emu; /* Name of device emulation */ 49 50 /* instance creation */ 51 int (*pe_init)(struct vmctx *, struct pci_devinst *, 52 char *opts); 53 54 /* ACPI DSDT enumeration */ 55 void (*pe_write_dsdt)(struct pci_devinst *); 56 57 /* config space read/write callbacks */ 58 int (*pe_cfgwrite)(struct vmctx *ctx, int vcpu, 59 struct pci_devinst *pi, int offset, 60 int bytes, uint32_t val); 61 int (*pe_cfgread)(struct vmctx *ctx, int vcpu, 62 struct pci_devinst *pi, int offset, 63 int bytes, uint32_t *retval); 64 65 /* BAR read/write callbacks */ 66 void (*pe_barwrite)(struct vmctx *ctx, int vcpu, 67 struct pci_devinst *pi, int baridx, 68 uint64_t offset, int size, uint64_t value); 69 uint64_t (*pe_barread)(struct vmctx *ctx, int vcpu, 70 struct pci_devinst *pi, int baridx, 71 uint64_t offset, int size); 72}; 73#define PCI_EMUL_SET(x) DATA_SET(pci_devemu_set, x); 74 75enum pcibar_type { 76 PCIBAR_NONE, 77 PCIBAR_IO, 78 PCIBAR_MEM32, 79 PCIBAR_MEM64, 80 PCIBAR_MEMHI64 81}; 82 83struct pcibar { 84 enum pcibar_type type; /* io or memory */ 85 uint64_t size; 86 uint64_t addr; 87}; 88 89#define PI_NAMESZ 40 90 91struct msix_table_entry { 92 uint64_t addr; 93 uint32_t msg_data; 94 uint32_t vector_control; 95} __packed; 96 97/* 98 * In case the structure is modified to hold extra information, use a define 99 * for the size that should be emulated. 100 */ 101#define MSIX_TABLE_ENTRY_SIZE 16 102#define MAX_MSIX_TABLE_ENTRIES 2048 103#define PBA_SIZE(msgnum) (roundup2((msgnum), 64) / 8) 104 105enum lintr_stat { 106 IDLE, 107 ASSERTED, 108 PENDING 109}; 110 111struct pci_devinst { 112 struct pci_devemu *pi_d; 113 struct vmctx *pi_vmctx; 114 uint8_t pi_bus, pi_slot, pi_func; 115 char pi_name[PI_NAMESZ]; 116 int pi_bar_getsize; 117 int pi_prevcap; 118 int pi_capend; 119 120 struct { 121 int8_t pin; 122 enum lintr_stat state; 123 int ioapic_irq; 124 pthread_mutex_t lock; 125 } pi_lintr; 126 127 struct { 128 int enabled; 129 uint64_t addr; 130 uint64_t msg_data; 131 int maxmsgnum; 132 } pi_msi; 133 134 struct { 135 int enabled; 136 int table_bar; 137 int pba_bar; 138 uint32_t table_offset; 139 int table_count; 140 uint32_t pba_offset; 141 int pba_size; 142 int function_mask; 143 struct msix_table_entry *table; /* allocated at runtime */ 144 } pi_msix; 145 146 void *pi_arg; /* devemu-private data */ 147 148 u_char pi_cfgdata[PCI_REGMAX + 1]; 149 struct pcibar pi_bar[PCI_BARMAX + 1]; 150}; 151 152struct msicap { 153 uint8_t capid; 154 uint8_t nextptr; 155 uint16_t msgctrl; 156 uint32_t addrlo; 157 uint32_t addrhi; 158 uint16_t msgdata; 159} __packed; 160 161struct msixcap { 162 uint8_t capid; 163 uint8_t nextptr; 164 uint16_t msgctrl; 165 uint32_t table_info; /* bar index and offset within it */ 166 uint32_t pba_info; /* bar index and offset within it */ 167} __packed; 168 169struct pciecap { 170 uint8_t capid; 171 uint8_t nextptr; 172 uint16_t pcie_capabilities; 173 174 uint32_t dev_capabilities; /* all devices */ 175 uint16_t dev_control; 176 uint16_t dev_status; 177 178 uint32_t link_capabilities; /* devices with links */ 179 uint16_t link_control; 180 uint16_t link_status; 181 182 uint32_t slot_capabilities; /* ports with slots */ 183 uint16_t slot_control; 184 uint16_t slot_status; 185 186 uint16_t root_control; /* root ports */ 187 uint16_t root_capabilities; 188 uint32_t root_status; 189 190 uint32_t dev_capabilities2; /* all devices */ 191 uint16_t dev_control2; 192 uint16_t dev_status2; 193 194 uint32_t link_capabilities2; /* devices with links */ 195 uint16_t link_control2; 196 uint16_t link_status2; 197 198 uint32_t slot_capabilities2; /* ports with slots */ 199 uint16_t slot_control2; 200 uint16_t slot_status2; 201} __packed; 202 203typedef void (*pci_lintr_cb)(int b, int s, int pin, int ioapic_irq, void *arg); 204 205int init_pci(struct vmctx *ctx); 206void msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 207 int bytes, uint32_t val); 208void msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 209 int bytes, uint32_t val); 210void pci_callback(void); 211int pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, 212 enum pcibar_type type, uint64_t size); 213int pci_emul_alloc_pbar(struct pci_devinst *pdi, int idx, 214 uint64_t hostbase, enum pcibar_type type, uint64_t size); 215int pci_emul_add_msicap(struct pci_devinst *pi, int msgnum); 216int pci_emul_add_pciecap(struct pci_devinst *pi, int pcie_device_type); 217void pci_generate_msi(struct pci_devinst *pi, int msgnum); 218void pci_generate_msix(struct pci_devinst *pi, int msgnum); 219void pci_lintr_assert(struct pci_devinst *pi); 220void pci_lintr_deassert(struct pci_devinst *pi); 221int pci_lintr_request(struct pci_devinst *pi); 222int pci_msi_enabled(struct pci_devinst *pi); 223int pci_msix_enabled(struct pci_devinst *pi); 224int pci_msix_table_bar(struct pci_devinst *pi); 225int pci_msix_pba_bar(struct pci_devinst *pi); 226int pci_msi_msgnum(struct pci_devinst *pi); 227int pci_parse_slot(char *opt); 228void pci_populate_msicap(struct msicap *cap, int msgs, int nextptr); 229int pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum); 230int pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size, 231 uint64_t value); 232uint64_t pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size); 233int pci_count_lintr(int bus); 234void pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg); 235void pci_write_dsdt(void); 236int pci_bus_configured(int bus); 237 238static __inline void 239pci_set_cfgdata8(struct pci_devinst *pi, int offset, uint8_t val) 240{ 241 assert(offset <= PCI_REGMAX); 242 *(uint8_t *)(pi->pi_cfgdata + offset) = val; 243} 244 245static __inline void 246pci_set_cfgdata16(struct pci_devinst *pi, int offset, uint16_t val) 247{ 248 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0); 249 *(uint16_t *)(pi->pi_cfgdata + offset) = val; 250} 251 252static __inline void 253pci_set_cfgdata32(struct pci_devinst *pi, int offset, uint32_t val) 254{ 255 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0); 256 *(uint32_t *)(pi->pi_cfgdata + offset) = val; 257} 258 259static __inline uint8_t 260pci_get_cfgdata8(struct pci_devinst *pi, int offset) 261{ 262 assert(offset <= PCI_REGMAX); 263 return (*(uint8_t *)(pi->pi_cfgdata + offset)); 264} 265 266static __inline uint16_t 267pci_get_cfgdata16(struct pci_devinst *pi, int offset) 268{ 269 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0); 270 return (*(uint16_t *)(pi->pi_cfgdata + offset)); 271} 272 273static __inline uint32_t 274pci_get_cfgdata32(struct pci_devinst *pi, int offset) 275{ 276 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0); 277 return (*(uint32_t *)(pi->pi_cfgdata + offset)); 278} 279 280#endif /* _PCI_EMUL_H_ */ 281