pci_emul.h revision 261265
1/*- 2 * Copyright (c) 2011 NetApp, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: stable/10/usr.sbin/bhyve/pci_emul.h 261265 2014-01-29 13:35:12Z jhb $ 27 */ 28 29#ifndef _PCI_EMUL_H_ 30#define _PCI_EMUL_H_ 31 32#include <sys/types.h> 33#include <sys/queue.h> 34#include <sys/kernel.h> 35 36#include <dev/pci/pcireg.h> 37 38#include <assert.h> 39 40#define PCI_BARMAX PCIR_MAX_BAR_0 /* BAR registers in a Type 0 header */ 41#define PCIY_RESERVED 0x00 42 43struct vmctx; 44struct pci_devinst; 45struct memory_region; 46 47struct pci_devemu { 48 char *pe_emu; /* Name of device emulation */ 49 50 /* instance creation */ 51 int (*pe_init)(struct vmctx *, struct pci_devinst *, 52 char *opts); 53 54 /* ACPI DSDT enumeration */ 55 void (*pe_write_dsdt)(struct pci_devinst *); 56 57 /* config space read/write callbacks */ 58 int (*pe_cfgwrite)(struct vmctx *ctx, int vcpu, 59 struct pci_devinst *pi, int offset, 60 int bytes, uint32_t val); 61 int (*pe_cfgread)(struct vmctx *ctx, int vcpu, 62 struct pci_devinst *pi, int offset, 63 int bytes, uint32_t *retval); 64 65 /* BAR read/write callbacks */ 66 void (*pe_barwrite)(struct vmctx *ctx, int vcpu, 67 struct pci_devinst *pi, int baridx, 68 uint64_t offset, int size, uint64_t value); 69 uint64_t (*pe_barread)(struct vmctx *ctx, int vcpu, 70 struct pci_devinst *pi, int baridx, 71 uint64_t offset, int size); 72}; 73#define PCI_EMUL_SET(x) DATA_SET(pci_devemu_set, x); 74 75enum pcibar_type { 76 PCIBAR_NONE, 77 PCIBAR_IO, 78 PCIBAR_MEM32, 79 PCIBAR_MEM64, 80 PCIBAR_MEMHI64 81}; 82 83struct pcibar { 84 enum pcibar_type type; /* io or memory */ 85 uint64_t size; 86 uint64_t addr; 87}; 88 89#define PI_NAMESZ 40 90 91struct msix_table_entry { 92 uint64_t addr; 93 uint32_t msg_data; 94 uint32_t vector_control; 95} __packed; 96 97/* 98 * In case the structure is modified to hold extra information, use a define 99 * for the size that should be emulated. 100 */ 101#define MSIX_TABLE_ENTRY_SIZE 16 102#define MAX_MSIX_TABLE_ENTRIES 2048 103#define PBA_TABLE_ENTRY_SIZE 8 104 105struct pci_devinst { 106 struct pci_devemu *pi_d; 107 struct vmctx *pi_vmctx; 108 uint8_t pi_bus, pi_slot, pi_func; 109 int8_t pi_lintr_pin; 110 int8_t pi_lintr_state; 111 char pi_name[PI_NAMESZ]; 112 int pi_bar_getsize; 113 114 struct { 115 int enabled; 116 int cpu; 117 int vector; 118 int msgnum; 119 } pi_msi; 120 121 struct { 122 int enabled; 123 int table_bar; 124 int pba_bar; 125 size_t table_offset; 126 int table_count; 127 size_t pba_offset; 128 size_t pba_size; 129 int function_mask; 130 struct msix_table_entry *table; /* allocated at runtime */ 131 } pi_msix; 132 133 void *pi_arg; /* devemu-private data */ 134 135 u_char pi_cfgdata[PCI_REGMAX + 1]; 136 struct pcibar pi_bar[PCI_BARMAX + 1]; 137}; 138 139struct msicap { 140 uint8_t capid; 141 uint8_t nextptr; 142 uint16_t msgctrl; 143 uint32_t addrlo; 144 uint32_t addrhi; 145 uint16_t msgdata; 146} __packed; 147 148struct msixcap { 149 uint8_t capid; 150 uint8_t nextptr; 151 uint16_t msgctrl; 152 uint32_t table_info; /* bar index and offset within it */ 153 uint32_t pba_info; /* bar index and offset within it */ 154} __packed; 155 156struct pciecap { 157 uint8_t capid; 158 uint8_t nextptr; 159 uint16_t pcie_capabilities; 160 161 uint32_t dev_capabilities; /* all devices */ 162 uint16_t dev_control; 163 uint16_t dev_status; 164 165 uint32_t link_capabilities; /* devices with links */ 166 uint16_t link_control; 167 uint16_t link_status; 168 169 uint32_t slot_capabilities; /* ports with slots */ 170 uint16_t slot_control; 171 uint16_t slot_status; 172 173 uint16_t root_control; /* root ports */ 174 uint16_t root_capabilities; 175 uint32_t root_status; 176 177 uint32_t dev_capabilities2; /* all devices */ 178 uint16_t dev_control2; 179 uint16_t dev_status2; 180 181 uint32_t link_capabilities2; /* devices with links */ 182 uint16_t link_control2; 183 uint16_t link_status2; 184 185 uint32_t slot_capabilities2; /* ports with slots */ 186 uint16_t slot_control2; 187 uint16_t slot_status2; 188} __packed; 189 190int init_pci(struct vmctx *ctx); 191void msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 192 int bytes, uint32_t val); 193void msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 194 int bytes, uint32_t val); 195void pci_callback(void); 196int pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, 197 enum pcibar_type type, uint64_t size); 198int pci_emul_alloc_pbar(struct pci_devinst *pdi, int idx, 199 uint64_t hostbase, enum pcibar_type type, uint64_t size); 200int pci_emul_add_msicap(struct pci_devinst *pi, int msgnum); 201int pci_emul_add_pciecap(struct pci_devinst *pi, int pcie_device_type); 202int pci_is_legacy(struct pci_devinst *pi); 203void pci_generate_msi(struct pci_devinst *pi, int msgnum); 204void pci_generate_msix(struct pci_devinst *pi, int msgnum); 205void pci_lintr_assert(struct pci_devinst *pi); 206void pci_lintr_deassert(struct pci_devinst *pi); 207int pci_lintr_request(struct pci_devinst *pi, int ivec); 208int pci_msi_enabled(struct pci_devinst *pi); 209int pci_msix_enabled(struct pci_devinst *pi); 210int pci_msix_table_bar(struct pci_devinst *pi); 211int pci_msix_pba_bar(struct pci_devinst *pi); 212int pci_msi_msgnum(struct pci_devinst *pi); 213int pci_parse_slot(char *opt, int legacy); 214void pci_populate_msicap(struct msicap *cap, int msgs, int nextptr); 215int pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum); 216int pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size, 217 uint64_t value); 218uint64_t pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size); 219void pci_write_dsdt(void); 220 221static __inline void 222pci_set_cfgdata8(struct pci_devinst *pi, int offset, uint8_t val) 223{ 224 assert(offset <= PCI_REGMAX); 225 *(uint8_t *)(pi->pi_cfgdata + offset) = val; 226} 227 228static __inline void 229pci_set_cfgdata16(struct pci_devinst *pi, int offset, uint16_t val) 230{ 231 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0); 232 *(uint16_t *)(pi->pi_cfgdata + offset) = val; 233} 234 235static __inline void 236pci_set_cfgdata32(struct pci_devinst *pi, int offset, uint32_t val) 237{ 238 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0); 239 *(uint32_t *)(pi->pi_cfgdata + offset) = val; 240} 241 242static __inline uint8_t 243pci_get_cfgdata8(struct pci_devinst *pi, int offset) 244{ 245 assert(offset <= PCI_REGMAX); 246 return (*(uint8_t *)(pi->pi_cfgdata + offset)); 247} 248 249static __inline uint16_t 250pci_get_cfgdata16(struct pci_devinst *pi, int offset) 251{ 252 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0); 253 return (*(uint16_t *)(pi->pi_cfgdata + offset)); 254} 255 256static __inline uint32_t 257pci_get_cfgdata32(struct pci_devinst *pi, int offset) 258{ 259 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0); 260 return (*(uint32_t *)(pi->pi_cfgdata + offset)); 261} 262 263#endif /* _PCI_EMUL_H_ */ 264