pci_emul.h revision 257396
1/*- 2 * Copyright (c) 2011 NetApp, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: stable/10/usr.sbin/bhyve/pci_emul.h 257396 2013-10-30 20:42:09Z neel $ 27 */ 28 29#ifndef _PCI_EMUL_H_ 30#define _PCI_EMUL_H_ 31 32#include <sys/types.h> 33#include <sys/queue.h> 34#include <sys/kernel.h> 35 36#include <dev/pci/pcireg.h> 37 38#include <assert.h> 39 40#define PCI_BARMAX PCIR_MAX_BAR_0 /* BAR registers in a Type 0 header */ 41#define PCIY_RESERVED 0x00 42 43struct vmctx; 44struct pci_devinst; 45struct memory_region; 46 47struct pci_devemu { 48 char *pe_emu; /* Name of device emulation */ 49 50 /* instance creation */ 51 int (*pe_init)(struct vmctx *, struct pci_devinst *, 52 char *opts); 53 54 /* config space read/write callbacks */ 55 int (*pe_cfgwrite)(struct vmctx *ctx, int vcpu, 56 struct pci_devinst *pi, int offset, 57 int bytes, uint32_t val); 58 int (*pe_cfgread)(struct vmctx *ctx, int vcpu, 59 struct pci_devinst *pi, int offset, 60 int bytes, uint32_t *retval); 61 62 /* BAR read/write callbacks */ 63 void (*pe_barwrite)(struct vmctx *ctx, int vcpu, 64 struct pci_devinst *pi, int baridx, 65 uint64_t offset, int size, uint64_t value); 66 uint64_t (*pe_barread)(struct vmctx *ctx, int vcpu, 67 struct pci_devinst *pi, int baridx, 68 uint64_t offset, int size); 69}; 70#define PCI_EMUL_SET(x) DATA_SET(pci_devemu_set, x); 71 72enum pcibar_type { 73 PCIBAR_NONE, 74 PCIBAR_IO, 75 PCIBAR_MEM32, 76 PCIBAR_MEM64, 77 PCIBAR_MEMHI64 78}; 79 80struct pcibar { 81 enum pcibar_type type; /* io or memory */ 82 uint64_t size; 83 uint64_t addr; 84}; 85 86#define PI_NAMESZ 40 87 88struct msix_table_entry { 89 uint64_t addr; 90 uint32_t msg_data; 91 uint32_t vector_control; 92} __packed; 93 94/* 95 * In case the structure is modified to hold extra information, use a define 96 * for the size that should be emulated. 97 */ 98#define MSIX_TABLE_ENTRY_SIZE 16 99#define MAX_MSIX_TABLE_ENTRIES 2048 100#define PBA_TABLE_ENTRY_SIZE 8 101 102struct pci_devinst { 103 struct pci_devemu *pi_d; 104 struct vmctx *pi_vmctx; 105 uint8_t pi_bus, pi_slot, pi_func; 106 int8_t pi_lintr_pin; 107 char pi_name[PI_NAMESZ]; 108 int pi_bar_getsize; 109 110 struct { 111 int enabled; 112 int cpu; 113 int vector; 114 int msgnum; 115 } pi_msi; 116 117 struct { 118 int enabled; 119 int table_bar; 120 int pba_bar; 121 size_t table_offset; 122 int table_count; 123 size_t pba_offset; 124 size_t pba_size; 125 int function_mask; 126 struct msix_table_entry *table; /* allocated at runtime */ 127 } pi_msix; 128 129 void *pi_arg; /* devemu-private data */ 130 131 u_char pi_cfgdata[PCI_REGMAX + 1]; 132 struct pcibar pi_bar[PCI_BARMAX + 1]; 133}; 134 135struct msicap { 136 uint8_t capid; 137 uint8_t nextptr; 138 uint16_t msgctrl; 139 uint32_t addrlo; 140 uint32_t addrhi; 141 uint16_t msgdata; 142} __packed; 143 144struct msixcap { 145 uint8_t capid; 146 uint8_t nextptr; 147 uint16_t msgctrl; 148 uint32_t table_info; /* bar index and offset within it */ 149 uint32_t pba_info; /* bar index and offset within it */ 150} __packed; 151 152struct pciecap { 153 uint8_t capid; 154 uint8_t nextptr; 155 uint16_t pcie_capabilities; 156 157 uint32_t dev_capabilities; /* all devices */ 158 uint16_t dev_control; 159 uint16_t dev_status; 160 161 uint32_t link_capabilities; /* devices with links */ 162 uint16_t link_control; 163 uint16_t link_status; 164 165 uint32_t slot_capabilities; /* ports with slots */ 166 uint16_t slot_control; 167 uint16_t slot_status; 168 169 uint16_t root_control; /* root ports */ 170 uint16_t root_capabilities; 171 uint32_t root_status; 172 173 uint32_t dev_capabilities2; /* all devices */ 174 uint16_t dev_control2; 175 uint16_t dev_status2; 176 177 uint32_t link_capabilities2; /* devices with links */ 178 uint16_t link_control2; 179 uint16_t link_status2; 180 181 uint32_t slot_capabilities2; /* ports with slots */ 182 uint16_t slot_control2; 183 uint16_t slot_status2; 184} __packed; 185 186int init_pci(struct vmctx *ctx); 187void msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 188 int bytes, uint32_t val); 189void msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 190 int bytes, uint32_t val); 191void pci_callback(void); 192int pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, 193 enum pcibar_type type, uint64_t size); 194int pci_emul_alloc_pbar(struct pci_devinst *pdi, int idx, 195 uint64_t hostbase, enum pcibar_type type, uint64_t size); 196int pci_emul_add_msicap(struct pci_devinst *pi, int msgnum); 197int pci_emul_add_pciecap(struct pci_devinst *pi, int pcie_device_type); 198int pci_is_legacy(struct pci_devinst *pi); 199void pci_generate_msi(struct pci_devinst *pi, int msgnum); 200void pci_generate_msix(struct pci_devinst *pi, int msgnum); 201void pci_lintr_assert(struct pci_devinst *pi); 202void pci_lintr_deassert(struct pci_devinst *pi); 203int pci_lintr_request(struct pci_devinst *pi, int ivec); 204int pci_msi_enabled(struct pci_devinst *pi); 205int pci_msix_enabled(struct pci_devinst *pi); 206int pci_msix_table_bar(struct pci_devinst *pi); 207int pci_msix_pba_bar(struct pci_devinst *pi); 208int pci_msi_msgnum(struct pci_devinst *pi); 209int pci_parse_slot(char *opt, int legacy); 210void pci_populate_msicap(struct msicap *cap, int msgs, int nextptr); 211int pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum); 212int pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size, 213 uint64_t value); 214uint64_t pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size); 215 216static __inline void 217pci_set_cfgdata8(struct pci_devinst *pi, int offset, uint8_t val) 218{ 219 assert(offset <= PCI_REGMAX); 220 *(uint8_t *)(pi->pi_cfgdata + offset) = val; 221} 222 223static __inline void 224pci_set_cfgdata16(struct pci_devinst *pi, int offset, uint16_t val) 225{ 226 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0); 227 *(uint16_t *)(pi->pi_cfgdata + offset) = val; 228} 229 230static __inline void 231pci_set_cfgdata32(struct pci_devinst *pi, int offset, uint32_t val) 232{ 233 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0); 234 *(uint32_t *)(pi->pi_cfgdata + offset) = val; 235} 236 237static __inline uint8_t 238pci_get_cfgdata8(struct pci_devinst *pi, int offset) 239{ 240 assert(offset <= PCI_REGMAX); 241 return (*(uint8_t *)(pi->pi_cfgdata + offset)); 242} 243 244static __inline uint16_t 245pci_get_cfgdata16(struct pci_devinst *pi, int offset) 246{ 247 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0); 248 return (*(uint16_t *)(pi->pi_cfgdata + offset)); 249} 250 251static __inline uint32_t 252pci_get_cfgdata32(struct pci_devinst *pi, int offset) 253{ 254 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0); 255 return (*(uint32_t *)(pi->pi_cfgdata + offset)); 256} 257 258#endif /* _PCI_EMUL_H_ */ 259