pci_emul.c revision 293290
1/*- 2 * Copyright (c) 2011 NetApp, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: stable/10/usr.sbin/bhyve/pci_emul.c 293290 2016-01-07 00:40:51Z bdrewery $ 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: stable/10/usr.sbin/bhyve/pci_emul.c 293290 2016-01-07 00:40:51Z bdrewery $"); 31 32#include <sys/param.h> 33#include <sys/linker_set.h> 34#include <sys/errno.h> 35 36#include <ctype.h> 37#include <pthread.h> 38#include <stdio.h> 39#include <stdlib.h> 40#include <string.h> 41#include <strings.h> 42#include <assert.h> 43#include <stdbool.h> 44 45#include <machine/vmm.h> 46#include <vmmapi.h> 47 48#include "acpi.h" 49#include "bhyverun.h" 50#include "inout.h" 51#include "ioapic.h" 52#include "mem.h" 53#include "pci_emul.h" 54#include "pci_irq.h" 55#include "pci_lpc.h" 56 57#define CONF1_ADDR_PORT 0x0cf8 58#define CONF1_DATA_PORT 0x0cfc 59 60#define CONF1_ENABLE 0x80000000ul 61 62#define MAXBUSES (PCI_BUSMAX + 1) 63#define MAXSLOTS (PCI_SLOTMAX + 1) 64#define MAXFUNCS (PCI_FUNCMAX + 1) 65 66struct funcinfo { 67 char *fi_name; 68 char *fi_param; 69 struct pci_devinst *fi_devi; 70}; 71 72struct intxinfo { 73 int ii_count; 74 int ii_pirq_pin; 75 int ii_ioapic_irq; 76}; 77 78struct slotinfo { 79 struct intxinfo si_intpins[4]; 80 struct funcinfo si_funcs[MAXFUNCS]; 81}; 82 83struct businfo { 84 uint16_t iobase, iolimit; /* I/O window */ 85 uint32_t membase32, memlimit32; /* mmio window below 4GB */ 86 uint64_t membase64, memlimit64; /* mmio window above 4GB */ 87 struct slotinfo slotinfo[MAXSLOTS]; 88}; 89 90static struct businfo *pci_businfo[MAXBUSES]; 91 92SET_DECLARE(pci_devemu_set, struct pci_devemu); 93 94static uint64_t pci_emul_iobase; 95static uint64_t pci_emul_membase32; 96static uint64_t pci_emul_membase64; 97 98#define PCI_EMUL_IOBASE 0x2000 99#define PCI_EMUL_IOLIMIT 0x10000 100 101#define PCI_EMUL_ECFG_BASE 0xE0000000 /* 3.5GB */ 102#define PCI_EMUL_ECFG_SIZE (MAXBUSES * 1024 * 1024) /* 1MB per bus */ 103SYSRES_MEM(PCI_EMUL_ECFG_BASE, PCI_EMUL_ECFG_SIZE); 104 105#define PCI_EMUL_MEMLIMIT32 PCI_EMUL_ECFG_BASE 106 107#define PCI_EMUL_MEMBASE64 0xD000000000UL 108#define PCI_EMUL_MEMLIMIT64 0xFD00000000UL 109 110static struct pci_devemu *pci_emul_finddev(char *name); 111static void pci_lintr_route(struct pci_devinst *pi); 112static void pci_lintr_update(struct pci_devinst *pi); 113static void pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot, 114 int func, int coff, int bytes, uint32_t *val); 115 116static __inline void 117CFGWRITE(struct pci_devinst *pi, int coff, uint32_t val, int bytes) 118{ 119 120 if (bytes == 1) 121 pci_set_cfgdata8(pi, coff, val); 122 else if (bytes == 2) 123 pci_set_cfgdata16(pi, coff, val); 124 else 125 pci_set_cfgdata32(pi, coff, val); 126} 127 128static __inline uint32_t 129CFGREAD(struct pci_devinst *pi, int coff, int bytes) 130{ 131 132 if (bytes == 1) 133 return (pci_get_cfgdata8(pi, coff)); 134 else if (bytes == 2) 135 return (pci_get_cfgdata16(pi, coff)); 136 else 137 return (pci_get_cfgdata32(pi, coff)); 138} 139 140/* 141 * I/O access 142 */ 143 144/* 145 * Slot options are in the form: 146 * 147 * <bus>:<slot>:<func>,<emul>[,<config>] 148 * <slot>[:<func>],<emul>[,<config>] 149 * 150 * slot is 0..31 151 * func is 0..7 152 * emul is a string describing the type of PCI device e.g. virtio-net 153 * config is an optional string, depending on the device, that can be 154 * used for configuration. 155 * Examples are: 156 * 1,virtio-net,tap0 157 * 3:0,dummy 158 */ 159static void 160pci_parse_slot_usage(char *aopt) 161{ 162 163 fprintf(stderr, "Invalid PCI slot info field \"%s\"\n", aopt); 164} 165 166int 167pci_parse_slot(char *opt) 168{ 169 struct businfo *bi; 170 struct slotinfo *si; 171 char *emul, *config, *str, *cp; 172 int error, bnum, snum, fnum; 173 174 error = -1; 175 str = strdup(opt); 176 177 emul = config = NULL; 178 if ((cp = strchr(str, ',')) != NULL) { 179 *cp = '\0'; 180 emul = cp + 1; 181 if ((cp = strchr(emul, ',')) != NULL) { 182 *cp = '\0'; 183 config = cp + 1; 184 } 185 } else { 186 pci_parse_slot_usage(opt); 187 goto done; 188 } 189 190 /* <bus>:<slot>:<func> */ 191 if (sscanf(str, "%d:%d:%d", &bnum, &snum, &fnum) != 3) { 192 bnum = 0; 193 /* <slot>:<func> */ 194 if (sscanf(str, "%d:%d", &snum, &fnum) != 2) { 195 fnum = 0; 196 /* <slot> */ 197 if (sscanf(str, "%d", &snum) != 1) { 198 snum = -1; 199 } 200 } 201 } 202 203 if (bnum < 0 || bnum >= MAXBUSES || snum < 0 || snum >= MAXSLOTS || 204 fnum < 0 || fnum >= MAXFUNCS) { 205 pci_parse_slot_usage(opt); 206 goto done; 207 } 208 209 if (pci_businfo[bnum] == NULL) 210 pci_businfo[bnum] = calloc(1, sizeof(struct businfo)); 211 212 bi = pci_businfo[bnum]; 213 si = &bi->slotinfo[snum]; 214 215 if (si->si_funcs[fnum].fi_name != NULL) { 216 fprintf(stderr, "pci slot %d:%d already occupied!\n", 217 snum, fnum); 218 goto done; 219 } 220 221 if (pci_emul_finddev(emul) == NULL) { 222 fprintf(stderr, "pci slot %d:%d: unknown device \"%s\"\n", 223 snum, fnum, emul); 224 goto done; 225 } 226 227 error = 0; 228 si->si_funcs[fnum].fi_name = emul; 229 si->si_funcs[fnum].fi_param = config; 230 231done: 232 if (error) 233 free(str); 234 235 return (error); 236} 237 238static int 239pci_valid_pba_offset(struct pci_devinst *pi, uint64_t offset) 240{ 241 242 if (offset < pi->pi_msix.pba_offset) 243 return (0); 244 245 if (offset >= pi->pi_msix.pba_offset + pi->pi_msix.pba_size) { 246 return (0); 247 } 248 249 return (1); 250} 251 252int 253pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size, 254 uint64_t value) 255{ 256 int msix_entry_offset; 257 int tab_index; 258 char *dest; 259 260 /* support only 4 or 8 byte writes */ 261 if (size != 4 && size != 8) 262 return (-1); 263 264 /* 265 * Return if table index is beyond what device supports 266 */ 267 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 268 if (tab_index >= pi->pi_msix.table_count) 269 return (-1); 270 271 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 272 273 /* support only aligned writes */ 274 if ((msix_entry_offset % size) != 0) 275 return (-1); 276 277 dest = (char *)(pi->pi_msix.table + tab_index); 278 dest += msix_entry_offset; 279 280 if (size == 4) 281 *((uint32_t *)dest) = value; 282 else 283 *((uint64_t *)dest) = value; 284 285 return (0); 286} 287 288uint64_t 289pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size) 290{ 291 char *dest; 292 int msix_entry_offset; 293 int tab_index; 294 uint64_t retval = ~0; 295 296 /* 297 * The PCI standard only allows 4 and 8 byte accesses to the MSI-X 298 * table but we also allow 1 byte access to accommodate reads from 299 * ddb. 300 */ 301 if (size != 1 && size != 4 && size != 8) 302 return (retval); 303 304 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 305 306 /* support only aligned reads */ 307 if ((msix_entry_offset % size) != 0) { 308 return (retval); 309 } 310 311 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 312 313 if (tab_index < pi->pi_msix.table_count) { 314 /* valid MSI-X Table access */ 315 dest = (char *)(pi->pi_msix.table + tab_index); 316 dest += msix_entry_offset; 317 318 if (size == 1) 319 retval = *((uint8_t *)dest); 320 else if (size == 4) 321 retval = *((uint32_t *)dest); 322 else 323 retval = *((uint64_t *)dest); 324 } else if (pci_valid_pba_offset(pi, offset)) { 325 /* return 0 for PBA access */ 326 retval = 0; 327 } 328 329 return (retval); 330} 331 332int 333pci_msix_table_bar(struct pci_devinst *pi) 334{ 335 336 if (pi->pi_msix.table != NULL) 337 return (pi->pi_msix.table_bar); 338 else 339 return (-1); 340} 341 342int 343pci_msix_pba_bar(struct pci_devinst *pi) 344{ 345 346 if (pi->pi_msix.table != NULL) 347 return (pi->pi_msix.pba_bar); 348 else 349 return (-1); 350} 351 352static int 353pci_emul_io_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 354 uint32_t *eax, void *arg) 355{ 356 struct pci_devinst *pdi = arg; 357 struct pci_devemu *pe = pdi->pi_d; 358 uint64_t offset; 359 int i; 360 361 for (i = 0; i <= PCI_BARMAX; i++) { 362 if (pdi->pi_bar[i].type == PCIBAR_IO && 363 port >= pdi->pi_bar[i].addr && 364 port + bytes <= pdi->pi_bar[i].addr + pdi->pi_bar[i].size) { 365 offset = port - pdi->pi_bar[i].addr; 366 if (in) 367 *eax = (*pe->pe_barread)(ctx, vcpu, pdi, i, 368 offset, bytes); 369 else 370 (*pe->pe_barwrite)(ctx, vcpu, pdi, i, offset, 371 bytes, *eax); 372 return (0); 373 } 374 } 375 return (-1); 376} 377 378static int 379pci_emul_mem_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr, 380 int size, uint64_t *val, void *arg1, long arg2) 381{ 382 struct pci_devinst *pdi = arg1; 383 struct pci_devemu *pe = pdi->pi_d; 384 uint64_t offset; 385 int bidx = (int) arg2; 386 387 assert(bidx <= PCI_BARMAX); 388 assert(pdi->pi_bar[bidx].type == PCIBAR_MEM32 || 389 pdi->pi_bar[bidx].type == PCIBAR_MEM64); 390 assert(addr >= pdi->pi_bar[bidx].addr && 391 addr + size <= pdi->pi_bar[bidx].addr + pdi->pi_bar[bidx].size); 392 393 offset = addr - pdi->pi_bar[bidx].addr; 394 395 if (dir == MEM_F_WRITE) { 396 if (size == 8) { 397 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset, 398 4, *val & 0xffffffff); 399 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset + 4, 400 4, *val >> 32); 401 } else { 402 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset, 403 size, *val); 404 } 405 } else { 406 if (size == 8) { 407 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx, 408 offset, 4); 409 *val |= (*pe->pe_barread)(ctx, vcpu, pdi, bidx, 410 offset + 4, 4) << 32; 411 } else { 412 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx, 413 offset, size); 414 } 415 } 416 417 return (0); 418} 419 420 421static int 422pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size, 423 uint64_t *addr) 424{ 425 uint64_t base; 426 427 assert((size & (size - 1)) == 0); /* must be a power of 2 */ 428 429 base = roundup2(*baseptr, size); 430 431 if (base + size <= limit) { 432 *addr = base; 433 *baseptr = base + size; 434 return (0); 435 } else 436 return (-1); 437} 438 439int 440pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, enum pcibar_type type, 441 uint64_t size) 442{ 443 444 return (pci_emul_alloc_pbar(pdi, idx, 0, type, size)); 445} 446 447/* 448 * Register (or unregister) the MMIO or I/O region associated with the BAR 449 * register 'idx' of an emulated pci device. 450 */ 451static void 452modify_bar_registration(struct pci_devinst *pi, int idx, int registration) 453{ 454 int error; 455 struct inout_port iop; 456 struct mem_range mr; 457 458 switch (pi->pi_bar[idx].type) { 459 case PCIBAR_IO: 460 bzero(&iop, sizeof(struct inout_port)); 461 iop.name = pi->pi_name; 462 iop.port = pi->pi_bar[idx].addr; 463 iop.size = pi->pi_bar[idx].size; 464 if (registration) { 465 iop.flags = IOPORT_F_INOUT; 466 iop.handler = pci_emul_io_handler; 467 iop.arg = pi; 468 error = register_inout(&iop); 469 } else 470 error = unregister_inout(&iop); 471 break; 472 case PCIBAR_MEM32: 473 case PCIBAR_MEM64: 474 bzero(&mr, sizeof(struct mem_range)); 475 mr.name = pi->pi_name; 476 mr.base = pi->pi_bar[idx].addr; 477 mr.size = pi->pi_bar[idx].size; 478 if (registration) { 479 mr.flags = MEM_F_RW; 480 mr.handler = pci_emul_mem_handler; 481 mr.arg1 = pi; 482 mr.arg2 = idx; 483 error = register_mem(&mr); 484 } else 485 error = unregister_mem(&mr); 486 break; 487 default: 488 error = EINVAL; 489 break; 490 } 491 assert(error == 0); 492} 493 494static void 495unregister_bar(struct pci_devinst *pi, int idx) 496{ 497 498 modify_bar_registration(pi, idx, 0); 499} 500 501static void 502register_bar(struct pci_devinst *pi, int idx) 503{ 504 505 modify_bar_registration(pi, idx, 1); 506} 507 508/* Are we decoding i/o port accesses for the emulated pci device? */ 509static int 510porten(struct pci_devinst *pi) 511{ 512 uint16_t cmd; 513 514 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 515 516 return (cmd & PCIM_CMD_PORTEN); 517} 518 519/* Are we decoding memory accesses for the emulated pci device? */ 520static int 521memen(struct pci_devinst *pi) 522{ 523 uint16_t cmd; 524 525 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 526 527 return (cmd & PCIM_CMD_MEMEN); 528} 529 530/* 531 * Update the MMIO or I/O address that is decoded by the BAR register. 532 * 533 * If the pci device has enabled the address space decoding then intercept 534 * the address range decoded by the BAR register. 535 */ 536static void 537update_bar_address(struct pci_devinst *pi, uint64_t addr, int idx, int type) 538{ 539 int decode; 540 541 if (pi->pi_bar[idx].type == PCIBAR_IO) 542 decode = porten(pi); 543 else 544 decode = memen(pi); 545 546 if (decode) 547 unregister_bar(pi, idx); 548 549 switch (type) { 550 case PCIBAR_IO: 551 case PCIBAR_MEM32: 552 pi->pi_bar[idx].addr = addr; 553 break; 554 case PCIBAR_MEM64: 555 pi->pi_bar[idx].addr &= ~0xffffffffUL; 556 pi->pi_bar[idx].addr |= addr; 557 break; 558 case PCIBAR_MEMHI64: 559 pi->pi_bar[idx].addr &= 0xffffffff; 560 pi->pi_bar[idx].addr |= addr; 561 break; 562 default: 563 assert(0); 564 } 565 566 if (decode) 567 register_bar(pi, idx); 568} 569 570int 571pci_emul_alloc_pbar(struct pci_devinst *pdi, int idx, uint64_t hostbase, 572 enum pcibar_type type, uint64_t size) 573{ 574 int error; 575 uint64_t *baseptr, limit, addr, mask, lobits, bar; 576 577 assert(idx >= 0 && idx <= PCI_BARMAX); 578 579 if ((size & (size - 1)) != 0) 580 size = 1UL << flsl(size); /* round up to a power of 2 */ 581 582 /* Enforce minimum BAR sizes required by the PCI standard */ 583 if (type == PCIBAR_IO) { 584 if (size < 4) 585 size = 4; 586 } else { 587 if (size < 16) 588 size = 16; 589 } 590 591 switch (type) { 592 case PCIBAR_NONE: 593 baseptr = NULL; 594 addr = mask = lobits = 0; 595 break; 596 case PCIBAR_IO: 597 baseptr = &pci_emul_iobase; 598 limit = PCI_EMUL_IOLIMIT; 599 mask = PCIM_BAR_IO_BASE; 600 lobits = PCIM_BAR_IO_SPACE; 601 break; 602 case PCIBAR_MEM64: 603 /* 604 * XXX 605 * Some drivers do not work well if the 64-bit BAR is allocated 606 * above 4GB. Allow for this by allocating small requests under 607 * 4GB unless then allocation size is larger than some arbitrary 608 * number (32MB currently). 609 */ 610 if (size > 32 * 1024 * 1024) { 611 /* 612 * XXX special case for device requiring peer-peer DMA 613 */ 614 if (size == 0x100000000UL) 615 baseptr = &hostbase; 616 else 617 baseptr = &pci_emul_membase64; 618 limit = PCI_EMUL_MEMLIMIT64; 619 mask = PCIM_BAR_MEM_BASE; 620 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 | 621 PCIM_BAR_MEM_PREFETCH; 622 break; 623 } else { 624 baseptr = &pci_emul_membase32; 625 limit = PCI_EMUL_MEMLIMIT32; 626 mask = PCIM_BAR_MEM_BASE; 627 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64; 628 } 629 break; 630 case PCIBAR_MEM32: 631 baseptr = &pci_emul_membase32; 632 limit = PCI_EMUL_MEMLIMIT32; 633 mask = PCIM_BAR_MEM_BASE; 634 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32; 635 break; 636 default: 637 printf("pci_emul_alloc_base: invalid bar type %d\n", type); 638 assert(0); 639 } 640 641 if (baseptr != NULL) { 642 error = pci_emul_alloc_resource(baseptr, limit, size, &addr); 643 if (error != 0) 644 return (error); 645 } 646 647 pdi->pi_bar[idx].type = type; 648 pdi->pi_bar[idx].addr = addr; 649 pdi->pi_bar[idx].size = size; 650 651 /* Initialize the BAR register in config space */ 652 bar = (addr & mask) | lobits; 653 pci_set_cfgdata32(pdi, PCIR_BAR(idx), bar); 654 655 if (type == PCIBAR_MEM64) { 656 assert(idx + 1 <= PCI_BARMAX); 657 pdi->pi_bar[idx + 1].type = PCIBAR_MEMHI64; 658 pci_set_cfgdata32(pdi, PCIR_BAR(idx + 1), bar >> 32); 659 } 660 661 register_bar(pdi, idx); 662 663 return (0); 664} 665 666#define CAP_START_OFFSET 0x40 667static int 668pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata, int caplen) 669{ 670 int i, capoff, reallen; 671 uint16_t sts; 672 673 assert(caplen > 0); 674 675 reallen = roundup2(caplen, 4); /* dword aligned */ 676 677 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 678 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) 679 capoff = CAP_START_OFFSET; 680 else 681 capoff = pi->pi_capend + 1; 682 683 /* Check if we have enough space */ 684 if (capoff + reallen > PCI_REGMAX + 1) 685 return (-1); 686 687 /* Set the previous capability pointer */ 688 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) { 689 pci_set_cfgdata8(pi, PCIR_CAP_PTR, capoff); 690 pci_set_cfgdata16(pi, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT); 691 } else 692 pci_set_cfgdata8(pi, pi->pi_prevcap + 1, capoff); 693 694 /* Copy the capability */ 695 for (i = 0; i < caplen; i++) 696 pci_set_cfgdata8(pi, capoff + i, capdata[i]); 697 698 /* Set the next capability pointer */ 699 pci_set_cfgdata8(pi, capoff + 1, 0); 700 701 pi->pi_prevcap = capoff; 702 pi->pi_capend = capoff + reallen - 1; 703 return (0); 704} 705 706static struct pci_devemu * 707pci_emul_finddev(char *name) 708{ 709 struct pci_devemu **pdpp, *pdp; 710 711 SET_FOREACH(pdpp, pci_devemu_set) { 712 pdp = *pdpp; 713 if (!strcmp(pdp->pe_emu, name)) { 714 return (pdp); 715 } 716 } 717 718 return (NULL); 719} 720 721static int 722pci_emul_init(struct vmctx *ctx, struct pci_devemu *pde, int bus, int slot, 723 int func, struct funcinfo *fi) 724{ 725 struct pci_devinst *pdi; 726 int err; 727 728 pdi = calloc(1, sizeof(struct pci_devinst)); 729 730 pdi->pi_vmctx = ctx; 731 pdi->pi_bus = bus; 732 pdi->pi_slot = slot; 733 pdi->pi_func = func; 734 pthread_mutex_init(&pdi->pi_lintr.lock, NULL); 735 pdi->pi_lintr.pin = 0; 736 pdi->pi_lintr.state = IDLE; 737 pdi->pi_lintr.pirq_pin = 0; 738 pdi->pi_lintr.ioapic_irq = 0; 739 pdi->pi_d = pde; 740 snprintf(pdi->pi_name, PI_NAMESZ, "%s-pci-%d", pde->pe_emu, slot); 741 742 /* Disable legacy interrupts */ 743 pci_set_cfgdata8(pdi, PCIR_INTLINE, 255); 744 pci_set_cfgdata8(pdi, PCIR_INTPIN, 0); 745 746 pci_set_cfgdata8(pdi, PCIR_COMMAND, 747 PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 748 749 err = (*pde->pe_init)(ctx, pdi, fi->fi_param); 750 if (err == 0) 751 fi->fi_devi = pdi; 752 else 753 free(pdi); 754 755 return (err); 756} 757 758void 759pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr) 760{ 761 int mmc; 762 763 CTASSERT(sizeof(struct msicap) == 14); 764 765 /* Number of msi messages must be a power of 2 between 1 and 32 */ 766 assert((msgnum & (msgnum - 1)) == 0 && msgnum >= 1 && msgnum <= 32); 767 mmc = ffs(msgnum) - 1; 768 769 bzero(msicap, sizeof(struct msicap)); 770 msicap->capid = PCIY_MSI; 771 msicap->nextptr = nextptr; 772 msicap->msgctrl = PCIM_MSICTRL_64BIT | (mmc << 1); 773} 774 775int 776pci_emul_add_msicap(struct pci_devinst *pi, int msgnum) 777{ 778 struct msicap msicap; 779 780 pci_populate_msicap(&msicap, msgnum, 0); 781 782 return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap))); 783} 784 785static void 786pci_populate_msixcap(struct msixcap *msixcap, int msgnum, int barnum, 787 uint32_t msix_tab_size) 788{ 789 CTASSERT(sizeof(struct msixcap) == 12); 790 791 assert(msix_tab_size % 4096 == 0); 792 793 bzero(msixcap, sizeof(struct msixcap)); 794 msixcap->capid = PCIY_MSIX; 795 796 /* 797 * Message Control Register, all fields set to 798 * zero except for the Table Size. 799 * Note: Table size N is encoded as N-1 800 */ 801 msixcap->msgctrl = msgnum - 1; 802 803 /* 804 * MSI-X BAR setup: 805 * - MSI-X table start at offset 0 806 * - PBA table starts at a 4K aligned offset after the MSI-X table 807 */ 808 msixcap->table_info = barnum & PCIM_MSIX_BIR_MASK; 809 msixcap->pba_info = msix_tab_size | (barnum & PCIM_MSIX_BIR_MASK); 810} 811 812static void 813pci_msix_table_init(struct pci_devinst *pi, int table_entries) 814{ 815 int i, table_size; 816 817 assert(table_entries > 0); 818 assert(table_entries <= MAX_MSIX_TABLE_ENTRIES); 819 820 table_size = table_entries * MSIX_TABLE_ENTRY_SIZE; 821 pi->pi_msix.table = calloc(1, table_size); 822 823 /* set mask bit of vector control register */ 824 for (i = 0; i < table_entries; i++) 825 pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK; 826} 827 828int 829pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum) 830{ 831 uint32_t tab_size; 832 struct msixcap msixcap; 833 834 assert(msgnum >= 1 && msgnum <= MAX_MSIX_TABLE_ENTRIES); 835 assert(barnum >= 0 && barnum <= PCIR_MAX_BAR_0); 836 837 tab_size = msgnum * MSIX_TABLE_ENTRY_SIZE; 838 839 /* Align table size to nearest 4K */ 840 tab_size = roundup2(tab_size, 4096); 841 842 pi->pi_msix.table_bar = barnum; 843 pi->pi_msix.pba_bar = barnum; 844 pi->pi_msix.table_offset = 0; 845 pi->pi_msix.table_count = msgnum; 846 pi->pi_msix.pba_offset = tab_size; 847 pi->pi_msix.pba_size = PBA_SIZE(msgnum); 848 849 pci_msix_table_init(pi, msgnum); 850 851 pci_populate_msixcap(&msixcap, msgnum, barnum, tab_size); 852 853 /* allocate memory for MSI-X Table and PBA */ 854 pci_emul_alloc_bar(pi, barnum, PCIBAR_MEM32, 855 tab_size + pi->pi_msix.pba_size); 856 857 return (pci_emul_add_capability(pi, (u_char *)&msixcap, 858 sizeof(msixcap))); 859} 860 861void 862msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 863 int bytes, uint32_t val) 864{ 865 uint16_t msgctrl, rwmask; 866 int off, table_bar; 867 868 off = offset - capoff; 869 table_bar = pi->pi_msix.table_bar; 870 /* Message Control Register */ 871 if (off == 2 && bytes == 2) { 872 rwmask = PCIM_MSIXCTRL_MSIX_ENABLE | PCIM_MSIXCTRL_FUNCTION_MASK; 873 msgctrl = pci_get_cfgdata16(pi, offset); 874 msgctrl &= ~rwmask; 875 msgctrl |= val & rwmask; 876 val = msgctrl; 877 878 pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE; 879 pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK; 880 pci_lintr_update(pi); 881 } 882 883 CFGWRITE(pi, offset, val, bytes); 884} 885 886void 887msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 888 int bytes, uint32_t val) 889{ 890 uint16_t msgctrl, rwmask, msgdata, mme; 891 uint32_t addrlo; 892 893 /* 894 * If guest is writing to the message control register make sure 895 * we do not overwrite read-only fields. 896 */ 897 if ((offset - capoff) == 2 && bytes == 2) { 898 rwmask = PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE; 899 msgctrl = pci_get_cfgdata16(pi, offset); 900 msgctrl &= ~rwmask; 901 msgctrl |= val & rwmask; 902 val = msgctrl; 903 904 addrlo = pci_get_cfgdata32(pi, capoff + 4); 905 if (msgctrl & PCIM_MSICTRL_64BIT) 906 msgdata = pci_get_cfgdata16(pi, capoff + 12); 907 else 908 msgdata = pci_get_cfgdata16(pi, capoff + 8); 909 910 mme = msgctrl & PCIM_MSICTRL_MME_MASK; 911 pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0; 912 if (pi->pi_msi.enabled) { 913 pi->pi_msi.addr = addrlo; 914 pi->pi_msi.msg_data = msgdata; 915 pi->pi_msi.maxmsgnum = 1 << (mme >> 4); 916 } else { 917 pi->pi_msi.maxmsgnum = 0; 918 } 919 pci_lintr_update(pi); 920 } 921 922 CFGWRITE(pi, offset, val, bytes); 923} 924 925void 926pciecap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 927 int bytes, uint32_t val) 928{ 929 930 /* XXX don't write to the readonly parts */ 931 CFGWRITE(pi, offset, val, bytes); 932} 933 934#define PCIECAP_VERSION 0x2 935int 936pci_emul_add_pciecap(struct pci_devinst *pi, int type) 937{ 938 int err; 939 struct pciecap pciecap; 940 941 CTASSERT(sizeof(struct pciecap) == 60); 942 943 if (type != PCIEM_TYPE_ROOT_PORT) 944 return (-1); 945 946 bzero(&pciecap, sizeof(pciecap)); 947 948 pciecap.capid = PCIY_EXPRESS; 949 pciecap.pcie_capabilities = PCIECAP_VERSION | PCIEM_TYPE_ROOT_PORT; 950 pciecap.link_capabilities = 0x411; /* gen1, x1 */ 951 pciecap.link_status = 0x11; /* gen1, x1 */ 952 953 err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap)); 954 return (err); 955} 956 957/* 958 * This function assumes that 'coff' is in the capabilities region of the 959 * config space. 960 */ 961static void 962pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val) 963{ 964 int capid; 965 uint8_t capoff, nextoff; 966 967 /* Do not allow un-aligned writes */ 968 if ((offset & (bytes - 1)) != 0) 969 return; 970 971 /* Find the capability that we want to update */ 972 capoff = CAP_START_OFFSET; 973 while (1) { 974 nextoff = pci_get_cfgdata8(pi, capoff + 1); 975 if (nextoff == 0) 976 break; 977 if (offset >= capoff && offset < nextoff) 978 break; 979 980 capoff = nextoff; 981 } 982 assert(offset >= capoff); 983 984 /* 985 * Capability ID and Next Capability Pointer are readonly. 986 * However, some o/s's do 4-byte writes that include these. 987 * For this case, trim the write back to 2 bytes and adjust 988 * the data. 989 */ 990 if (offset == capoff || offset == capoff + 1) { 991 if (offset == capoff && bytes == 4) { 992 bytes = 2; 993 offset += 2; 994 val >>= 16; 995 } else 996 return; 997 } 998 999 capid = pci_get_cfgdata8(pi, capoff); 1000 switch (capid) { 1001 case PCIY_MSI: 1002 msicap_cfgwrite(pi, capoff, offset, bytes, val); 1003 break; 1004 case PCIY_MSIX: 1005 msixcap_cfgwrite(pi, capoff, offset, bytes, val); 1006 break; 1007 case PCIY_EXPRESS: 1008 pciecap_cfgwrite(pi, capoff, offset, bytes, val); 1009 break; 1010 default: 1011 break; 1012 } 1013} 1014 1015static int 1016pci_emul_iscap(struct pci_devinst *pi, int offset) 1017{ 1018 uint16_t sts; 1019 1020 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 1021 if ((sts & PCIM_STATUS_CAPPRESENT) != 0) { 1022 if (offset >= CAP_START_OFFSET && offset <= pi->pi_capend) 1023 return (1); 1024 } 1025 return (0); 1026} 1027 1028static int 1029pci_emul_fallback_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr, 1030 int size, uint64_t *val, void *arg1, long arg2) 1031{ 1032 /* 1033 * Ignore writes; return 0xff's for reads. The mem read code 1034 * will take care of truncating to the correct size. 1035 */ 1036 if (dir == MEM_F_READ) { 1037 *val = 0xffffffffffffffff; 1038 } 1039 1040 return (0); 1041} 1042 1043static int 1044pci_emul_ecfg_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr, 1045 int bytes, uint64_t *val, void *arg1, long arg2) 1046{ 1047 int bus, slot, func, coff, in; 1048 1049 coff = addr & 0xfff; 1050 func = (addr >> 12) & 0x7; 1051 slot = (addr >> 15) & 0x1f; 1052 bus = (addr >> 20) & 0xff; 1053 in = (dir == MEM_F_READ); 1054 if (in) 1055 *val = ~0UL; 1056 pci_cfgrw(ctx, vcpu, in, bus, slot, func, coff, bytes, (uint32_t *)val); 1057 return (0); 1058} 1059 1060uint64_t 1061pci_ecfg_base(void) 1062{ 1063 1064 return (PCI_EMUL_ECFG_BASE); 1065} 1066 1067#define BUSIO_ROUNDUP 32 1068#define BUSMEM_ROUNDUP (1024 * 1024) 1069 1070int 1071init_pci(struct vmctx *ctx) 1072{ 1073 struct mem_range mr; 1074 struct pci_devemu *pde; 1075 struct businfo *bi; 1076 struct slotinfo *si; 1077 struct funcinfo *fi; 1078 size_t lowmem; 1079 int bus, slot, func; 1080 int error; 1081 1082 pci_emul_iobase = PCI_EMUL_IOBASE; 1083 pci_emul_membase32 = vm_get_lowmem_limit(ctx); 1084 pci_emul_membase64 = PCI_EMUL_MEMBASE64; 1085 1086 for (bus = 0; bus < MAXBUSES; bus++) { 1087 if ((bi = pci_businfo[bus]) == NULL) 1088 continue; 1089 /* 1090 * Keep track of the i/o and memory resources allocated to 1091 * this bus. 1092 */ 1093 bi->iobase = pci_emul_iobase; 1094 bi->membase32 = pci_emul_membase32; 1095 bi->membase64 = pci_emul_membase64; 1096 1097 for (slot = 0; slot < MAXSLOTS; slot++) { 1098 si = &bi->slotinfo[slot]; 1099 for (func = 0; func < MAXFUNCS; func++) { 1100 fi = &si->si_funcs[func]; 1101 if (fi->fi_name == NULL) 1102 continue; 1103 pde = pci_emul_finddev(fi->fi_name); 1104 assert(pde != NULL); 1105 error = pci_emul_init(ctx, pde, bus, slot, 1106 func, fi); 1107 if (error) 1108 return (error); 1109 } 1110 } 1111 1112 /* 1113 * Add some slop to the I/O and memory resources decoded by 1114 * this bus to give a guest some flexibility if it wants to 1115 * reprogram the BARs. 1116 */ 1117 pci_emul_iobase += BUSIO_ROUNDUP; 1118 pci_emul_iobase = roundup2(pci_emul_iobase, BUSIO_ROUNDUP); 1119 bi->iolimit = pci_emul_iobase; 1120 1121 pci_emul_membase32 += BUSMEM_ROUNDUP; 1122 pci_emul_membase32 = roundup2(pci_emul_membase32, 1123 BUSMEM_ROUNDUP); 1124 bi->memlimit32 = pci_emul_membase32; 1125 1126 pci_emul_membase64 += BUSMEM_ROUNDUP; 1127 pci_emul_membase64 = roundup2(pci_emul_membase64, 1128 BUSMEM_ROUNDUP); 1129 bi->memlimit64 = pci_emul_membase64; 1130 } 1131 1132 /* 1133 * PCI backends are initialized before routing INTx interrupts 1134 * so that LPC devices are able to reserve ISA IRQs before 1135 * routing PIRQ pins. 1136 */ 1137 for (bus = 0; bus < MAXBUSES; bus++) { 1138 if ((bi = pci_businfo[bus]) == NULL) 1139 continue; 1140 1141 for (slot = 0; slot < MAXSLOTS; slot++) { 1142 si = &bi->slotinfo[slot]; 1143 for (func = 0; func < MAXFUNCS; func++) { 1144 fi = &si->si_funcs[func]; 1145 if (fi->fi_devi == NULL) 1146 continue; 1147 pci_lintr_route(fi->fi_devi); 1148 } 1149 } 1150 } 1151 lpc_pirq_routed(); 1152 1153 /* 1154 * The guest physical memory map looks like the following: 1155 * [0, lowmem) guest system memory 1156 * [lowmem, lowmem_limit) memory hole (may be absent) 1157 * [lowmem_limit, 0xE0000000) PCI hole (32-bit BAR allocation) 1158 * [0xE0000000, 0xF0000000) PCI extended config window 1159 * [0xF0000000, 4GB) LAPIC, IOAPIC, HPET, firmware 1160 * [4GB, 4GB + highmem) 1161 */ 1162 1163 /* 1164 * Accesses to memory addresses that are not allocated to system 1165 * memory or PCI devices return 0xff's. 1166 */ 1167 lowmem = vm_get_lowmem_size(ctx); 1168 bzero(&mr, sizeof(struct mem_range)); 1169 mr.name = "PCI hole"; 1170 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE; 1171 mr.base = lowmem; 1172 mr.size = (4ULL * 1024 * 1024 * 1024) - lowmem; 1173 mr.handler = pci_emul_fallback_handler; 1174 error = register_mem_fallback(&mr); 1175 assert(error == 0); 1176 1177 /* PCI extended config space */ 1178 bzero(&mr, sizeof(struct mem_range)); 1179 mr.name = "PCI ECFG"; 1180 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE; 1181 mr.base = PCI_EMUL_ECFG_BASE; 1182 mr.size = PCI_EMUL_ECFG_SIZE; 1183 mr.handler = pci_emul_ecfg_handler; 1184 error = register_mem(&mr); 1185 assert(error == 0); 1186 1187 return (0); 1188} 1189 1190static void 1191pci_apic_prt_entry(int bus, int slot, int pin, int pirq_pin, int ioapic_irq, 1192 void *arg) 1193{ 1194 1195 dsdt_line(" Package ()"); 1196 dsdt_line(" {"); 1197 dsdt_line(" 0x%X,", slot << 16 | 0xffff); 1198 dsdt_line(" 0x%02X,", pin - 1); 1199 dsdt_line(" Zero,"); 1200 dsdt_line(" 0x%X", ioapic_irq); 1201 dsdt_line(" },"); 1202} 1203 1204static void 1205pci_pirq_prt_entry(int bus, int slot, int pin, int pirq_pin, int ioapic_irq, 1206 void *arg) 1207{ 1208 char *name; 1209 1210 name = lpc_pirq_name(pirq_pin); 1211 if (name == NULL) 1212 return; 1213 dsdt_line(" Package ()"); 1214 dsdt_line(" {"); 1215 dsdt_line(" 0x%X,", slot << 16 | 0xffff); 1216 dsdt_line(" 0x%02X,", pin - 1); 1217 dsdt_line(" %s,", name); 1218 dsdt_line(" 0x00"); 1219 dsdt_line(" },"); 1220 free(name); 1221} 1222 1223/* 1224 * A bhyve virtual machine has a flat PCI hierarchy with a root port 1225 * corresponding to each PCI bus. 1226 */ 1227static void 1228pci_bus_write_dsdt(int bus) 1229{ 1230 struct businfo *bi; 1231 struct slotinfo *si; 1232 struct pci_devinst *pi; 1233 int count, func, slot; 1234 1235 /* 1236 * If there are no devices on this 'bus' then just return. 1237 */ 1238 if ((bi = pci_businfo[bus]) == NULL) { 1239 /* 1240 * Bus 0 is special because it decodes the I/O ports used 1241 * for PCI config space access even if there are no devices 1242 * on it. 1243 */ 1244 if (bus != 0) 1245 return; 1246 } 1247 1248 dsdt_line(" Device (PC%02X)", bus); 1249 dsdt_line(" {"); 1250 dsdt_line(" Name (_HID, EisaId (\"PNP0A03\"))"); 1251 dsdt_line(" Name (_ADR, Zero)"); 1252 1253 dsdt_line(" Method (_BBN, 0, NotSerialized)"); 1254 dsdt_line(" {"); 1255 dsdt_line(" Return (0x%08X)", bus); 1256 dsdt_line(" }"); 1257 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 1258 dsdt_line(" {"); 1259 dsdt_line(" WordBusNumber (ResourceProducer, MinFixed, " 1260 "MaxFixed, PosDecode,"); 1261 dsdt_line(" 0x0000, // Granularity"); 1262 dsdt_line(" 0x%04X, // Range Minimum", bus); 1263 dsdt_line(" 0x%04X, // Range Maximum", bus); 1264 dsdt_line(" 0x0000, // Translation Offset"); 1265 dsdt_line(" 0x0001, // Length"); 1266 dsdt_line(" ,, )"); 1267 1268 if (bus == 0) { 1269 dsdt_indent(3); 1270 dsdt_fixed_ioport(0xCF8, 8); 1271 dsdt_unindent(3); 1272 1273 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1274 "PosDecode, EntireRange,"); 1275 dsdt_line(" 0x0000, // Granularity"); 1276 dsdt_line(" 0x0000, // Range Minimum"); 1277 dsdt_line(" 0x0CF7, // Range Maximum"); 1278 dsdt_line(" 0x0000, // Translation Offset"); 1279 dsdt_line(" 0x0CF8, // Length"); 1280 dsdt_line(" ,, , TypeStatic)"); 1281 1282 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1283 "PosDecode, EntireRange,"); 1284 dsdt_line(" 0x0000, // Granularity"); 1285 dsdt_line(" 0x0D00, // Range Minimum"); 1286 dsdt_line(" 0x%04X, // Range Maximum", 1287 PCI_EMUL_IOBASE - 1); 1288 dsdt_line(" 0x0000, // Translation Offset"); 1289 dsdt_line(" 0x%04X, // Length", 1290 PCI_EMUL_IOBASE - 0x0D00); 1291 dsdt_line(" ,, , TypeStatic)"); 1292 1293 if (bi == NULL) { 1294 dsdt_line(" })"); 1295 goto done; 1296 } 1297 } 1298 assert(bi != NULL); 1299 1300 /* i/o window */ 1301 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1302 "PosDecode, EntireRange,"); 1303 dsdt_line(" 0x0000, // Granularity"); 1304 dsdt_line(" 0x%04X, // Range Minimum", bi->iobase); 1305 dsdt_line(" 0x%04X, // Range Maximum", 1306 bi->iolimit - 1); 1307 dsdt_line(" 0x0000, // Translation Offset"); 1308 dsdt_line(" 0x%04X, // Length", 1309 bi->iolimit - bi->iobase); 1310 dsdt_line(" ,, , TypeStatic)"); 1311 1312 /* mmio window (32-bit) */ 1313 dsdt_line(" DWordMemory (ResourceProducer, PosDecode, " 1314 "MinFixed, MaxFixed, NonCacheable, ReadWrite,"); 1315 dsdt_line(" 0x00000000, // Granularity"); 1316 dsdt_line(" 0x%08X, // Range Minimum\n", bi->membase32); 1317 dsdt_line(" 0x%08X, // Range Maximum\n", 1318 bi->memlimit32 - 1); 1319 dsdt_line(" 0x00000000, // Translation Offset"); 1320 dsdt_line(" 0x%08X, // Length\n", 1321 bi->memlimit32 - bi->membase32); 1322 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)"); 1323 1324 /* mmio window (64-bit) */ 1325 dsdt_line(" QWordMemory (ResourceProducer, PosDecode, " 1326 "MinFixed, MaxFixed, NonCacheable, ReadWrite,"); 1327 dsdt_line(" 0x0000000000000000, // Granularity"); 1328 dsdt_line(" 0x%016lX, // Range Minimum\n", bi->membase64); 1329 dsdt_line(" 0x%016lX, // Range Maximum\n", 1330 bi->memlimit64 - 1); 1331 dsdt_line(" 0x0000000000000000, // Translation Offset"); 1332 dsdt_line(" 0x%016lX, // Length\n", 1333 bi->memlimit64 - bi->membase64); 1334 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)"); 1335 dsdt_line(" })"); 1336 1337 count = pci_count_lintr(bus); 1338 if (count != 0) { 1339 dsdt_indent(2); 1340 dsdt_line("Name (PPRT, Package ()"); 1341 dsdt_line("{"); 1342 pci_walk_lintr(bus, pci_pirq_prt_entry, NULL); 1343 dsdt_line("})"); 1344 dsdt_line("Name (APRT, Package ()"); 1345 dsdt_line("{"); 1346 pci_walk_lintr(bus, pci_apic_prt_entry, NULL); 1347 dsdt_line("})"); 1348 dsdt_line("Method (_PRT, 0, NotSerialized)"); 1349 dsdt_line("{"); 1350 dsdt_line(" If (PICM)"); 1351 dsdt_line(" {"); 1352 dsdt_line(" Return (APRT)"); 1353 dsdt_line(" }"); 1354 dsdt_line(" Else"); 1355 dsdt_line(" {"); 1356 dsdt_line(" Return (PPRT)"); 1357 dsdt_line(" }"); 1358 dsdt_line("}"); 1359 dsdt_unindent(2); 1360 } 1361 1362 dsdt_indent(2); 1363 for (slot = 0; slot < MAXSLOTS; slot++) { 1364 si = &bi->slotinfo[slot]; 1365 for (func = 0; func < MAXFUNCS; func++) { 1366 pi = si->si_funcs[func].fi_devi; 1367 if (pi != NULL && pi->pi_d->pe_write_dsdt != NULL) 1368 pi->pi_d->pe_write_dsdt(pi); 1369 } 1370 } 1371 dsdt_unindent(2); 1372done: 1373 dsdt_line(" }"); 1374} 1375 1376void 1377pci_write_dsdt(void) 1378{ 1379 int bus; 1380 1381 dsdt_indent(1); 1382 dsdt_line("Name (PICM, 0x00)"); 1383 dsdt_line("Method (_PIC, 1, NotSerialized)"); 1384 dsdt_line("{"); 1385 dsdt_line(" Store (Arg0, PICM)"); 1386 dsdt_line("}"); 1387 dsdt_line(""); 1388 dsdt_line("Scope (_SB)"); 1389 dsdt_line("{"); 1390 for (bus = 0; bus < MAXBUSES; bus++) 1391 pci_bus_write_dsdt(bus); 1392 dsdt_line("}"); 1393 dsdt_unindent(1); 1394} 1395 1396int 1397pci_bus_configured(int bus) 1398{ 1399 assert(bus >= 0 && bus < MAXBUSES); 1400 return (pci_businfo[bus] != NULL); 1401} 1402 1403int 1404pci_msi_enabled(struct pci_devinst *pi) 1405{ 1406 return (pi->pi_msi.enabled); 1407} 1408 1409int 1410pci_msi_maxmsgnum(struct pci_devinst *pi) 1411{ 1412 if (pi->pi_msi.enabled) 1413 return (pi->pi_msi.maxmsgnum); 1414 else 1415 return (0); 1416} 1417 1418int 1419pci_msix_enabled(struct pci_devinst *pi) 1420{ 1421 1422 return (pi->pi_msix.enabled && !pi->pi_msi.enabled); 1423} 1424 1425void 1426pci_generate_msix(struct pci_devinst *pi, int index) 1427{ 1428 struct msix_table_entry *mte; 1429 1430 if (!pci_msix_enabled(pi)) 1431 return; 1432 1433 if (pi->pi_msix.function_mask) 1434 return; 1435 1436 if (index >= pi->pi_msix.table_count) 1437 return; 1438 1439 mte = &pi->pi_msix.table[index]; 1440 if ((mte->vector_control & PCIM_MSIX_VCTRL_MASK) == 0) { 1441 /* XXX Set PBA bit if interrupt is disabled */ 1442 vm_lapic_msi(pi->pi_vmctx, mte->addr, mte->msg_data); 1443 } 1444} 1445 1446void 1447pci_generate_msi(struct pci_devinst *pi, int index) 1448{ 1449 1450 if (pci_msi_enabled(pi) && index < pci_msi_maxmsgnum(pi)) { 1451 vm_lapic_msi(pi->pi_vmctx, pi->pi_msi.addr, 1452 pi->pi_msi.msg_data + index); 1453 } 1454} 1455 1456static bool 1457pci_lintr_permitted(struct pci_devinst *pi) 1458{ 1459 uint16_t cmd; 1460 1461 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 1462 return (!(pi->pi_msi.enabled || pi->pi_msix.enabled || 1463 (cmd & PCIM_CMD_INTxDIS))); 1464} 1465 1466void 1467pci_lintr_request(struct pci_devinst *pi) 1468{ 1469 struct businfo *bi; 1470 struct slotinfo *si; 1471 int bestpin, bestcount, pin; 1472 1473 bi = pci_businfo[pi->pi_bus]; 1474 assert(bi != NULL); 1475 1476 /* 1477 * Just allocate a pin from our slot. The pin will be 1478 * assigned IRQs later when interrupts are routed. 1479 */ 1480 si = &bi->slotinfo[pi->pi_slot]; 1481 bestpin = 0; 1482 bestcount = si->si_intpins[0].ii_count; 1483 for (pin = 1; pin < 4; pin++) { 1484 if (si->si_intpins[pin].ii_count < bestcount) { 1485 bestpin = pin; 1486 bestcount = si->si_intpins[pin].ii_count; 1487 } 1488 } 1489 1490 si->si_intpins[bestpin].ii_count++; 1491 pi->pi_lintr.pin = bestpin + 1; 1492 pci_set_cfgdata8(pi, PCIR_INTPIN, bestpin + 1); 1493} 1494 1495static void 1496pci_lintr_route(struct pci_devinst *pi) 1497{ 1498 struct businfo *bi; 1499 struct intxinfo *ii; 1500 1501 if (pi->pi_lintr.pin == 0) 1502 return; 1503 1504 bi = pci_businfo[pi->pi_bus]; 1505 assert(bi != NULL); 1506 ii = &bi->slotinfo[pi->pi_slot].si_intpins[pi->pi_lintr.pin - 1]; 1507 1508 /* 1509 * Attempt to allocate an I/O APIC pin for this intpin if one 1510 * is not yet assigned. 1511 */ 1512 if (ii->ii_ioapic_irq == 0) 1513 ii->ii_ioapic_irq = ioapic_pci_alloc_irq(); 1514 assert(ii->ii_ioapic_irq > 0); 1515 1516 /* 1517 * Attempt to allocate a PIRQ pin for this intpin if one is 1518 * not yet assigned. 1519 */ 1520 if (ii->ii_pirq_pin == 0) 1521 ii->ii_pirq_pin = pirq_alloc_pin(pi->pi_vmctx); 1522 assert(ii->ii_pirq_pin > 0); 1523 1524 pi->pi_lintr.ioapic_irq = ii->ii_ioapic_irq; 1525 pi->pi_lintr.pirq_pin = ii->ii_pirq_pin; 1526 pci_set_cfgdata8(pi, PCIR_INTLINE, pirq_irq(ii->ii_pirq_pin)); 1527} 1528 1529void 1530pci_lintr_assert(struct pci_devinst *pi) 1531{ 1532 1533 assert(pi->pi_lintr.pin > 0); 1534 1535 pthread_mutex_lock(&pi->pi_lintr.lock); 1536 if (pi->pi_lintr.state == IDLE) { 1537 if (pci_lintr_permitted(pi)) { 1538 pi->pi_lintr.state = ASSERTED; 1539 pci_irq_assert(pi); 1540 } else 1541 pi->pi_lintr.state = PENDING; 1542 } 1543 pthread_mutex_unlock(&pi->pi_lintr.lock); 1544} 1545 1546void 1547pci_lintr_deassert(struct pci_devinst *pi) 1548{ 1549 1550 assert(pi->pi_lintr.pin > 0); 1551 1552 pthread_mutex_lock(&pi->pi_lintr.lock); 1553 if (pi->pi_lintr.state == ASSERTED) { 1554 pi->pi_lintr.state = IDLE; 1555 pci_irq_deassert(pi); 1556 } else if (pi->pi_lintr.state == PENDING) 1557 pi->pi_lintr.state = IDLE; 1558 pthread_mutex_unlock(&pi->pi_lintr.lock); 1559} 1560 1561static void 1562pci_lintr_update(struct pci_devinst *pi) 1563{ 1564 1565 pthread_mutex_lock(&pi->pi_lintr.lock); 1566 if (pi->pi_lintr.state == ASSERTED && !pci_lintr_permitted(pi)) { 1567 pci_irq_deassert(pi); 1568 pi->pi_lintr.state = PENDING; 1569 } else if (pi->pi_lintr.state == PENDING && pci_lintr_permitted(pi)) { 1570 pi->pi_lintr.state = ASSERTED; 1571 pci_irq_assert(pi); 1572 } 1573 pthread_mutex_unlock(&pi->pi_lintr.lock); 1574} 1575 1576int 1577pci_count_lintr(int bus) 1578{ 1579 int count, slot, pin; 1580 struct slotinfo *slotinfo; 1581 1582 count = 0; 1583 if (pci_businfo[bus] != NULL) { 1584 for (slot = 0; slot < MAXSLOTS; slot++) { 1585 slotinfo = &pci_businfo[bus]->slotinfo[slot]; 1586 for (pin = 0; pin < 4; pin++) { 1587 if (slotinfo->si_intpins[pin].ii_count != 0) 1588 count++; 1589 } 1590 } 1591 } 1592 return (count); 1593} 1594 1595void 1596pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg) 1597{ 1598 struct businfo *bi; 1599 struct slotinfo *si; 1600 struct intxinfo *ii; 1601 int slot, pin; 1602 1603 if ((bi = pci_businfo[bus]) == NULL) 1604 return; 1605 1606 for (slot = 0; slot < MAXSLOTS; slot++) { 1607 si = &bi->slotinfo[slot]; 1608 for (pin = 0; pin < 4; pin++) { 1609 ii = &si->si_intpins[pin]; 1610 if (ii->ii_count != 0) 1611 cb(bus, slot, pin + 1, ii->ii_pirq_pin, 1612 ii->ii_ioapic_irq, arg); 1613 } 1614 } 1615} 1616 1617/* 1618 * Return 1 if the emulated device in 'slot' is a multi-function device. 1619 * Return 0 otherwise. 1620 */ 1621static int 1622pci_emul_is_mfdev(int bus, int slot) 1623{ 1624 struct businfo *bi; 1625 struct slotinfo *si; 1626 int f, numfuncs; 1627 1628 numfuncs = 0; 1629 if ((bi = pci_businfo[bus]) != NULL) { 1630 si = &bi->slotinfo[slot]; 1631 for (f = 0; f < MAXFUNCS; f++) { 1632 if (si->si_funcs[f].fi_devi != NULL) { 1633 numfuncs++; 1634 } 1635 } 1636 } 1637 return (numfuncs > 1); 1638} 1639 1640/* 1641 * Ensure that the PCIM_MFDEV bit is properly set (or unset) depending on 1642 * whether or not is a multi-function being emulated in the pci 'slot'. 1643 */ 1644static void 1645pci_emul_hdrtype_fixup(int bus, int slot, int off, int bytes, uint32_t *rv) 1646{ 1647 int mfdev; 1648 1649 if (off <= PCIR_HDRTYPE && off + bytes > PCIR_HDRTYPE) { 1650 mfdev = pci_emul_is_mfdev(bus, slot); 1651 switch (bytes) { 1652 case 1: 1653 case 2: 1654 *rv &= ~PCIM_MFDEV; 1655 if (mfdev) { 1656 *rv |= PCIM_MFDEV; 1657 } 1658 break; 1659 case 4: 1660 *rv &= ~(PCIM_MFDEV << 16); 1661 if (mfdev) { 1662 *rv |= (PCIM_MFDEV << 16); 1663 } 1664 break; 1665 } 1666 } 1667} 1668 1669static void 1670pci_emul_cmdsts_write(struct pci_devinst *pi, int coff, uint32_t new, int bytes) 1671{ 1672 int i, rshift; 1673 uint32_t cmd, cmd2, changed, old, readonly; 1674 1675 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); /* stash old value */ 1676 1677 /* 1678 * From PCI Local Bus Specification 3.0 sections 6.2.2 and 6.2.3. 1679 * 1680 * XXX Bits 8, 11, 12, 13, 14 and 15 in the status register are 1681 * 'write 1 to clear'. However these bits are not set to '1' by 1682 * any device emulation so it is simpler to treat them as readonly. 1683 */ 1684 rshift = (coff & 0x3) * 8; 1685 readonly = 0xFFFFF880 >> rshift; 1686 1687 old = CFGREAD(pi, coff, bytes); 1688 new &= ~readonly; 1689 new |= (old & readonly); 1690 CFGWRITE(pi, coff, new, bytes); /* update config */ 1691 1692 cmd2 = pci_get_cfgdata16(pi, PCIR_COMMAND); /* get updated value */ 1693 changed = cmd ^ cmd2; 1694 1695 /* 1696 * If the MMIO or I/O address space decoding has changed then 1697 * register/unregister all BARs that decode that address space. 1698 */ 1699 for (i = 0; i <= PCI_BARMAX; i++) { 1700 switch (pi->pi_bar[i].type) { 1701 case PCIBAR_NONE: 1702 case PCIBAR_MEMHI64: 1703 break; 1704 case PCIBAR_IO: 1705 /* I/O address space decoding changed? */ 1706 if (changed & PCIM_CMD_PORTEN) { 1707 if (porten(pi)) 1708 register_bar(pi, i); 1709 else 1710 unregister_bar(pi, i); 1711 } 1712 break; 1713 case PCIBAR_MEM32: 1714 case PCIBAR_MEM64: 1715 /* MMIO address space decoding changed? */ 1716 if (changed & PCIM_CMD_MEMEN) { 1717 if (memen(pi)) 1718 register_bar(pi, i); 1719 else 1720 unregister_bar(pi, i); 1721 } 1722 break; 1723 default: 1724 assert(0); 1725 } 1726 } 1727 1728 /* 1729 * If INTx has been unmasked and is pending, assert the 1730 * interrupt. 1731 */ 1732 pci_lintr_update(pi); 1733} 1734 1735static void 1736pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot, int func, 1737 int coff, int bytes, uint32_t *eax) 1738{ 1739 struct businfo *bi; 1740 struct slotinfo *si; 1741 struct pci_devinst *pi; 1742 struct pci_devemu *pe; 1743 int idx, needcfg; 1744 uint64_t addr, bar, mask; 1745 1746 if ((bi = pci_businfo[bus]) != NULL) { 1747 si = &bi->slotinfo[slot]; 1748 pi = si->si_funcs[func].fi_devi; 1749 } else 1750 pi = NULL; 1751 1752 /* 1753 * Just return if there is no device at this slot:func or if the 1754 * the guest is doing an un-aligned access. 1755 */ 1756 if (pi == NULL || (bytes != 1 && bytes != 2 && bytes != 4) || 1757 (coff & (bytes - 1)) != 0) { 1758 if (in) 1759 *eax = 0xffffffff; 1760 return; 1761 } 1762 1763 /* 1764 * Ignore all writes beyond the standard config space and return all 1765 * ones on reads. 1766 */ 1767 if (coff >= PCI_REGMAX + 1) { 1768 if (in) { 1769 *eax = 0xffffffff; 1770 /* 1771 * Extended capabilities begin at offset 256 in config 1772 * space. Absence of extended capabilities is signaled 1773 * with all 0s in the extended capability header at 1774 * offset 256. 1775 */ 1776 if (coff <= PCI_REGMAX + 4) 1777 *eax = 0x00000000; 1778 } 1779 return; 1780 } 1781 1782 pe = pi->pi_d; 1783 1784 /* 1785 * Config read 1786 */ 1787 if (in) { 1788 /* Let the device emulation override the default handler */ 1789 if (pe->pe_cfgread != NULL) { 1790 needcfg = pe->pe_cfgread(ctx, vcpu, pi, coff, bytes, 1791 eax); 1792 } else { 1793 needcfg = 1; 1794 } 1795 1796 if (needcfg) 1797 *eax = CFGREAD(pi, coff, bytes); 1798 1799 pci_emul_hdrtype_fixup(bus, slot, coff, bytes, eax); 1800 } else { 1801 /* Let the device emulation override the default handler */ 1802 if (pe->pe_cfgwrite != NULL && 1803 (*pe->pe_cfgwrite)(ctx, vcpu, pi, coff, bytes, *eax) == 0) 1804 return; 1805 1806 /* 1807 * Special handling for write to BAR registers 1808 */ 1809 if (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1)) { 1810 /* 1811 * Ignore writes to BAR registers that are not 1812 * 4-byte aligned. 1813 */ 1814 if (bytes != 4 || (coff & 0x3) != 0) 1815 return; 1816 idx = (coff - PCIR_BAR(0)) / 4; 1817 mask = ~(pi->pi_bar[idx].size - 1); 1818 switch (pi->pi_bar[idx].type) { 1819 case PCIBAR_NONE: 1820 pi->pi_bar[idx].addr = bar = 0; 1821 break; 1822 case PCIBAR_IO: 1823 addr = *eax & mask; 1824 addr &= 0xffff; 1825 bar = addr | PCIM_BAR_IO_SPACE; 1826 /* 1827 * Register the new BAR value for interception 1828 */ 1829 if (addr != pi->pi_bar[idx].addr) { 1830 update_bar_address(pi, addr, idx, 1831 PCIBAR_IO); 1832 } 1833 break; 1834 case PCIBAR_MEM32: 1835 addr = bar = *eax & mask; 1836 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32; 1837 if (addr != pi->pi_bar[idx].addr) { 1838 update_bar_address(pi, addr, idx, 1839 PCIBAR_MEM32); 1840 } 1841 break; 1842 case PCIBAR_MEM64: 1843 addr = bar = *eax & mask; 1844 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 | 1845 PCIM_BAR_MEM_PREFETCH; 1846 if (addr != (uint32_t)pi->pi_bar[idx].addr) { 1847 update_bar_address(pi, addr, idx, 1848 PCIBAR_MEM64); 1849 } 1850 break; 1851 case PCIBAR_MEMHI64: 1852 mask = ~(pi->pi_bar[idx - 1].size - 1); 1853 addr = ((uint64_t)*eax << 32) & mask; 1854 bar = addr >> 32; 1855 if (bar != pi->pi_bar[idx - 1].addr >> 32) { 1856 update_bar_address(pi, addr, idx - 1, 1857 PCIBAR_MEMHI64); 1858 } 1859 break; 1860 default: 1861 assert(0); 1862 } 1863 pci_set_cfgdata32(pi, coff, bar); 1864 1865 } else if (pci_emul_iscap(pi, coff)) { 1866 pci_emul_capwrite(pi, coff, bytes, *eax); 1867 } else if (coff >= PCIR_COMMAND && coff < PCIR_REVID) { 1868 pci_emul_cmdsts_write(pi, coff, *eax, bytes); 1869 } else { 1870 CFGWRITE(pi, coff, *eax, bytes); 1871 } 1872 } 1873} 1874 1875static int cfgenable, cfgbus, cfgslot, cfgfunc, cfgoff; 1876 1877static int 1878pci_emul_cfgaddr(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 1879 uint32_t *eax, void *arg) 1880{ 1881 uint32_t x; 1882 1883 if (bytes != 4) { 1884 if (in) 1885 *eax = (bytes == 2) ? 0xffff : 0xff; 1886 return (0); 1887 } 1888 1889 if (in) { 1890 x = (cfgbus << 16) | (cfgslot << 11) | (cfgfunc << 8) | cfgoff; 1891 if (cfgenable) 1892 x |= CONF1_ENABLE; 1893 *eax = x; 1894 } else { 1895 x = *eax; 1896 cfgenable = (x & CONF1_ENABLE) == CONF1_ENABLE; 1897 cfgoff = x & PCI_REGMAX; 1898 cfgfunc = (x >> 8) & PCI_FUNCMAX; 1899 cfgslot = (x >> 11) & PCI_SLOTMAX; 1900 cfgbus = (x >> 16) & PCI_BUSMAX; 1901 } 1902 1903 return (0); 1904} 1905INOUT_PORT(pci_cfgaddr, CONF1_ADDR_PORT, IOPORT_F_INOUT, pci_emul_cfgaddr); 1906 1907static int 1908pci_emul_cfgdata(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 1909 uint32_t *eax, void *arg) 1910{ 1911 int coff; 1912 1913 assert(bytes == 1 || bytes == 2 || bytes == 4); 1914 1915 coff = cfgoff + (port - CONF1_DATA_PORT); 1916 if (cfgenable) { 1917 pci_cfgrw(ctx, vcpu, in, cfgbus, cfgslot, cfgfunc, coff, bytes, 1918 eax); 1919 } else { 1920 /* Ignore accesses to cfgdata if not enabled by cfgaddr */ 1921 if (in) 1922 *eax = 0xffffffff; 1923 } 1924 return (0); 1925} 1926 1927INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+0, IOPORT_F_INOUT, pci_emul_cfgdata); 1928INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+1, IOPORT_F_INOUT, pci_emul_cfgdata); 1929INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+2, IOPORT_F_INOUT, pci_emul_cfgdata); 1930INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+3, IOPORT_F_INOUT, pci_emul_cfgdata); 1931 1932#define PCI_EMUL_TEST 1933#ifdef PCI_EMUL_TEST 1934/* 1935 * Define a dummy test device 1936 */ 1937#define DIOSZ 8 1938#define DMEMSZ 4096 1939struct pci_emul_dsoftc { 1940 uint8_t ioregs[DIOSZ]; 1941 uint8_t memregs[2][DMEMSZ]; 1942}; 1943 1944#define PCI_EMUL_MSI_MSGS 4 1945#define PCI_EMUL_MSIX_MSGS 16 1946 1947static int 1948pci_emul_dinit(struct vmctx *ctx, struct pci_devinst *pi, char *opts) 1949{ 1950 int error; 1951 struct pci_emul_dsoftc *sc; 1952 1953 sc = calloc(1, sizeof(struct pci_emul_dsoftc)); 1954 1955 pi->pi_arg = sc; 1956 1957 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0001); 1958 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x10DD); 1959 pci_set_cfgdata8(pi, PCIR_CLASS, 0x02); 1960 1961 error = pci_emul_add_msicap(pi, PCI_EMUL_MSI_MSGS); 1962 assert(error == 0); 1963 1964 error = pci_emul_alloc_bar(pi, 0, PCIBAR_IO, DIOSZ); 1965 assert(error == 0); 1966 1967 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, DMEMSZ); 1968 assert(error == 0); 1969 1970 error = pci_emul_alloc_bar(pi, 2, PCIBAR_MEM32, DMEMSZ); 1971 assert(error == 0); 1972 1973 return (0); 1974} 1975 1976static void 1977pci_emul_diow(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 1978 uint64_t offset, int size, uint64_t value) 1979{ 1980 int i; 1981 struct pci_emul_dsoftc *sc = pi->pi_arg; 1982 1983 if (baridx == 0) { 1984 if (offset + size > DIOSZ) { 1985 printf("diow: iow too large, offset %ld size %d\n", 1986 offset, size); 1987 return; 1988 } 1989 1990 if (size == 1) { 1991 sc->ioregs[offset] = value & 0xff; 1992 } else if (size == 2) { 1993 *(uint16_t *)&sc->ioregs[offset] = value & 0xffff; 1994 } else if (size == 4) { 1995 *(uint32_t *)&sc->ioregs[offset] = value; 1996 } else { 1997 printf("diow: iow unknown size %d\n", size); 1998 } 1999 2000 /* 2001 * Special magic value to generate an interrupt 2002 */ 2003 if (offset == 4 && size == 4 && pci_msi_enabled(pi)) 2004 pci_generate_msi(pi, value % pci_msi_maxmsgnum(pi)); 2005 2006 if (value == 0xabcdef) { 2007 for (i = 0; i < pci_msi_maxmsgnum(pi); i++) 2008 pci_generate_msi(pi, i); 2009 } 2010 } 2011 2012 if (baridx == 1 || baridx == 2) { 2013 if (offset + size > DMEMSZ) { 2014 printf("diow: memw too large, offset %ld size %d\n", 2015 offset, size); 2016 return; 2017 } 2018 2019 i = baridx - 1; /* 'memregs' index */ 2020 2021 if (size == 1) { 2022 sc->memregs[i][offset] = value; 2023 } else if (size == 2) { 2024 *(uint16_t *)&sc->memregs[i][offset] = value; 2025 } else if (size == 4) { 2026 *(uint32_t *)&sc->memregs[i][offset] = value; 2027 } else if (size == 8) { 2028 *(uint64_t *)&sc->memregs[i][offset] = value; 2029 } else { 2030 printf("diow: memw unknown size %d\n", size); 2031 } 2032 2033 /* 2034 * magic interrupt ?? 2035 */ 2036 } 2037 2038 if (baridx > 2) { 2039 printf("diow: unknown bar idx %d\n", baridx); 2040 } 2041} 2042 2043static uint64_t 2044pci_emul_dior(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 2045 uint64_t offset, int size) 2046{ 2047 struct pci_emul_dsoftc *sc = pi->pi_arg; 2048 uint32_t value; 2049 int i; 2050 2051 if (baridx == 0) { 2052 if (offset + size > DIOSZ) { 2053 printf("dior: ior too large, offset %ld size %d\n", 2054 offset, size); 2055 return (0); 2056 } 2057 2058 if (size == 1) { 2059 value = sc->ioregs[offset]; 2060 } else if (size == 2) { 2061 value = *(uint16_t *) &sc->ioregs[offset]; 2062 } else if (size == 4) { 2063 value = *(uint32_t *) &sc->ioregs[offset]; 2064 } else { 2065 printf("dior: ior unknown size %d\n", size); 2066 } 2067 } 2068 2069 if (baridx == 1 || baridx == 2) { 2070 if (offset + size > DMEMSZ) { 2071 printf("dior: memr too large, offset %ld size %d\n", 2072 offset, size); 2073 return (0); 2074 } 2075 2076 i = baridx - 1; /* 'memregs' index */ 2077 2078 if (size == 1) { 2079 value = sc->memregs[i][offset]; 2080 } else if (size == 2) { 2081 value = *(uint16_t *) &sc->memregs[i][offset]; 2082 } else if (size == 4) { 2083 value = *(uint32_t *) &sc->memregs[i][offset]; 2084 } else if (size == 8) { 2085 value = *(uint64_t *) &sc->memregs[i][offset]; 2086 } else { 2087 printf("dior: ior unknown size %d\n", size); 2088 } 2089 } 2090 2091 2092 if (baridx > 2) { 2093 printf("dior: unknown bar idx %d\n", baridx); 2094 return (0); 2095 } 2096 2097 return (value); 2098} 2099 2100struct pci_devemu pci_dummy = { 2101 .pe_emu = "dummy", 2102 .pe_init = pci_emul_dinit, 2103 .pe_barwrite = pci_emul_diow, 2104 .pe_barread = pci_emul_dior 2105}; 2106PCI_EMUL_SET(pci_dummy); 2107 2108#endif /* PCI_EMUL_TEST */ 2109