pci_ahci.c revision 280733
1311116Sdim/*- 2311116Sdim * Copyright (c) 2013 Zhixiang Yu <zcore@freebsd.org> 3353358Sdim * All rights reserved. 4353358Sdim * 5353358Sdim * Redistribution and use in source and binary forms, with or without 6311116Sdim * modification, are permitted provided that the following conditions 7311116Sdim * are met: 8311116Sdim * 1. Redistributions of source code must retain the above copyright 9311116Sdim * notice, this list of conditions and the following disclaimer. 10311116Sdim * 2. Redistributions in binary form must reproduce the above copyright 11311116Sdim * notice, this list of conditions and the following disclaimer in the 12311116Sdim * documentation and/or other materials provided with the distribution. 13311116Sdim * 14353358Sdim * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 15311833Sdim * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16321369Sdim * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17321369Sdim * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18311116Sdim * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19311116Sdim * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20311116Sdim * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21311833Sdim * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22311116Sdim * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23311833Sdim * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24311116Sdim * SUCH DAMAGE. 25311116Sdim * 26311116Sdim * $FreeBSD: stable/10/usr.sbin/bhyve/pci_ahci.c 280733 2015-03-27 08:43:45Z mav $ 27311116Sdim */ 28311116Sdim 29311116Sdim#include <sys/cdefs.h> 30311116Sdim__FBSDID("$FreeBSD: stable/10/usr.sbin/bhyve/pci_ahci.c 280733 2015-03-27 08:43:45Z mav $"); 31311116Sdim 32311116Sdim#include <sys/param.h> 33311116Sdim#include <sys/linker_set.h> 34311116Sdim#include <sys/stat.h> 35311116Sdim#include <sys/uio.h> 36341825Sdim#include <sys/ioctl.h> 37341825Sdim#include <sys/disk.h> 38341825Sdim#include <sys/ata.h> 39341825Sdim#include <sys/endian.h> 40341825Sdim 41341825Sdim#include <errno.h> 42341825Sdim#include <fcntl.h> 43353358Sdim#include <stdio.h> 44341825Sdim#include <stdlib.h> 45341825Sdim#include <stdint.h> 46341825Sdim#include <string.h> 47341825Sdim#include <strings.h> 48341825Sdim#include <unistd.h> 49341825Sdim#include <assert.h> 50341825Sdim#include <pthread.h> 51341825Sdim#include <pthread_np.h> 52341825Sdim#include <inttypes.h> 53341825Sdim 54341825Sdim#include "bhyverun.h" 55341825Sdim#include "pci_emul.h" 56341825Sdim#include "ahci.h" 57341825Sdim#include "block_if.h" 58341825Sdim 59341825Sdim#define MAX_PORTS 6 /* Intel ICH8 AHCI supports 6 ports */ 60341825Sdim 61341825Sdim#define PxSIG_ATA 0x00000101 /* ATA drive */ 62341825Sdim#define PxSIG_ATAPI 0xeb140101 /* ATAPI drive */ 63341825Sdim 64311116Sdimenum sata_fis_type { 65311116Sdim FIS_TYPE_REGH2D = 0x27, /* Register FIS - host to device */ 66311833Sdim FIS_TYPE_REGD2H = 0x34, /* Register FIS - device to host */ 67311116Sdim FIS_TYPE_DMAACT = 0x39, /* DMA activate FIS - device to host */ 68311116Sdim FIS_TYPE_DMASETUP = 0x41, /* DMA setup FIS - bidirectional */ 69311116Sdim FIS_TYPE_DATA = 0x46, /* Data FIS - bidirectional */ 70311116Sdim FIS_TYPE_BIST = 0x58, /* BIST activate FIS - bidirectional */ 71341825Sdim FIS_TYPE_PIOSETUP = 0x5F, /* PIO setup FIS - device to host */ 72341825Sdim FIS_TYPE_SETDEVBITS = 0xA1, /* Set dev bits FIS - device to host */ 73341825Sdim}; 74341825Sdim 75311116Sdim/* 76311116Sdim * SCSI opcodes 77311833Sdim */ 78311833Sdim#define TEST_UNIT_READY 0x00 79311116Sdim#define REQUEST_SENSE 0x03 80311116Sdim#define INQUIRY 0x12 81311116Sdim#define START_STOP_UNIT 0x1B 82311116Sdim#define PREVENT_ALLOW 0x1E 83311116Sdim#define READ_CAPACITY 0x25 84311116Sdim#define READ_10 0x28 85311116Sdim#define POSITION_TO_ELEMENT 0x2B 86360784Sdim#define READ_TOC 0x43 87311116Sdim#define GET_EVENT_STATUS_NOTIFICATION 0x4A 88311116Sdim#define MODE_SENSE_10 0x5A 89311116Sdim#define READ_12 0xA8 90311116Sdim#define READ_CD 0xBE 91311116Sdim 92311116Sdim/* 93311116Sdim * SCSI mode page codes 94311116Sdim */ 95311116Sdim#define MODEPAGE_RW_ERROR_RECOVERY 0x01 96311116Sdim#define MODEPAGE_CD_CAPABILITIES 0x2A 97311116Sdim 98311116Sdim/* 99311116Sdim * ATA commands 100311116Sdim */ 101311116Sdim#define ATA_SF_ENAB_SATA_SF 0x10 102311116Sdim#define ATA_SATA_SF_AN 0x05 103311116Sdim#define ATA_SF_DIS_SATA_SF 0x90 104311116Sdim 105311116Sdim/* 106311116Sdim * Debug printf 107311116Sdim */ 108311116Sdim#ifdef AHCI_DEBUG 109311116Sdimstatic FILE *dbg; 110311116Sdim#define DPRINTF(format, arg...) do{fprintf(dbg, format, ##arg);fflush(dbg);}while(0) 111327952Sdim#else 112327952Sdim#define DPRINTF(format, arg...) 113327952Sdim#endif 114327952Sdim#define WPRINTF(format, arg...) printf(format, ##arg) 115327952Sdim 116327952Sdimstruct ahci_ioreq { 117327952Sdim struct blockif_req io_req; 118327952Sdim struct ahci_port *io_pr; 119327952Sdim STAILQ_ENTRY(ahci_ioreq) io_flist; 120327952Sdim TAILQ_ENTRY(ahci_ioreq) io_blist; 121327952Sdim uint8_t *cfis; 122327952Sdim uint32_t len; 123327952Sdim uint32_t done; 124327952Sdim int slot; 125327952Sdim int prdtl; 126311116Sdim}; 127311116Sdim 128311116Sdimstruct ahci_port { 129311116Sdim struct blockif_ctxt *bctx; 130311116Sdim struct pci_ahci_softc *pr_sc; 131311116Sdim uint8_t *cmd_lst; 132311116Sdim uint8_t *rfis; 133311116Sdim int atapi; 134311116Sdim int reset; 135311116Sdim int mult_sectors; 136311116Sdim uint8_t xfermode; 137311116Sdim uint8_t sense_key; 138321369Sdim uint8_t asc; 139321369Sdim uint32_t pending; 140311116Sdim 141311116Sdim uint32_t clb; 142311116Sdim uint32_t clbu; 143311116Sdim uint32_t fb; 144311116Sdim uint32_t fbu; 145311116Sdim uint32_t is; 146311116Sdim uint32_t ie; 147311116Sdim uint32_t cmd; 148321369Sdim uint32_t unused0; 149321369Sdim uint32_t tfd; 150321369Sdim uint32_t sig; 151321369Sdim uint32_t ssts; 152321369Sdim uint32_t sctl; 153321369Sdim uint32_t serr; 154321369Sdim uint32_t sact; 155321369Sdim uint32_t ci; 156311116Sdim uint32_t sntf; 157311116Sdim uint32_t fbs; 158311116Sdim 159311116Sdim /* 160311116Sdim * i/o request info 161311116Sdim */ 162311116Sdim struct ahci_ioreq *ioreq; 163311116Sdim int ioqsz; 164311116Sdim STAILQ_HEAD(ahci_fhead, ahci_ioreq) iofhd; 165321369Sdim TAILQ_HEAD(ahci_bhead, ahci_ioreq) iobhd; 166321369Sdim}; 167311116Sdim 168311116Sdimstruct ahci_cmd_hdr { 169321369Sdim uint16_t flags; 170311116Sdim uint16_t prdtl; 171311116Sdim uint32_t prdbc; 172341825Sdim uint64_t ctba; 173353358Sdim uint32_t reserved[4]; 174341825Sdim}; 175341825Sdim 176353358Sdimstruct ahci_prdt_entry { 177341825Sdim uint64_t dba; 178341825Sdim uint32_t reserved; 179341825Sdim#define DBCMASK 0x3fffff 180341825Sdim uint32_t dbc; 181341825Sdim}; 182341825Sdim 183341825Sdimstruct pci_ahci_softc { 184311116Sdim struct pci_devinst *asc_pi; 185311116Sdim pthread_mutex_t mtx; 186311116Sdim int ports; 187327952Sdim uint32_t cap; 188327952Sdim uint32_t ghc; 189311116Sdim uint32_t is; 190311116Sdim uint32_t pi; 191311116Sdim uint32_t vs; 192311116Sdim uint32_t ccc_ctl; 193311116Sdim uint32_t ccc_pts; 194321369Sdim uint32_t em_loc; 195321369Sdim uint32_t em_ctl; 196321369Sdim uint32_t cap2; 197321369Sdim uint32_t bohc; 198311116Sdim uint32_t lintr; 199311116Sdim struct ahci_port port[MAX_PORTS]; 200311116Sdim}; 201311116Sdim#define ahci_ctx(sc) ((sc)->asc_pi->pi_vmctx) 202311116Sdim 203311116Sdimstatic inline void lba_to_msf(uint8_t *buf, int lba) 204311116Sdim{ 205311116Sdim lba += 150; 206311116Sdim buf[0] = (lba / 75) / 60; 207311116Sdim buf[1] = (lba / 75) % 60; 208311116Sdim buf[2] = lba % 75; 209311116Sdim} 210311116Sdim 211311116Sdim/* 212311116Sdim * generate HBA intr depending on whether or not ports within 213311116Sdim * the controller have an interrupt pending. 214311116Sdim */ 215311116Sdimstatic void 216311116Sdimahci_generate_intr(struct pci_ahci_softc *sc) 217311116Sdim{ 218311116Sdim struct pci_devinst *pi; 219311116Sdim int i; 220311116Sdim 221 pi = sc->asc_pi; 222 223 for (i = 0; i < sc->ports; i++) { 224 struct ahci_port *pr; 225 pr = &sc->port[i]; 226 if (pr->is & pr->ie) 227 sc->is |= (1 << i); 228 } 229 230 DPRINTF("%s %x\n", __func__, sc->is); 231 232 if (sc->is && (sc->ghc & AHCI_GHC_IE)) { 233 if (pci_msi_enabled(pi)) { 234 /* 235 * Generate an MSI interrupt on every edge 236 */ 237 pci_generate_msi(pi, 0); 238 } else if (!sc->lintr) { 239 /* 240 * Only generate a pin-based interrupt if one wasn't 241 * in progress 242 */ 243 sc->lintr = 1; 244 pci_lintr_assert(pi); 245 } 246 } else if (sc->lintr) { 247 /* 248 * No interrupts: deassert pin-based signal if it had 249 * been asserted 250 */ 251 pci_lintr_deassert(pi); 252 sc->lintr = 0; 253 } 254} 255 256static void 257ahci_write_fis(struct ahci_port *p, enum sata_fis_type ft, uint8_t *fis) 258{ 259 int offset, len, irq; 260 261 if (p->rfis == NULL || !(p->cmd & AHCI_P_CMD_FRE)) 262 return; 263 264 switch (ft) { 265 case FIS_TYPE_REGD2H: 266 offset = 0x40; 267 len = 20; 268 irq = AHCI_P_IX_DHR; 269 break; 270 case FIS_TYPE_SETDEVBITS: 271 offset = 0x58; 272 len = 8; 273 irq = AHCI_P_IX_SDB; 274 break; 275 case FIS_TYPE_PIOSETUP: 276 offset = 0x20; 277 len = 20; 278 irq = 0; 279 break; 280 default: 281 WPRINTF("unsupported fis type %d\n", ft); 282 return; 283 } 284 memcpy(p->rfis + offset, fis, len); 285 if (irq) { 286 p->is |= irq; 287 ahci_generate_intr(p->pr_sc); 288 } 289} 290 291static void 292ahci_write_fis_piosetup(struct ahci_port *p) 293{ 294 uint8_t fis[20]; 295 296 memset(fis, 0, sizeof(fis)); 297 fis[0] = FIS_TYPE_PIOSETUP; 298 ahci_write_fis(p, FIS_TYPE_PIOSETUP, fis); 299} 300 301static void 302ahci_write_fis_sdb(struct ahci_port *p, int slot, uint32_t tfd) 303{ 304 uint8_t fis[8]; 305 uint8_t error; 306 307 error = (tfd >> 8) & 0xff; 308 memset(fis, 0, sizeof(fis)); 309 fis[0] = error; 310 fis[2] = tfd & 0x77; 311 *(uint32_t *)(fis + 4) = (1 << slot); 312 if (fis[2] & ATA_S_ERROR) 313 p->is |= AHCI_P_IX_TFE; 314 p->tfd = tfd; 315 ahci_write_fis(p, FIS_TYPE_SETDEVBITS, fis); 316} 317 318static void 319ahci_write_fis_d2h(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd) 320{ 321 uint8_t fis[20]; 322 uint8_t error; 323 324 error = (tfd >> 8) & 0xff; 325 memset(fis, 0, sizeof(fis)); 326 fis[0] = FIS_TYPE_REGD2H; 327 fis[1] = (1 << 6); 328 fis[2] = tfd & 0xff; 329 fis[3] = error; 330 fis[4] = cfis[4]; 331 fis[5] = cfis[5]; 332 fis[6] = cfis[6]; 333 fis[7] = cfis[7]; 334 fis[8] = cfis[8]; 335 fis[9] = cfis[9]; 336 fis[10] = cfis[10]; 337 fis[11] = cfis[11]; 338 fis[12] = cfis[12]; 339 fis[13] = cfis[13]; 340 if (fis[2] & ATA_S_ERROR) 341 p->is |= AHCI_P_IX_TFE; 342 else 343 p->ci &= ~(1 << slot); 344 p->tfd = tfd; 345 ahci_write_fis(p, FIS_TYPE_REGD2H, fis); 346} 347 348static void 349ahci_write_reset_fis_d2h(struct ahci_port *p) 350{ 351 uint8_t fis[20]; 352 353 memset(fis, 0, sizeof(fis)); 354 fis[0] = FIS_TYPE_REGD2H; 355 fis[3] = 1; 356 fis[4] = 1; 357 if (p->atapi) { 358 fis[5] = 0x14; 359 fis[6] = 0xeb; 360 } 361 fis[12] = 1; 362 ahci_write_fis(p, FIS_TYPE_REGD2H, fis); 363} 364 365static void 366ahci_check_stopped(struct ahci_port *p) 367{ 368 /* 369 * If we are no longer processing the command list and nothing 370 * is in-flight, clear the running bit, the current command 371 * slot, the command issue and active bits. 372 */ 373 if (!(p->cmd & AHCI_P_CMD_ST)) { 374 if (p->pending == 0) { 375 p->cmd &= ~(AHCI_P_CMD_CR | AHCI_P_CMD_CCS_MASK); 376 p->ci = 0; 377 p->sact = 0; 378 } 379 } 380} 381 382static void 383ahci_port_stop(struct ahci_port *p) 384{ 385 struct ahci_ioreq *aior; 386 uint8_t *cfis; 387 int slot; 388 int ncq; 389 int error; 390 391 assert(pthread_mutex_isowned_np(&p->pr_sc->mtx)); 392 393 TAILQ_FOREACH(aior, &p->iobhd, io_blist) { 394 /* 395 * Try to cancel the outstanding blockif request. 396 */ 397 error = blockif_cancel(p->bctx, &aior->io_req); 398 if (error != 0) 399 continue; 400 401 slot = aior->slot; 402 cfis = aior->cfis; 403 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED || 404 cfis[2] == ATA_READ_FPDMA_QUEUED) 405 ncq = 1; 406 407 if (ncq) 408 p->sact &= ~(1 << slot); 409 else 410 p->ci &= ~(1 << slot); 411 412 /* 413 * This command is now done. 414 */ 415 p->pending &= ~(1 << slot); 416 417 /* 418 * Delete the blockif request from the busy list 419 */ 420 TAILQ_REMOVE(&p->iobhd, aior, io_blist); 421 422 /* 423 * Move the blockif request back to the free list 424 */ 425 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist); 426 } 427 428 ahci_check_stopped(p); 429} 430 431static void 432ahci_port_reset(struct ahci_port *pr) 433{ 434 pr->serr = 0; 435 pr->sact = 0; 436 pr->xfermode = ATA_UDMA6; 437 pr->mult_sectors = 128; 438 439 if (!pr->bctx) { 440 pr->ssts = ATA_SS_DET_NO_DEVICE; 441 pr->sig = 0xFFFFFFFF; 442 pr->tfd = 0x7F; 443 return; 444 } 445 pr->ssts = ATA_SS_DET_PHY_ONLINE | ATA_SS_IPM_ACTIVE; 446 if (pr->sctl & ATA_SC_SPD_MASK) 447 pr->ssts |= (pr->sctl & ATA_SC_SPD_MASK); 448 else 449 pr->ssts |= ATA_SS_SPD_GEN3; 450 pr->tfd = (1 << 8) | ATA_S_DSC | ATA_S_DMA; 451 if (!pr->atapi) { 452 pr->sig = PxSIG_ATA; 453 pr->tfd |= ATA_S_READY; 454 } else 455 pr->sig = PxSIG_ATAPI; 456 ahci_write_reset_fis_d2h(pr); 457} 458 459static void 460ahci_reset(struct pci_ahci_softc *sc) 461{ 462 int i; 463 464 sc->ghc = AHCI_GHC_AE; 465 sc->is = 0; 466 467 if (sc->lintr) { 468 pci_lintr_deassert(sc->asc_pi); 469 sc->lintr = 0; 470 } 471 472 for (i = 0; i < sc->ports; i++) { 473 sc->port[i].ie = 0; 474 sc->port[i].is = 0; 475 sc->port[i].sctl = 0; 476 ahci_port_reset(&sc->port[i]); 477 } 478} 479 480static void 481ata_string(uint8_t *dest, const char *src, int len) 482{ 483 int i; 484 485 for (i = 0; i < len; i++) { 486 if (*src) 487 dest[i ^ 1] = *src++; 488 else 489 dest[i ^ 1] = ' '; 490 } 491} 492 493static void 494atapi_string(uint8_t *dest, const char *src, int len) 495{ 496 int i; 497 498 for (i = 0; i < len; i++) { 499 if (*src) 500 dest[i] = *src++; 501 else 502 dest[i] = ' '; 503 } 504} 505 506static void 507ahci_handle_dma(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done, 508 int seek) 509{ 510 struct ahci_ioreq *aior; 511 struct blockif_req *breq; 512 struct pci_ahci_softc *sc; 513 struct ahci_prdt_entry *prdt; 514 struct ahci_cmd_hdr *hdr; 515 uint64_t lba; 516 uint32_t len; 517 int i, err, iovcnt, ncq, readop; 518 519 sc = p->pr_sc; 520 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 521 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 522 ncq = 0; 523 readop = 1; 524 525 prdt += seek; 526 if (cfis[2] == ATA_WRITE || cfis[2] == ATA_WRITE48 || 527 cfis[2] == ATA_WRITE_MUL || cfis[2] == ATA_WRITE_MUL48 || 528 cfis[2] == ATA_WRITE_DMA || cfis[2] == ATA_WRITE_DMA48 || 529 cfis[2] == ATA_WRITE_FPDMA_QUEUED) 530 readop = 0; 531 532 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED || 533 cfis[2] == ATA_READ_FPDMA_QUEUED) { 534 lba = ((uint64_t)cfis[10] << 40) | 535 ((uint64_t)cfis[9] << 32) | 536 ((uint64_t)cfis[8] << 24) | 537 ((uint64_t)cfis[6] << 16) | 538 ((uint64_t)cfis[5] << 8) | 539 cfis[4]; 540 len = cfis[11] << 8 | cfis[3]; 541 if (!len) 542 len = 65536; 543 ncq = 1; 544 } else if (cfis[2] == ATA_READ48 || cfis[2] == ATA_WRITE48 || 545 cfis[2] == ATA_READ_MUL48 || cfis[2] == ATA_WRITE_MUL48 || 546 cfis[2] == ATA_READ_DMA48 || cfis[2] == ATA_WRITE_DMA48) { 547 lba = ((uint64_t)cfis[10] << 40) | 548 ((uint64_t)cfis[9] << 32) | 549 ((uint64_t)cfis[8] << 24) | 550 ((uint64_t)cfis[6] << 16) | 551 ((uint64_t)cfis[5] << 8) | 552 cfis[4]; 553 len = cfis[13] << 8 | cfis[12]; 554 if (!len) 555 len = 65536; 556 } else { 557 lba = ((cfis[7] & 0xf) << 24) | (cfis[6] << 16) | 558 (cfis[5] << 8) | cfis[4]; 559 len = cfis[12]; 560 if (!len) 561 len = 256; 562 } 563 lba *= blockif_sectsz(p->bctx); 564 len *= blockif_sectsz(p->bctx); 565 566 /* 567 * Pull request off free list 568 */ 569 aior = STAILQ_FIRST(&p->iofhd); 570 assert(aior != NULL); 571 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist); 572 aior->cfis = cfis; 573 aior->slot = slot; 574 aior->len = len; 575 aior->done = done; 576 breq = &aior->io_req; 577 breq->br_offset = lba + done; 578 iovcnt = hdr->prdtl - seek; 579 if (iovcnt > BLOCKIF_IOV_MAX) { 580 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX; 581 iovcnt = BLOCKIF_IOV_MAX; 582 } else 583 aior->prdtl = 0; 584 breq->br_iovcnt = iovcnt; 585 586 /* 587 * Mark this command in-flight. 588 */ 589 p->pending |= 1 << slot; 590 591 /* 592 * Stuff request onto busy list 593 */ 594 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist); 595 596 /* 597 * Build up the iovec based on the prdt 598 */ 599 for (i = 0; i < iovcnt; i++) { 600 uint32_t dbcsz; 601 602 dbcsz = (prdt->dbc & DBCMASK) + 1; 603 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc), 604 prdt->dba, dbcsz); 605 breq->br_iov[i].iov_len = dbcsz; 606 aior->done += dbcsz; 607 prdt++; 608 } 609 if (readop) 610 err = blockif_read(p->bctx, breq); 611 else 612 err = blockif_write(p->bctx, breq); 613 assert(err == 0); 614 615 if (ncq) 616 p->ci &= ~(1 << slot); 617} 618 619static void 620ahci_handle_flush(struct ahci_port *p, int slot, uint8_t *cfis) 621{ 622 struct ahci_ioreq *aior; 623 struct blockif_req *breq; 624 int err; 625 626 /* 627 * Pull request off free list 628 */ 629 aior = STAILQ_FIRST(&p->iofhd); 630 assert(aior != NULL); 631 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist); 632 aior->cfis = cfis; 633 aior->slot = slot; 634 aior->len = 0; 635 aior->done = 0; 636 aior->prdtl = 0; 637 breq = &aior->io_req; 638 639 /* 640 * Mark this command in-flight. 641 */ 642 p->pending |= 1 << slot; 643 644 /* 645 * Stuff request onto busy list 646 */ 647 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist); 648 649 err = blockif_flush(p->bctx, breq); 650 assert(err == 0); 651} 652 653static inline void 654read_prdt(struct ahci_port *p, int slot, uint8_t *cfis, 655 void *buf, int size) 656{ 657 struct ahci_cmd_hdr *hdr; 658 struct ahci_prdt_entry *prdt; 659 void *to; 660 int i, len; 661 662 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 663 len = size; 664 to = buf; 665 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 666 for (i = 0; i < hdr->prdtl && len; i++) { 667 uint8_t *ptr; 668 uint32_t dbcsz; 669 int sublen; 670 671 dbcsz = (prdt->dbc & DBCMASK) + 1; 672 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz); 673 sublen = len < dbcsz ? len : dbcsz; 674 memcpy(to, ptr, sublen); 675 len -= sublen; 676 to += sublen; 677 prdt++; 678 } 679} 680 681static void 682ahci_handle_dsm_trim(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done) 683{ 684 struct ahci_ioreq *aior; 685 struct blockif_req *breq; 686 uint8_t *entry; 687 uint64_t elba; 688 uint32_t len, elen; 689 int err; 690 uint8_t buf[512]; 691 692 len = (uint16_t)cfis[13] << 8 | cfis[12]; 693 len *= 512; 694 read_prdt(p, slot, cfis, buf, sizeof(buf)); 695 696next: 697 entry = &buf[done]; 698 elba = ((uint64_t)entry[5] << 40) | 699 ((uint64_t)entry[4] << 32) | 700 ((uint64_t)entry[3] << 24) | 701 ((uint64_t)entry[2] << 16) | 702 ((uint64_t)entry[1] << 8) | 703 entry[0]; 704 elen = (uint16_t)entry[7] << 8 | entry[6]; 705 done += 8; 706 if (elen == 0) { 707 if (done >= len) { 708 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 709 p->pending &= ~(1 << slot); 710 ahci_check_stopped(p); 711 return; 712 } 713 goto next; 714 } 715 716 /* 717 * Pull request off free list 718 */ 719 aior = STAILQ_FIRST(&p->iofhd); 720 assert(aior != NULL); 721 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist); 722 aior->cfis = cfis; 723 aior->slot = slot; 724 aior->len = len; 725 aior->done = done; 726 aior->prdtl = 0; 727 728 breq = &aior->io_req; 729 breq->br_offset = elba * blockif_sectsz(p->bctx); 730 breq->br_iovcnt = 1; 731 breq->br_iov[0].iov_len = elen * blockif_sectsz(p->bctx); 732 733 /* 734 * Mark this command in-flight. 735 */ 736 p->pending |= 1 << slot; 737 738 /* 739 * Stuff request onto busy list 740 */ 741 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist); 742 743 err = blockif_delete(p->bctx, breq); 744 assert(err == 0); 745} 746 747static inline void 748write_prdt(struct ahci_port *p, int slot, uint8_t *cfis, 749 void *buf, int size) 750{ 751 struct ahci_cmd_hdr *hdr; 752 struct ahci_prdt_entry *prdt; 753 void *from; 754 int i, len; 755 756 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 757 len = size; 758 from = buf; 759 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 760 for (i = 0; i < hdr->prdtl && len; i++) { 761 uint8_t *ptr; 762 uint32_t dbcsz; 763 int sublen; 764 765 dbcsz = (prdt->dbc & DBCMASK) + 1; 766 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz); 767 sublen = len < dbcsz ? len : dbcsz; 768 memcpy(ptr, from, sublen); 769 len -= sublen; 770 from += sublen; 771 prdt++; 772 } 773 hdr->prdbc = size - len; 774} 775 776static void 777handle_identify(struct ahci_port *p, int slot, uint8_t *cfis) 778{ 779 struct ahci_cmd_hdr *hdr; 780 781 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 782 if (p->atapi || hdr->prdtl == 0) { 783 ahci_write_fis_d2h(p, slot, cfis, 784 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 785 } else { 786 uint16_t buf[256]; 787 uint64_t sectors; 788 int sectsz, psectsz, psectoff, candelete, ro; 789 uint16_t cyl; 790 uint8_t sech, heads; 791 792 ro = blockif_is_ro(p->bctx); 793 candelete = blockif_candelete(p->bctx); 794 sectsz = blockif_sectsz(p->bctx); 795 sectors = blockif_size(p->bctx) / sectsz; 796 blockif_chs(p->bctx, &cyl, &heads, &sech); 797 blockif_psectsz(p->bctx, &psectsz, &psectoff); 798 memset(buf, 0, sizeof(buf)); 799 buf[0] = 0x0040; 800 buf[1] = cyl; 801 buf[3] = heads; 802 buf[6] = sech; 803 /* TODO emulate different serial? */ 804 ata_string((uint8_t *)(buf+10), "123456", 20); 805 ata_string((uint8_t *)(buf+23), "001", 8); 806 ata_string((uint8_t *)(buf+27), "BHYVE SATA DISK", 40); 807 buf[47] = (0x8000 | 128); 808 buf[48] = 0x1; 809 buf[49] = (1 << 8 | 1 << 9 | 1 << 11); 810 buf[50] = (1 << 14); 811 buf[53] = (1 << 1 | 1 << 2); 812 if (p->mult_sectors) 813 buf[59] = (0x100 | p->mult_sectors); 814 if (sectors <= 0x0fffffff) { 815 buf[60] = sectors; 816 buf[61] = (sectors >> 16); 817 } else { 818 buf[60] = 0xffff; 819 buf[61] = 0x0fff; 820 } 821 buf[63] = 0x7; 822 if (p->xfermode & ATA_WDMA0) 823 buf[63] |= (1 << ((p->xfermode & 7) + 8)); 824 buf[64] = 0x3; 825 buf[65] = 120; 826 buf[66] = 120; 827 buf[67] = 120; 828 buf[68] = 120; 829 buf[69] = 0; 830 buf[75] = 31; 831 buf[76] = (ATA_SATA_GEN1 | ATA_SATA_GEN2 | ATA_SATA_GEN3 | 832 ATA_SUPPORT_NCQ); 833 buf[80] = 0x1f0; 834 buf[81] = 0x28; 835 buf[82] = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE| 836 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP); 837 buf[83] = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE | 838 ATA_SUPPORT_FLUSHCACHE48 | 1 << 14); 839 buf[84] = (1 << 14); 840 buf[85] = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE| 841 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP); 842 buf[86] = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE | 843 ATA_SUPPORT_FLUSHCACHE48); 844 buf[87] = (1 << 14); 845 buf[88] = 0x7f; 846 if (p->xfermode & ATA_UDMA0) 847 buf[88] |= (1 << ((p->xfermode & 7) + 8)); 848 buf[93] = (1 | 1 <<14); 849 buf[100] = sectors; 850 buf[101] = (sectors >> 16); 851 buf[102] = (sectors >> 32); 852 buf[103] = (sectors >> 48); 853 if (candelete && !ro) { 854 buf[69] |= ATA_SUPPORT_RZAT | ATA_SUPPORT_DRAT; 855 buf[105] = 1; 856 buf[169] = ATA_SUPPORT_DSM_TRIM; 857 } 858 buf[106] = 0x4000; 859 buf[209] = 0x4000; 860 if (psectsz > sectsz) { 861 buf[106] |= 0x2000; 862 buf[106] |= ffsl(psectsz / sectsz) - 1; 863 buf[209] |= (psectoff / sectsz); 864 } 865 if (sectsz > 512) { 866 buf[106] |= 0x1000; 867 buf[117] = sectsz / 2; 868 buf[118] = ((sectsz / 2) >> 16); 869 } 870 buf[222] = 0x1020; 871 ahci_write_fis_piosetup(p); 872 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf)); 873 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY); 874 } 875} 876 877static void 878handle_atapi_identify(struct ahci_port *p, int slot, uint8_t *cfis) 879{ 880 if (!p->atapi) { 881 ahci_write_fis_d2h(p, slot, cfis, 882 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 883 } else { 884 uint16_t buf[256]; 885 886 memset(buf, 0, sizeof(buf)); 887 buf[0] = (2 << 14 | 5 << 8 | 1 << 7 | 2 << 5); 888 /* TODO emulate different serial? */ 889 ata_string((uint8_t *)(buf+10), "123456", 20); 890 ata_string((uint8_t *)(buf+23), "001", 8); 891 ata_string((uint8_t *)(buf+27), "BHYVE SATA DVD ROM", 40); 892 buf[49] = (1 << 9 | 1 << 8); 893 buf[50] = (1 << 14 | 1); 894 buf[53] = (1 << 2 | 1 << 1); 895 buf[62] = 0x3f; 896 buf[63] = 7; 897 buf[64] = 3; 898 buf[65] = 100; 899 buf[66] = 100; 900 buf[67] = 100; 901 buf[68] = 100; 902 buf[76] = (1 << 2 | 1 << 1); 903 buf[78] = (1 << 5); 904 buf[80] = (0x1f << 4); 905 buf[82] = (1 << 4); 906 buf[83] = (1 << 14); 907 buf[84] = (1 << 14); 908 buf[85] = (1 << 4); 909 buf[87] = (1 << 14); 910 buf[88] = (1 << 14 | 0x7f); 911 ahci_write_fis_piosetup(p); 912 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf)); 913 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY); 914 } 915} 916 917static void 918atapi_inquiry(struct ahci_port *p, int slot, uint8_t *cfis) 919{ 920 uint8_t buf[36]; 921 uint8_t *acmd; 922 int len; 923 924 acmd = cfis + 0x40; 925 926 buf[0] = 0x05; 927 buf[1] = 0x80; 928 buf[2] = 0x00; 929 buf[3] = 0x21; 930 buf[4] = 31; 931 buf[5] = 0; 932 buf[6] = 0; 933 buf[7] = 0; 934 atapi_string(buf + 8, "BHYVE", 8); 935 atapi_string(buf + 16, "BHYVE DVD-ROM", 16); 936 atapi_string(buf + 32, "001", 4); 937 938 len = sizeof(buf); 939 if (len > acmd[4]) 940 len = acmd[4]; 941 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 942 write_prdt(p, slot, cfis, buf, len); 943 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 944} 945 946static void 947atapi_read_capacity(struct ahci_port *p, int slot, uint8_t *cfis) 948{ 949 uint8_t buf[8]; 950 uint64_t sectors; 951 952 sectors = blockif_size(p->bctx) / 2048; 953 be32enc(buf, sectors - 1); 954 be32enc(buf + 4, 2048); 955 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 956 write_prdt(p, slot, cfis, buf, sizeof(buf)); 957 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 958} 959 960static void 961atapi_read_toc(struct ahci_port *p, int slot, uint8_t *cfis) 962{ 963 uint8_t *acmd; 964 uint8_t format; 965 int len; 966 967 acmd = cfis + 0x40; 968 969 len = be16dec(acmd + 7); 970 format = acmd[9] >> 6; 971 switch (format) { 972 case 0: 973 { 974 int msf, size; 975 uint64_t sectors; 976 uint8_t start_track, buf[20], *bp; 977 978 msf = (acmd[1] >> 1) & 1; 979 start_track = acmd[6]; 980 if (start_track > 1 && start_track != 0xaa) { 981 uint32_t tfd; 982 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 983 p->asc = 0x24; 984 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 985 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 986 ahci_write_fis_d2h(p, slot, cfis, tfd); 987 return; 988 } 989 bp = buf + 2; 990 *bp++ = 1; 991 *bp++ = 1; 992 if (start_track <= 1) { 993 *bp++ = 0; 994 *bp++ = 0x14; 995 *bp++ = 1; 996 *bp++ = 0; 997 if (msf) { 998 *bp++ = 0; 999 lba_to_msf(bp, 0); 1000 bp += 3; 1001 } else { 1002 *bp++ = 0; 1003 *bp++ = 0; 1004 *bp++ = 0; 1005 *bp++ = 0; 1006 } 1007 } 1008 *bp++ = 0; 1009 *bp++ = 0x14; 1010 *bp++ = 0xaa; 1011 *bp++ = 0; 1012 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx); 1013 sectors >>= 2; 1014 if (msf) { 1015 *bp++ = 0; 1016 lba_to_msf(bp, sectors); 1017 bp += 3; 1018 } else { 1019 be32enc(bp, sectors); 1020 bp += 4; 1021 } 1022 size = bp - buf; 1023 be16enc(buf, size - 2); 1024 if (len > size) 1025 len = size; 1026 write_prdt(p, slot, cfis, buf, len); 1027 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1028 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1029 break; 1030 } 1031 case 1: 1032 { 1033 uint8_t buf[12]; 1034 1035 memset(buf, 0, sizeof(buf)); 1036 buf[1] = 0xa; 1037 buf[2] = 0x1; 1038 buf[3] = 0x1; 1039 if (len > sizeof(buf)) 1040 len = sizeof(buf); 1041 write_prdt(p, slot, cfis, buf, len); 1042 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1043 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1044 break; 1045 } 1046 case 2: 1047 { 1048 int msf, size; 1049 uint64_t sectors; 1050 uint8_t start_track, *bp, buf[50]; 1051 1052 msf = (acmd[1] >> 1) & 1; 1053 start_track = acmd[6]; 1054 bp = buf + 2; 1055 *bp++ = 1; 1056 *bp++ = 1; 1057 1058 *bp++ = 1; 1059 *bp++ = 0x14; 1060 *bp++ = 0; 1061 *bp++ = 0xa0; 1062 *bp++ = 0; 1063 *bp++ = 0; 1064 *bp++ = 0; 1065 *bp++ = 0; 1066 *bp++ = 1; 1067 *bp++ = 0; 1068 *bp++ = 0; 1069 1070 *bp++ = 1; 1071 *bp++ = 0x14; 1072 *bp++ = 0; 1073 *bp++ = 0xa1; 1074 *bp++ = 0; 1075 *bp++ = 0; 1076 *bp++ = 0; 1077 *bp++ = 0; 1078 *bp++ = 1; 1079 *bp++ = 0; 1080 *bp++ = 0; 1081 1082 *bp++ = 1; 1083 *bp++ = 0x14; 1084 *bp++ = 0; 1085 *bp++ = 0xa2; 1086 *bp++ = 0; 1087 *bp++ = 0; 1088 *bp++ = 0; 1089 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx); 1090 sectors >>= 2; 1091 if (msf) { 1092 *bp++ = 0; 1093 lba_to_msf(bp, sectors); 1094 bp += 3; 1095 } else { 1096 be32enc(bp, sectors); 1097 bp += 4; 1098 } 1099 1100 *bp++ = 1; 1101 *bp++ = 0x14; 1102 *bp++ = 0; 1103 *bp++ = 1; 1104 *bp++ = 0; 1105 *bp++ = 0; 1106 *bp++ = 0; 1107 if (msf) { 1108 *bp++ = 0; 1109 lba_to_msf(bp, 0); 1110 bp += 3; 1111 } else { 1112 *bp++ = 0; 1113 *bp++ = 0; 1114 *bp++ = 0; 1115 *bp++ = 0; 1116 } 1117 1118 size = bp - buf; 1119 be16enc(buf, size - 2); 1120 if (len > size) 1121 len = size; 1122 write_prdt(p, slot, cfis, buf, len); 1123 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1124 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1125 break; 1126 } 1127 default: 1128 { 1129 uint32_t tfd; 1130 1131 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1132 p->asc = 0x24; 1133 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1134 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1135 ahci_write_fis_d2h(p, slot, cfis, tfd); 1136 break; 1137 } 1138 } 1139} 1140 1141static void 1142atapi_read(struct ahci_port *p, int slot, uint8_t *cfis, 1143 uint32_t done, int seek) 1144{ 1145 struct ahci_ioreq *aior; 1146 struct ahci_cmd_hdr *hdr; 1147 struct ahci_prdt_entry *prdt; 1148 struct blockif_req *breq; 1149 struct pci_ahci_softc *sc; 1150 uint8_t *acmd; 1151 uint64_t lba; 1152 uint32_t len; 1153 int i, err, iovcnt; 1154 1155 sc = p->pr_sc; 1156 acmd = cfis + 0x40; 1157 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 1158 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 1159 1160 prdt += seek; 1161 lba = be32dec(acmd + 2); 1162 if (acmd[0] == READ_10) 1163 len = be16dec(acmd + 7); 1164 else 1165 len = be32dec(acmd + 6); 1166 if (len == 0) { 1167 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1168 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1169 } 1170 lba *= 2048; 1171 len *= 2048; 1172 1173 /* 1174 * Pull request off free list 1175 */ 1176 aior = STAILQ_FIRST(&p->iofhd); 1177 assert(aior != NULL); 1178 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist); 1179 aior->cfis = cfis; 1180 aior->slot = slot; 1181 aior->len = len; 1182 aior->done = done; 1183 breq = &aior->io_req; 1184 breq->br_offset = lba + done; 1185 iovcnt = hdr->prdtl - seek; 1186 if (iovcnt > BLOCKIF_IOV_MAX) { 1187 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX; 1188 iovcnt = BLOCKIF_IOV_MAX; 1189 } else 1190 aior->prdtl = 0; 1191 breq->br_iovcnt = iovcnt; 1192 1193 /* 1194 * Mark this command in-flight. 1195 */ 1196 p->pending |= 1 << slot; 1197 1198 /* 1199 * Stuff request onto busy list 1200 */ 1201 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist); 1202 1203 /* 1204 * Build up the iovec based on the prdt 1205 */ 1206 for (i = 0; i < iovcnt; i++) { 1207 uint32_t dbcsz; 1208 1209 dbcsz = (prdt->dbc & DBCMASK) + 1; 1210 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc), 1211 prdt->dba, dbcsz); 1212 breq->br_iov[i].iov_len = dbcsz; 1213 aior->done += dbcsz; 1214 prdt++; 1215 } 1216 err = blockif_read(p->bctx, breq); 1217 assert(err == 0); 1218} 1219 1220static void 1221atapi_request_sense(struct ahci_port *p, int slot, uint8_t *cfis) 1222{ 1223 uint8_t buf[64]; 1224 uint8_t *acmd; 1225 int len; 1226 1227 acmd = cfis + 0x40; 1228 len = acmd[4]; 1229 if (len > sizeof(buf)) 1230 len = sizeof(buf); 1231 memset(buf, 0, len); 1232 buf[0] = 0x70 | (1 << 7); 1233 buf[2] = p->sense_key; 1234 buf[7] = 10; 1235 buf[12] = p->asc; 1236 write_prdt(p, slot, cfis, buf, len); 1237 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1238 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1239} 1240 1241static void 1242atapi_start_stop_unit(struct ahci_port *p, int slot, uint8_t *cfis) 1243{ 1244 uint8_t *acmd = cfis + 0x40; 1245 uint32_t tfd; 1246 1247 switch (acmd[4] & 3) { 1248 case 0: 1249 case 1: 1250 case 3: 1251 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1252 tfd = ATA_S_READY | ATA_S_DSC; 1253 break; 1254 case 2: 1255 /* TODO eject media */ 1256 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1257 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1258 p->asc = 0x53; 1259 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1260 break; 1261 } 1262 ahci_write_fis_d2h(p, slot, cfis, tfd); 1263} 1264 1265static void 1266atapi_mode_sense(struct ahci_port *p, int slot, uint8_t *cfis) 1267{ 1268 uint8_t *acmd; 1269 uint32_t tfd; 1270 uint8_t pc, code; 1271 int len; 1272 1273 acmd = cfis + 0x40; 1274 len = be16dec(acmd + 7); 1275 pc = acmd[2] >> 6; 1276 code = acmd[2] & 0x3f; 1277 1278 switch (pc) { 1279 case 0: 1280 switch (code) { 1281 case MODEPAGE_RW_ERROR_RECOVERY: 1282 { 1283 uint8_t buf[16]; 1284 1285 if (len > sizeof(buf)) 1286 len = sizeof(buf); 1287 1288 memset(buf, 0, sizeof(buf)); 1289 be16enc(buf, 16 - 2); 1290 buf[2] = 0x70; 1291 buf[8] = 0x01; 1292 buf[9] = 16 - 10; 1293 buf[11] = 0x05; 1294 write_prdt(p, slot, cfis, buf, len); 1295 tfd = ATA_S_READY | ATA_S_DSC; 1296 break; 1297 } 1298 case MODEPAGE_CD_CAPABILITIES: 1299 { 1300 uint8_t buf[30]; 1301 1302 if (len > sizeof(buf)) 1303 len = sizeof(buf); 1304 1305 memset(buf, 0, sizeof(buf)); 1306 be16enc(buf, 30 - 2); 1307 buf[2] = 0x70; 1308 buf[8] = 0x2A; 1309 buf[9] = 30 - 10; 1310 buf[10] = 0x08; 1311 buf[12] = 0x71; 1312 be16enc(&buf[18], 2); 1313 be16enc(&buf[20], 512); 1314 write_prdt(p, slot, cfis, buf, len); 1315 tfd = ATA_S_READY | ATA_S_DSC; 1316 break; 1317 } 1318 default: 1319 goto error; 1320 break; 1321 } 1322 break; 1323 case 3: 1324 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1325 p->asc = 0x39; 1326 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1327 break; 1328error: 1329 case 1: 1330 case 2: 1331 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1332 p->asc = 0x24; 1333 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1334 break; 1335 } 1336 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1337 ahci_write_fis_d2h(p, slot, cfis, tfd); 1338} 1339 1340static void 1341atapi_get_event_status_notification(struct ahci_port *p, int slot, 1342 uint8_t *cfis) 1343{ 1344 uint8_t *acmd; 1345 uint32_t tfd; 1346 1347 acmd = cfis + 0x40; 1348 1349 /* we don't support asynchronous operation */ 1350 if (!(acmd[1] & 1)) { 1351 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1352 p->asc = 0x24; 1353 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1354 } else { 1355 uint8_t buf[8]; 1356 int len; 1357 1358 len = be16dec(acmd + 7); 1359 if (len > sizeof(buf)) 1360 len = sizeof(buf); 1361 1362 memset(buf, 0, sizeof(buf)); 1363 be16enc(buf, 8 - 2); 1364 buf[2] = 0x04; 1365 buf[3] = 0x10; 1366 buf[5] = 0x02; 1367 write_prdt(p, slot, cfis, buf, len); 1368 tfd = ATA_S_READY | ATA_S_DSC; 1369 } 1370 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1371 ahci_write_fis_d2h(p, slot, cfis, tfd); 1372} 1373 1374static void 1375handle_packet_cmd(struct ahci_port *p, int slot, uint8_t *cfis) 1376{ 1377 uint8_t *acmd; 1378 1379 acmd = cfis + 0x40; 1380 1381#ifdef AHCI_DEBUG 1382 { 1383 int i; 1384 DPRINTF("ACMD:"); 1385 for (i = 0; i < 16; i++) 1386 DPRINTF("%02x ", acmd[i]); 1387 DPRINTF("\n"); 1388 } 1389#endif 1390 1391 switch (acmd[0]) { 1392 case TEST_UNIT_READY: 1393 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1394 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1395 break; 1396 case INQUIRY: 1397 atapi_inquiry(p, slot, cfis); 1398 break; 1399 case READ_CAPACITY: 1400 atapi_read_capacity(p, slot, cfis); 1401 break; 1402 case PREVENT_ALLOW: 1403 /* TODO */ 1404 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1405 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1406 break; 1407 case READ_TOC: 1408 atapi_read_toc(p, slot, cfis); 1409 break; 1410 case READ_10: 1411 case READ_12: 1412 atapi_read(p, slot, cfis, 0, 0); 1413 break; 1414 case REQUEST_SENSE: 1415 atapi_request_sense(p, slot, cfis); 1416 break; 1417 case START_STOP_UNIT: 1418 atapi_start_stop_unit(p, slot, cfis); 1419 break; 1420 case MODE_SENSE_10: 1421 atapi_mode_sense(p, slot, cfis); 1422 break; 1423 case GET_EVENT_STATUS_NOTIFICATION: 1424 atapi_get_event_status_notification(p, slot, cfis); 1425 break; 1426 default: 1427 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1428 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1429 p->asc = 0x20; 1430 ahci_write_fis_d2h(p, slot, cfis, (p->sense_key << 12) | 1431 ATA_S_READY | ATA_S_ERROR); 1432 break; 1433 } 1434} 1435 1436static void 1437ahci_handle_cmd(struct ahci_port *p, int slot, uint8_t *cfis) 1438{ 1439 1440 switch (cfis[2]) { 1441 case ATA_ATA_IDENTIFY: 1442 handle_identify(p, slot, cfis); 1443 break; 1444 case ATA_SETFEATURES: 1445 { 1446 switch (cfis[3]) { 1447 case ATA_SF_ENAB_SATA_SF: 1448 switch (cfis[12]) { 1449 case ATA_SATA_SF_AN: 1450 p->tfd = ATA_S_DSC | ATA_S_READY; 1451 break; 1452 default: 1453 p->tfd = ATA_S_ERROR | ATA_S_READY; 1454 p->tfd |= (ATA_ERROR_ABORT << 8); 1455 break; 1456 } 1457 break; 1458 case ATA_SF_ENAB_WCACHE: 1459 case ATA_SF_DIS_WCACHE: 1460 case ATA_SF_ENAB_RCACHE: 1461 case ATA_SF_DIS_RCACHE: 1462 p->tfd = ATA_S_DSC | ATA_S_READY; 1463 break; 1464 case ATA_SF_SETXFER: 1465 { 1466 switch (cfis[12] & 0xf8) { 1467 case ATA_PIO: 1468 case ATA_PIO0: 1469 break; 1470 case ATA_WDMA0: 1471 case ATA_UDMA0: 1472 p->xfermode = (cfis[12] & 0x7); 1473 break; 1474 } 1475 p->tfd = ATA_S_DSC | ATA_S_READY; 1476 break; 1477 } 1478 default: 1479 p->tfd = ATA_S_ERROR | ATA_S_READY; 1480 p->tfd |= (ATA_ERROR_ABORT << 8); 1481 break; 1482 } 1483 ahci_write_fis_d2h(p, slot, cfis, p->tfd); 1484 break; 1485 } 1486 case ATA_SET_MULTI: 1487 if (cfis[12] != 0 && 1488 (cfis[12] > 128 || (cfis[12] & (cfis[12] - 1)))) { 1489 p->tfd = ATA_S_ERROR | ATA_S_READY; 1490 p->tfd |= (ATA_ERROR_ABORT << 8); 1491 } else { 1492 p->mult_sectors = cfis[12]; 1493 p->tfd = ATA_S_DSC | ATA_S_READY; 1494 } 1495 ahci_write_fis_d2h(p, slot, cfis, p->tfd); 1496 break; 1497 case ATA_READ: 1498 case ATA_WRITE: 1499 case ATA_READ48: 1500 case ATA_WRITE48: 1501 case ATA_READ_MUL: 1502 case ATA_WRITE_MUL: 1503 case ATA_READ_MUL48: 1504 case ATA_WRITE_MUL48: 1505 case ATA_READ_DMA: 1506 case ATA_WRITE_DMA: 1507 case ATA_READ_DMA48: 1508 case ATA_WRITE_DMA48: 1509 case ATA_READ_FPDMA_QUEUED: 1510 case ATA_WRITE_FPDMA_QUEUED: 1511 ahci_handle_dma(p, slot, cfis, 0, 0); 1512 break; 1513 case ATA_FLUSHCACHE: 1514 case ATA_FLUSHCACHE48: 1515 ahci_handle_flush(p, slot, cfis); 1516 break; 1517 case ATA_DATA_SET_MANAGEMENT: 1518 if (cfis[11] == 0 && cfis[3] == ATA_DSM_TRIM && 1519 cfis[13] == 0 && cfis[12] == 1) { 1520 ahci_handle_dsm_trim(p, slot, cfis, 0); 1521 break; 1522 } 1523 ahci_write_fis_d2h(p, slot, cfis, 1524 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 1525 break; 1526 case ATA_STANDBY_CMD: 1527 break; 1528 case ATA_NOP: 1529 case ATA_STANDBY_IMMEDIATE: 1530 case ATA_IDLE_IMMEDIATE: 1531 case ATA_SLEEP: 1532 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1533 break; 1534 case ATA_ATAPI_IDENTIFY: 1535 handle_atapi_identify(p, slot, cfis); 1536 break; 1537 case ATA_PACKET_CMD: 1538 if (!p->atapi) { 1539 ahci_write_fis_d2h(p, slot, cfis, 1540 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 1541 } else 1542 handle_packet_cmd(p, slot, cfis); 1543 break; 1544 default: 1545 WPRINTF("Unsupported cmd:%02x\n", cfis[2]); 1546 ahci_write_fis_d2h(p, slot, cfis, 1547 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 1548 break; 1549 } 1550} 1551 1552static void 1553ahci_handle_slot(struct ahci_port *p, int slot) 1554{ 1555 struct ahci_cmd_hdr *hdr; 1556 struct ahci_prdt_entry *prdt; 1557 struct pci_ahci_softc *sc; 1558 uint8_t *cfis; 1559 int cfl; 1560 1561 sc = p->pr_sc; 1562 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 1563 cfl = (hdr->flags & 0x1f) * 4; 1564 cfis = paddr_guest2host(ahci_ctx(sc), hdr->ctba, 1565 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry)); 1566 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 1567 1568#ifdef AHCI_DEBUG 1569 DPRINTF("\ncfis:"); 1570 for (i = 0; i < cfl; i++) { 1571 if (i % 10 == 0) 1572 DPRINTF("\n"); 1573 DPRINTF("%02x ", cfis[i]); 1574 } 1575 DPRINTF("\n"); 1576 1577 for (i = 0; i < hdr->prdtl; i++) { 1578 DPRINTF("%d@%08"PRIx64"\n", prdt->dbc & 0x3fffff, prdt->dba); 1579 prdt++; 1580 } 1581#endif 1582 1583 if (cfis[0] != FIS_TYPE_REGH2D) { 1584 WPRINTF("Not a H2D FIS:%02x\n", cfis[0]); 1585 return; 1586 } 1587 1588 if (cfis[1] & 0x80) { 1589 ahci_handle_cmd(p, slot, cfis); 1590 } else { 1591 if (cfis[15] & (1 << 2)) 1592 p->reset = 1; 1593 else if (p->reset) { 1594 p->reset = 0; 1595 ahci_port_reset(p); 1596 } 1597 p->ci &= ~(1 << slot); 1598 } 1599} 1600 1601static void 1602ahci_handle_port(struct ahci_port *p) 1603{ 1604 int i; 1605 1606 if (!(p->cmd & AHCI_P_CMD_ST)) 1607 return; 1608 1609 /* 1610 * Search for any new commands to issue ignoring those that 1611 * are already in-flight. 1612 */ 1613 for (i = 0; (i < 32) && p->ci; i++) { 1614 if ((p->ci & (1 << i)) && !(p->pending & (1 << i))) { 1615 p->cmd &= ~AHCI_P_CMD_CCS_MASK; 1616 p->cmd |= i << AHCI_P_CMD_CCS_SHIFT; 1617 ahci_handle_slot(p, i); 1618 } 1619 } 1620} 1621 1622/* 1623 * blockif callback routine - this runs in the context of the blockif 1624 * i/o thread, so the mutex needs to be acquired. 1625 */ 1626static void 1627ata_ioreq_cb(struct blockif_req *br, int err) 1628{ 1629 struct ahci_cmd_hdr *hdr; 1630 struct ahci_ioreq *aior; 1631 struct ahci_port *p; 1632 struct pci_ahci_softc *sc; 1633 uint32_t tfd; 1634 uint8_t *cfis; 1635 int pending, slot, ncq, dsm; 1636 1637 DPRINTF("%s %d\n", __func__, err); 1638 1639 ncq = dsm = 0; 1640 aior = br->br_param; 1641 p = aior->io_pr; 1642 cfis = aior->cfis; 1643 slot = aior->slot; 1644 pending = aior->prdtl; 1645 sc = p->pr_sc; 1646 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 1647 1648 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED || 1649 cfis[2] == ATA_READ_FPDMA_QUEUED) 1650 ncq = 1; 1651 if (cfis[2] == ATA_DATA_SET_MANAGEMENT) 1652 dsm = 1; 1653 1654 pthread_mutex_lock(&sc->mtx); 1655 1656 /* 1657 * Delete the blockif request from the busy list 1658 */ 1659 TAILQ_REMOVE(&p->iobhd, aior, io_blist); 1660 1661 /* 1662 * Move the blockif request back to the free list 1663 */ 1664 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist); 1665 1666 if (dsm) { 1667 if (aior->done != aior->len && !err) { 1668 ahci_handle_dsm_trim(p, slot, cfis, aior->done); 1669 goto out; 1670 } 1671 } else { 1672 if (pending && !err) { 1673 ahci_handle_dma(p, slot, cfis, aior->done, 1674 hdr->prdtl - pending); 1675 goto out; 1676 } 1677 } 1678 1679 if (!err && aior->done == aior->len) { 1680 tfd = ATA_S_READY | ATA_S_DSC; 1681 if (ncq) 1682 hdr->prdbc = 0; 1683 else 1684 hdr->prdbc = aior->len; 1685 } else { 1686 tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR; 1687 hdr->prdbc = 0; 1688 if (ncq) 1689 p->serr |= (1 << slot); 1690 } 1691 1692 if (ncq) { 1693 p->sact &= ~(1 << slot); 1694 ahci_write_fis_sdb(p, slot, tfd); 1695 } else 1696 ahci_write_fis_d2h(p, slot, cfis, tfd); 1697 1698 /* 1699 * This command is now complete. 1700 */ 1701 p->pending &= ~(1 << slot); 1702 1703 ahci_check_stopped(p); 1704out: 1705 pthread_mutex_unlock(&sc->mtx); 1706 DPRINTF("%s exit\n", __func__); 1707} 1708 1709static void 1710atapi_ioreq_cb(struct blockif_req *br, int err) 1711{ 1712 struct ahci_cmd_hdr *hdr; 1713 struct ahci_ioreq *aior; 1714 struct ahci_port *p; 1715 struct pci_ahci_softc *sc; 1716 uint8_t *cfis; 1717 uint32_t tfd; 1718 int pending, slot; 1719 1720 DPRINTF("%s %d\n", __func__, err); 1721 1722 aior = br->br_param; 1723 p = aior->io_pr; 1724 cfis = aior->cfis; 1725 slot = aior->slot; 1726 pending = aior->prdtl; 1727 sc = p->pr_sc; 1728 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + aior->slot * AHCI_CL_SIZE); 1729 1730 pthread_mutex_lock(&sc->mtx); 1731 1732 /* 1733 * Delete the blockif request from the busy list 1734 */ 1735 TAILQ_REMOVE(&p->iobhd, aior, io_blist); 1736 1737 /* 1738 * Move the blockif request back to the free list 1739 */ 1740 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist); 1741 1742 if (pending && !err) { 1743 atapi_read(p, slot, cfis, aior->done, hdr->prdtl - pending); 1744 goto out; 1745 } 1746 1747 if (!err && aior->done == aior->len) { 1748 tfd = ATA_S_READY | ATA_S_DSC; 1749 hdr->prdbc = aior->len; 1750 } else { 1751 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1752 p->asc = 0x21; 1753 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1754 hdr->prdbc = 0; 1755 } 1756 1757 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1758 ahci_write_fis_d2h(p, slot, cfis, tfd); 1759 1760 /* 1761 * This command is now complete. 1762 */ 1763 p->pending &= ~(1 << slot); 1764 1765 ahci_check_stopped(p); 1766out: 1767 pthread_mutex_unlock(&sc->mtx); 1768 DPRINTF("%s exit\n", __func__); 1769} 1770 1771static void 1772pci_ahci_ioreq_init(struct ahci_port *pr) 1773{ 1774 struct ahci_ioreq *vr; 1775 int i; 1776 1777 pr->ioqsz = blockif_queuesz(pr->bctx); 1778 pr->ioreq = calloc(pr->ioqsz, sizeof(struct ahci_ioreq)); 1779 STAILQ_INIT(&pr->iofhd); 1780 1781 /* 1782 * Add all i/o request entries to the free queue 1783 */ 1784 for (i = 0; i < pr->ioqsz; i++) { 1785 vr = &pr->ioreq[i]; 1786 vr->io_pr = pr; 1787 if (!pr->atapi) 1788 vr->io_req.br_callback = ata_ioreq_cb; 1789 else 1790 vr->io_req.br_callback = atapi_ioreq_cb; 1791 vr->io_req.br_param = vr; 1792 STAILQ_INSERT_TAIL(&pr->iofhd, vr, io_flist); 1793 } 1794 1795 TAILQ_INIT(&pr->iobhd); 1796} 1797 1798static void 1799pci_ahci_port_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value) 1800{ 1801 int port = (offset - AHCI_OFFSET) / AHCI_STEP; 1802 offset = (offset - AHCI_OFFSET) % AHCI_STEP; 1803 struct ahci_port *p = &sc->port[port]; 1804 1805 DPRINTF("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"\n", 1806 port, offset, value); 1807 1808 switch (offset) { 1809 case AHCI_P_CLB: 1810 p->clb = value; 1811 break; 1812 case AHCI_P_CLBU: 1813 p->clbu = value; 1814 break; 1815 case AHCI_P_FB: 1816 p->fb = value; 1817 break; 1818 case AHCI_P_FBU: 1819 p->fbu = value; 1820 break; 1821 case AHCI_P_IS: 1822 p->is &= ~value; 1823 break; 1824 case AHCI_P_IE: 1825 p->ie = value & 0xFDC000FF; 1826 ahci_generate_intr(sc); 1827 break; 1828 case AHCI_P_CMD: 1829 { 1830 p->cmd = value; 1831 1832 if (!(value & AHCI_P_CMD_ST)) { 1833 ahci_port_stop(p); 1834 } else { 1835 uint64_t clb; 1836 1837 p->cmd |= AHCI_P_CMD_CR; 1838 clb = (uint64_t)p->clbu << 32 | p->clb; 1839 p->cmd_lst = paddr_guest2host(ahci_ctx(sc), clb, 1840 AHCI_CL_SIZE * AHCI_MAX_SLOTS); 1841 } 1842 1843 if (value & AHCI_P_CMD_FRE) { 1844 uint64_t fb; 1845 1846 p->cmd |= AHCI_P_CMD_FR; 1847 fb = (uint64_t)p->fbu << 32 | p->fb; 1848 /* we don't support FBSCP, so rfis size is 256Bytes */ 1849 p->rfis = paddr_guest2host(ahci_ctx(sc), fb, 256); 1850 } else { 1851 p->cmd &= ~AHCI_P_CMD_FR; 1852 } 1853 1854 if (value & AHCI_P_CMD_CLO) { 1855 p->tfd = 0; 1856 p->cmd &= ~AHCI_P_CMD_CLO; 1857 } 1858 1859 ahci_handle_port(p); 1860 break; 1861 } 1862 case AHCI_P_TFD: 1863 case AHCI_P_SIG: 1864 case AHCI_P_SSTS: 1865 WPRINTF("pci_ahci_port: read only registers 0x%"PRIx64"\n", offset); 1866 break; 1867 case AHCI_P_SCTL: 1868 p->sctl = value; 1869 if (!(p->cmd & AHCI_P_CMD_ST)) { 1870 if (value & ATA_SC_DET_RESET) 1871 ahci_port_reset(p); 1872 } 1873 break; 1874 case AHCI_P_SERR: 1875 p->serr &= ~value; 1876 break; 1877 case AHCI_P_SACT: 1878 p->sact |= value; 1879 break; 1880 case AHCI_P_CI: 1881 p->ci |= value; 1882 ahci_handle_port(p); 1883 break; 1884 case AHCI_P_SNTF: 1885 case AHCI_P_FBS: 1886 default: 1887 break; 1888 } 1889} 1890 1891static void 1892pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value) 1893{ 1894 DPRINTF("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"\n", 1895 offset, value); 1896 1897 switch (offset) { 1898 case AHCI_CAP: 1899 case AHCI_PI: 1900 case AHCI_VS: 1901 case AHCI_CAP2: 1902 DPRINTF("pci_ahci_host: read only registers 0x%"PRIx64"\n", offset); 1903 break; 1904 case AHCI_GHC: 1905 if (value & AHCI_GHC_HR) 1906 ahci_reset(sc); 1907 else if (value & AHCI_GHC_IE) { 1908 sc->ghc |= AHCI_GHC_IE; 1909 ahci_generate_intr(sc); 1910 } 1911 break; 1912 case AHCI_IS: 1913 sc->is &= ~value; 1914 ahci_generate_intr(sc); 1915 break; 1916 default: 1917 break; 1918 } 1919} 1920 1921static void 1922pci_ahci_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, 1923 int baridx, uint64_t offset, int size, uint64_t value) 1924{ 1925 struct pci_ahci_softc *sc = pi->pi_arg; 1926 1927 assert(baridx == 5); 1928 assert(size == 4); 1929 1930 pthread_mutex_lock(&sc->mtx); 1931 1932 if (offset < AHCI_OFFSET) 1933 pci_ahci_host_write(sc, offset, value); 1934 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP) 1935 pci_ahci_port_write(sc, offset, value); 1936 else 1937 WPRINTF("pci_ahci: unknown i/o write offset 0x%"PRIx64"\n", offset); 1938 1939 pthread_mutex_unlock(&sc->mtx); 1940} 1941 1942static uint64_t 1943pci_ahci_host_read(struct pci_ahci_softc *sc, uint64_t offset) 1944{ 1945 uint32_t value; 1946 1947 switch (offset) { 1948 case AHCI_CAP: 1949 case AHCI_GHC: 1950 case AHCI_IS: 1951 case AHCI_PI: 1952 case AHCI_VS: 1953 case AHCI_CCCC: 1954 case AHCI_CCCP: 1955 case AHCI_EM_LOC: 1956 case AHCI_EM_CTL: 1957 case AHCI_CAP2: 1958 { 1959 uint32_t *p = &sc->cap; 1960 p += (offset - AHCI_CAP) / sizeof(uint32_t); 1961 value = *p; 1962 break; 1963 } 1964 default: 1965 value = 0; 1966 break; 1967 } 1968 DPRINTF("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x\n", 1969 offset, value); 1970 1971 return (value); 1972} 1973 1974static uint64_t 1975pci_ahci_port_read(struct pci_ahci_softc *sc, uint64_t offset) 1976{ 1977 uint32_t value; 1978 int port = (offset - AHCI_OFFSET) / AHCI_STEP; 1979 offset = (offset - AHCI_OFFSET) % AHCI_STEP; 1980 1981 switch (offset) { 1982 case AHCI_P_CLB: 1983 case AHCI_P_CLBU: 1984 case AHCI_P_FB: 1985 case AHCI_P_FBU: 1986 case AHCI_P_IS: 1987 case AHCI_P_IE: 1988 case AHCI_P_CMD: 1989 case AHCI_P_TFD: 1990 case AHCI_P_SIG: 1991 case AHCI_P_SSTS: 1992 case AHCI_P_SCTL: 1993 case AHCI_P_SERR: 1994 case AHCI_P_SACT: 1995 case AHCI_P_CI: 1996 case AHCI_P_SNTF: 1997 case AHCI_P_FBS: 1998 { 1999 uint32_t *p= &sc->port[port].clb; 2000 p += (offset - AHCI_P_CLB) / sizeof(uint32_t); 2001 value = *p; 2002 break; 2003 } 2004 default: 2005 value = 0; 2006 break; 2007 } 2008 2009 DPRINTF("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x\n", 2010 port, offset, value); 2011 2012 return value; 2013} 2014 2015static uint64_t 2016pci_ahci_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 2017 uint64_t offset, int size) 2018{ 2019 struct pci_ahci_softc *sc = pi->pi_arg; 2020 uint32_t value; 2021 2022 assert(baridx == 5); 2023 assert(size == 4); 2024 2025 pthread_mutex_lock(&sc->mtx); 2026 2027 if (offset < AHCI_OFFSET) 2028 value = pci_ahci_host_read(sc, offset); 2029 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP) 2030 value = pci_ahci_port_read(sc, offset); 2031 else { 2032 value = 0; 2033 WPRINTF("pci_ahci: unknown i/o read offset 0x%"PRIx64"\n", offset); 2034 } 2035 2036 pthread_mutex_unlock(&sc->mtx); 2037 2038 return (value); 2039} 2040 2041static int 2042pci_ahci_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts, int atapi) 2043{ 2044 char bident[sizeof("XX:X:X")]; 2045 struct blockif_ctxt *bctxt; 2046 struct pci_ahci_softc *sc; 2047 int ret, slots; 2048 2049 ret = 0; 2050 2051 if (opts == NULL) { 2052 fprintf(stderr, "pci_ahci: backing device required\n"); 2053 return (1); 2054 } 2055 2056#ifdef AHCI_DEBUG 2057 dbg = fopen("/tmp/log", "w+"); 2058#endif 2059 2060 sc = calloc(1, sizeof(struct pci_ahci_softc)); 2061 pi->pi_arg = sc; 2062 sc->asc_pi = pi; 2063 sc->ports = MAX_PORTS; 2064 2065 /* 2066 * Only use port 0 for a backing device. All other ports will be 2067 * marked as unused 2068 */ 2069 sc->port[0].atapi = atapi; 2070 2071 /* 2072 * Attempt to open the backing image. Use the PCI 2073 * slot/func for the identifier string. 2074 */ 2075 snprintf(bident, sizeof(bident), "%d:%d", pi->pi_slot, pi->pi_func); 2076 bctxt = blockif_open(opts, bident); 2077 if (bctxt == NULL) { 2078 ret = 1; 2079 goto open_fail; 2080 } 2081 sc->port[0].bctx = bctxt; 2082 sc->port[0].pr_sc = sc; 2083 2084 /* 2085 * Allocate blockif request structures and add them 2086 * to the free list 2087 */ 2088 pci_ahci_ioreq_init(&sc->port[0]); 2089 2090 pthread_mutex_init(&sc->mtx, NULL); 2091 2092 /* Intel ICH8 AHCI */ 2093 slots = sc->port[0].ioqsz; 2094 if (slots > 32) 2095 slots = 32; 2096 --slots; 2097 sc->cap = AHCI_CAP_64BIT | AHCI_CAP_SNCQ | AHCI_CAP_SSNTF | 2098 AHCI_CAP_SMPS | AHCI_CAP_SSS | AHCI_CAP_SALP | 2099 AHCI_CAP_SAL | AHCI_CAP_SCLO | (0x3 << AHCI_CAP_ISS_SHIFT)| 2100 AHCI_CAP_PMD | AHCI_CAP_SSC | AHCI_CAP_PSC | 2101 (slots << AHCI_CAP_NCS_SHIFT) | AHCI_CAP_SXS | (sc->ports - 1); 2102 2103 /* Only port 0 implemented */ 2104 sc->pi = 1; 2105 sc->vs = 0x10300; 2106 sc->cap2 = AHCI_CAP2_APST; 2107 ahci_reset(sc); 2108 2109 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x2821); 2110 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086); 2111 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_STORAGE); 2112 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_STORAGE_SATA); 2113 pci_set_cfgdata8(pi, PCIR_PROGIF, PCIP_STORAGE_SATA_AHCI_1_0); 2114 pci_emul_add_msicap(pi, 1); 2115 pci_emul_alloc_bar(pi, 5, PCIBAR_MEM32, 2116 AHCI_OFFSET + sc->ports * AHCI_STEP); 2117 2118 pci_lintr_request(pi); 2119 2120open_fail: 2121 if (ret) { 2122 blockif_close(sc->port[0].bctx); 2123 free(sc); 2124 } 2125 2126 return (ret); 2127} 2128 2129static int 2130pci_ahci_hd_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts) 2131{ 2132 2133 return (pci_ahci_init(ctx, pi, opts, 0)); 2134} 2135 2136static int 2137pci_ahci_atapi_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts) 2138{ 2139 2140 return (pci_ahci_init(ctx, pi, opts, 1)); 2141} 2142 2143/* 2144 * Use separate emulation names to distinguish drive and atapi devices 2145 */ 2146struct pci_devemu pci_de_ahci_hd = { 2147 .pe_emu = "ahci-hd", 2148 .pe_init = pci_ahci_hd_init, 2149 .pe_barwrite = pci_ahci_write, 2150 .pe_barread = pci_ahci_read 2151}; 2152PCI_EMUL_SET(pci_de_ahci_hd); 2153 2154struct pci_devemu pci_de_ahci_cd = { 2155 .pe_emu = "ahci-cd", 2156 .pe_init = pci_ahci_atapi_init, 2157 .pe_barwrite = pci_ahci_write, 2158 .pe_barread = pci_ahci_read 2159}; 2160PCI_EMUL_SET(pci_de_ahci_cd); 2161