pci_ahci.c revision 280731
1/*- 2 * Copyright (c) 2013 Zhixiang Yu <zcore@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: stable/10/usr.sbin/bhyve/pci_ahci.c 280731 2015-03-27 08:41:49Z mav $ 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: stable/10/usr.sbin/bhyve/pci_ahci.c 280731 2015-03-27 08:41:49Z mav $"); 31 32#include <sys/param.h> 33#include <sys/linker_set.h> 34#include <sys/stat.h> 35#include <sys/uio.h> 36#include <sys/ioctl.h> 37#include <sys/disk.h> 38#include <sys/ata.h> 39#include <sys/endian.h> 40 41#include <errno.h> 42#include <fcntl.h> 43#include <stdio.h> 44#include <stdlib.h> 45#include <stdint.h> 46#include <string.h> 47#include <strings.h> 48#include <unistd.h> 49#include <assert.h> 50#include <pthread.h> 51#include <pthread_np.h> 52#include <inttypes.h> 53 54#include "bhyverun.h" 55#include "pci_emul.h" 56#include "ahci.h" 57#include "block_if.h" 58 59#define MAX_PORTS 6 /* Intel ICH8 AHCI supports 6 ports */ 60 61#define PxSIG_ATA 0x00000101 /* ATA drive */ 62#define PxSIG_ATAPI 0xeb140101 /* ATAPI drive */ 63 64enum sata_fis_type { 65 FIS_TYPE_REGH2D = 0x27, /* Register FIS - host to device */ 66 FIS_TYPE_REGD2H = 0x34, /* Register FIS - device to host */ 67 FIS_TYPE_DMAACT = 0x39, /* DMA activate FIS - device to host */ 68 FIS_TYPE_DMASETUP = 0x41, /* DMA setup FIS - bidirectional */ 69 FIS_TYPE_DATA = 0x46, /* Data FIS - bidirectional */ 70 FIS_TYPE_BIST = 0x58, /* BIST activate FIS - bidirectional */ 71 FIS_TYPE_PIOSETUP = 0x5F, /* PIO setup FIS - device to host */ 72 FIS_TYPE_SETDEVBITS = 0xA1, /* Set dev bits FIS - device to host */ 73}; 74 75/* 76 * SCSI opcodes 77 */ 78#define TEST_UNIT_READY 0x00 79#define REQUEST_SENSE 0x03 80#define INQUIRY 0x12 81#define START_STOP_UNIT 0x1B 82#define PREVENT_ALLOW 0x1E 83#define READ_CAPACITY 0x25 84#define READ_10 0x28 85#define POSITION_TO_ELEMENT 0x2B 86#define READ_TOC 0x43 87#define GET_EVENT_STATUS_NOTIFICATION 0x4A 88#define MODE_SENSE_10 0x5A 89#define READ_12 0xA8 90#define READ_CD 0xBE 91 92/* 93 * SCSI mode page codes 94 */ 95#define MODEPAGE_RW_ERROR_RECOVERY 0x01 96#define MODEPAGE_CD_CAPABILITIES 0x2A 97 98/* 99 * ATA commands 100 */ 101#define ATA_SF_ENAB_SATA_SF 0x10 102#define ATA_SATA_SF_AN 0x05 103#define ATA_SF_DIS_SATA_SF 0x90 104 105/* 106 * Debug printf 107 */ 108#ifdef AHCI_DEBUG 109static FILE *dbg; 110#define DPRINTF(format, arg...) do{fprintf(dbg, format, ##arg);fflush(dbg);}while(0) 111#else 112#define DPRINTF(format, arg...) 113#endif 114#define WPRINTF(format, arg...) printf(format, ##arg) 115 116struct ahci_ioreq { 117 struct blockif_req io_req; 118 struct ahci_port *io_pr; 119 STAILQ_ENTRY(ahci_ioreq) io_flist; 120 TAILQ_ENTRY(ahci_ioreq) io_blist; 121 uint8_t *cfis; 122 uint32_t len; 123 uint32_t done; 124 int slot; 125 int prdtl; 126}; 127 128struct ahci_port { 129 struct blockif_ctxt *bctx; 130 struct pci_ahci_softc *pr_sc; 131 uint8_t *cmd_lst; 132 uint8_t *rfis; 133 int atapi; 134 int reset; 135 int mult_sectors; 136 uint8_t xfermode; 137 uint8_t sense_key; 138 uint8_t asc; 139 uint32_t pending; 140 141 uint32_t clb; 142 uint32_t clbu; 143 uint32_t fb; 144 uint32_t fbu; 145 uint32_t is; 146 uint32_t ie; 147 uint32_t cmd; 148 uint32_t unused0; 149 uint32_t tfd; 150 uint32_t sig; 151 uint32_t ssts; 152 uint32_t sctl; 153 uint32_t serr; 154 uint32_t sact; 155 uint32_t ci; 156 uint32_t sntf; 157 uint32_t fbs; 158 159 /* 160 * i/o request info 161 */ 162 struct ahci_ioreq *ioreq; 163 int ioqsz; 164 STAILQ_HEAD(ahci_fhead, ahci_ioreq) iofhd; 165 TAILQ_HEAD(ahci_bhead, ahci_ioreq) iobhd; 166}; 167 168struct ahci_cmd_hdr { 169 uint16_t flags; 170 uint16_t prdtl; 171 uint32_t prdbc; 172 uint64_t ctba; 173 uint32_t reserved[4]; 174}; 175 176struct ahci_prdt_entry { 177 uint64_t dba; 178 uint32_t reserved; 179#define DBCMASK 0x3fffff 180 uint32_t dbc; 181}; 182 183struct pci_ahci_softc { 184 struct pci_devinst *asc_pi; 185 pthread_mutex_t mtx; 186 int ports; 187 uint32_t cap; 188 uint32_t ghc; 189 uint32_t is; 190 uint32_t pi; 191 uint32_t vs; 192 uint32_t ccc_ctl; 193 uint32_t ccc_pts; 194 uint32_t em_loc; 195 uint32_t em_ctl; 196 uint32_t cap2; 197 uint32_t bohc; 198 uint32_t lintr; 199 struct ahci_port port[MAX_PORTS]; 200}; 201#define ahci_ctx(sc) ((sc)->asc_pi->pi_vmctx) 202 203static inline void lba_to_msf(uint8_t *buf, int lba) 204{ 205 lba += 150; 206 buf[0] = (lba / 75) / 60; 207 buf[1] = (lba / 75) % 60; 208 buf[2] = lba % 75; 209} 210 211/* 212 * generate HBA intr depending on whether or not ports within 213 * the controller have an interrupt pending. 214 */ 215static void 216ahci_generate_intr(struct pci_ahci_softc *sc) 217{ 218 struct pci_devinst *pi; 219 int i; 220 221 pi = sc->asc_pi; 222 223 for (i = 0; i < sc->ports; i++) { 224 struct ahci_port *pr; 225 pr = &sc->port[i]; 226 if (pr->is & pr->ie) 227 sc->is |= (1 << i); 228 } 229 230 DPRINTF("%s %x\n", __func__, sc->is); 231 232 if (sc->is && (sc->ghc & AHCI_GHC_IE)) { 233 if (pci_msi_enabled(pi)) { 234 /* 235 * Generate an MSI interrupt on every edge 236 */ 237 pci_generate_msi(pi, 0); 238 } else if (!sc->lintr) { 239 /* 240 * Only generate a pin-based interrupt if one wasn't 241 * in progress 242 */ 243 sc->lintr = 1; 244 pci_lintr_assert(pi); 245 } 246 } else if (sc->lintr) { 247 /* 248 * No interrupts: deassert pin-based signal if it had 249 * been asserted 250 */ 251 pci_lintr_deassert(pi); 252 sc->lintr = 0; 253 } 254} 255 256static void 257ahci_write_fis(struct ahci_port *p, enum sata_fis_type ft, uint8_t *fis) 258{ 259 int offset, len, irq; 260 261 if (p->rfis == NULL || !(p->cmd & AHCI_P_CMD_FRE)) 262 return; 263 264 switch (ft) { 265 case FIS_TYPE_REGD2H: 266 offset = 0x40; 267 len = 20; 268 irq = AHCI_P_IX_DHR; 269 break; 270 case FIS_TYPE_SETDEVBITS: 271 offset = 0x58; 272 len = 8; 273 irq = AHCI_P_IX_SDB; 274 break; 275 case FIS_TYPE_PIOSETUP: 276 offset = 0x20; 277 len = 20; 278 irq = 0; 279 break; 280 default: 281 WPRINTF("unsupported fis type %d\n", ft); 282 return; 283 } 284 memcpy(p->rfis + offset, fis, len); 285 if (irq) { 286 p->is |= irq; 287 ahci_generate_intr(p->pr_sc); 288 } 289} 290 291static void 292ahci_write_fis_piosetup(struct ahci_port *p) 293{ 294 uint8_t fis[20]; 295 296 memset(fis, 0, sizeof(fis)); 297 fis[0] = FIS_TYPE_PIOSETUP; 298 ahci_write_fis(p, FIS_TYPE_PIOSETUP, fis); 299} 300 301static void 302ahci_write_fis_sdb(struct ahci_port *p, int slot, uint32_t tfd) 303{ 304 uint8_t fis[8]; 305 uint8_t error; 306 307 error = (tfd >> 8) & 0xff; 308 memset(fis, 0, sizeof(fis)); 309 fis[0] = error; 310 fis[2] = tfd & 0x77; 311 *(uint32_t *)(fis + 4) = (1 << slot); 312 if (fis[2] & ATA_S_ERROR) 313 p->is |= AHCI_P_IX_TFE; 314 p->tfd = tfd; 315 ahci_write_fis(p, FIS_TYPE_SETDEVBITS, fis); 316} 317 318static void 319ahci_write_fis_d2h(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd) 320{ 321 uint8_t fis[20]; 322 uint8_t error; 323 324 error = (tfd >> 8) & 0xff; 325 memset(fis, 0, sizeof(fis)); 326 fis[0] = FIS_TYPE_REGD2H; 327 fis[1] = (1 << 6); 328 fis[2] = tfd & 0xff; 329 fis[3] = error; 330 fis[4] = cfis[4]; 331 fis[5] = cfis[5]; 332 fis[6] = cfis[6]; 333 fis[7] = cfis[7]; 334 fis[8] = cfis[8]; 335 fis[9] = cfis[9]; 336 fis[10] = cfis[10]; 337 fis[11] = cfis[11]; 338 fis[12] = cfis[12]; 339 fis[13] = cfis[13]; 340 if (fis[2] & ATA_S_ERROR) 341 p->is |= AHCI_P_IX_TFE; 342 else 343 p->ci &= ~(1 << slot); 344 p->tfd = tfd; 345 ahci_write_fis(p, FIS_TYPE_REGD2H, fis); 346} 347 348static void 349ahci_write_reset_fis_d2h(struct ahci_port *p) 350{ 351 uint8_t fis[20]; 352 353 memset(fis, 0, sizeof(fis)); 354 fis[0] = FIS_TYPE_REGD2H; 355 fis[3] = 1; 356 fis[4] = 1; 357 if (p->atapi) { 358 fis[5] = 0x14; 359 fis[6] = 0xeb; 360 } 361 fis[12] = 1; 362 ahci_write_fis(p, FIS_TYPE_REGD2H, fis); 363} 364 365static void 366ahci_check_stopped(struct ahci_port *p) 367{ 368 /* 369 * If we are no longer processing the command list and nothing 370 * is in-flight, clear the running bit, the current command 371 * slot, the command issue and active bits. 372 */ 373 if (!(p->cmd & AHCI_P_CMD_ST)) { 374 if (p->pending == 0) { 375 p->cmd &= ~(AHCI_P_CMD_CR | AHCI_P_CMD_CCS_MASK); 376 p->ci = 0; 377 p->sact = 0; 378 } 379 } 380} 381 382static void 383ahci_port_stop(struct ahci_port *p) 384{ 385 struct ahci_ioreq *aior; 386 uint8_t *cfis; 387 int slot; 388 int ncq; 389 int error; 390 391 assert(pthread_mutex_isowned_np(&p->pr_sc->mtx)); 392 393 TAILQ_FOREACH(aior, &p->iobhd, io_blist) { 394 /* 395 * Try to cancel the outstanding blockif request. 396 */ 397 error = blockif_cancel(p->bctx, &aior->io_req); 398 if (error != 0) 399 continue; 400 401 slot = aior->slot; 402 cfis = aior->cfis; 403 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED || 404 cfis[2] == ATA_READ_FPDMA_QUEUED) 405 ncq = 1; 406 407 if (ncq) 408 p->sact &= ~(1 << slot); 409 else 410 p->ci &= ~(1 << slot); 411 412 /* 413 * This command is now done. 414 */ 415 p->pending &= ~(1 << slot); 416 417 /* 418 * Delete the blockif request from the busy list 419 */ 420 TAILQ_REMOVE(&p->iobhd, aior, io_blist); 421 422 /* 423 * Move the blockif request back to the free list 424 */ 425 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist); 426 } 427 428 ahci_check_stopped(p); 429} 430 431static void 432ahci_port_reset(struct ahci_port *pr) 433{ 434 pr->sctl = 0; 435 pr->serr = 0; 436 pr->sact = 0; 437 pr->xfermode = ATA_UDMA6; 438 pr->mult_sectors = 128; 439 440 if (!pr->bctx) { 441 pr->ssts = ATA_SS_DET_NO_DEVICE; 442 pr->sig = 0xFFFFFFFF; 443 pr->tfd = 0x7F; 444 return; 445 } 446 pr->ssts = ATA_SS_DET_PHY_ONLINE | ATA_SS_SPD_GEN2 | 447 ATA_SS_IPM_ACTIVE; 448 pr->tfd = (1 << 8) | ATA_S_DSC | ATA_S_DMA; 449 if (!pr->atapi) { 450 pr->sig = PxSIG_ATA; 451 pr->tfd |= ATA_S_READY; 452 } else 453 pr->sig = PxSIG_ATAPI; 454 ahci_write_reset_fis_d2h(pr); 455} 456 457static void 458ahci_reset(struct pci_ahci_softc *sc) 459{ 460 int i; 461 462 sc->ghc = AHCI_GHC_AE; 463 sc->is = 0; 464 465 if (sc->lintr) { 466 pci_lintr_deassert(sc->asc_pi); 467 sc->lintr = 0; 468 } 469 470 for (i = 0; i < sc->ports; i++) { 471 sc->port[i].ie = 0; 472 sc->port[i].is = 0; 473 ahci_port_reset(&sc->port[i]); 474 } 475} 476 477static void 478ata_string(uint8_t *dest, const char *src, int len) 479{ 480 int i; 481 482 for (i = 0; i < len; i++) { 483 if (*src) 484 dest[i ^ 1] = *src++; 485 else 486 dest[i ^ 1] = ' '; 487 } 488} 489 490static void 491atapi_string(uint8_t *dest, const char *src, int len) 492{ 493 int i; 494 495 for (i = 0; i < len; i++) { 496 if (*src) 497 dest[i] = *src++; 498 else 499 dest[i] = ' '; 500 } 501} 502 503static void 504ahci_handle_dma(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done, 505 int seek) 506{ 507 struct ahci_ioreq *aior; 508 struct blockif_req *breq; 509 struct pci_ahci_softc *sc; 510 struct ahci_prdt_entry *prdt; 511 struct ahci_cmd_hdr *hdr; 512 uint64_t lba; 513 uint32_t len; 514 int i, err, iovcnt, ncq, readop; 515 516 sc = p->pr_sc; 517 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 518 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 519 ncq = 0; 520 readop = 1; 521 522 prdt += seek; 523 if (cfis[2] == ATA_WRITE_DMA || cfis[2] == ATA_WRITE_DMA48 || 524 cfis[2] == ATA_WRITE_FPDMA_QUEUED) 525 readop = 0; 526 527 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED || 528 cfis[2] == ATA_READ_FPDMA_QUEUED) { 529 lba = ((uint64_t)cfis[10] << 40) | 530 ((uint64_t)cfis[9] << 32) | 531 ((uint64_t)cfis[8] << 24) | 532 ((uint64_t)cfis[6] << 16) | 533 ((uint64_t)cfis[5] << 8) | 534 cfis[4]; 535 len = cfis[11] << 8 | cfis[3]; 536 if (!len) 537 len = 65536; 538 ncq = 1; 539 } else if (cfis[2] == ATA_READ_DMA48 || cfis[2] == ATA_WRITE_DMA48) { 540 lba = ((uint64_t)cfis[10] << 40) | 541 ((uint64_t)cfis[9] << 32) | 542 ((uint64_t)cfis[8] << 24) | 543 ((uint64_t)cfis[6] << 16) | 544 ((uint64_t)cfis[5] << 8) | 545 cfis[4]; 546 len = cfis[13] << 8 | cfis[12]; 547 if (!len) 548 len = 65536; 549 } else { 550 lba = ((cfis[7] & 0xf) << 24) | (cfis[6] << 16) | 551 (cfis[5] << 8) | cfis[4]; 552 len = cfis[12]; 553 if (!len) 554 len = 256; 555 } 556 lba *= blockif_sectsz(p->bctx); 557 len *= blockif_sectsz(p->bctx); 558 559 /* 560 * Pull request off free list 561 */ 562 aior = STAILQ_FIRST(&p->iofhd); 563 assert(aior != NULL); 564 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist); 565 aior->cfis = cfis; 566 aior->slot = slot; 567 aior->len = len; 568 aior->done = done; 569 breq = &aior->io_req; 570 breq->br_offset = lba + done; 571 iovcnt = hdr->prdtl - seek; 572 if (iovcnt > BLOCKIF_IOV_MAX) { 573 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX; 574 iovcnt = BLOCKIF_IOV_MAX; 575 } else 576 aior->prdtl = 0; 577 breq->br_iovcnt = iovcnt; 578 579 /* 580 * Mark this command in-flight. 581 */ 582 p->pending |= 1 << slot; 583 584 /* 585 * Stuff request onto busy list 586 */ 587 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist); 588 589 /* 590 * Build up the iovec based on the prdt 591 */ 592 for (i = 0; i < iovcnt; i++) { 593 uint32_t dbcsz; 594 595 dbcsz = (prdt->dbc & DBCMASK) + 1; 596 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc), 597 prdt->dba, dbcsz); 598 breq->br_iov[i].iov_len = dbcsz; 599 aior->done += dbcsz; 600 prdt++; 601 } 602 if (readop) 603 err = blockif_read(p->bctx, breq); 604 else 605 err = blockif_write(p->bctx, breq); 606 assert(err == 0); 607 608 if (ncq) 609 p->ci &= ~(1 << slot); 610} 611 612static void 613ahci_handle_flush(struct ahci_port *p, int slot, uint8_t *cfis) 614{ 615 struct ahci_ioreq *aior; 616 struct blockif_req *breq; 617 int err; 618 619 /* 620 * Pull request off free list 621 */ 622 aior = STAILQ_FIRST(&p->iofhd); 623 assert(aior != NULL); 624 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist); 625 aior->cfis = cfis; 626 aior->slot = slot; 627 aior->len = 0; 628 aior->done = 0; 629 aior->prdtl = 0; 630 breq = &aior->io_req; 631 632 /* 633 * Mark this command in-flight. 634 */ 635 p->pending |= 1 << slot; 636 637 /* 638 * Stuff request onto busy list 639 */ 640 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist); 641 642 err = blockif_flush(p->bctx, breq); 643 assert(err == 0); 644} 645 646static inline void 647read_prdt(struct ahci_port *p, int slot, uint8_t *cfis, 648 void *buf, int size) 649{ 650 struct ahci_cmd_hdr *hdr; 651 struct ahci_prdt_entry *prdt; 652 void *to; 653 int i, len; 654 655 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 656 len = size; 657 to = buf; 658 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 659 for (i = 0; i < hdr->prdtl && len; i++) { 660 uint8_t *ptr; 661 uint32_t dbcsz; 662 int sublen; 663 664 dbcsz = (prdt->dbc & DBCMASK) + 1; 665 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz); 666 sublen = len < dbcsz ? len : dbcsz; 667 memcpy(to, ptr, sublen); 668 len -= sublen; 669 to += sublen; 670 prdt++; 671 } 672} 673 674static void 675ahci_handle_dsm_trim(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done) 676{ 677 struct ahci_ioreq *aior; 678 struct blockif_req *breq; 679 uint8_t *entry; 680 uint64_t elba; 681 uint32_t len, elen; 682 int err; 683 uint8_t buf[512]; 684 685 len = (uint16_t)cfis[13] << 8 | cfis[12]; 686 len *= 512; 687 read_prdt(p, slot, cfis, buf, sizeof(buf)); 688 689next: 690 entry = &buf[done]; 691 elba = ((uint64_t)entry[5] << 40) | 692 ((uint64_t)entry[4] << 32) | 693 ((uint64_t)entry[3] << 24) | 694 ((uint64_t)entry[2] << 16) | 695 ((uint64_t)entry[1] << 8) | 696 entry[0]; 697 elen = (uint16_t)entry[7] << 8 | entry[6]; 698 done += 8; 699 if (elen == 0) { 700 if (done >= len) { 701 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 702 p->pending &= ~(1 << slot); 703 ahci_check_stopped(p); 704 return; 705 } 706 goto next; 707 } 708 709 /* 710 * Pull request off free list 711 */ 712 aior = STAILQ_FIRST(&p->iofhd); 713 assert(aior != NULL); 714 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist); 715 aior->cfis = cfis; 716 aior->slot = slot; 717 aior->len = len; 718 aior->done = done; 719 aior->prdtl = 0; 720 721 breq = &aior->io_req; 722 breq->br_offset = elba * blockif_sectsz(p->bctx); 723 breq->br_iovcnt = 1; 724 breq->br_iov[0].iov_len = elen * blockif_sectsz(p->bctx); 725 726 /* 727 * Mark this command in-flight. 728 */ 729 p->pending |= 1 << slot; 730 731 /* 732 * Stuff request onto busy list 733 */ 734 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist); 735 736 err = blockif_delete(p->bctx, breq); 737 assert(err == 0); 738} 739 740static inline void 741write_prdt(struct ahci_port *p, int slot, uint8_t *cfis, 742 void *buf, int size) 743{ 744 struct ahci_cmd_hdr *hdr; 745 struct ahci_prdt_entry *prdt; 746 void *from; 747 int i, len; 748 749 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 750 len = size; 751 from = buf; 752 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 753 for (i = 0; i < hdr->prdtl && len; i++) { 754 uint8_t *ptr; 755 uint32_t dbcsz; 756 int sublen; 757 758 dbcsz = (prdt->dbc & DBCMASK) + 1; 759 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz); 760 sublen = len < dbcsz ? len : dbcsz; 761 memcpy(ptr, from, sublen); 762 len -= sublen; 763 from += sublen; 764 prdt++; 765 } 766 hdr->prdbc = size - len; 767} 768 769static void 770handle_identify(struct ahci_port *p, int slot, uint8_t *cfis) 771{ 772 struct ahci_cmd_hdr *hdr; 773 774 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 775 if (p->atapi || hdr->prdtl == 0) { 776 ahci_write_fis_d2h(p, slot, cfis, 777 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 778 } else { 779 uint16_t buf[256]; 780 uint64_t sectors; 781 int sectsz, psectsz, psectoff, candelete, ro; 782 uint16_t cyl; 783 uint8_t sech, heads; 784 785 ro = blockif_is_ro(p->bctx); 786 candelete = blockif_candelete(p->bctx); 787 sectsz = blockif_sectsz(p->bctx); 788 sectors = blockif_size(p->bctx) / sectsz; 789 blockif_chs(p->bctx, &cyl, &heads, &sech); 790 blockif_psectsz(p->bctx, &psectsz, &psectoff); 791 memset(buf, 0, sizeof(buf)); 792 buf[0] = 0x0040; 793 buf[1] = cyl; 794 buf[3] = heads; 795 buf[6] = sech; 796 /* TODO emulate different serial? */ 797 ata_string((uint8_t *)(buf+10), "123456", 20); 798 ata_string((uint8_t *)(buf+23), "001", 8); 799 ata_string((uint8_t *)(buf+27), "BHYVE SATA DISK", 40); 800 buf[47] = (0x8000 | 128); 801 buf[48] = 0x1; 802 buf[49] = (1 << 8 | 1 << 9 | 1 << 11); 803 buf[50] = (1 << 14); 804 buf[53] = (1 << 1 | 1 << 2); 805 if (p->mult_sectors) 806 buf[59] = (0x100 | p->mult_sectors); 807 buf[60] = sectors; 808 buf[61] = (sectors >> 16); 809 buf[63] = 0x7; 810 if (p->xfermode & ATA_WDMA0) 811 buf[63] |= (1 << ((p->xfermode & 7) + 8)); 812 buf[64] = 0x3; 813 buf[65] = 100; 814 buf[66] = 100; 815 buf[67] = 100; 816 buf[68] = 100; 817 buf[69] = 0; 818 buf[75] = 31; 819 buf[76] = (1 << 8 | 1 << 2); 820 buf[80] = 0x1f0; 821 buf[81] = 0x28; 822 buf[82] = (1 << 5 | 1 << 14); 823 buf[83] = (1 << 10 | 1 << 12 | 1 << 13 | 1 << 14); 824 buf[84] = (1 << 14); 825 buf[85] = (1 << 5 | 1 << 14); 826 buf[86] = (1 << 10 | 1 << 12 | 1 << 13); 827 buf[87] = (1 << 14); 828 buf[88] = 0x7f; 829 if (p->xfermode & ATA_UDMA0) 830 buf[88] |= (1 << ((p->xfermode & 7) + 8)); 831 buf[93] = (1 | 1 <<14); 832 buf[100] = sectors; 833 buf[101] = (sectors >> 16); 834 buf[102] = (sectors >> 32); 835 buf[103] = (sectors >> 48); 836 if (candelete && !ro) { 837 buf[69] |= ATA_SUPPORT_RZAT | ATA_SUPPORT_DRAT; 838 buf[105] = 1; 839 buf[169] = ATA_SUPPORT_DSM_TRIM; 840 } 841 buf[106] = 0x4000; 842 buf[209] = 0x4000; 843 if (psectsz > sectsz) { 844 buf[106] |= 0x2000; 845 buf[106] |= ffsl(psectsz / sectsz) - 1; 846 buf[209] |= (psectoff / sectsz); 847 } 848 if (sectsz > 512) { 849 buf[106] |= 0x1000; 850 buf[117] = sectsz / 2; 851 buf[118] = ((sectsz / 2) >> 16); 852 } 853 ahci_write_fis_piosetup(p); 854 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf)); 855 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY); 856 } 857} 858 859static void 860handle_atapi_identify(struct ahci_port *p, int slot, uint8_t *cfis) 861{ 862 if (!p->atapi) { 863 ahci_write_fis_d2h(p, slot, cfis, 864 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 865 } else { 866 uint16_t buf[256]; 867 868 memset(buf, 0, sizeof(buf)); 869 buf[0] = (2 << 14 | 5 << 8 | 1 << 7 | 2 << 5); 870 /* TODO emulate different serial? */ 871 ata_string((uint8_t *)(buf+10), "123456", 20); 872 ata_string((uint8_t *)(buf+23), "001", 8); 873 ata_string((uint8_t *)(buf+27), "BHYVE SATA DVD ROM", 40); 874 buf[49] = (1 << 9 | 1 << 8); 875 buf[50] = (1 << 14 | 1); 876 buf[53] = (1 << 2 | 1 << 1); 877 buf[62] = 0x3f; 878 buf[63] = 7; 879 buf[64] = 3; 880 buf[65] = 100; 881 buf[66] = 100; 882 buf[67] = 100; 883 buf[68] = 100; 884 buf[76] = (1 << 2 | 1 << 1); 885 buf[78] = (1 << 5); 886 buf[80] = (0x1f << 4); 887 buf[82] = (1 << 4); 888 buf[83] = (1 << 14); 889 buf[84] = (1 << 14); 890 buf[85] = (1 << 4); 891 buf[87] = (1 << 14); 892 buf[88] = (1 << 14 | 0x7f); 893 ahci_write_fis_piosetup(p); 894 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf)); 895 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY); 896 } 897} 898 899static void 900atapi_inquiry(struct ahci_port *p, int slot, uint8_t *cfis) 901{ 902 uint8_t buf[36]; 903 uint8_t *acmd; 904 int len; 905 906 acmd = cfis + 0x40; 907 908 buf[0] = 0x05; 909 buf[1] = 0x80; 910 buf[2] = 0x00; 911 buf[3] = 0x21; 912 buf[4] = 31; 913 buf[5] = 0; 914 buf[6] = 0; 915 buf[7] = 0; 916 atapi_string(buf + 8, "BHYVE", 8); 917 atapi_string(buf + 16, "BHYVE DVD-ROM", 16); 918 atapi_string(buf + 32, "001", 4); 919 920 len = sizeof(buf); 921 if (len > acmd[4]) 922 len = acmd[4]; 923 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 924 write_prdt(p, slot, cfis, buf, len); 925 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 926} 927 928static void 929atapi_read_capacity(struct ahci_port *p, int slot, uint8_t *cfis) 930{ 931 uint8_t buf[8]; 932 uint64_t sectors; 933 934 sectors = blockif_size(p->bctx) / 2048; 935 be32enc(buf, sectors - 1); 936 be32enc(buf + 4, 2048); 937 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 938 write_prdt(p, slot, cfis, buf, sizeof(buf)); 939 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 940} 941 942static void 943atapi_read_toc(struct ahci_port *p, int slot, uint8_t *cfis) 944{ 945 uint8_t *acmd; 946 uint8_t format; 947 int len; 948 949 acmd = cfis + 0x40; 950 951 len = be16dec(acmd + 7); 952 format = acmd[9] >> 6; 953 switch (format) { 954 case 0: 955 { 956 int msf, size; 957 uint64_t sectors; 958 uint8_t start_track, buf[20], *bp; 959 960 msf = (acmd[1] >> 1) & 1; 961 start_track = acmd[6]; 962 if (start_track > 1 && start_track != 0xaa) { 963 uint32_t tfd; 964 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 965 p->asc = 0x24; 966 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 967 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 968 ahci_write_fis_d2h(p, slot, cfis, tfd); 969 return; 970 } 971 bp = buf + 2; 972 *bp++ = 1; 973 *bp++ = 1; 974 if (start_track <= 1) { 975 *bp++ = 0; 976 *bp++ = 0x14; 977 *bp++ = 1; 978 *bp++ = 0; 979 if (msf) { 980 *bp++ = 0; 981 lba_to_msf(bp, 0); 982 bp += 3; 983 } else { 984 *bp++ = 0; 985 *bp++ = 0; 986 *bp++ = 0; 987 *bp++ = 0; 988 } 989 } 990 *bp++ = 0; 991 *bp++ = 0x14; 992 *bp++ = 0xaa; 993 *bp++ = 0; 994 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx); 995 sectors >>= 2; 996 if (msf) { 997 *bp++ = 0; 998 lba_to_msf(bp, sectors); 999 bp += 3; 1000 } else { 1001 be32enc(bp, sectors); 1002 bp += 4; 1003 } 1004 size = bp - buf; 1005 be16enc(buf, size - 2); 1006 if (len > size) 1007 len = size; 1008 write_prdt(p, slot, cfis, buf, len); 1009 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1010 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1011 break; 1012 } 1013 case 1: 1014 { 1015 uint8_t buf[12]; 1016 1017 memset(buf, 0, sizeof(buf)); 1018 buf[1] = 0xa; 1019 buf[2] = 0x1; 1020 buf[3] = 0x1; 1021 if (len > sizeof(buf)) 1022 len = sizeof(buf); 1023 write_prdt(p, slot, cfis, buf, len); 1024 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1025 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1026 break; 1027 } 1028 case 2: 1029 { 1030 int msf, size; 1031 uint64_t sectors; 1032 uint8_t start_track, *bp, buf[50]; 1033 1034 msf = (acmd[1] >> 1) & 1; 1035 start_track = acmd[6]; 1036 bp = buf + 2; 1037 *bp++ = 1; 1038 *bp++ = 1; 1039 1040 *bp++ = 1; 1041 *bp++ = 0x14; 1042 *bp++ = 0; 1043 *bp++ = 0xa0; 1044 *bp++ = 0; 1045 *bp++ = 0; 1046 *bp++ = 0; 1047 *bp++ = 0; 1048 *bp++ = 1; 1049 *bp++ = 0; 1050 *bp++ = 0; 1051 1052 *bp++ = 1; 1053 *bp++ = 0x14; 1054 *bp++ = 0; 1055 *bp++ = 0xa1; 1056 *bp++ = 0; 1057 *bp++ = 0; 1058 *bp++ = 0; 1059 *bp++ = 0; 1060 *bp++ = 1; 1061 *bp++ = 0; 1062 *bp++ = 0; 1063 1064 *bp++ = 1; 1065 *bp++ = 0x14; 1066 *bp++ = 0; 1067 *bp++ = 0xa2; 1068 *bp++ = 0; 1069 *bp++ = 0; 1070 *bp++ = 0; 1071 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx); 1072 sectors >>= 2; 1073 if (msf) { 1074 *bp++ = 0; 1075 lba_to_msf(bp, sectors); 1076 bp += 3; 1077 } else { 1078 be32enc(bp, sectors); 1079 bp += 4; 1080 } 1081 1082 *bp++ = 1; 1083 *bp++ = 0x14; 1084 *bp++ = 0; 1085 *bp++ = 1; 1086 *bp++ = 0; 1087 *bp++ = 0; 1088 *bp++ = 0; 1089 if (msf) { 1090 *bp++ = 0; 1091 lba_to_msf(bp, 0); 1092 bp += 3; 1093 } else { 1094 *bp++ = 0; 1095 *bp++ = 0; 1096 *bp++ = 0; 1097 *bp++ = 0; 1098 } 1099 1100 size = bp - buf; 1101 be16enc(buf, size - 2); 1102 if (len > size) 1103 len = size; 1104 write_prdt(p, slot, cfis, buf, len); 1105 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1106 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1107 break; 1108 } 1109 default: 1110 { 1111 uint32_t tfd; 1112 1113 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1114 p->asc = 0x24; 1115 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1116 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1117 ahci_write_fis_d2h(p, slot, cfis, tfd); 1118 break; 1119 } 1120 } 1121} 1122 1123static void 1124atapi_read(struct ahci_port *p, int slot, uint8_t *cfis, 1125 uint32_t done, int seek) 1126{ 1127 struct ahci_ioreq *aior; 1128 struct ahci_cmd_hdr *hdr; 1129 struct ahci_prdt_entry *prdt; 1130 struct blockif_req *breq; 1131 struct pci_ahci_softc *sc; 1132 uint8_t *acmd; 1133 uint64_t lba; 1134 uint32_t len; 1135 int i, err, iovcnt; 1136 1137 sc = p->pr_sc; 1138 acmd = cfis + 0x40; 1139 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 1140 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 1141 1142 prdt += seek; 1143 lba = be32dec(acmd + 2); 1144 if (acmd[0] == READ_10) 1145 len = be16dec(acmd + 7); 1146 else 1147 len = be32dec(acmd + 6); 1148 if (len == 0) { 1149 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1150 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1151 } 1152 lba *= 2048; 1153 len *= 2048; 1154 1155 /* 1156 * Pull request off free list 1157 */ 1158 aior = STAILQ_FIRST(&p->iofhd); 1159 assert(aior != NULL); 1160 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist); 1161 aior->cfis = cfis; 1162 aior->slot = slot; 1163 aior->len = len; 1164 aior->done = done; 1165 breq = &aior->io_req; 1166 breq->br_offset = lba + done; 1167 iovcnt = hdr->prdtl - seek; 1168 if (iovcnt > BLOCKIF_IOV_MAX) { 1169 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX; 1170 iovcnt = BLOCKIF_IOV_MAX; 1171 } else 1172 aior->prdtl = 0; 1173 breq->br_iovcnt = iovcnt; 1174 1175 /* 1176 * Mark this command in-flight. 1177 */ 1178 p->pending |= 1 << slot; 1179 1180 /* 1181 * Stuff request onto busy list 1182 */ 1183 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist); 1184 1185 /* 1186 * Build up the iovec based on the prdt 1187 */ 1188 for (i = 0; i < iovcnt; i++) { 1189 uint32_t dbcsz; 1190 1191 dbcsz = (prdt->dbc & DBCMASK) + 1; 1192 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc), 1193 prdt->dba, dbcsz); 1194 breq->br_iov[i].iov_len = dbcsz; 1195 aior->done += dbcsz; 1196 prdt++; 1197 } 1198 err = blockif_read(p->bctx, breq); 1199 assert(err == 0); 1200} 1201 1202static void 1203atapi_request_sense(struct ahci_port *p, int slot, uint8_t *cfis) 1204{ 1205 uint8_t buf[64]; 1206 uint8_t *acmd; 1207 int len; 1208 1209 acmd = cfis + 0x40; 1210 len = acmd[4]; 1211 if (len > sizeof(buf)) 1212 len = sizeof(buf); 1213 memset(buf, 0, len); 1214 buf[0] = 0x70 | (1 << 7); 1215 buf[2] = p->sense_key; 1216 buf[7] = 10; 1217 buf[12] = p->asc; 1218 write_prdt(p, slot, cfis, buf, len); 1219 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1220 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1221} 1222 1223static void 1224atapi_start_stop_unit(struct ahci_port *p, int slot, uint8_t *cfis) 1225{ 1226 uint8_t *acmd = cfis + 0x40; 1227 uint32_t tfd; 1228 1229 switch (acmd[4] & 3) { 1230 case 0: 1231 case 1: 1232 case 3: 1233 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1234 tfd = ATA_S_READY | ATA_S_DSC; 1235 break; 1236 case 2: 1237 /* TODO eject media */ 1238 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1239 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1240 p->asc = 0x53; 1241 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1242 break; 1243 } 1244 ahci_write_fis_d2h(p, slot, cfis, tfd); 1245} 1246 1247static void 1248atapi_mode_sense(struct ahci_port *p, int slot, uint8_t *cfis) 1249{ 1250 uint8_t *acmd; 1251 uint32_t tfd; 1252 uint8_t pc, code; 1253 int len; 1254 1255 acmd = cfis + 0x40; 1256 len = be16dec(acmd + 7); 1257 pc = acmd[2] >> 6; 1258 code = acmd[2] & 0x3f; 1259 1260 switch (pc) { 1261 case 0: 1262 switch (code) { 1263 case MODEPAGE_RW_ERROR_RECOVERY: 1264 { 1265 uint8_t buf[16]; 1266 1267 if (len > sizeof(buf)) 1268 len = sizeof(buf); 1269 1270 memset(buf, 0, sizeof(buf)); 1271 be16enc(buf, 16 - 2); 1272 buf[2] = 0x70; 1273 buf[8] = 0x01; 1274 buf[9] = 16 - 10; 1275 buf[11] = 0x05; 1276 write_prdt(p, slot, cfis, buf, len); 1277 tfd = ATA_S_READY | ATA_S_DSC; 1278 break; 1279 } 1280 case MODEPAGE_CD_CAPABILITIES: 1281 { 1282 uint8_t buf[30]; 1283 1284 if (len > sizeof(buf)) 1285 len = sizeof(buf); 1286 1287 memset(buf, 0, sizeof(buf)); 1288 be16enc(buf, 30 - 2); 1289 buf[2] = 0x70; 1290 buf[8] = 0x2A; 1291 buf[9] = 30 - 10; 1292 buf[10] = 0x08; 1293 buf[12] = 0x71; 1294 be16enc(&buf[18], 2); 1295 be16enc(&buf[20], 512); 1296 write_prdt(p, slot, cfis, buf, len); 1297 tfd = ATA_S_READY | ATA_S_DSC; 1298 break; 1299 } 1300 default: 1301 goto error; 1302 break; 1303 } 1304 break; 1305 case 3: 1306 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1307 p->asc = 0x39; 1308 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1309 break; 1310error: 1311 case 1: 1312 case 2: 1313 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1314 p->asc = 0x24; 1315 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1316 break; 1317 } 1318 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1319 ahci_write_fis_d2h(p, slot, cfis, tfd); 1320} 1321 1322static void 1323atapi_get_event_status_notification(struct ahci_port *p, int slot, 1324 uint8_t *cfis) 1325{ 1326 uint8_t *acmd; 1327 uint32_t tfd; 1328 1329 acmd = cfis + 0x40; 1330 1331 /* we don't support asynchronous operation */ 1332 if (!(acmd[1] & 1)) { 1333 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1334 p->asc = 0x24; 1335 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1336 } else { 1337 uint8_t buf[8]; 1338 int len; 1339 1340 len = be16dec(acmd + 7); 1341 if (len > sizeof(buf)) 1342 len = sizeof(buf); 1343 1344 memset(buf, 0, sizeof(buf)); 1345 be16enc(buf, 8 - 2); 1346 buf[2] = 0x04; 1347 buf[3] = 0x10; 1348 buf[5] = 0x02; 1349 write_prdt(p, slot, cfis, buf, len); 1350 tfd = ATA_S_READY | ATA_S_DSC; 1351 } 1352 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1353 ahci_write_fis_d2h(p, slot, cfis, tfd); 1354} 1355 1356static void 1357handle_packet_cmd(struct ahci_port *p, int slot, uint8_t *cfis) 1358{ 1359 uint8_t *acmd; 1360 1361 acmd = cfis + 0x40; 1362 1363#ifdef AHCI_DEBUG 1364 { 1365 int i; 1366 DPRINTF("ACMD:"); 1367 for (i = 0; i < 16; i++) 1368 DPRINTF("%02x ", acmd[i]); 1369 DPRINTF("\n"); 1370 } 1371#endif 1372 1373 switch (acmd[0]) { 1374 case TEST_UNIT_READY: 1375 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1376 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1377 break; 1378 case INQUIRY: 1379 atapi_inquiry(p, slot, cfis); 1380 break; 1381 case READ_CAPACITY: 1382 atapi_read_capacity(p, slot, cfis); 1383 break; 1384 case PREVENT_ALLOW: 1385 /* TODO */ 1386 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1387 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1388 break; 1389 case READ_TOC: 1390 atapi_read_toc(p, slot, cfis); 1391 break; 1392 case READ_10: 1393 case READ_12: 1394 atapi_read(p, slot, cfis, 0, 0); 1395 break; 1396 case REQUEST_SENSE: 1397 atapi_request_sense(p, slot, cfis); 1398 break; 1399 case START_STOP_UNIT: 1400 atapi_start_stop_unit(p, slot, cfis); 1401 break; 1402 case MODE_SENSE_10: 1403 atapi_mode_sense(p, slot, cfis); 1404 break; 1405 case GET_EVENT_STATUS_NOTIFICATION: 1406 atapi_get_event_status_notification(p, slot, cfis); 1407 break; 1408 default: 1409 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1410 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1411 p->asc = 0x20; 1412 ahci_write_fis_d2h(p, slot, cfis, (p->sense_key << 12) | 1413 ATA_S_READY | ATA_S_ERROR); 1414 break; 1415 } 1416} 1417 1418static void 1419ahci_handle_cmd(struct ahci_port *p, int slot, uint8_t *cfis) 1420{ 1421 1422 switch (cfis[2]) { 1423 case ATA_ATA_IDENTIFY: 1424 handle_identify(p, slot, cfis); 1425 break; 1426 case ATA_SETFEATURES: 1427 { 1428 switch (cfis[3]) { 1429 case ATA_SF_ENAB_SATA_SF: 1430 switch (cfis[12]) { 1431 case ATA_SATA_SF_AN: 1432 p->tfd = ATA_S_DSC | ATA_S_READY; 1433 break; 1434 default: 1435 p->tfd = ATA_S_ERROR | ATA_S_READY; 1436 p->tfd |= (ATA_ERROR_ABORT << 8); 1437 break; 1438 } 1439 break; 1440 case ATA_SF_ENAB_WCACHE: 1441 case ATA_SF_DIS_WCACHE: 1442 case ATA_SF_ENAB_RCACHE: 1443 case ATA_SF_DIS_RCACHE: 1444 p->tfd = ATA_S_DSC | ATA_S_READY; 1445 break; 1446 case ATA_SF_SETXFER: 1447 { 1448 switch (cfis[12] & 0xf8) { 1449 case ATA_PIO: 1450 case ATA_PIO0: 1451 break; 1452 case ATA_WDMA0: 1453 case ATA_UDMA0: 1454 p->xfermode = (cfis[12] & 0x7); 1455 break; 1456 } 1457 p->tfd = ATA_S_DSC | ATA_S_READY; 1458 break; 1459 } 1460 default: 1461 p->tfd = ATA_S_ERROR | ATA_S_READY; 1462 p->tfd |= (ATA_ERROR_ABORT << 8); 1463 break; 1464 } 1465 ahci_write_fis_d2h(p, slot, cfis, p->tfd); 1466 break; 1467 } 1468 case ATA_SET_MULTI: 1469 if (cfis[12] != 0 && 1470 (cfis[12] > 128 || (cfis[12] & (cfis[12] - 1)))) { 1471 p->tfd = ATA_S_ERROR | ATA_S_READY; 1472 p->tfd |= (ATA_ERROR_ABORT << 8); 1473 } else { 1474 p->mult_sectors = cfis[12]; 1475 p->tfd = ATA_S_DSC | ATA_S_READY; 1476 } 1477 ahci_write_fis_d2h(p, slot, cfis, p->tfd); 1478 break; 1479 case ATA_READ_DMA: 1480 case ATA_WRITE_DMA: 1481 case ATA_READ_DMA48: 1482 case ATA_WRITE_DMA48: 1483 case ATA_READ_FPDMA_QUEUED: 1484 case ATA_WRITE_FPDMA_QUEUED: 1485 ahci_handle_dma(p, slot, cfis, 0, 0); 1486 break; 1487 case ATA_FLUSHCACHE: 1488 case ATA_FLUSHCACHE48: 1489 ahci_handle_flush(p, slot, cfis); 1490 break; 1491 case ATA_DATA_SET_MANAGEMENT: 1492 if (cfis[11] == 0 && cfis[3] == ATA_DSM_TRIM && 1493 cfis[13] == 0 && cfis[12] == 1) { 1494 ahci_handle_dsm_trim(p, slot, cfis, 0); 1495 break; 1496 } 1497 ahci_write_fis_d2h(p, slot, cfis, 1498 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 1499 break; 1500 case ATA_STANDBY_CMD: 1501 break; 1502 case ATA_NOP: 1503 case ATA_STANDBY_IMMEDIATE: 1504 case ATA_IDLE_IMMEDIATE: 1505 case ATA_SLEEP: 1506 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1507 break; 1508 case ATA_ATAPI_IDENTIFY: 1509 handle_atapi_identify(p, slot, cfis); 1510 break; 1511 case ATA_PACKET_CMD: 1512 if (!p->atapi) { 1513 ahci_write_fis_d2h(p, slot, cfis, 1514 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 1515 } else 1516 handle_packet_cmd(p, slot, cfis); 1517 break; 1518 default: 1519 WPRINTF("Unsupported cmd:%02x\n", cfis[2]); 1520 ahci_write_fis_d2h(p, slot, cfis, 1521 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 1522 break; 1523 } 1524} 1525 1526static void 1527ahci_handle_slot(struct ahci_port *p, int slot) 1528{ 1529 struct ahci_cmd_hdr *hdr; 1530 struct ahci_prdt_entry *prdt; 1531 struct pci_ahci_softc *sc; 1532 uint8_t *cfis; 1533 int cfl; 1534 1535 sc = p->pr_sc; 1536 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 1537 cfl = (hdr->flags & 0x1f) * 4; 1538 cfis = paddr_guest2host(ahci_ctx(sc), hdr->ctba, 1539 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry)); 1540 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 1541 1542#ifdef AHCI_DEBUG 1543 DPRINTF("\ncfis:"); 1544 for (i = 0; i < cfl; i++) { 1545 if (i % 10 == 0) 1546 DPRINTF("\n"); 1547 DPRINTF("%02x ", cfis[i]); 1548 } 1549 DPRINTF("\n"); 1550 1551 for (i = 0; i < hdr->prdtl; i++) { 1552 DPRINTF("%d@%08"PRIx64"\n", prdt->dbc & 0x3fffff, prdt->dba); 1553 prdt++; 1554 } 1555#endif 1556 1557 if (cfis[0] != FIS_TYPE_REGH2D) { 1558 WPRINTF("Not a H2D FIS:%02x\n", cfis[0]); 1559 return; 1560 } 1561 1562 if (cfis[1] & 0x80) { 1563 ahci_handle_cmd(p, slot, cfis); 1564 } else { 1565 if (cfis[15] & (1 << 2)) 1566 p->reset = 1; 1567 else if (p->reset) { 1568 p->reset = 0; 1569 ahci_port_reset(p); 1570 } 1571 p->ci &= ~(1 << slot); 1572 } 1573} 1574 1575static void 1576ahci_handle_port(struct ahci_port *p) 1577{ 1578 int i; 1579 1580 if (!(p->cmd & AHCI_P_CMD_ST)) 1581 return; 1582 1583 /* 1584 * Search for any new commands to issue ignoring those that 1585 * are already in-flight. 1586 */ 1587 for (i = 0; (i < 32) && p->ci; i++) { 1588 if ((p->ci & (1 << i)) && !(p->pending & (1 << i))) { 1589 p->cmd &= ~AHCI_P_CMD_CCS_MASK; 1590 p->cmd |= i << AHCI_P_CMD_CCS_SHIFT; 1591 ahci_handle_slot(p, i); 1592 } 1593 } 1594} 1595 1596/* 1597 * blockif callback routine - this runs in the context of the blockif 1598 * i/o thread, so the mutex needs to be acquired. 1599 */ 1600static void 1601ata_ioreq_cb(struct blockif_req *br, int err) 1602{ 1603 struct ahci_cmd_hdr *hdr; 1604 struct ahci_ioreq *aior; 1605 struct ahci_port *p; 1606 struct pci_ahci_softc *sc; 1607 uint32_t tfd; 1608 uint8_t *cfis; 1609 int pending, slot, ncq, dsm; 1610 1611 DPRINTF("%s %d\n", __func__, err); 1612 1613 ncq = dsm = 0; 1614 aior = br->br_param; 1615 p = aior->io_pr; 1616 cfis = aior->cfis; 1617 slot = aior->slot; 1618 pending = aior->prdtl; 1619 sc = p->pr_sc; 1620 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 1621 1622 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED || 1623 cfis[2] == ATA_READ_FPDMA_QUEUED) 1624 ncq = 1; 1625 if (cfis[2] == ATA_DATA_SET_MANAGEMENT) 1626 dsm = 1; 1627 1628 pthread_mutex_lock(&sc->mtx); 1629 1630 /* 1631 * Delete the blockif request from the busy list 1632 */ 1633 TAILQ_REMOVE(&p->iobhd, aior, io_blist); 1634 1635 /* 1636 * Move the blockif request back to the free list 1637 */ 1638 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist); 1639 1640 if (dsm) { 1641 if (aior->done != aior->len && !err) { 1642 ahci_handle_dsm_trim(p, slot, cfis, aior->done); 1643 goto out; 1644 } 1645 } else { 1646 if (pending && !err) { 1647 ahci_handle_dma(p, slot, cfis, aior->done, 1648 hdr->prdtl - pending); 1649 goto out; 1650 } 1651 } 1652 1653 if (!err && aior->done == aior->len) { 1654 tfd = ATA_S_READY | ATA_S_DSC; 1655 if (ncq) 1656 hdr->prdbc = 0; 1657 else 1658 hdr->prdbc = aior->len; 1659 } else { 1660 tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR; 1661 hdr->prdbc = 0; 1662 if (ncq) 1663 p->serr |= (1 << slot); 1664 } 1665 1666 if (ncq) { 1667 p->sact &= ~(1 << slot); 1668 ahci_write_fis_sdb(p, slot, tfd); 1669 } else 1670 ahci_write_fis_d2h(p, slot, cfis, tfd); 1671 1672 /* 1673 * This command is now complete. 1674 */ 1675 p->pending &= ~(1 << slot); 1676 1677 ahci_check_stopped(p); 1678out: 1679 pthread_mutex_unlock(&sc->mtx); 1680 DPRINTF("%s exit\n", __func__); 1681} 1682 1683static void 1684atapi_ioreq_cb(struct blockif_req *br, int err) 1685{ 1686 struct ahci_cmd_hdr *hdr; 1687 struct ahci_ioreq *aior; 1688 struct ahci_port *p; 1689 struct pci_ahci_softc *sc; 1690 uint8_t *cfis; 1691 uint32_t tfd; 1692 int pending, slot; 1693 1694 DPRINTF("%s %d\n", __func__, err); 1695 1696 aior = br->br_param; 1697 p = aior->io_pr; 1698 cfis = aior->cfis; 1699 slot = aior->slot; 1700 pending = aior->prdtl; 1701 sc = p->pr_sc; 1702 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + aior->slot * AHCI_CL_SIZE); 1703 1704 pthread_mutex_lock(&sc->mtx); 1705 1706 /* 1707 * Delete the blockif request from the busy list 1708 */ 1709 TAILQ_REMOVE(&p->iobhd, aior, io_blist); 1710 1711 /* 1712 * Move the blockif request back to the free list 1713 */ 1714 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist); 1715 1716 if (pending && !err) { 1717 atapi_read(p, slot, cfis, aior->done, hdr->prdtl - pending); 1718 goto out; 1719 } 1720 1721 if (!err && aior->done == aior->len) { 1722 tfd = ATA_S_READY | ATA_S_DSC; 1723 hdr->prdbc = aior->len; 1724 } else { 1725 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1726 p->asc = 0x21; 1727 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1728 hdr->prdbc = 0; 1729 } 1730 1731 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1732 ahci_write_fis_d2h(p, slot, cfis, tfd); 1733 1734 /* 1735 * This command is now complete. 1736 */ 1737 p->pending &= ~(1 << slot); 1738 1739 ahci_check_stopped(p); 1740out: 1741 pthread_mutex_unlock(&sc->mtx); 1742 DPRINTF("%s exit\n", __func__); 1743} 1744 1745static void 1746pci_ahci_ioreq_init(struct ahci_port *pr) 1747{ 1748 struct ahci_ioreq *vr; 1749 int i; 1750 1751 pr->ioqsz = blockif_queuesz(pr->bctx); 1752 pr->ioreq = calloc(pr->ioqsz, sizeof(struct ahci_ioreq)); 1753 STAILQ_INIT(&pr->iofhd); 1754 1755 /* 1756 * Add all i/o request entries to the free queue 1757 */ 1758 for (i = 0; i < pr->ioqsz; i++) { 1759 vr = &pr->ioreq[i]; 1760 vr->io_pr = pr; 1761 if (!pr->atapi) 1762 vr->io_req.br_callback = ata_ioreq_cb; 1763 else 1764 vr->io_req.br_callback = atapi_ioreq_cb; 1765 vr->io_req.br_param = vr; 1766 STAILQ_INSERT_TAIL(&pr->iofhd, vr, io_flist); 1767 } 1768 1769 TAILQ_INIT(&pr->iobhd); 1770} 1771 1772static void 1773pci_ahci_port_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value) 1774{ 1775 int port = (offset - AHCI_OFFSET) / AHCI_STEP; 1776 offset = (offset - AHCI_OFFSET) % AHCI_STEP; 1777 struct ahci_port *p = &sc->port[port]; 1778 1779 DPRINTF("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"\n", 1780 port, offset, value); 1781 1782 switch (offset) { 1783 case AHCI_P_CLB: 1784 p->clb = value; 1785 break; 1786 case AHCI_P_CLBU: 1787 p->clbu = value; 1788 break; 1789 case AHCI_P_FB: 1790 p->fb = value; 1791 break; 1792 case AHCI_P_FBU: 1793 p->fbu = value; 1794 break; 1795 case AHCI_P_IS: 1796 p->is &= ~value; 1797 break; 1798 case AHCI_P_IE: 1799 p->ie = value & 0xFDC000FF; 1800 ahci_generate_intr(sc); 1801 break; 1802 case AHCI_P_CMD: 1803 { 1804 p->cmd = value; 1805 1806 if (!(value & AHCI_P_CMD_ST)) { 1807 ahci_port_stop(p); 1808 } else { 1809 uint64_t clb; 1810 1811 p->cmd |= AHCI_P_CMD_CR; 1812 clb = (uint64_t)p->clbu << 32 | p->clb; 1813 p->cmd_lst = paddr_guest2host(ahci_ctx(sc), clb, 1814 AHCI_CL_SIZE * AHCI_MAX_SLOTS); 1815 } 1816 1817 if (value & AHCI_P_CMD_FRE) { 1818 uint64_t fb; 1819 1820 p->cmd |= AHCI_P_CMD_FR; 1821 fb = (uint64_t)p->fbu << 32 | p->fb; 1822 /* we don't support FBSCP, so rfis size is 256Bytes */ 1823 p->rfis = paddr_guest2host(ahci_ctx(sc), fb, 256); 1824 } else { 1825 p->cmd &= ~AHCI_P_CMD_FR; 1826 } 1827 1828 if (value & AHCI_P_CMD_CLO) { 1829 p->tfd = 0; 1830 p->cmd &= ~AHCI_P_CMD_CLO; 1831 } 1832 1833 ahci_handle_port(p); 1834 break; 1835 } 1836 case AHCI_P_TFD: 1837 case AHCI_P_SIG: 1838 case AHCI_P_SSTS: 1839 WPRINTF("pci_ahci_port: read only registers 0x%"PRIx64"\n", offset); 1840 break; 1841 case AHCI_P_SCTL: 1842 if (!(p->cmd & AHCI_P_CMD_ST)) { 1843 if (value & ATA_SC_DET_RESET) 1844 ahci_port_reset(p); 1845 p->sctl = value; 1846 } 1847 break; 1848 case AHCI_P_SERR: 1849 p->serr &= ~value; 1850 break; 1851 case AHCI_P_SACT: 1852 p->sact |= value; 1853 break; 1854 case AHCI_P_CI: 1855 p->ci |= value; 1856 ahci_handle_port(p); 1857 break; 1858 case AHCI_P_SNTF: 1859 case AHCI_P_FBS: 1860 default: 1861 break; 1862 } 1863} 1864 1865static void 1866pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value) 1867{ 1868 DPRINTF("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"\n", 1869 offset, value); 1870 1871 switch (offset) { 1872 case AHCI_CAP: 1873 case AHCI_PI: 1874 case AHCI_VS: 1875 case AHCI_CAP2: 1876 DPRINTF("pci_ahci_host: read only registers 0x%"PRIx64"\n", offset); 1877 break; 1878 case AHCI_GHC: 1879 if (value & AHCI_GHC_HR) 1880 ahci_reset(sc); 1881 else if (value & AHCI_GHC_IE) { 1882 sc->ghc |= AHCI_GHC_IE; 1883 ahci_generate_intr(sc); 1884 } 1885 break; 1886 case AHCI_IS: 1887 sc->is &= ~value; 1888 ahci_generate_intr(sc); 1889 break; 1890 default: 1891 break; 1892 } 1893} 1894 1895static void 1896pci_ahci_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, 1897 int baridx, uint64_t offset, int size, uint64_t value) 1898{ 1899 struct pci_ahci_softc *sc = pi->pi_arg; 1900 1901 assert(baridx == 5); 1902 assert(size == 4); 1903 1904 pthread_mutex_lock(&sc->mtx); 1905 1906 if (offset < AHCI_OFFSET) 1907 pci_ahci_host_write(sc, offset, value); 1908 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP) 1909 pci_ahci_port_write(sc, offset, value); 1910 else 1911 WPRINTF("pci_ahci: unknown i/o write offset 0x%"PRIx64"\n", offset); 1912 1913 pthread_mutex_unlock(&sc->mtx); 1914} 1915 1916static uint64_t 1917pci_ahci_host_read(struct pci_ahci_softc *sc, uint64_t offset) 1918{ 1919 uint32_t value; 1920 1921 switch (offset) { 1922 case AHCI_CAP: 1923 case AHCI_GHC: 1924 case AHCI_IS: 1925 case AHCI_PI: 1926 case AHCI_VS: 1927 case AHCI_CCCC: 1928 case AHCI_CCCP: 1929 case AHCI_EM_LOC: 1930 case AHCI_EM_CTL: 1931 case AHCI_CAP2: 1932 { 1933 uint32_t *p = &sc->cap; 1934 p += (offset - AHCI_CAP) / sizeof(uint32_t); 1935 value = *p; 1936 break; 1937 } 1938 default: 1939 value = 0; 1940 break; 1941 } 1942 DPRINTF("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x\n", 1943 offset, value); 1944 1945 return (value); 1946} 1947 1948static uint64_t 1949pci_ahci_port_read(struct pci_ahci_softc *sc, uint64_t offset) 1950{ 1951 uint32_t value; 1952 int port = (offset - AHCI_OFFSET) / AHCI_STEP; 1953 offset = (offset - AHCI_OFFSET) % AHCI_STEP; 1954 1955 switch (offset) { 1956 case AHCI_P_CLB: 1957 case AHCI_P_CLBU: 1958 case AHCI_P_FB: 1959 case AHCI_P_FBU: 1960 case AHCI_P_IS: 1961 case AHCI_P_IE: 1962 case AHCI_P_CMD: 1963 case AHCI_P_TFD: 1964 case AHCI_P_SIG: 1965 case AHCI_P_SSTS: 1966 case AHCI_P_SCTL: 1967 case AHCI_P_SERR: 1968 case AHCI_P_SACT: 1969 case AHCI_P_CI: 1970 case AHCI_P_SNTF: 1971 case AHCI_P_FBS: 1972 { 1973 uint32_t *p= &sc->port[port].clb; 1974 p += (offset - AHCI_P_CLB) / sizeof(uint32_t); 1975 value = *p; 1976 break; 1977 } 1978 default: 1979 value = 0; 1980 break; 1981 } 1982 1983 DPRINTF("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x\n", 1984 port, offset, value); 1985 1986 return value; 1987} 1988 1989static uint64_t 1990pci_ahci_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 1991 uint64_t offset, int size) 1992{ 1993 struct pci_ahci_softc *sc = pi->pi_arg; 1994 uint32_t value; 1995 1996 assert(baridx == 5); 1997 assert(size == 4); 1998 1999 pthread_mutex_lock(&sc->mtx); 2000 2001 if (offset < AHCI_OFFSET) 2002 value = pci_ahci_host_read(sc, offset); 2003 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP) 2004 value = pci_ahci_port_read(sc, offset); 2005 else { 2006 value = 0; 2007 WPRINTF("pci_ahci: unknown i/o read offset 0x%"PRIx64"\n", offset); 2008 } 2009 2010 pthread_mutex_unlock(&sc->mtx); 2011 2012 return (value); 2013} 2014 2015static int 2016pci_ahci_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts, int atapi) 2017{ 2018 char bident[sizeof("XX:X:X")]; 2019 struct blockif_ctxt *bctxt; 2020 struct pci_ahci_softc *sc; 2021 int ret, slots; 2022 2023 ret = 0; 2024 2025 if (opts == NULL) { 2026 fprintf(stderr, "pci_ahci: backing device required\n"); 2027 return (1); 2028 } 2029 2030#ifdef AHCI_DEBUG 2031 dbg = fopen("/tmp/log", "w+"); 2032#endif 2033 2034 sc = calloc(1, sizeof(struct pci_ahci_softc)); 2035 pi->pi_arg = sc; 2036 sc->asc_pi = pi; 2037 sc->ports = MAX_PORTS; 2038 2039 /* 2040 * Only use port 0 for a backing device. All other ports will be 2041 * marked as unused 2042 */ 2043 sc->port[0].atapi = atapi; 2044 2045 /* 2046 * Attempt to open the backing image. Use the PCI 2047 * slot/func for the identifier string. 2048 */ 2049 snprintf(bident, sizeof(bident), "%d:%d", pi->pi_slot, pi->pi_func); 2050 bctxt = blockif_open(opts, bident); 2051 if (bctxt == NULL) { 2052 ret = 1; 2053 goto open_fail; 2054 } 2055 sc->port[0].bctx = bctxt; 2056 sc->port[0].pr_sc = sc; 2057 2058 /* 2059 * Allocate blockif request structures and add them 2060 * to the free list 2061 */ 2062 pci_ahci_ioreq_init(&sc->port[0]); 2063 2064 pthread_mutex_init(&sc->mtx, NULL); 2065 2066 /* Intel ICH8 AHCI */ 2067 slots = sc->port[0].ioqsz; 2068 if (slots > 32) 2069 slots = 32; 2070 --slots; 2071 sc->cap = AHCI_CAP_64BIT | AHCI_CAP_SNCQ | AHCI_CAP_SSNTF | 2072 AHCI_CAP_SMPS | AHCI_CAP_SSS | AHCI_CAP_SALP | 2073 AHCI_CAP_SAL | AHCI_CAP_SCLO | (0x3 << AHCI_CAP_ISS_SHIFT)| 2074 AHCI_CAP_PMD | AHCI_CAP_SSC | AHCI_CAP_PSC | 2075 (slots << AHCI_CAP_NCS_SHIFT) | AHCI_CAP_SXS | (sc->ports - 1); 2076 2077 /* Only port 0 implemented */ 2078 sc->pi = 1; 2079 sc->vs = 0x10300; 2080 sc->cap2 = AHCI_CAP2_APST; 2081 ahci_reset(sc); 2082 2083 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x2821); 2084 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086); 2085 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_STORAGE); 2086 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_STORAGE_SATA); 2087 pci_set_cfgdata8(pi, PCIR_PROGIF, PCIP_STORAGE_SATA_AHCI_1_0); 2088 pci_emul_add_msicap(pi, 1); 2089 pci_emul_alloc_bar(pi, 5, PCIBAR_MEM32, 2090 AHCI_OFFSET + sc->ports * AHCI_STEP); 2091 2092 pci_lintr_request(pi); 2093 2094open_fail: 2095 if (ret) { 2096 blockif_close(sc->port[0].bctx); 2097 free(sc); 2098 } 2099 2100 return (ret); 2101} 2102 2103static int 2104pci_ahci_hd_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts) 2105{ 2106 2107 return (pci_ahci_init(ctx, pi, opts, 0)); 2108} 2109 2110static int 2111pci_ahci_atapi_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts) 2112{ 2113 2114 return (pci_ahci_init(ctx, pi, opts, 1)); 2115} 2116 2117/* 2118 * Use separate emulation names to distinguish drive and atapi devices 2119 */ 2120struct pci_devemu pci_de_ahci_hd = { 2121 .pe_emu = "ahci-hd", 2122 .pe_init = pci_ahci_hd_init, 2123 .pe_barwrite = pci_ahci_write, 2124 .pe_barread = pci_ahci_read 2125}; 2126PCI_EMUL_SET(pci_de_ahci_hd); 2127 2128struct pci_devemu pci_de_ahci_cd = { 2129 .pe_emu = "ahci-cd", 2130 .pe_init = pci_ahci_atapi_init, 2131 .pe_barwrite = pci_ahci_write, 2132 .pe_barread = pci_ahci_read 2133}; 2134PCI_EMUL_SET(pci_de_ahci_cd); 2135