pci_ahci.c revision 280370
1/*- 2 * Copyright (c) 2013 Zhixiang Yu <zcore@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: stable/10/usr.sbin/bhyve/pci_ahci.c 280370 2015-03-23 14:36:53Z mav $ 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: stable/10/usr.sbin/bhyve/pci_ahci.c 280370 2015-03-23 14:36:53Z mav $"); 31 32#include <sys/param.h> 33#include <sys/linker_set.h> 34#include <sys/stat.h> 35#include <sys/uio.h> 36#include <sys/ioctl.h> 37#include <sys/disk.h> 38#include <sys/ata.h> 39#include <sys/endian.h> 40 41#include <errno.h> 42#include <fcntl.h> 43#include <stdio.h> 44#include <stdlib.h> 45#include <stdint.h> 46#include <string.h> 47#include <strings.h> 48#include <unistd.h> 49#include <assert.h> 50#include <pthread.h> 51#include <pthread_np.h> 52#include <inttypes.h> 53 54#include "bhyverun.h" 55#include "pci_emul.h" 56#include "ahci.h" 57#include "block_if.h" 58 59#define MAX_PORTS 6 /* Intel ICH8 AHCI supports 6 ports */ 60 61#define PxSIG_ATA 0x00000101 /* ATA drive */ 62#define PxSIG_ATAPI 0xeb140101 /* ATAPI drive */ 63 64enum sata_fis_type { 65 FIS_TYPE_REGH2D = 0x27, /* Register FIS - host to device */ 66 FIS_TYPE_REGD2H = 0x34, /* Register FIS - device to host */ 67 FIS_TYPE_DMAACT = 0x39, /* DMA activate FIS - device to host */ 68 FIS_TYPE_DMASETUP = 0x41, /* DMA setup FIS - bidirectional */ 69 FIS_TYPE_DATA = 0x46, /* Data FIS - bidirectional */ 70 FIS_TYPE_BIST = 0x58, /* BIST activate FIS - bidirectional */ 71 FIS_TYPE_PIOSETUP = 0x5F, /* PIO setup FIS - device to host */ 72 FIS_TYPE_SETDEVBITS = 0xA1, /* Set dev bits FIS - device to host */ 73}; 74 75/* 76 * SCSI opcodes 77 */ 78#define TEST_UNIT_READY 0x00 79#define REQUEST_SENSE 0x03 80#define INQUIRY 0x12 81#define START_STOP_UNIT 0x1B 82#define PREVENT_ALLOW 0x1E 83#define READ_CAPACITY 0x25 84#define READ_10 0x28 85#define POSITION_TO_ELEMENT 0x2B 86#define READ_TOC 0x43 87#define GET_EVENT_STATUS_NOTIFICATION 0x4A 88#define MODE_SENSE_10 0x5A 89#define READ_12 0xA8 90#define READ_CD 0xBE 91 92/* 93 * SCSI mode page codes 94 */ 95#define MODEPAGE_RW_ERROR_RECOVERY 0x01 96#define MODEPAGE_CD_CAPABILITIES 0x2A 97 98/* 99 * ATA commands 100 */ 101#define ATA_SF_ENAB_SATA_SF 0x10 102#define ATA_SATA_SF_AN 0x05 103#define ATA_SF_DIS_SATA_SF 0x90 104 105/* 106 * Debug printf 107 */ 108#ifdef AHCI_DEBUG 109static FILE *dbg; 110#define DPRINTF(format, arg...) do{fprintf(dbg, format, ##arg);fflush(dbg);}while(0) 111#else 112#define DPRINTF(format, arg...) 113#endif 114#define WPRINTF(format, arg...) printf(format, ##arg) 115 116struct ahci_ioreq { 117 struct blockif_req io_req; 118 struct ahci_port *io_pr; 119 STAILQ_ENTRY(ahci_ioreq) io_flist; 120 TAILQ_ENTRY(ahci_ioreq) io_blist; 121 uint8_t *cfis; 122 uint32_t len; 123 uint32_t done; 124 int slot; 125 int prdtl; 126}; 127 128struct ahci_port { 129 struct blockif_ctxt *bctx; 130 struct pci_ahci_softc *pr_sc; 131 uint8_t *cmd_lst; 132 uint8_t *rfis; 133 int atapi; 134 int reset; 135 int mult_sectors; 136 uint8_t xfermode; 137 uint8_t sense_key; 138 uint8_t asc; 139 uint32_t pending; 140 141 uint32_t clb; 142 uint32_t clbu; 143 uint32_t fb; 144 uint32_t fbu; 145 uint32_t is; 146 uint32_t ie; 147 uint32_t cmd; 148 uint32_t unused0; 149 uint32_t tfd; 150 uint32_t sig; 151 uint32_t ssts; 152 uint32_t sctl; 153 uint32_t serr; 154 uint32_t sact; 155 uint32_t ci; 156 uint32_t sntf; 157 uint32_t fbs; 158 159 /* 160 * i/o request info 161 */ 162 struct ahci_ioreq *ioreq; 163 int ioqsz; 164 STAILQ_HEAD(ahci_fhead, ahci_ioreq) iofhd; 165 TAILQ_HEAD(ahci_bhead, ahci_ioreq) iobhd; 166}; 167 168struct ahci_cmd_hdr { 169 uint16_t flags; 170 uint16_t prdtl; 171 uint32_t prdbc; 172 uint64_t ctba; 173 uint32_t reserved[4]; 174}; 175 176struct ahci_prdt_entry { 177 uint64_t dba; 178 uint32_t reserved; 179#define DBCMASK 0x3fffff 180 uint32_t dbc; 181}; 182 183struct pci_ahci_softc { 184 struct pci_devinst *asc_pi; 185 pthread_mutex_t mtx; 186 int ports; 187 uint32_t cap; 188 uint32_t ghc; 189 uint32_t is; 190 uint32_t pi; 191 uint32_t vs; 192 uint32_t ccc_ctl; 193 uint32_t ccc_pts; 194 uint32_t em_loc; 195 uint32_t em_ctl; 196 uint32_t cap2; 197 uint32_t bohc; 198 uint32_t lintr; 199 struct ahci_port port[MAX_PORTS]; 200}; 201#define ahci_ctx(sc) ((sc)->asc_pi->pi_vmctx) 202 203static inline void lba_to_msf(uint8_t *buf, int lba) 204{ 205 lba += 150; 206 buf[0] = (lba / 75) / 60; 207 buf[1] = (lba / 75) % 60; 208 buf[2] = lba % 75; 209} 210 211/* 212 * generate HBA intr depending on whether or not ports within 213 * the controller have an interrupt pending. 214 */ 215static void 216ahci_generate_intr(struct pci_ahci_softc *sc) 217{ 218 struct pci_devinst *pi; 219 int i; 220 221 pi = sc->asc_pi; 222 223 for (i = 0; i < sc->ports; i++) { 224 struct ahci_port *pr; 225 pr = &sc->port[i]; 226 if (pr->is & pr->ie) 227 sc->is |= (1 << i); 228 } 229 230 DPRINTF("%s %x\n", __func__, sc->is); 231 232 if (sc->is && (sc->ghc & AHCI_GHC_IE)) { 233 if (pci_msi_enabled(pi)) { 234 /* 235 * Generate an MSI interrupt on every edge 236 */ 237 pci_generate_msi(pi, 0); 238 } else if (!sc->lintr) { 239 /* 240 * Only generate a pin-based interrupt if one wasn't 241 * in progress 242 */ 243 sc->lintr = 1; 244 pci_lintr_assert(pi); 245 } 246 } else if (sc->lintr) { 247 /* 248 * No interrupts: deassert pin-based signal if it had 249 * been asserted 250 */ 251 pci_lintr_deassert(pi); 252 sc->lintr = 0; 253 } 254} 255 256static void 257ahci_write_fis(struct ahci_port *p, enum sata_fis_type ft, uint8_t *fis) 258{ 259 int offset, len, irq; 260 261 if (p->rfis == NULL || !(p->cmd & AHCI_P_CMD_FRE)) 262 return; 263 264 switch (ft) { 265 case FIS_TYPE_REGD2H: 266 offset = 0x40; 267 len = 20; 268 irq = AHCI_P_IX_DHR; 269 break; 270 case FIS_TYPE_SETDEVBITS: 271 offset = 0x58; 272 len = 8; 273 irq = AHCI_P_IX_SDB; 274 break; 275 case FIS_TYPE_PIOSETUP: 276 offset = 0x20; 277 len = 20; 278 irq = 0; 279 break; 280 default: 281 WPRINTF("unsupported fis type %d\n", ft); 282 return; 283 } 284 memcpy(p->rfis + offset, fis, len); 285 if (irq) { 286 p->is |= irq; 287 ahci_generate_intr(p->pr_sc); 288 } 289} 290 291static void 292ahci_write_fis_piosetup(struct ahci_port *p) 293{ 294 uint8_t fis[20]; 295 296 memset(fis, 0, sizeof(fis)); 297 fis[0] = FIS_TYPE_PIOSETUP; 298 ahci_write_fis(p, FIS_TYPE_PIOSETUP, fis); 299} 300 301static void 302ahci_write_fis_sdb(struct ahci_port *p, int slot, uint32_t tfd) 303{ 304 uint8_t fis[8]; 305 uint8_t error; 306 307 error = (tfd >> 8) & 0xff; 308 memset(fis, 0, sizeof(fis)); 309 fis[0] = error; 310 fis[2] = tfd & 0x77; 311 *(uint32_t *)(fis + 4) = (1 << slot); 312 if (fis[2] & ATA_S_ERROR) 313 p->is |= AHCI_P_IX_TFE; 314 p->tfd = tfd; 315 ahci_write_fis(p, FIS_TYPE_SETDEVBITS, fis); 316} 317 318static void 319ahci_write_fis_d2h(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd) 320{ 321 uint8_t fis[20]; 322 uint8_t error; 323 324 error = (tfd >> 8) & 0xff; 325 memset(fis, 0, sizeof(fis)); 326 fis[0] = FIS_TYPE_REGD2H; 327 fis[1] = (1 << 6); 328 fis[2] = tfd & 0xff; 329 fis[3] = error; 330 fis[4] = cfis[4]; 331 fis[5] = cfis[5]; 332 fis[6] = cfis[6]; 333 fis[7] = cfis[7]; 334 fis[8] = cfis[8]; 335 fis[9] = cfis[9]; 336 fis[10] = cfis[10]; 337 fis[11] = cfis[11]; 338 fis[12] = cfis[12]; 339 fis[13] = cfis[13]; 340 if (fis[2] & ATA_S_ERROR) 341 p->is |= AHCI_P_IX_TFE; 342 else 343 p->ci &= ~(1 << slot); 344 p->tfd = tfd; 345 ahci_write_fis(p, FIS_TYPE_REGD2H, fis); 346} 347 348static void 349ahci_write_reset_fis_d2h(struct ahci_port *p) 350{ 351 uint8_t fis[20]; 352 353 memset(fis, 0, sizeof(fis)); 354 fis[0] = FIS_TYPE_REGD2H; 355 fis[3] = 1; 356 fis[4] = 1; 357 if (p->atapi) { 358 fis[5] = 0x14; 359 fis[6] = 0xeb; 360 } 361 fis[12] = 1; 362 ahci_write_fis(p, FIS_TYPE_REGD2H, fis); 363} 364 365static void 366ahci_check_stopped(struct ahci_port *p) 367{ 368 /* 369 * If we are no longer processing the command list and nothing 370 * is in-flight, clear the running bit, the current command 371 * slot, the command issue and active bits. 372 */ 373 if (!(p->cmd & AHCI_P_CMD_ST)) { 374 if (p->pending == 0) { 375 p->cmd &= ~(AHCI_P_CMD_CR | AHCI_P_CMD_CCS_MASK); 376 p->ci = 0; 377 p->sact = 0; 378 } 379 } 380} 381 382static void 383ahci_port_stop(struct ahci_port *p) 384{ 385 struct ahci_ioreq *aior; 386 uint8_t *cfis; 387 int slot; 388 int ncq; 389 int error; 390 391 assert(pthread_mutex_isowned_np(&p->pr_sc->mtx)); 392 393 TAILQ_FOREACH(aior, &p->iobhd, io_blist) { 394 /* 395 * Try to cancel the outstanding blockif request. 396 */ 397 error = blockif_cancel(p->bctx, &aior->io_req); 398 if (error != 0) 399 continue; 400 401 slot = aior->slot; 402 cfis = aior->cfis; 403 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED || 404 cfis[2] == ATA_READ_FPDMA_QUEUED) 405 ncq = 1; 406 407 if (ncq) 408 p->sact &= ~(1 << slot); 409 else 410 p->ci &= ~(1 << slot); 411 412 /* 413 * This command is now done. 414 */ 415 p->pending &= ~(1 << slot); 416 417 /* 418 * Delete the blockif request from the busy list 419 */ 420 TAILQ_REMOVE(&p->iobhd, aior, io_blist); 421 422 /* 423 * Move the blockif request back to the free list 424 */ 425 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist); 426 } 427 428 ahci_check_stopped(p); 429} 430 431static void 432ahci_port_reset(struct ahci_port *pr) 433{ 434 pr->sctl = 0; 435 pr->serr = 0; 436 pr->sact = 0; 437 pr->xfermode = ATA_UDMA6; 438 pr->mult_sectors = 128; 439 440 if (!pr->bctx) { 441 pr->ssts = ATA_SS_DET_NO_DEVICE; 442 pr->sig = 0xFFFFFFFF; 443 pr->tfd = 0x7F; 444 return; 445 } 446 pr->ssts = ATA_SS_DET_PHY_ONLINE | ATA_SS_SPD_GEN2 | 447 ATA_SS_IPM_ACTIVE; 448 pr->tfd = (1 << 8) | ATA_S_DSC | ATA_S_DMA; 449 if (!pr->atapi) { 450 pr->sig = PxSIG_ATA; 451 pr->tfd |= ATA_S_READY; 452 } else 453 pr->sig = PxSIG_ATAPI; 454 ahci_write_reset_fis_d2h(pr); 455} 456 457static void 458ahci_reset(struct pci_ahci_softc *sc) 459{ 460 int i; 461 462 sc->ghc = AHCI_GHC_AE; 463 sc->is = 0; 464 465 if (sc->lintr) { 466 pci_lintr_deassert(sc->asc_pi); 467 sc->lintr = 0; 468 } 469 470 for (i = 0; i < sc->ports; i++) { 471 sc->port[i].ie = 0; 472 sc->port[i].is = 0; 473 ahci_port_reset(&sc->port[i]); 474 } 475} 476 477static void 478ata_string(uint8_t *dest, const char *src, int len) 479{ 480 int i; 481 482 for (i = 0; i < len; i++) { 483 if (*src) 484 dest[i ^ 1] = *src++; 485 else 486 dest[i ^ 1] = ' '; 487 } 488} 489 490static void 491atapi_string(uint8_t *dest, const char *src, int len) 492{ 493 int i; 494 495 for (i = 0; i < len; i++) { 496 if (*src) 497 dest[i] = *src++; 498 else 499 dest[i] = ' '; 500 } 501} 502 503static void 504ahci_handle_dma(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done, 505 int seek) 506{ 507 struct ahci_ioreq *aior; 508 struct blockif_req *breq; 509 struct pci_ahci_softc *sc; 510 struct ahci_prdt_entry *prdt; 511 struct ahci_cmd_hdr *hdr; 512 uint64_t lba; 513 uint32_t len; 514 int i, err, iovcnt, ncq, readop; 515 516 sc = p->pr_sc; 517 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 518 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 519 ncq = 0; 520 readop = 1; 521 522 prdt += seek; 523 if (cfis[2] == ATA_WRITE_DMA || cfis[2] == ATA_WRITE_DMA48 || 524 cfis[2] == ATA_WRITE_FPDMA_QUEUED) 525 readop = 0; 526 527 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED || 528 cfis[2] == ATA_READ_FPDMA_QUEUED) { 529 lba = ((uint64_t)cfis[10] << 40) | 530 ((uint64_t)cfis[9] << 32) | 531 ((uint64_t)cfis[8] << 24) | 532 ((uint64_t)cfis[6] << 16) | 533 ((uint64_t)cfis[5] << 8) | 534 cfis[4]; 535 len = cfis[11] << 8 | cfis[3]; 536 if (!len) 537 len = 65536; 538 ncq = 1; 539 } else if (cfis[2] == ATA_READ_DMA48 || cfis[2] == ATA_WRITE_DMA48) { 540 lba = ((uint64_t)cfis[10] << 40) | 541 ((uint64_t)cfis[9] << 32) | 542 ((uint64_t)cfis[8] << 24) | 543 ((uint64_t)cfis[6] << 16) | 544 ((uint64_t)cfis[5] << 8) | 545 cfis[4]; 546 len = cfis[13] << 8 | cfis[12]; 547 if (!len) 548 len = 65536; 549 } else { 550 lba = ((cfis[7] & 0xf) << 24) | (cfis[6] << 16) | 551 (cfis[5] << 8) | cfis[4]; 552 len = cfis[12]; 553 if (!len) 554 len = 256; 555 } 556 lba *= blockif_sectsz(p->bctx); 557 len *= blockif_sectsz(p->bctx); 558 559 /* 560 * Pull request off free list 561 */ 562 aior = STAILQ_FIRST(&p->iofhd); 563 assert(aior != NULL); 564 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist); 565 aior->cfis = cfis; 566 aior->slot = slot; 567 aior->len = len; 568 aior->done = done; 569 breq = &aior->io_req; 570 breq->br_offset = lba + done; 571 iovcnt = hdr->prdtl - seek; 572 if (iovcnt > BLOCKIF_IOV_MAX) { 573 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX; 574 iovcnt = BLOCKIF_IOV_MAX; 575 } else 576 aior->prdtl = 0; 577 breq->br_iovcnt = iovcnt; 578 579 /* 580 * Mark this command in-flight. 581 */ 582 p->pending |= 1 << slot; 583 584 /* 585 * Stuff request onto busy list 586 */ 587 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist); 588 589 /* 590 * Build up the iovec based on the prdt 591 */ 592 for (i = 0; i < iovcnt; i++) { 593 uint32_t dbcsz; 594 595 dbcsz = (prdt->dbc & DBCMASK) + 1; 596 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc), 597 prdt->dba, dbcsz); 598 breq->br_iov[i].iov_len = dbcsz; 599 aior->done += dbcsz; 600 prdt++; 601 } 602 if (readop) 603 err = blockif_read(p->bctx, breq); 604 else 605 err = blockif_write(p->bctx, breq); 606 assert(err == 0); 607 608 if (ncq) 609 p->ci &= ~(1 << slot); 610} 611 612static void 613ahci_handle_flush(struct ahci_port *p, int slot, uint8_t *cfis) 614{ 615 struct ahci_ioreq *aior; 616 struct blockif_req *breq; 617 int err; 618 619 /* 620 * Pull request off free list 621 */ 622 aior = STAILQ_FIRST(&p->iofhd); 623 assert(aior != NULL); 624 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist); 625 aior->cfis = cfis; 626 aior->slot = slot; 627 aior->len = 0; 628 aior->done = 0; 629 aior->prdtl = 0; 630 breq = &aior->io_req; 631 632 /* 633 * Mark this command in-flight. 634 */ 635 p->pending |= 1 << slot; 636 637 /* 638 * Stuff request onto busy list 639 */ 640 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist); 641 642 err = blockif_flush(p->bctx, breq); 643 assert(err == 0); 644} 645 646static inline void 647read_prdt(struct ahci_port *p, int slot, uint8_t *cfis, 648 void *buf, int size) 649{ 650 struct ahci_cmd_hdr *hdr; 651 struct ahci_prdt_entry *prdt; 652 void *to; 653 int i, len; 654 655 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 656 len = size; 657 to = buf; 658 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 659 for (i = 0; i < hdr->prdtl && len; i++) { 660 uint8_t *ptr; 661 uint32_t dbcsz; 662 int sublen; 663 664 dbcsz = (prdt->dbc & DBCMASK) + 1; 665 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz); 666 sublen = len < dbcsz ? len : dbcsz; 667 memcpy(to, ptr, sublen); 668 len -= sublen; 669 to += sublen; 670 prdt++; 671 } 672} 673 674static void 675ahci_handle_dsm_trim(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done) 676{ 677 struct ahci_ioreq *aior; 678 struct blockif_req *breq; 679 uint8_t *entry; 680 uint64_t elba; 681 uint32_t len, elen; 682 int err; 683 uint8_t buf[512]; 684 685 len = (uint16_t)cfis[13] << 8 | cfis[12]; 686 len *= 512; 687 read_prdt(p, slot, cfis, buf, sizeof(buf)); 688 689next: 690 entry = &buf[done]; 691 elba = ((uint64_t)entry[5] << 40) | 692 ((uint64_t)entry[4] << 32) | 693 ((uint64_t)entry[3] << 24) | 694 ((uint64_t)entry[2] << 16) | 695 ((uint64_t)entry[1] << 8) | 696 entry[0]; 697 elen = (uint16_t)entry[7] << 8 | entry[6]; 698 done += 8; 699 if (elen == 0) { 700 if (done >= len) { 701 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 702 p->pending &= ~(1 << slot); 703 ahci_check_stopped(p); 704 return; 705 } 706 goto next; 707 } 708 709 /* 710 * Pull request off free list 711 */ 712 aior = STAILQ_FIRST(&p->iofhd); 713 assert(aior != NULL); 714 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist); 715 aior->cfis = cfis; 716 aior->slot = slot; 717 aior->len = len; 718 aior->done = done; 719 aior->prdtl = 0; 720 721 breq = &aior->io_req; 722 breq->br_offset = elba * blockif_sectsz(p->bctx); 723 breq->br_iovcnt = 1; 724 breq->br_iov[0].iov_len = elen * blockif_sectsz(p->bctx); 725 726 /* 727 * Mark this command in-flight. 728 */ 729 p->pending |= 1 << slot; 730 731 /* 732 * Stuff request onto busy list 733 */ 734 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist); 735 736 err = blockif_delete(p->bctx, breq); 737 assert(err == 0); 738} 739 740static inline void 741write_prdt(struct ahci_port *p, int slot, uint8_t *cfis, 742 void *buf, int size) 743{ 744 struct ahci_cmd_hdr *hdr; 745 struct ahci_prdt_entry *prdt; 746 void *from; 747 int i, len; 748 749 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 750 len = size; 751 from = buf; 752 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 753 for (i = 0; i < hdr->prdtl && len; i++) { 754 uint8_t *ptr; 755 uint32_t dbcsz; 756 int sublen; 757 758 dbcsz = (prdt->dbc & DBCMASK) + 1; 759 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz); 760 sublen = len < dbcsz ? len : dbcsz; 761 memcpy(ptr, from, sublen); 762 len -= sublen; 763 from += sublen; 764 prdt++; 765 } 766 hdr->prdbc = size - len; 767} 768 769static void 770handle_identify(struct ahci_port *p, int slot, uint8_t *cfis) 771{ 772 struct ahci_cmd_hdr *hdr; 773 774 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 775 if (p->atapi || hdr->prdtl == 0) { 776 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR; 777 p->is |= AHCI_P_IX_TFE; 778 } else { 779 uint16_t buf[256]; 780 uint64_t sectors; 781 int sectsz, psectsz, psectoff, candelete, ro; 782 uint16_t cyl; 783 uint8_t sech, heads; 784 785 ro = blockif_is_ro(p->bctx); 786 candelete = blockif_candelete(p->bctx); 787 sectsz = blockif_sectsz(p->bctx); 788 sectors = blockif_size(p->bctx) / sectsz; 789 blockif_chs(p->bctx, &cyl, &heads, &sech); 790 blockif_psectsz(p->bctx, &psectsz, &psectoff); 791 memset(buf, 0, sizeof(buf)); 792 buf[0] = 0x0040; 793 buf[1] = cyl; 794 buf[3] = heads; 795 buf[6] = sech; 796 /* TODO emulate different serial? */ 797 ata_string((uint8_t *)(buf+10), "123456", 20); 798 ata_string((uint8_t *)(buf+23), "001", 8); 799 ata_string((uint8_t *)(buf+27), "BHYVE SATA DISK", 40); 800 buf[47] = (0x8000 | 128); 801 buf[48] = 0x1; 802 buf[49] = (1 << 8 | 1 << 9 | 1 << 11); 803 buf[50] = (1 << 14); 804 buf[53] = (1 << 1 | 1 << 2); 805 if (p->mult_sectors) 806 buf[59] = (0x100 | p->mult_sectors); 807 buf[60] = sectors; 808 buf[61] = (sectors >> 16); 809 buf[63] = 0x7; 810 if (p->xfermode & ATA_WDMA0) 811 buf[63] |= (1 << ((p->xfermode & 7) + 8)); 812 buf[64] = 0x3; 813 buf[65] = 100; 814 buf[66] = 100; 815 buf[67] = 100; 816 buf[68] = 100; 817 buf[69] = 0; 818 buf[75] = 31; 819 buf[76] = (1 << 8 | 1 << 2); 820 buf[80] = 0x1f0; 821 buf[81] = 0x28; 822 buf[82] = (1 << 5 | 1 << 14); 823 buf[83] = (1 << 10 | 1 << 12 | 1 << 13 | 1 << 14); 824 buf[84] = (1 << 14); 825 buf[85] = (1 << 5 | 1 << 14); 826 buf[86] = (1 << 10 | 1 << 12 | 1 << 13); 827 buf[87] = (1 << 14); 828 buf[88] = 0x7f; 829 if (p->xfermode & ATA_UDMA0) 830 buf[88] |= (1 << ((p->xfermode & 7) + 8)); 831 buf[93] = (1 | 1 <<14); 832 buf[100] = sectors; 833 buf[101] = (sectors >> 16); 834 buf[102] = (sectors >> 32); 835 buf[103] = (sectors >> 48); 836 if (candelete && !ro) { 837 buf[69] |= ATA_SUPPORT_RZAT | ATA_SUPPORT_DRAT; 838 buf[105] = 1; 839 buf[169] = ATA_SUPPORT_DSM_TRIM; 840 } 841 buf[106] = 0x4000; 842 buf[209] = 0x4000; 843 if (psectsz > sectsz) { 844 buf[106] |= 0x2000; 845 buf[106] |= ffsl(psectsz / sectsz) - 1; 846 buf[209] |= (psectoff / sectsz); 847 } 848 if (sectsz > 512) { 849 buf[106] |= 0x1000; 850 buf[117] = sectsz / 2; 851 buf[118] = ((sectsz / 2) >> 16); 852 } 853 ahci_write_fis_piosetup(p); 854 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf)); 855 p->tfd = ATA_S_DSC | ATA_S_READY; 856 p->is |= AHCI_P_IX_DP; 857 p->ci &= ~(1 << slot); 858 } 859 ahci_generate_intr(p->pr_sc); 860} 861 862static void 863handle_atapi_identify(struct ahci_port *p, int slot, uint8_t *cfis) 864{ 865 if (!p->atapi) { 866 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR; 867 p->is |= AHCI_P_IX_TFE; 868 } else { 869 uint16_t buf[256]; 870 871 memset(buf, 0, sizeof(buf)); 872 buf[0] = (2 << 14 | 5 << 8 | 1 << 7 | 2 << 5); 873 /* TODO emulate different serial? */ 874 ata_string((uint8_t *)(buf+10), "123456", 20); 875 ata_string((uint8_t *)(buf+23), "001", 8); 876 ata_string((uint8_t *)(buf+27), "BHYVE SATA DVD ROM", 40); 877 buf[49] = (1 << 9 | 1 << 8); 878 buf[50] = (1 << 14 | 1); 879 buf[53] = (1 << 2 | 1 << 1); 880 buf[62] = 0x3f; 881 buf[63] = 7; 882 buf[64] = 3; 883 buf[65] = 100; 884 buf[66] = 100; 885 buf[67] = 100; 886 buf[68] = 100; 887 buf[76] = (1 << 2 | 1 << 1); 888 buf[78] = (1 << 5); 889 buf[80] = (0x1f << 4); 890 buf[82] = (1 << 4); 891 buf[83] = (1 << 14); 892 buf[84] = (1 << 14); 893 buf[85] = (1 << 4); 894 buf[87] = (1 << 14); 895 buf[88] = (1 << 14 | 0x7f); 896 ahci_write_fis_piosetup(p); 897 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf)); 898 p->tfd = ATA_S_DSC | ATA_S_READY; 899 p->is |= AHCI_P_IX_DHR; 900 p->ci &= ~(1 << slot); 901 } 902 ahci_generate_intr(p->pr_sc); 903} 904 905static void 906atapi_inquiry(struct ahci_port *p, int slot, uint8_t *cfis) 907{ 908 uint8_t buf[36]; 909 uint8_t *acmd; 910 int len; 911 912 acmd = cfis + 0x40; 913 914 buf[0] = 0x05; 915 buf[1] = 0x80; 916 buf[2] = 0x00; 917 buf[3] = 0x21; 918 buf[4] = 31; 919 buf[5] = 0; 920 buf[6] = 0; 921 buf[7] = 0; 922 atapi_string(buf + 8, "BHYVE", 8); 923 atapi_string(buf + 16, "BHYVE DVD-ROM", 16); 924 atapi_string(buf + 32, "001", 4); 925 926 len = sizeof(buf); 927 if (len > acmd[4]) 928 len = acmd[4]; 929 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 930 write_prdt(p, slot, cfis, buf, len); 931 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 932} 933 934static void 935atapi_read_capacity(struct ahci_port *p, int slot, uint8_t *cfis) 936{ 937 uint8_t buf[8]; 938 uint64_t sectors; 939 940 sectors = blockif_size(p->bctx) / 2048; 941 be32enc(buf, sectors - 1); 942 be32enc(buf + 4, 2048); 943 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 944 write_prdt(p, slot, cfis, buf, sizeof(buf)); 945 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 946} 947 948static void 949atapi_read_toc(struct ahci_port *p, int slot, uint8_t *cfis) 950{ 951 uint8_t *acmd; 952 uint8_t format; 953 int len; 954 955 acmd = cfis + 0x40; 956 957 len = be16dec(acmd + 7); 958 format = acmd[9] >> 6; 959 switch (format) { 960 case 0: 961 { 962 int msf, size; 963 uint64_t sectors; 964 uint8_t start_track, buf[20], *bp; 965 966 msf = (acmd[1] >> 1) & 1; 967 start_track = acmd[6]; 968 if (start_track > 1 && start_track != 0xaa) { 969 uint32_t tfd; 970 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 971 p->asc = 0x24; 972 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 973 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 974 ahci_write_fis_d2h(p, slot, cfis, tfd); 975 return; 976 } 977 bp = buf + 2; 978 *bp++ = 1; 979 *bp++ = 1; 980 if (start_track <= 1) { 981 *bp++ = 0; 982 *bp++ = 0x14; 983 *bp++ = 1; 984 *bp++ = 0; 985 if (msf) { 986 *bp++ = 0; 987 lba_to_msf(bp, 0); 988 bp += 3; 989 } else { 990 *bp++ = 0; 991 *bp++ = 0; 992 *bp++ = 0; 993 *bp++ = 0; 994 } 995 } 996 *bp++ = 0; 997 *bp++ = 0x14; 998 *bp++ = 0xaa; 999 *bp++ = 0; 1000 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx); 1001 sectors >>= 2; 1002 if (msf) { 1003 *bp++ = 0; 1004 lba_to_msf(bp, sectors); 1005 bp += 3; 1006 } else { 1007 be32enc(bp, sectors); 1008 bp += 4; 1009 } 1010 size = bp - buf; 1011 be16enc(buf, size - 2); 1012 if (len > size) 1013 len = size; 1014 write_prdt(p, slot, cfis, buf, len); 1015 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1016 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1017 break; 1018 } 1019 case 1: 1020 { 1021 uint8_t buf[12]; 1022 1023 memset(buf, 0, sizeof(buf)); 1024 buf[1] = 0xa; 1025 buf[2] = 0x1; 1026 buf[3] = 0x1; 1027 if (len > sizeof(buf)) 1028 len = sizeof(buf); 1029 write_prdt(p, slot, cfis, buf, len); 1030 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1031 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1032 break; 1033 } 1034 case 2: 1035 { 1036 int msf, size; 1037 uint64_t sectors; 1038 uint8_t start_track, *bp, buf[50]; 1039 1040 msf = (acmd[1] >> 1) & 1; 1041 start_track = acmd[6]; 1042 bp = buf + 2; 1043 *bp++ = 1; 1044 *bp++ = 1; 1045 1046 *bp++ = 1; 1047 *bp++ = 0x14; 1048 *bp++ = 0; 1049 *bp++ = 0xa0; 1050 *bp++ = 0; 1051 *bp++ = 0; 1052 *bp++ = 0; 1053 *bp++ = 0; 1054 *bp++ = 1; 1055 *bp++ = 0; 1056 *bp++ = 0; 1057 1058 *bp++ = 1; 1059 *bp++ = 0x14; 1060 *bp++ = 0; 1061 *bp++ = 0xa1; 1062 *bp++ = 0; 1063 *bp++ = 0; 1064 *bp++ = 0; 1065 *bp++ = 0; 1066 *bp++ = 1; 1067 *bp++ = 0; 1068 *bp++ = 0; 1069 1070 *bp++ = 1; 1071 *bp++ = 0x14; 1072 *bp++ = 0; 1073 *bp++ = 0xa2; 1074 *bp++ = 0; 1075 *bp++ = 0; 1076 *bp++ = 0; 1077 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx); 1078 sectors >>= 2; 1079 if (msf) { 1080 *bp++ = 0; 1081 lba_to_msf(bp, sectors); 1082 bp += 3; 1083 } else { 1084 be32enc(bp, sectors); 1085 bp += 4; 1086 } 1087 1088 *bp++ = 1; 1089 *bp++ = 0x14; 1090 *bp++ = 0; 1091 *bp++ = 1; 1092 *bp++ = 0; 1093 *bp++ = 0; 1094 *bp++ = 0; 1095 if (msf) { 1096 *bp++ = 0; 1097 lba_to_msf(bp, 0); 1098 bp += 3; 1099 } else { 1100 *bp++ = 0; 1101 *bp++ = 0; 1102 *bp++ = 0; 1103 *bp++ = 0; 1104 } 1105 1106 size = bp - buf; 1107 be16enc(buf, size - 2); 1108 if (len > size) 1109 len = size; 1110 write_prdt(p, slot, cfis, buf, len); 1111 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1112 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1113 break; 1114 } 1115 default: 1116 { 1117 uint32_t tfd; 1118 1119 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1120 p->asc = 0x24; 1121 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1122 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1123 ahci_write_fis_d2h(p, slot, cfis, tfd); 1124 break; 1125 } 1126 } 1127} 1128 1129static void 1130atapi_read(struct ahci_port *p, int slot, uint8_t *cfis, 1131 uint32_t done, int seek) 1132{ 1133 struct ahci_ioreq *aior; 1134 struct ahci_cmd_hdr *hdr; 1135 struct ahci_prdt_entry *prdt; 1136 struct blockif_req *breq; 1137 struct pci_ahci_softc *sc; 1138 uint8_t *acmd; 1139 uint64_t lba; 1140 uint32_t len; 1141 int i, err, iovcnt; 1142 1143 sc = p->pr_sc; 1144 acmd = cfis + 0x40; 1145 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 1146 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 1147 1148 prdt += seek; 1149 lba = be32dec(acmd + 2); 1150 if (acmd[0] == READ_10) 1151 len = be16dec(acmd + 7); 1152 else 1153 len = be32dec(acmd + 6); 1154 if (len == 0) { 1155 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1156 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1157 } 1158 lba *= 2048; 1159 len *= 2048; 1160 1161 /* 1162 * Pull request off free list 1163 */ 1164 aior = STAILQ_FIRST(&p->iofhd); 1165 assert(aior != NULL); 1166 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist); 1167 aior->cfis = cfis; 1168 aior->slot = slot; 1169 aior->len = len; 1170 aior->done = done; 1171 breq = &aior->io_req; 1172 breq->br_offset = lba + done; 1173 iovcnt = hdr->prdtl - seek; 1174 if (iovcnt > BLOCKIF_IOV_MAX) { 1175 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX; 1176 iovcnt = BLOCKIF_IOV_MAX; 1177 } else 1178 aior->prdtl = 0; 1179 breq->br_iovcnt = iovcnt; 1180 1181 /* 1182 * Mark this command in-flight. 1183 */ 1184 p->pending |= 1 << slot; 1185 1186 /* 1187 * Stuff request onto busy list 1188 */ 1189 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist); 1190 1191 /* 1192 * Build up the iovec based on the prdt 1193 */ 1194 for (i = 0; i < iovcnt; i++) { 1195 uint32_t dbcsz; 1196 1197 dbcsz = (prdt->dbc & DBCMASK) + 1; 1198 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc), 1199 prdt->dba, dbcsz); 1200 breq->br_iov[i].iov_len = dbcsz; 1201 aior->done += dbcsz; 1202 prdt++; 1203 } 1204 err = blockif_read(p->bctx, breq); 1205 assert(err == 0); 1206} 1207 1208static void 1209atapi_request_sense(struct ahci_port *p, int slot, uint8_t *cfis) 1210{ 1211 uint8_t buf[64]; 1212 uint8_t *acmd; 1213 int len; 1214 1215 acmd = cfis + 0x40; 1216 len = acmd[4]; 1217 if (len > sizeof(buf)) 1218 len = sizeof(buf); 1219 memset(buf, 0, len); 1220 buf[0] = 0x70 | (1 << 7); 1221 buf[2] = p->sense_key; 1222 buf[7] = 10; 1223 buf[12] = p->asc; 1224 write_prdt(p, slot, cfis, buf, len); 1225 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1226 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1227} 1228 1229static void 1230atapi_start_stop_unit(struct ahci_port *p, int slot, uint8_t *cfis) 1231{ 1232 uint8_t *acmd = cfis + 0x40; 1233 uint32_t tfd; 1234 1235 switch (acmd[4] & 3) { 1236 case 0: 1237 case 1: 1238 case 3: 1239 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1240 tfd = ATA_S_READY | ATA_S_DSC; 1241 break; 1242 case 2: 1243 /* TODO eject media */ 1244 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1245 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1246 p->asc = 0x53; 1247 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1248 break; 1249 } 1250 ahci_write_fis_d2h(p, slot, cfis, tfd); 1251} 1252 1253static void 1254atapi_mode_sense(struct ahci_port *p, int slot, uint8_t *cfis) 1255{ 1256 uint8_t *acmd; 1257 uint32_t tfd; 1258 uint8_t pc, code; 1259 int len; 1260 1261 acmd = cfis + 0x40; 1262 len = be16dec(acmd + 7); 1263 pc = acmd[2] >> 6; 1264 code = acmd[2] & 0x3f; 1265 1266 switch (pc) { 1267 case 0: 1268 switch (code) { 1269 case MODEPAGE_RW_ERROR_RECOVERY: 1270 { 1271 uint8_t buf[16]; 1272 1273 if (len > sizeof(buf)) 1274 len = sizeof(buf); 1275 1276 memset(buf, 0, sizeof(buf)); 1277 be16enc(buf, 16 - 2); 1278 buf[2] = 0x70; 1279 buf[8] = 0x01; 1280 buf[9] = 16 - 10; 1281 buf[11] = 0x05; 1282 write_prdt(p, slot, cfis, buf, len); 1283 tfd = ATA_S_READY | ATA_S_DSC; 1284 break; 1285 } 1286 case MODEPAGE_CD_CAPABILITIES: 1287 { 1288 uint8_t buf[30]; 1289 1290 if (len > sizeof(buf)) 1291 len = sizeof(buf); 1292 1293 memset(buf, 0, sizeof(buf)); 1294 be16enc(buf, 30 - 2); 1295 buf[2] = 0x70; 1296 buf[8] = 0x2A; 1297 buf[9] = 30 - 10; 1298 buf[10] = 0x08; 1299 buf[12] = 0x71; 1300 be16enc(&buf[18], 2); 1301 be16enc(&buf[20], 512); 1302 write_prdt(p, slot, cfis, buf, len); 1303 tfd = ATA_S_READY | ATA_S_DSC; 1304 break; 1305 } 1306 default: 1307 goto error; 1308 break; 1309 } 1310 break; 1311 case 3: 1312 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1313 p->asc = 0x39; 1314 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1315 break; 1316error: 1317 case 1: 1318 case 2: 1319 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1320 p->asc = 0x24; 1321 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1322 break; 1323 } 1324 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1325 ahci_write_fis_d2h(p, slot, cfis, tfd); 1326} 1327 1328static void 1329atapi_get_event_status_notification(struct ahci_port *p, int slot, 1330 uint8_t *cfis) 1331{ 1332 uint8_t *acmd; 1333 uint32_t tfd; 1334 1335 acmd = cfis + 0x40; 1336 1337 /* we don't support asynchronous operation */ 1338 if (!(acmd[1] & 1)) { 1339 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1340 p->asc = 0x24; 1341 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1342 } else { 1343 uint8_t buf[8]; 1344 int len; 1345 1346 len = be16dec(acmd + 7); 1347 if (len > sizeof(buf)) 1348 len = sizeof(buf); 1349 1350 memset(buf, 0, sizeof(buf)); 1351 be16enc(buf, 8 - 2); 1352 buf[2] = 0x04; 1353 buf[3] = 0x10; 1354 buf[5] = 0x02; 1355 write_prdt(p, slot, cfis, buf, len); 1356 tfd = ATA_S_READY | ATA_S_DSC; 1357 } 1358 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1359 ahci_write_fis_d2h(p, slot, cfis, tfd); 1360} 1361 1362static void 1363handle_packet_cmd(struct ahci_port *p, int slot, uint8_t *cfis) 1364{ 1365 uint8_t *acmd; 1366 1367 acmd = cfis + 0x40; 1368 1369#ifdef AHCI_DEBUG 1370 { 1371 int i; 1372 DPRINTF("ACMD:"); 1373 for (i = 0; i < 16; i++) 1374 DPRINTF("%02x ", acmd[i]); 1375 DPRINTF("\n"); 1376 } 1377#endif 1378 1379 switch (acmd[0]) { 1380 case TEST_UNIT_READY: 1381 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1382 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1383 break; 1384 case INQUIRY: 1385 atapi_inquiry(p, slot, cfis); 1386 break; 1387 case READ_CAPACITY: 1388 atapi_read_capacity(p, slot, cfis); 1389 break; 1390 case PREVENT_ALLOW: 1391 /* TODO */ 1392 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1393 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1394 break; 1395 case READ_TOC: 1396 atapi_read_toc(p, slot, cfis); 1397 break; 1398 case READ_10: 1399 case READ_12: 1400 atapi_read(p, slot, cfis, 0, 0); 1401 break; 1402 case REQUEST_SENSE: 1403 atapi_request_sense(p, slot, cfis); 1404 break; 1405 case START_STOP_UNIT: 1406 atapi_start_stop_unit(p, slot, cfis); 1407 break; 1408 case MODE_SENSE_10: 1409 atapi_mode_sense(p, slot, cfis); 1410 break; 1411 case GET_EVENT_STATUS_NOTIFICATION: 1412 atapi_get_event_status_notification(p, slot, cfis); 1413 break; 1414 default: 1415 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1416 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1417 p->asc = 0x20; 1418 ahci_write_fis_d2h(p, slot, cfis, (p->sense_key << 12) | 1419 ATA_S_READY | ATA_S_ERROR); 1420 break; 1421 } 1422} 1423 1424static void 1425ahci_handle_cmd(struct ahci_port *p, int slot, uint8_t *cfis) 1426{ 1427 1428 switch (cfis[2]) { 1429 case ATA_ATA_IDENTIFY: 1430 handle_identify(p, slot, cfis); 1431 break; 1432 case ATA_SETFEATURES: 1433 { 1434 switch (cfis[3]) { 1435 case ATA_SF_ENAB_SATA_SF: 1436 switch (cfis[12]) { 1437 case ATA_SATA_SF_AN: 1438 p->tfd = ATA_S_DSC | ATA_S_READY; 1439 break; 1440 default: 1441 p->tfd = ATA_S_ERROR | ATA_S_READY; 1442 p->tfd |= (ATA_ERROR_ABORT << 8); 1443 break; 1444 } 1445 break; 1446 case ATA_SF_ENAB_WCACHE: 1447 case ATA_SF_DIS_WCACHE: 1448 case ATA_SF_ENAB_RCACHE: 1449 case ATA_SF_DIS_RCACHE: 1450 p->tfd = ATA_S_DSC | ATA_S_READY; 1451 break; 1452 case ATA_SF_SETXFER: 1453 { 1454 switch (cfis[12] & 0xf8) { 1455 case ATA_PIO: 1456 case ATA_PIO0: 1457 break; 1458 case ATA_WDMA0: 1459 case ATA_UDMA0: 1460 p->xfermode = (cfis[12] & 0x7); 1461 break; 1462 } 1463 p->tfd = ATA_S_DSC | ATA_S_READY; 1464 break; 1465 } 1466 default: 1467 p->tfd = ATA_S_ERROR | ATA_S_READY; 1468 p->tfd |= (ATA_ERROR_ABORT << 8); 1469 break; 1470 } 1471 ahci_write_fis_d2h(p, slot, cfis, p->tfd); 1472 break; 1473 } 1474 case ATA_SET_MULTI: 1475 if (cfis[12] != 0 && 1476 (cfis[12] > 128 || (cfis[12] & (cfis[12] - 1)))) { 1477 p->tfd = ATA_S_ERROR | ATA_S_READY; 1478 p->tfd |= (ATA_ERROR_ABORT << 8); 1479 } else { 1480 p->mult_sectors = cfis[12]; 1481 p->tfd = ATA_S_DSC | ATA_S_READY; 1482 } 1483 p->is |= AHCI_P_IX_DP; 1484 p->ci &= ~(1 << slot); 1485 ahci_generate_intr(p->pr_sc); 1486 break; 1487 case ATA_READ_DMA: 1488 case ATA_WRITE_DMA: 1489 case ATA_READ_DMA48: 1490 case ATA_WRITE_DMA48: 1491 case ATA_READ_FPDMA_QUEUED: 1492 case ATA_WRITE_FPDMA_QUEUED: 1493 ahci_handle_dma(p, slot, cfis, 0, 0); 1494 break; 1495 case ATA_FLUSHCACHE: 1496 case ATA_FLUSHCACHE48: 1497 ahci_handle_flush(p, slot, cfis); 1498 break; 1499 case ATA_DATA_SET_MANAGEMENT: 1500 if (cfis[11] == 0 && cfis[3] == ATA_DSM_TRIM && 1501 cfis[13] == 0 && cfis[12] == 1) { 1502 ahci_handle_dsm_trim(p, slot, cfis, 0); 1503 break; 1504 } 1505 ahci_write_fis_d2h(p, slot, cfis, 1506 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 1507 break; 1508 case ATA_STANDBY_CMD: 1509 break; 1510 case ATA_NOP: 1511 case ATA_STANDBY_IMMEDIATE: 1512 case ATA_IDLE_IMMEDIATE: 1513 case ATA_SLEEP: 1514 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1515 break; 1516 case ATA_ATAPI_IDENTIFY: 1517 handle_atapi_identify(p, slot, cfis); 1518 break; 1519 case ATA_PACKET_CMD: 1520 if (!p->atapi) { 1521 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR; 1522 p->is |= AHCI_P_IX_TFE; 1523 ahci_generate_intr(p->pr_sc); 1524 } else 1525 handle_packet_cmd(p, slot, cfis); 1526 break; 1527 default: 1528 WPRINTF("Unsupported cmd:%02x\n", cfis[2]); 1529 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR; 1530 p->is |= AHCI_P_IX_TFE; 1531 ahci_generate_intr(p->pr_sc); 1532 break; 1533 } 1534} 1535 1536static void 1537ahci_handle_slot(struct ahci_port *p, int slot) 1538{ 1539 struct ahci_cmd_hdr *hdr; 1540 struct ahci_prdt_entry *prdt; 1541 struct pci_ahci_softc *sc; 1542 uint8_t *cfis; 1543 int cfl; 1544 1545 sc = p->pr_sc; 1546 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 1547 cfl = (hdr->flags & 0x1f) * 4; 1548 cfis = paddr_guest2host(ahci_ctx(sc), hdr->ctba, 1549 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry)); 1550 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 1551 1552#ifdef AHCI_DEBUG 1553 DPRINTF("\ncfis:"); 1554 for (i = 0; i < cfl; i++) { 1555 if (i % 10 == 0) 1556 DPRINTF("\n"); 1557 DPRINTF("%02x ", cfis[i]); 1558 } 1559 DPRINTF("\n"); 1560 1561 for (i = 0; i < hdr->prdtl; i++) { 1562 DPRINTF("%d@%08"PRIx64"\n", prdt->dbc & 0x3fffff, prdt->dba); 1563 prdt++; 1564 } 1565#endif 1566 1567 if (cfis[0] != FIS_TYPE_REGH2D) { 1568 WPRINTF("Not a H2D FIS:%02x\n", cfis[0]); 1569 return; 1570 } 1571 1572 if (cfis[1] & 0x80) { 1573 ahci_handle_cmd(p, slot, cfis); 1574 } else { 1575 if (cfis[15] & (1 << 2)) 1576 p->reset = 1; 1577 else if (p->reset) { 1578 p->reset = 0; 1579 ahci_port_reset(p); 1580 } 1581 p->ci &= ~(1 << slot); 1582 } 1583} 1584 1585static void 1586ahci_handle_port(struct ahci_port *p) 1587{ 1588 int i; 1589 1590 if (!(p->cmd & AHCI_P_CMD_ST)) 1591 return; 1592 1593 /* 1594 * Search for any new commands to issue ignoring those that 1595 * are already in-flight. 1596 */ 1597 for (i = 0; (i < 32) && p->ci; i++) { 1598 if ((p->ci & (1 << i)) && !(p->pending & (1 << i))) { 1599 p->cmd &= ~AHCI_P_CMD_CCS_MASK; 1600 p->cmd |= i << AHCI_P_CMD_CCS_SHIFT; 1601 ahci_handle_slot(p, i); 1602 } 1603 } 1604} 1605 1606/* 1607 * blockif callback routine - this runs in the context of the blockif 1608 * i/o thread, so the mutex needs to be acquired. 1609 */ 1610static void 1611ata_ioreq_cb(struct blockif_req *br, int err) 1612{ 1613 struct ahci_cmd_hdr *hdr; 1614 struct ahci_ioreq *aior; 1615 struct ahci_port *p; 1616 struct pci_ahci_softc *sc; 1617 uint32_t tfd; 1618 uint8_t *cfis; 1619 int pending, slot, ncq, dsm; 1620 1621 DPRINTF("%s %d\n", __func__, err); 1622 1623 ncq = dsm = 0; 1624 aior = br->br_param; 1625 p = aior->io_pr; 1626 cfis = aior->cfis; 1627 slot = aior->slot; 1628 pending = aior->prdtl; 1629 sc = p->pr_sc; 1630 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 1631 1632 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED || 1633 cfis[2] == ATA_READ_FPDMA_QUEUED) 1634 ncq = 1; 1635 if (cfis[2] == ATA_DATA_SET_MANAGEMENT) 1636 dsm = 1; 1637 1638 pthread_mutex_lock(&sc->mtx); 1639 1640 /* 1641 * Delete the blockif request from the busy list 1642 */ 1643 TAILQ_REMOVE(&p->iobhd, aior, io_blist); 1644 1645 /* 1646 * Move the blockif request back to the free list 1647 */ 1648 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist); 1649 1650 if (dsm) { 1651 if (aior->done != aior->len && !err) { 1652 ahci_handle_dsm_trim(p, slot, cfis, aior->done); 1653 goto out; 1654 } 1655 } else { 1656 if (pending && !err) { 1657 ahci_handle_dma(p, slot, cfis, aior->done, 1658 hdr->prdtl - pending); 1659 goto out; 1660 } 1661 } 1662 1663 if (!err && aior->done == aior->len) { 1664 tfd = ATA_S_READY | ATA_S_DSC; 1665 if (ncq) 1666 hdr->prdbc = 0; 1667 else 1668 hdr->prdbc = aior->len; 1669 } else { 1670 tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR; 1671 hdr->prdbc = 0; 1672 if (ncq) 1673 p->serr |= (1 << slot); 1674 } 1675 1676 if (ncq) { 1677 p->sact &= ~(1 << slot); 1678 ahci_write_fis_sdb(p, slot, tfd); 1679 } else 1680 ahci_write_fis_d2h(p, slot, cfis, tfd); 1681 1682 /* 1683 * This command is now complete. 1684 */ 1685 p->pending &= ~(1 << slot); 1686 1687 ahci_check_stopped(p); 1688out: 1689 pthread_mutex_unlock(&sc->mtx); 1690 DPRINTF("%s exit\n", __func__); 1691} 1692 1693static void 1694atapi_ioreq_cb(struct blockif_req *br, int err) 1695{ 1696 struct ahci_cmd_hdr *hdr; 1697 struct ahci_ioreq *aior; 1698 struct ahci_port *p; 1699 struct pci_ahci_softc *sc; 1700 uint8_t *cfis; 1701 uint32_t tfd; 1702 int pending, slot; 1703 1704 DPRINTF("%s %d\n", __func__, err); 1705 1706 aior = br->br_param; 1707 p = aior->io_pr; 1708 cfis = aior->cfis; 1709 slot = aior->slot; 1710 pending = aior->prdtl; 1711 sc = p->pr_sc; 1712 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + aior->slot * AHCI_CL_SIZE); 1713 1714 pthread_mutex_lock(&sc->mtx); 1715 1716 /* 1717 * Delete the blockif request from the busy list 1718 */ 1719 TAILQ_REMOVE(&p->iobhd, aior, io_blist); 1720 1721 /* 1722 * Move the blockif request back to the free list 1723 */ 1724 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist); 1725 1726 if (pending && !err) { 1727 atapi_read(p, slot, cfis, aior->done, hdr->prdtl - pending); 1728 goto out; 1729 } 1730 1731 if (!err && aior->done == aior->len) { 1732 tfd = ATA_S_READY | ATA_S_DSC; 1733 hdr->prdbc = aior->len; 1734 } else { 1735 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1736 p->asc = 0x21; 1737 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1738 hdr->prdbc = 0; 1739 } 1740 1741 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1742 ahci_write_fis_d2h(p, slot, cfis, tfd); 1743 1744 /* 1745 * This command is now complete. 1746 */ 1747 p->pending &= ~(1 << slot); 1748 1749 ahci_check_stopped(p); 1750out: 1751 pthread_mutex_unlock(&sc->mtx); 1752 DPRINTF("%s exit\n", __func__); 1753} 1754 1755static void 1756pci_ahci_ioreq_init(struct ahci_port *pr) 1757{ 1758 struct ahci_ioreq *vr; 1759 int i; 1760 1761 pr->ioqsz = blockif_queuesz(pr->bctx); 1762 pr->ioreq = calloc(pr->ioqsz, sizeof(struct ahci_ioreq)); 1763 STAILQ_INIT(&pr->iofhd); 1764 1765 /* 1766 * Add all i/o request entries to the free queue 1767 */ 1768 for (i = 0; i < pr->ioqsz; i++) { 1769 vr = &pr->ioreq[i]; 1770 vr->io_pr = pr; 1771 if (!pr->atapi) 1772 vr->io_req.br_callback = ata_ioreq_cb; 1773 else 1774 vr->io_req.br_callback = atapi_ioreq_cb; 1775 vr->io_req.br_param = vr; 1776 STAILQ_INSERT_TAIL(&pr->iofhd, vr, io_flist); 1777 } 1778 1779 TAILQ_INIT(&pr->iobhd); 1780} 1781 1782static void 1783pci_ahci_port_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value) 1784{ 1785 int port = (offset - AHCI_OFFSET) / AHCI_STEP; 1786 offset = (offset - AHCI_OFFSET) % AHCI_STEP; 1787 struct ahci_port *p = &sc->port[port]; 1788 1789 DPRINTF("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"\n", 1790 port, offset, value); 1791 1792 switch (offset) { 1793 case AHCI_P_CLB: 1794 p->clb = value; 1795 break; 1796 case AHCI_P_CLBU: 1797 p->clbu = value; 1798 break; 1799 case AHCI_P_FB: 1800 p->fb = value; 1801 break; 1802 case AHCI_P_FBU: 1803 p->fbu = value; 1804 break; 1805 case AHCI_P_IS: 1806 p->is &= ~value; 1807 break; 1808 case AHCI_P_IE: 1809 p->ie = value & 0xFDC000FF; 1810 ahci_generate_intr(sc); 1811 break; 1812 case AHCI_P_CMD: 1813 { 1814 p->cmd = value; 1815 1816 if (!(value & AHCI_P_CMD_ST)) { 1817 ahci_port_stop(p); 1818 } else { 1819 uint64_t clb; 1820 1821 p->cmd |= AHCI_P_CMD_CR; 1822 clb = (uint64_t)p->clbu << 32 | p->clb; 1823 p->cmd_lst = paddr_guest2host(ahci_ctx(sc), clb, 1824 AHCI_CL_SIZE * AHCI_MAX_SLOTS); 1825 } 1826 1827 if (value & AHCI_P_CMD_FRE) { 1828 uint64_t fb; 1829 1830 p->cmd |= AHCI_P_CMD_FR; 1831 fb = (uint64_t)p->fbu << 32 | p->fb; 1832 /* we don't support FBSCP, so rfis size is 256Bytes */ 1833 p->rfis = paddr_guest2host(ahci_ctx(sc), fb, 256); 1834 } else { 1835 p->cmd &= ~AHCI_P_CMD_FR; 1836 } 1837 1838 if (value & AHCI_P_CMD_CLO) { 1839 p->tfd = 0; 1840 p->cmd &= ~AHCI_P_CMD_CLO; 1841 } 1842 1843 ahci_handle_port(p); 1844 break; 1845 } 1846 case AHCI_P_TFD: 1847 case AHCI_P_SIG: 1848 case AHCI_P_SSTS: 1849 WPRINTF("pci_ahci_port: read only registers 0x%"PRIx64"\n", offset); 1850 break; 1851 case AHCI_P_SCTL: 1852 if (!(p->cmd & AHCI_P_CMD_ST)) { 1853 if (value & ATA_SC_DET_RESET) 1854 ahci_port_reset(p); 1855 p->sctl = value; 1856 } 1857 break; 1858 case AHCI_P_SERR: 1859 p->serr &= ~value; 1860 break; 1861 case AHCI_P_SACT: 1862 p->sact |= value; 1863 break; 1864 case AHCI_P_CI: 1865 p->ci |= value; 1866 ahci_handle_port(p); 1867 break; 1868 case AHCI_P_SNTF: 1869 case AHCI_P_FBS: 1870 default: 1871 break; 1872 } 1873} 1874 1875static void 1876pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value) 1877{ 1878 DPRINTF("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"\n", 1879 offset, value); 1880 1881 switch (offset) { 1882 case AHCI_CAP: 1883 case AHCI_PI: 1884 case AHCI_VS: 1885 case AHCI_CAP2: 1886 DPRINTF("pci_ahci_host: read only registers 0x%"PRIx64"\n", offset); 1887 break; 1888 case AHCI_GHC: 1889 if (value & AHCI_GHC_HR) 1890 ahci_reset(sc); 1891 else if (value & AHCI_GHC_IE) { 1892 sc->ghc |= AHCI_GHC_IE; 1893 ahci_generate_intr(sc); 1894 } 1895 break; 1896 case AHCI_IS: 1897 sc->is &= ~value; 1898 ahci_generate_intr(sc); 1899 break; 1900 default: 1901 break; 1902 } 1903} 1904 1905static void 1906pci_ahci_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, 1907 int baridx, uint64_t offset, int size, uint64_t value) 1908{ 1909 struct pci_ahci_softc *sc = pi->pi_arg; 1910 1911 assert(baridx == 5); 1912 assert(size == 4); 1913 1914 pthread_mutex_lock(&sc->mtx); 1915 1916 if (offset < AHCI_OFFSET) 1917 pci_ahci_host_write(sc, offset, value); 1918 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP) 1919 pci_ahci_port_write(sc, offset, value); 1920 else 1921 WPRINTF("pci_ahci: unknown i/o write offset 0x%"PRIx64"\n", offset); 1922 1923 pthread_mutex_unlock(&sc->mtx); 1924} 1925 1926static uint64_t 1927pci_ahci_host_read(struct pci_ahci_softc *sc, uint64_t offset) 1928{ 1929 uint32_t value; 1930 1931 switch (offset) { 1932 case AHCI_CAP: 1933 case AHCI_GHC: 1934 case AHCI_IS: 1935 case AHCI_PI: 1936 case AHCI_VS: 1937 case AHCI_CCCC: 1938 case AHCI_CCCP: 1939 case AHCI_EM_LOC: 1940 case AHCI_EM_CTL: 1941 case AHCI_CAP2: 1942 { 1943 uint32_t *p = &sc->cap; 1944 p += (offset - AHCI_CAP) / sizeof(uint32_t); 1945 value = *p; 1946 break; 1947 } 1948 default: 1949 value = 0; 1950 break; 1951 } 1952 DPRINTF("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x\n", 1953 offset, value); 1954 1955 return (value); 1956} 1957 1958static uint64_t 1959pci_ahci_port_read(struct pci_ahci_softc *sc, uint64_t offset) 1960{ 1961 uint32_t value; 1962 int port = (offset - AHCI_OFFSET) / AHCI_STEP; 1963 offset = (offset - AHCI_OFFSET) % AHCI_STEP; 1964 1965 switch (offset) { 1966 case AHCI_P_CLB: 1967 case AHCI_P_CLBU: 1968 case AHCI_P_FB: 1969 case AHCI_P_FBU: 1970 case AHCI_P_IS: 1971 case AHCI_P_IE: 1972 case AHCI_P_CMD: 1973 case AHCI_P_TFD: 1974 case AHCI_P_SIG: 1975 case AHCI_P_SSTS: 1976 case AHCI_P_SCTL: 1977 case AHCI_P_SERR: 1978 case AHCI_P_SACT: 1979 case AHCI_P_CI: 1980 case AHCI_P_SNTF: 1981 case AHCI_P_FBS: 1982 { 1983 uint32_t *p= &sc->port[port].clb; 1984 p += (offset - AHCI_P_CLB) / sizeof(uint32_t); 1985 value = *p; 1986 break; 1987 } 1988 default: 1989 value = 0; 1990 break; 1991 } 1992 1993 DPRINTF("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x\n", 1994 port, offset, value); 1995 1996 return value; 1997} 1998 1999static uint64_t 2000pci_ahci_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 2001 uint64_t offset, int size) 2002{ 2003 struct pci_ahci_softc *sc = pi->pi_arg; 2004 uint32_t value; 2005 2006 assert(baridx == 5); 2007 assert(size == 4); 2008 2009 pthread_mutex_lock(&sc->mtx); 2010 2011 if (offset < AHCI_OFFSET) 2012 value = pci_ahci_host_read(sc, offset); 2013 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP) 2014 value = pci_ahci_port_read(sc, offset); 2015 else { 2016 value = 0; 2017 WPRINTF("pci_ahci: unknown i/o read offset 0x%"PRIx64"\n", offset); 2018 } 2019 2020 pthread_mutex_unlock(&sc->mtx); 2021 2022 return (value); 2023} 2024 2025static int 2026pci_ahci_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts, int atapi) 2027{ 2028 char bident[sizeof("XX:X:X")]; 2029 struct blockif_ctxt *bctxt; 2030 struct pci_ahci_softc *sc; 2031 int ret, slots; 2032 2033 ret = 0; 2034 2035 if (opts == NULL) { 2036 fprintf(stderr, "pci_ahci: backing device required\n"); 2037 return (1); 2038 } 2039 2040#ifdef AHCI_DEBUG 2041 dbg = fopen("/tmp/log", "w+"); 2042#endif 2043 2044 sc = calloc(1, sizeof(struct pci_ahci_softc)); 2045 pi->pi_arg = sc; 2046 sc->asc_pi = pi; 2047 sc->ports = MAX_PORTS; 2048 2049 /* 2050 * Only use port 0 for a backing device. All other ports will be 2051 * marked as unused 2052 */ 2053 sc->port[0].atapi = atapi; 2054 2055 /* 2056 * Attempt to open the backing image. Use the PCI 2057 * slot/func for the identifier string. 2058 */ 2059 snprintf(bident, sizeof(bident), "%d:%d", pi->pi_slot, pi->pi_func); 2060 bctxt = blockif_open(opts, bident); 2061 if (bctxt == NULL) { 2062 ret = 1; 2063 goto open_fail; 2064 } 2065 sc->port[0].bctx = bctxt; 2066 sc->port[0].pr_sc = sc; 2067 2068 /* 2069 * Allocate blockif request structures and add them 2070 * to the free list 2071 */ 2072 pci_ahci_ioreq_init(&sc->port[0]); 2073 2074 pthread_mutex_init(&sc->mtx, NULL); 2075 2076 /* Intel ICH8 AHCI */ 2077 slots = sc->port[0].ioqsz; 2078 if (slots > 32) 2079 slots = 32; 2080 --slots; 2081 sc->cap = AHCI_CAP_64BIT | AHCI_CAP_SNCQ | AHCI_CAP_SSNTF | 2082 AHCI_CAP_SMPS | AHCI_CAP_SSS | AHCI_CAP_SALP | 2083 AHCI_CAP_SAL | AHCI_CAP_SCLO | (0x3 << AHCI_CAP_ISS_SHIFT)| 2084 AHCI_CAP_PMD | AHCI_CAP_SSC | AHCI_CAP_PSC | 2085 (slots << AHCI_CAP_NCS_SHIFT) | AHCI_CAP_SXS | (sc->ports - 1); 2086 2087 /* Only port 0 implemented */ 2088 sc->pi = 1; 2089 sc->vs = 0x10300; 2090 sc->cap2 = AHCI_CAP2_APST; 2091 ahci_reset(sc); 2092 2093 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x2821); 2094 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086); 2095 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_STORAGE); 2096 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_STORAGE_SATA); 2097 pci_set_cfgdata8(pi, PCIR_PROGIF, PCIP_STORAGE_SATA_AHCI_1_0); 2098 pci_emul_add_msicap(pi, 1); 2099 pci_emul_alloc_bar(pi, 5, PCIBAR_MEM32, 2100 AHCI_OFFSET + sc->ports * AHCI_STEP); 2101 2102 pci_lintr_request(pi); 2103 2104open_fail: 2105 if (ret) { 2106 blockif_close(sc->port[0].bctx); 2107 free(sc); 2108 } 2109 2110 return (ret); 2111} 2112 2113static int 2114pci_ahci_hd_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts) 2115{ 2116 2117 return (pci_ahci_init(ctx, pi, opts, 0)); 2118} 2119 2120static int 2121pci_ahci_atapi_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts) 2122{ 2123 2124 return (pci_ahci_init(ctx, pi, opts, 1)); 2125} 2126 2127/* 2128 * Use separate emulation names to distinguish drive and atapi devices 2129 */ 2130struct pci_devemu pci_de_ahci_hd = { 2131 .pe_emu = "ahci-hd", 2132 .pe_init = pci_ahci_hd_init, 2133 .pe_barwrite = pci_ahci_write, 2134 .pe_barread = pci_ahci_read 2135}; 2136PCI_EMUL_SET(pci_de_ahci_hd); 2137 2138struct pci_devemu pci_de_ahci_cd = { 2139 .pe_emu = "ahci-cd", 2140 .pe_init = pci_ahci_atapi_init, 2141 .pe_barwrite = pci_ahci_write, 2142 .pe_barread = pci_ahci_read 2143}; 2144PCI_EMUL_SET(pci_de_ahci_cd); 2145