identcpu.c revision 295789
1187767Sluigi/*- 2187767Sluigi * Copyright (c) 1992 Terrence R. Lambert. 3187767Sluigi * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 4187767Sluigi * Copyright (c) 1997 KATO Takenori. 5187767Sluigi * All rights reserved. 6187767Sluigi * 7187767Sluigi * This code is derived from software contributed to Berkeley by 8187767Sluigi * William Jolitz. 9187767Sluigi * 10187767Sluigi * Redistribution and use in source and binary forms, with or without 11187767Sluigi * modification, are permitted provided that the following conditions 12187767Sluigi * are met: 13187767Sluigi * 1. Redistributions of source code must retain the above copyright 14187767Sluigi * notice, this list of conditions and the following disclaimer. 15187767Sluigi * 2. Redistributions in binary form must reproduce the above copyright 16187767Sluigi * notice, this list of conditions and the following disclaimer in the 17187767Sluigi * documentation and/or other materials provided with the distribution. 18187767Sluigi * 3. All advertising materials mentioning features or use of this software 19187767Sluigi * must display the following acknowledgement: 20187767Sluigi * This product includes software developed by the University of 21187767Sluigi * California, Berkeley and its contributors. 22187767Sluigi * 4. Neither the name of the University nor the names of its contributors 23187767Sluigi * may be used to endorse or promote products derived from this software 24187767Sluigi * without specific prior written permission. 25187767Sluigi * 26187767Sluigi * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27187767Sluigi * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28187767Sluigi * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29187767Sluigi * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30187767Sluigi * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31187767Sluigi * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32187767Sluigi * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33187767Sluigi * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34187767Sluigi * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35187767Sluigi * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36187767Sluigi * SUCH DAMAGE. 37187767Sluigi * 38204591Sluigi * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp 39187767Sluigi */ 40187767Sluigi 41187767Sluigi#include <sys/cdefs.h> 42187767Sluigi__FBSDID("$FreeBSD: stable/10/sys/x86/x86/identcpu.c 295789 2016-02-19 02:03:14Z sephe $"); 43187767Sluigi 44187767Sluigi#include "opt_cpu.h" 45187767Sluigi 46187767Sluigi#include <sys/param.h> 47187767Sluigi#include <sys/bus.h> 48187767Sluigi#include <sys/cpu.h> 49187767Sluigi#include <sys/eventhandler.h> 50187767Sluigi#include <sys/limits.h> 51187767Sluigi#include <sys/systm.h> 52187767Sluigi#include <sys/kernel.h> 53187767Sluigi#include <sys/sysctl.h> 54187767Sluigi#include <sys/power.h> 55187767Sluigi 56187767Sluigi#include <machine/asmacros.h> 57187767Sluigi#include <machine/clock.h> 58187767Sluigi#include <machine/cputypes.h> 59187767Sluigi#include <machine/frame.h> 60187767Sluigi#include <machine/intr_machdep.h> 61187767Sluigi#include <machine/md_var.h> 62187767Sluigi#include <machine/segments.h> 63187767Sluigi#include <machine/specialreg.h> 64187767Sluigi 65187767Sluigi#include <amd64/vmm/intel/vmx_controls.h> 66187767Sluigi#include <x86/isa/icu.h> 67187767Sluigi#include <x86/vmware.h> 68187767Sluigi 69187767Sluigi#ifdef __i386__ 70187767Sluigi#define IDENTBLUE_CYRIX486 0 71187767Sluigi#define IDENTBLUE_IBMCPU 1 72187767Sluigi#define IDENTBLUE_CYRIXM2 2 73187767Sluigi 74187769Sluigistatic void identifycyrix(void); 75187769Sluigistatic void print_transmeta_info(void); 76187769Sluigi#endif 77187769Sluigistatic u_int find_cpu_vendor_id(void); 78187769Sluigistatic void print_AMD_info(void); 79187769Sluigistatic void print_INTEL_info(void); 80187769Sluigistatic void print_INTEL_TLB(u_int data); 81187769Sluigistatic void print_hypervisor_info(void); 82187769Sluigistatic void print_svm_info(void); 83187769Sluigistatic void print_via_padlock_info(void); 84187769Sluigistatic void print_vmx_info(void); 85204591Sluigi 86187769Sluigiint cpu_class; 87204591Sluigichar machine[] = MACHINE; 88204591Sluigi 89187769Sluigi#ifdef __amd64__ 90187769Sluigi#ifdef SCTL_MASK32 91187769Sluigiextern int adaptive_machine_arch; 92187769Sluigi#endif 93187769Sluigi 94187769Sluigistatic int 95187769Sluigisysctl_hw_machine(SYSCTL_HANDLER_ARGS) 96187769Sluigi{ 97187769Sluigi#ifdef SCTL_MASK32 98187769Sluigi static const char machine32[] = "i386"; 99187769Sluigi#endif 100187769Sluigi int error; 101190633Spiso 102187769Sluigi#ifdef SCTL_MASK32 103187769Sluigi if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch) 104187769Sluigi error = SYSCTL_OUT(req, machine32, sizeof(machine32)); 105187769Sluigi else 106187769Sluigi#endif 107187769Sluigi error = SYSCTL_OUT(req, machine, sizeof(machine)); 108187769Sluigi return (error); 109187769Sluigi 110187769Sluigi} 111187769SluigiSYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD, 112187769Sluigi NULL, 0, sysctl_hw_machine, "A", "Machine class"); 113187769Sluigi#else 114187769SluigiSYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 115187769Sluigi machine, 0, "Machine class"); 116187769Sluigi#endif 117187769Sluigi 118187769Sluigistatic char cpu_model[128]; 119187769SluigiSYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, 120187769Sluigi cpu_model, 0, "Machine model"); 121187769Sluigi 122187769Sluigistatic int hw_clockrate; 123187769SluigiSYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 124187769Sluigi &hw_clockrate, 0, "CPU instruction clock rate"); 125187769Sluigi 126187769Sluigiu_int hv_high; 127187769Sluigichar hv_vendor[16]; 128205169SluigiSYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD, hv_vendor, 0, 129187769Sluigi "Hypervisor vendor"); 130187769Sluigi 131187769Sluigistatic eventhandler_tag tsc_post_tag; 132187769Sluigi 133187769Sluigistatic char cpu_brand[48]; 134187769Sluigi 135187769Sluigi#ifdef __i386__ 136187769Sluigi#define MAX_BRAND_INDEX 8 137187769Sluigi 138187769Sluigistatic const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = { 139187769Sluigi NULL, /* No brand */ 140187769Sluigi "Intel Celeron", 141187769Sluigi "Intel Pentium III", 142187769Sluigi "Intel Pentium III Xeon", 143187769Sluigi NULL, 144187769Sluigi NULL, 145187769Sluigi NULL, 146187769Sluigi NULL, 147187769Sluigi "Intel Pentium 4" 148187769Sluigi}; 149187769Sluigi#endif 150187769Sluigi 151187769Sluigistatic struct { 152187769Sluigi char *cpu_name; 153187769Sluigi int cpu_class; 154187769Sluigi} cpus[] = { 155187769Sluigi#ifdef __i386__ 156187769Sluigi { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */ 157187769Sluigi { "i386SX", CPUCLASS_386 }, /* CPU_386SX */ 158204591Sluigi { "i386DX", CPUCLASS_386 }, /* CPU_386 */ 159204591Sluigi { "i486SX", CPUCLASS_486 }, /* CPU_486SX */ 160187769Sluigi { "i486DX", CPUCLASS_486 }, /* CPU_486 */ 161187769Sluigi { "Pentium", CPUCLASS_586 }, /* CPU_586 */ 162204591Sluigi { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */ 163194930Soleg { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */ 164187769Sluigi { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */ 165187769Sluigi { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */ 166187769Sluigi { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */ 167187769Sluigi { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */ 168204591Sluigi { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */ 169187769Sluigi { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */ 170204591Sluigi { "Pentium II", CPUCLASS_686 }, /* CPU_PII */ 171204591Sluigi { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */ 172204591Sluigi { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */ 173204591Sluigi#else 174204591Sluigi { "Clawhammer", CPUCLASS_K8 }, /* CPU_CLAWHAMMER */ 175187769Sluigi { "Sledgehammer", CPUCLASS_K8 }, /* CPU_SLEDGEHAMMER */ 176187769Sluigi#endif 177187769Sluigi}; 178187769Sluigi 179187769Sluigistatic struct { 180187769Sluigi char *vendor; 181187769Sluigi u_int vendor_id; 182187769Sluigi} cpu_vendors[] = { 183187769Sluigi { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */ 184187769Sluigi { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */ 185187769Sluigi { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */ 186187769Sluigi#ifdef __i386__ 187187769Sluigi { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */ 188187769Sluigi { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */ 189187769Sluigi { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */ 190187769Sluigi { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */ 191187769Sluigi { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */ 192187769Sluigi { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */ 193187769Sluigi { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */ 194187769Sluigi#if 0 195187769Sluigi /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */ 196187769Sluigi { "TransmetaCPU", CPU_VENDOR_TRANSMETA }, 197187769Sluigi#endif 198187769Sluigi#endif 199187769Sluigi}; 200187769Sluigi 201200567Sluigivoid 202187769Sluigiprintcpuinfo(void) 203187767Sluigi{ 204187767Sluigi u_int regs[4], i; 205187767Sluigi char *brand; 206187767Sluigi 207204591Sluigi cpu_class = cpus[cpu].cpu_class; 208204591Sluigi printf("CPU: "); 209187767Sluigi strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model)); 210187787Sluigi 211187787Sluigi /* Check for extended CPUID information and a processor name. */ 212187767Sluigi if (cpu_exthigh >= 0x80000004) { 213187767Sluigi brand = cpu_brand; 214187767Sluigi for (i = 0x80000002; i < 0x80000005; i++) { 215187767Sluigi do_cpuid(i, regs); 216187770Sluigi memcpy(brand, regs, sizeof(regs)); 217187767Sluigi brand += sizeof(regs); 218187769Sluigi } 219187767Sluigi } 220187770Sluigi 221187769Sluigi switch (cpu_vendor_id) { 222187770Sluigi case CPU_VENDOR_INTEL: 223187770Sluigi#ifdef __i386__ 224187769Sluigi if ((cpu_id & 0xf00) > 0x300) { 225187769Sluigi u_int brand_index; 226187769Sluigi 227187769Sluigi cpu_model[0] = '\0'; 228187770Sluigi 229187769Sluigi switch (cpu_id & 0x3000) { 230187819Sluigi case 0x1000: 231187819Sluigi strcpy(cpu_model, "Overdrive "); 232187819Sluigi break; 233187819Sluigi case 0x2000: 234187819Sluigi strcpy(cpu_model, "Dual "); 235187819Sluigi break; 236187819Sluigi } 237187819Sluigi 238187819Sluigi switch (cpu_id & 0xf00) { 239187983Sluigi case 0x400: 240187819Sluigi strcat(cpu_model, "i486 "); 241187819Sluigi /* Check the particular flavor of 486 */ 242187819Sluigi switch (cpu_id & 0xf0) { 243187769Sluigi case 0x00: 244187767Sluigi case 0x10: 245187767Sluigi strcat(cpu_model, "DX"); 246187767Sluigi break; 247187767Sluigi case 0x20: 248187767Sluigi strcat(cpu_model, "SX"); 249187767Sluigi break; 250187767Sluigi case 0x30: 251187770Sluigi strcat(cpu_model, "DX2"); 252204591Sluigi break; 253187767Sluigi case 0x40: 254187767Sluigi strcat(cpu_model, "SL"); 255187767Sluigi break; 256204591Sluigi case 0x50: 257187767Sluigi strcat(cpu_model, "SX2"); 258204591Sluigi break; 259204591Sluigi case 0x70: 260187767Sluigi strcat(cpu_model, 261187767Sluigi "DX2 Write-Back Enhanced"); 262187767Sluigi break; 263187767Sluigi case 0x80: 264187983Sluigi strcat(cpu_model, "DX4"); 265187983Sluigi break; 266187983Sluigi } 267187983Sluigi break; 268187983Sluigi case 0x500: 269187983Sluigi /* Check the particular flavor of 586 */ 270187770Sluigi strcat(cpu_model, "Pentium"); 271204591Sluigi switch (cpu_id & 0xf0) { 272204591Sluigi case 0x00: 273187769Sluigi strcat(cpu_model, " A-step"); 274187769Sluigi break; 275187770Sluigi case 0x10: 276187770Sluigi strcat(cpu_model, "/P5"); 277187819Sluigi break; 278187819Sluigi case 0x20: 279187819Sluigi strcat(cpu_model, "/P54C"); 280187819Sluigi break; 281187770Sluigi case 0x30: 282187819Sluigi strcat(cpu_model, "/P24T"); 283187819Sluigi break; 284187770Sluigi case 0x40: 285187819Sluigi strcat(cpu_model, "/P55C"); 286187770Sluigi break; 287187819Sluigi case 0x70: 288187819Sluigi strcat(cpu_model, "/P54C"); 289 break; 290 case 0x80: 291 strcat(cpu_model, "/P55C (quarter-micron)"); 292 break; 293 default: 294 /* nothing */ 295 break; 296 } 297#if defined(I586_CPU) && !defined(NO_F00F_HACK) 298 /* 299 * XXX - If/when Intel fixes the bug, this 300 * should also check the version of the 301 * CPU, not just that it's a Pentium. 302 */ 303 has_f00f_bug = 1; 304#endif 305 break; 306 case 0x600: 307 /* Check the particular flavor of 686 */ 308 switch (cpu_id & 0xf0) { 309 case 0x00: 310 strcat(cpu_model, "Pentium Pro A-step"); 311 break; 312 case 0x10: 313 strcat(cpu_model, "Pentium Pro"); 314 break; 315 case 0x30: 316 case 0x50: 317 case 0x60: 318 strcat(cpu_model, 319 "Pentium II/Pentium II Xeon/Celeron"); 320 cpu = CPU_PII; 321 break; 322 case 0x70: 323 case 0x80: 324 case 0xa0: 325 case 0xb0: 326 strcat(cpu_model, 327 "Pentium III/Pentium III Xeon/Celeron"); 328 cpu = CPU_PIII; 329 break; 330 default: 331 strcat(cpu_model, "Unknown 80686"); 332 break; 333 } 334 break; 335 case 0xf00: 336 strcat(cpu_model, "Pentium 4"); 337 cpu = CPU_P4; 338 break; 339 default: 340 strcat(cpu_model, "unknown"); 341 break; 342 } 343 344 /* 345 * If we didn't get a brand name from the extended 346 * CPUID, try to look it up in the brand table. 347 */ 348 if (cpu_high > 0 && *cpu_brand == '\0') { 349 brand_index = cpu_procinfo & CPUID_BRAND_INDEX; 350 if (brand_index <= MAX_BRAND_INDEX && 351 cpu_brandtable[brand_index] != NULL) 352 strcpy(cpu_brand, 353 cpu_brandtable[brand_index]); 354 } 355 } 356#else 357 /* Please make up your mind folks! */ 358 strcat(cpu_model, "EM64T"); 359#endif 360 break; 361 case CPU_VENDOR_AMD: 362 /* 363 * Values taken from AMD Processor Recognition 364 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf 365 * (also describes ``Features'' encodings. 366 */ 367 strcpy(cpu_model, "AMD "); 368#ifdef __i386__ 369 switch (cpu_id & 0xFF0) { 370 case 0x410: 371 strcat(cpu_model, "Standard Am486DX"); 372 break; 373 case 0x430: 374 strcat(cpu_model, "Enhanced Am486DX2 Write-Through"); 375 break; 376 case 0x470: 377 strcat(cpu_model, "Enhanced Am486DX2 Write-Back"); 378 break; 379 case 0x480: 380 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through"); 381 break; 382 case 0x490: 383 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back"); 384 break; 385 case 0x4E0: 386 strcat(cpu_model, "Am5x86 Write-Through"); 387 break; 388 case 0x4F0: 389 strcat(cpu_model, "Am5x86 Write-Back"); 390 break; 391 case 0x500: 392 strcat(cpu_model, "K5 model 0"); 393 break; 394 case 0x510: 395 strcat(cpu_model, "K5 model 1"); 396 break; 397 case 0x520: 398 strcat(cpu_model, "K5 PR166 (model 2)"); 399 break; 400 case 0x530: 401 strcat(cpu_model, "K5 PR200 (model 3)"); 402 break; 403 case 0x560: 404 strcat(cpu_model, "K6"); 405 break; 406 case 0x570: 407 strcat(cpu_model, "K6 266 (model 1)"); 408 break; 409 case 0x580: 410 strcat(cpu_model, "K6-2"); 411 break; 412 case 0x590: 413 strcat(cpu_model, "K6-III"); 414 break; 415 case 0x5a0: 416 strcat(cpu_model, "Geode LX"); 417 break; 418 default: 419 strcat(cpu_model, "Unknown"); 420 break; 421 } 422#else 423 if ((cpu_id & 0xf00) == 0xf00) 424 strcat(cpu_model, "AMD64 Processor"); 425 else 426 strcat(cpu_model, "Unknown"); 427#endif 428 break; 429#ifdef __i386__ 430 case CPU_VENDOR_CYRIX: 431 strcpy(cpu_model, "Cyrix "); 432 switch (cpu_id & 0xff0) { 433 case 0x440: 434 strcat(cpu_model, "MediaGX"); 435 break; 436 case 0x520: 437 strcat(cpu_model, "6x86"); 438 break; 439 case 0x540: 440 cpu_class = CPUCLASS_586; 441 strcat(cpu_model, "GXm"); 442 break; 443 case 0x600: 444 strcat(cpu_model, "6x86MX"); 445 break; 446 default: 447 /* 448 * Even though CPU supports the cpuid 449 * instruction, it can be disabled. 450 * Therefore, this routine supports all Cyrix 451 * CPUs. 452 */ 453 switch (cyrix_did & 0xf0) { 454 case 0x00: 455 switch (cyrix_did & 0x0f) { 456 case 0x00: 457 strcat(cpu_model, "486SLC"); 458 break; 459 case 0x01: 460 strcat(cpu_model, "486DLC"); 461 break; 462 case 0x02: 463 strcat(cpu_model, "486SLC2"); 464 break; 465 case 0x03: 466 strcat(cpu_model, "486DLC2"); 467 break; 468 case 0x04: 469 strcat(cpu_model, "486SRx"); 470 break; 471 case 0x05: 472 strcat(cpu_model, "486DRx"); 473 break; 474 case 0x06: 475 strcat(cpu_model, "486SRx2"); 476 break; 477 case 0x07: 478 strcat(cpu_model, "486DRx2"); 479 break; 480 case 0x08: 481 strcat(cpu_model, "486SRu"); 482 break; 483 case 0x09: 484 strcat(cpu_model, "486DRu"); 485 break; 486 case 0x0a: 487 strcat(cpu_model, "486SRu2"); 488 break; 489 case 0x0b: 490 strcat(cpu_model, "486DRu2"); 491 break; 492 default: 493 strcat(cpu_model, "Unknown"); 494 break; 495 } 496 break; 497 case 0x10: 498 switch (cyrix_did & 0x0f) { 499 case 0x00: 500 strcat(cpu_model, "486S"); 501 break; 502 case 0x01: 503 strcat(cpu_model, "486S2"); 504 break; 505 case 0x02: 506 strcat(cpu_model, "486Se"); 507 break; 508 case 0x03: 509 strcat(cpu_model, "486S2e"); 510 break; 511 case 0x0a: 512 strcat(cpu_model, "486DX"); 513 break; 514 case 0x0b: 515 strcat(cpu_model, "486DX2"); 516 break; 517 case 0x0f: 518 strcat(cpu_model, "486DX4"); 519 break; 520 default: 521 strcat(cpu_model, "Unknown"); 522 break; 523 } 524 break; 525 case 0x20: 526 if ((cyrix_did & 0x0f) < 8) 527 strcat(cpu_model, "6x86"); /* Where did you get it? */ 528 else 529 strcat(cpu_model, "5x86"); 530 break; 531 case 0x30: 532 strcat(cpu_model, "6x86"); 533 break; 534 case 0x40: 535 if ((cyrix_did & 0xf000) == 0x3000) { 536 cpu_class = CPUCLASS_586; 537 strcat(cpu_model, "GXm"); 538 } else 539 strcat(cpu_model, "MediaGX"); 540 break; 541 case 0x50: 542 strcat(cpu_model, "6x86MX"); 543 break; 544 case 0xf0: 545 switch (cyrix_did & 0x0f) { 546 case 0x0d: 547 strcat(cpu_model, "Overdrive CPU"); 548 break; 549 case 0x0e: 550 strcpy(cpu_model, "Texas Instruments 486SXL"); 551 break; 552 case 0x0f: 553 strcat(cpu_model, "486SLC/DLC"); 554 break; 555 default: 556 strcat(cpu_model, "Unknown"); 557 break; 558 } 559 break; 560 default: 561 strcat(cpu_model, "Unknown"); 562 break; 563 } 564 break; 565 } 566 break; 567 case CPU_VENDOR_RISE: 568 strcpy(cpu_model, "Rise "); 569 switch (cpu_id & 0xff0) { 570 case 0x500: /* 6401 and 6441 (Kirin) */ 571 case 0x520: /* 6510 (Lynx) */ 572 strcat(cpu_model, "mP6"); 573 break; 574 default: 575 strcat(cpu_model, "Unknown"); 576 } 577 break; 578#endif 579 case CPU_VENDOR_CENTAUR: 580#ifdef __i386__ 581 switch (cpu_id & 0xff0) { 582 case 0x540: 583 strcpy(cpu_model, "IDT WinChip C6"); 584 break; 585 case 0x580: 586 strcpy(cpu_model, "IDT WinChip 2"); 587 break; 588 case 0x590: 589 strcpy(cpu_model, "IDT WinChip 3"); 590 break; 591 case 0x660: 592 strcpy(cpu_model, "VIA C3 Samuel"); 593 break; 594 case 0x670: 595 if (cpu_id & 0x8) 596 strcpy(cpu_model, "VIA C3 Ezra"); 597 else 598 strcpy(cpu_model, "VIA C3 Samuel 2"); 599 break; 600 case 0x680: 601 strcpy(cpu_model, "VIA C3 Ezra-T"); 602 break; 603 case 0x690: 604 strcpy(cpu_model, "VIA C3 Nehemiah"); 605 break; 606 case 0x6a0: 607 case 0x6d0: 608 strcpy(cpu_model, "VIA C7 Esther"); 609 break; 610 case 0x6f0: 611 strcpy(cpu_model, "VIA Nano"); 612 break; 613 default: 614 strcpy(cpu_model, "VIA/IDT Unknown"); 615 } 616#else 617 strcpy(cpu_model, "VIA "); 618 if ((cpu_id & 0xff0) == 0x6f0) 619 strcat(cpu_model, "Nano Processor"); 620 else 621 strcat(cpu_model, "Unknown"); 622#endif 623 break; 624#ifdef __i386__ 625 case CPU_VENDOR_IBM: 626 strcpy(cpu_model, "Blue Lightning CPU"); 627 break; 628 case CPU_VENDOR_NSC: 629 switch (cpu_id & 0xff0) { 630 case 0x540: 631 strcpy(cpu_model, "Geode SC1100"); 632 cpu = CPU_GEODE1100; 633 break; 634 default: 635 strcpy(cpu_model, "Geode/NSC unknown"); 636 break; 637 } 638 break; 639#endif 640 default: 641 strcat(cpu_model, "Unknown"); 642 break; 643 } 644 645 /* 646 * Replace cpu_model with cpu_brand minus leading spaces if 647 * we have one. 648 */ 649 brand = cpu_brand; 650 while (*brand == ' ') 651 ++brand; 652 if (*brand != '\0') 653 strcpy(cpu_model, brand); 654 655 printf("%s (", cpu_model); 656 if (tsc_freq != 0) { 657 hw_clockrate = (tsc_freq + 5000) / 1000000; 658 printf("%jd.%02d-MHz ", 659 (intmax_t)(tsc_freq + 4999) / 1000000, 660 (u_int)((tsc_freq + 4999) / 10000) % 100); 661 } 662 switch(cpu_class) { 663#ifdef __i386__ 664 case CPUCLASS_286: 665 printf("286"); 666 break; 667 case CPUCLASS_386: 668 printf("386"); 669 break; 670#if defined(I486_CPU) 671 case CPUCLASS_486: 672 printf("486"); 673 break; 674#endif 675#if defined(I586_CPU) 676 case CPUCLASS_586: 677 printf("586"); 678 break; 679#endif 680#if defined(I686_CPU) 681 case CPUCLASS_686: 682 printf("686"); 683 break; 684#endif 685#else 686 case CPUCLASS_K8: 687 printf("K8"); 688 break; 689#endif 690 default: 691 printf("Unknown"); /* will panic below... */ 692 } 693 printf("-class CPU)\n"); 694 if (*cpu_vendor) 695 printf(" Origin=\"%s\"", cpu_vendor); 696 if (cpu_id) 697 printf(" Id=0x%x", cpu_id); 698 699 if (cpu_vendor_id == CPU_VENDOR_INTEL || 700 cpu_vendor_id == CPU_VENDOR_AMD || 701 cpu_vendor_id == CPU_VENDOR_CENTAUR || 702#ifdef __i386__ 703 cpu_vendor_id == CPU_VENDOR_TRANSMETA || 704 cpu_vendor_id == CPU_VENDOR_RISE || 705 cpu_vendor_id == CPU_VENDOR_NSC || 706 (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) || 707#endif 708 0) { 709 printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id)); 710 printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id)); 711 printf(" Stepping=%u", cpu_id & CPUID_STEPPING); 712#ifdef __i386__ 713 if (cpu_vendor_id == CPU_VENDOR_CYRIX) 714 printf("\n DIR=0x%04x", cyrix_did); 715#endif 716 717 /* 718 * AMD CPUID Specification 719 * http://support.amd.com/us/Embedded_TechDocs/25481.pdf 720 * 721 * Intel Processor Identification and CPUID Instruction 722 * http://www.intel.com/assets/pdf/appnote/241618.pdf 723 */ 724 if (cpu_high > 0) { 725 726 /* 727 * Here we should probably set up flags indicating 728 * whether or not various features are available. 729 * The interesting ones are probably VME, PSE, PAE, 730 * and PGE. The code already assumes without bothering 731 * to check that all CPUs >= Pentium have a TSC and 732 * MSRs. 733 */ 734 printf("\n Features=0x%b", cpu_feature, 735 "\020" 736 "\001FPU" /* Integral FPU */ 737 "\002VME" /* Extended VM86 mode support */ 738 "\003DE" /* Debugging Extensions (CR4.DE) */ 739 "\004PSE" /* 4MByte page tables */ 740 "\005TSC" /* Timestamp counter */ 741 "\006MSR" /* Machine specific registers */ 742 "\007PAE" /* Physical address extension */ 743 "\010MCE" /* Machine Check support */ 744 "\011CX8" /* CMPEXCH8 instruction */ 745 "\012APIC" /* SMP local APIC */ 746 "\013oldMTRR" /* Previous implementation of MTRR */ 747 "\014SEP" /* Fast System Call */ 748 "\015MTRR" /* Memory Type Range Registers */ 749 "\016PGE" /* PG_G (global bit) support */ 750 "\017MCA" /* Machine Check Architecture */ 751 "\020CMOV" /* CMOV instruction */ 752 "\021PAT" /* Page attributes table */ 753 "\022PSE36" /* 36 bit address space support */ 754 "\023PN" /* Processor Serial number */ 755 "\024CLFLUSH" /* Has the CLFLUSH instruction */ 756 "\025<b20>" 757 "\026DTS" /* Debug Trace Store */ 758 "\027ACPI" /* ACPI support */ 759 "\030MMX" /* MMX instructions */ 760 "\031FXSR" /* FXSAVE/FXRSTOR */ 761 "\032SSE" /* Streaming SIMD Extensions */ 762 "\033SSE2" /* Streaming SIMD Extensions #2 */ 763 "\034SS" /* Self snoop */ 764 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */ 765 "\036TM" /* Thermal Monitor clock slowdown */ 766 "\037IA64" /* CPU can execute IA64 instructions */ 767 "\040PBE" /* Pending Break Enable */ 768 ); 769 770 if (cpu_feature2 != 0) { 771 printf("\n Features2=0x%b", cpu_feature2, 772 "\020" 773 "\001SSE3" /* SSE3 */ 774 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */ 775 "\003DTES64" /* 64-bit Debug Trace */ 776 "\004MON" /* MONITOR/MWAIT Instructions */ 777 "\005DS_CPL" /* CPL Qualified Debug Store */ 778 "\006VMX" /* Virtual Machine Extensions */ 779 "\007SMX" /* Safer Mode Extensions */ 780 "\010EST" /* Enhanced SpeedStep */ 781 "\011TM2" /* Thermal Monitor 2 */ 782 "\012SSSE3" /* SSSE3 */ 783 "\013CNXT-ID" /* L1 context ID available */ 784 "\014SDBG" /* IA32 silicon debug */ 785 "\015FMA" /* Fused Multiply Add */ 786 "\016CX16" /* CMPXCHG16B Instruction */ 787 "\017xTPR" /* Send Task Priority Messages*/ 788 "\020PDCM" /* Perf/Debug Capability MSR */ 789 "\021<b16>" 790 "\022PCID" /* Process-context Identifiers*/ 791 "\023DCA" /* Direct Cache Access */ 792 "\024SSE4.1" /* SSE 4.1 */ 793 "\025SSE4.2" /* SSE 4.2 */ 794 "\026x2APIC" /* xAPIC Extensions */ 795 "\027MOVBE" /* MOVBE Instruction */ 796 "\030POPCNT" /* POPCNT Instruction */ 797 "\031TSCDLT" /* TSC-Deadline Timer */ 798 "\032AESNI" /* AES Crypto */ 799 "\033XSAVE" /* XSAVE/XRSTOR States */ 800 "\034OSXSAVE" /* OS-Enabled State Management*/ 801 "\035AVX" /* Advanced Vector Extensions */ 802 "\036F16C" /* Half-precision conversions */ 803 "\037RDRAND" /* RDRAND Instruction */ 804 "\040HV" /* Hypervisor */ 805 ); 806 } 807 808 if (amd_feature != 0) { 809 printf("\n AMD Features=0x%b", amd_feature, 810 "\020" /* in hex */ 811 "\001<s0>" /* Same */ 812 "\002<s1>" /* Same */ 813 "\003<s2>" /* Same */ 814 "\004<s3>" /* Same */ 815 "\005<s4>" /* Same */ 816 "\006<s5>" /* Same */ 817 "\007<s6>" /* Same */ 818 "\010<s7>" /* Same */ 819 "\011<s8>" /* Same */ 820 "\012<s9>" /* Same */ 821 "\013<b10>" /* Undefined */ 822 "\014SYSCALL" /* Have SYSCALL/SYSRET */ 823 "\015<s12>" /* Same */ 824 "\016<s13>" /* Same */ 825 "\017<s14>" /* Same */ 826 "\020<s15>" /* Same */ 827 "\021<s16>" /* Same */ 828 "\022<s17>" /* Same */ 829 "\023<b18>" /* Reserved, unknown */ 830 "\024MP" /* Multiprocessor Capable */ 831 "\025NX" /* Has EFER.NXE, NX */ 832 "\026<b21>" /* Undefined */ 833 "\027MMX+" /* AMD MMX Extensions */ 834 "\030<s23>" /* Same */ 835 "\031<s24>" /* Same */ 836 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */ 837 "\033Page1GB" /* 1-GB large page support */ 838 "\034RDTSCP" /* RDTSCP */ 839 "\035<b28>" /* Undefined */ 840 "\036LM" /* 64 bit long mode */ 841 "\0373DNow!+" /* AMD 3DNow! Extensions */ 842 "\0403DNow!" /* AMD 3DNow! */ 843 ); 844 } 845 846 if (amd_feature2 != 0) { 847 printf("\n AMD Features2=0x%b", amd_feature2, 848 "\020" 849 "\001LAHF" /* LAHF/SAHF in long mode */ 850 "\002CMP" /* CMP legacy */ 851 "\003SVM" /* Secure Virtual Mode */ 852 "\004ExtAPIC" /* Extended APIC register */ 853 "\005CR8" /* CR8 in legacy mode */ 854 "\006ABM" /* LZCNT instruction */ 855 "\007SSE4A" /* SSE4A */ 856 "\010MAS" /* Misaligned SSE mode */ 857 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */ 858 "\012OSVW" /* OS visible workaround */ 859 "\013IBS" /* Instruction based sampling */ 860 "\014XOP" /* XOP extended instructions */ 861 "\015SKINIT" /* SKINIT/STGI */ 862 "\016WDT" /* Watchdog timer */ 863 "\017<b14>" 864 "\020LWP" /* Lightweight Profiling */ 865 "\021FMA4" /* 4-operand FMA instructions */ 866 "\022TCE" /* Translation Cache Extension */ 867 "\023<b18>" 868 "\024NodeId" /* NodeId MSR support */ 869 "\025<b20>" 870 "\026TBM" /* Trailing Bit Manipulation */ 871 "\027Topology" /* Topology Extensions */ 872 "\030PCXC" /* Core perf count */ 873 "\031PNXC" /* NB perf count */ 874 "\032<b25>" 875 "\033DBE" /* Data Breakpoint extension */ 876 "\034PTSC" /* Performance TSC */ 877 "\035PL2I" /* L2I perf count */ 878 "\036<b29>" 879 "\037<b30>" 880 "\040<b31>" 881 ); 882 } 883 884 if (cpu_stdext_feature != 0) { 885 printf("\n Structured Extended Features=0x%b", 886 cpu_stdext_feature, 887 "\020" 888 /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ 889 "\001FSGSBASE" 890 "\002TSCADJ" 891 /* Bit Manipulation Instructions */ 892 "\004BMI1" 893 /* Hardware Lock Elision */ 894 "\005HLE" 895 /* Advanced Vector Instructions 2 */ 896 "\006AVX2" 897 /* FDP_EXCPTN_ONLY */ 898 "\007FDPEXC" 899 /* Supervisor Mode Execution Prot. */ 900 "\010SMEP" 901 /* Bit Manipulation Instructions */ 902 "\011BMI2" 903 "\012ERMS" 904 /* Invalidate Processor Context ID */ 905 "\013INVPCID" 906 /* Restricted Transactional Memory */ 907 "\014RTM" 908 "\015PQM" 909 "\016NFPUSG" 910 "\020PQE" 911 /* Intel Memory Protection Extensions */ 912 "\017MPX" 913 /* AVX512 Foundation */ 914 "\021AVX512F" 915 /* Enhanced NRBG */ 916 "\023RDSEED" 917 /* ADCX + ADOX */ 918 "\024ADX" 919 /* Supervisor Mode Access Prevention */ 920 "\025SMAP" 921 "\030CLFLUSHOPT" 922 "\032PROCTRACE" 923 "\033AVX512PF" 924 "\034AVX512ER" 925 "\035AVX512CD" 926 "\036SHA" 927 ); 928 } 929 930 if (cpu_stdext_feature2 != 0) { 931 printf("\n Structured Extended Features2=0x%b", 932 cpu_stdext_feature2, 933 "\020" 934 "\001PREFETCHWT1" 935 "\004PKU" 936 "\005OSPKE" 937 ); 938 } 939 940 if ((cpu_feature2 & CPUID2_XSAVE) != 0) { 941 cpuid_count(0xd, 0x1, regs); 942 if (regs[0] != 0) { 943 printf("\n XSAVE Features=0x%b", 944 regs[0], 945 "\020" 946 "\001XSAVEOPT" 947 "\002XSAVEC" 948 "\003XINUSE" 949 "\004XSAVES"); 950 } 951 } 952 953 if (via_feature_rng != 0 || via_feature_xcrypt != 0) 954 print_via_padlock_info(); 955 956 if (cpu_feature2 & CPUID2_VMX) 957 print_vmx_info(); 958 959 if (amd_feature2 & AMDID2_SVM) 960 print_svm_info(); 961 962 if ((cpu_feature & CPUID_HTT) && 963 cpu_vendor_id == CPU_VENDOR_AMD) 964 cpu_feature &= ~CPUID_HTT; 965 966 /* 967 * If this CPU supports P-state invariant TSC then 968 * mention the capability. 969 */ 970 if (tsc_is_invariant) { 971 printf("\n TSC: P-state invariant"); 972 if (tsc_perf_stat) 973 printf(", performance statistics"); 974 } 975 } 976#ifdef __i386__ 977 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 978 printf(" DIR=0x%04x", cyrix_did); 979 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12); 980 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8); 981#ifndef CYRIX_CACHE_REALLY_WORKS 982 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700) 983 printf("\n CPU cache: write-through mode"); 984#endif 985#endif 986 } 987 988 /* Avoid ugly blank lines: only print newline when we have to. */ 989 if (*cpu_vendor || cpu_id) 990 printf("\n"); 991 992 if (bootverbose) { 993 if (cpu_vendor_id == CPU_VENDOR_AMD) 994 print_AMD_info(); 995 else if (cpu_vendor_id == CPU_VENDOR_INTEL) 996 print_INTEL_info(); 997#ifdef __i386__ 998 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA) 999 print_transmeta_info(); 1000#endif 1001 } 1002 1003 print_hypervisor_info(); 1004} 1005 1006void 1007panicifcpuunsupported(void) 1008{ 1009 1010#ifdef __i386__ 1011#if !defined(lint) 1012#if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU) 1013#error This kernel is not configured for one of the supported CPUs 1014#endif 1015#else /* lint */ 1016#endif /* lint */ 1017#else /* __amd64__ */ 1018#ifndef HAMMER 1019#error "You need to specify a cpu type" 1020#endif 1021#endif 1022 /* 1023 * Now that we have told the user what they have, 1024 * let them know if that machine type isn't configured. 1025 */ 1026 switch (cpu_class) { 1027#ifdef __i386__ 1028 case CPUCLASS_286: /* a 286 should not make it this far, anyway */ 1029 case CPUCLASS_386: 1030#if !defined(I486_CPU) 1031 case CPUCLASS_486: 1032#endif 1033#if !defined(I586_CPU) 1034 case CPUCLASS_586: 1035#endif 1036#if !defined(I686_CPU) 1037 case CPUCLASS_686: 1038#endif 1039#else /* __amd64__ */ 1040 case CPUCLASS_X86: 1041#ifndef HAMMER 1042 case CPUCLASS_K8: 1043#endif 1044#endif 1045 panic("CPU class not configured"); 1046 default: 1047 break; 1048 } 1049} 1050 1051#ifdef __i386__ 1052static volatile u_int trap_by_rdmsr; 1053 1054/* 1055 * Special exception 6 handler. 1056 * The rdmsr instruction generates invalid opcodes fault on 486-class 1057 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the 1058 * function identblue() when this handler is called. Stacked eip should 1059 * be advanced. 1060 */ 1061inthand_t bluetrap6; 1062#ifdef __GNUCLIKE_ASM 1063__asm 1064(" \n\ 1065 .text \n\ 1066 .p2align 2,0x90 \n\ 1067 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\ 1068" __XSTRING(CNAME(bluetrap6)) ": \n\ 1069 ss \n\ 1070 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ 1071 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ 1072 iret \n\ 1073"); 1074#endif 1075 1076/* 1077 * Special exception 13 handler. 1078 * Accessing non-existent MSR generates general protection fault. 1079 */ 1080inthand_t bluetrap13; 1081#ifdef __GNUCLIKE_ASM 1082__asm 1083(" \n\ 1084 .text \n\ 1085 .p2align 2,0x90 \n\ 1086 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\ 1087" __XSTRING(CNAME(bluetrap13)) ": \n\ 1088 ss \n\ 1089 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ 1090 popl %eax /* discard error code */ \n\ 1091 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ 1092 iret \n\ 1093"); 1094#endif 1095 1096/* 1097 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not 1098 * support cpuid instruction. This function should be called after 1099 * loading interrupt descriptor table register. 1100 * 1101 * I don't like this method that handles fault, but I couldn't get 1102 * information for any other methods. Does blue giant know? 1103 */ 1104static int 1105identblue(void) 1106{ 1107 1108 trap_by_rdmsr = 0; 1109 1110 /* 1111 * Cyrix 486-class CPU does not support rdmsr instruction. 1112 * The rdmsr instruction generates invalid opcode fault, and exception 1113 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The 1114 * bluetrap6() set the magic number to trap_by_rdmsr. 1115 */ 1116 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL, 1117 GSEL(GCODE_SEL, SEL_KPL)); 1118 1119 /* 1120 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU. 1121 * In this case, rdmsr generates general protection fault, and 1122 * exception will be trapped by bluetrap13(). 1123 */ 1124 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL, 1125 GSEL(GCODE_SEL, SEL_KPL)); 1126 1127 rdmsr(0x1002); /* Cyrix CPU generates fault. */ 1128 1129 if (trap_by_rdmsr == 0xa8c1d) 1130 return IDENTBLUE_CYRIX486; 1131 else if (trap_by_rdmsr == 0xa89c4) 1132 return IDENTBLUE_CYRIXM2; 1133 return IDENTBLUE_IBMCPU; 1134} 1135 1136 1137/* 1138 * identifycyrix() set lower 16 bits of cyrix_did as follows: 1139 * 1140 * F E D C B A 9 8 7 6 5 4 3 2 1 0 1141 * +-------+-------+---------------+ 1142 * | SID | RID | Device ID | 1143 * | (DIR 1) | (DIR 0) | 1144 * +-------+-------+---------------+ 1145 */ 1146static void 1147identifycyrix(void) 1148{ 1149 register_t saveintr; 1150 int ccr2_test = 0, dir_test = 0; 1151 u_char ccr2, ccr3; 1152 1153 saveintr = intr_disable(); 1154 1155 ccr2 = read_cyrix_reg(CCR2); 1156 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW); 1157 read_cyrix_reg(CCR2); 1158 if (read_cyrix_reg(CCR2) != ccr2) 1159 ccr2_test = 1; 1160 write_cyrix_reg(CCR2, ccr2); 1161 1162 ccr3 = read_cyrix_reg(CCR3); 1163 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3); 1164 read_cyrix_reg(CCR3); 1165 if (read_cyrix_reg(CCR3) != ccr3) 1166 dir_test = 1; /* CPU supports DIRs. */ 1167 write_cyrix_reg(CCR3, ccr3); 1168 1169 if (dir_test) { 1170 /* Device ID registers are available. */ 1171 cyrix_did = read_cyrix_reg(DIR1) << 8; 1172 cyrix_did += read_cyrix_reg(DIR0); 1173 } else if (ccr2_test) 1174 cyrix_did = 0x0010; /* 486S A-step */ 1175 else 1176 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */ 1177 1178 intr_restore(saveintr); 1179} 1180#endif 1181 1182/* Update TSC freq with the value indicated by the caller. */ 1183static void 1184tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status) 1185{ 1186 1187 /* If there was an error during the transition, don't do anything. */ 1188 if (status != 0) 1189 return; 1190 1191 /* Total setting for this level gives the new frequency in MHz. */ 1192 hw_clockrate = level->total_set.freq; 1193} 1194 1195static void 1196hook_tsc_freq(void *arg __unused) 1197{ 1198 1199 if (tsc_is_invariant) 1200 return; 1201 1202 tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change, 1203 tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY); 1204} 1205 1206SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL); 1207 1208#ifndef XEN 1209static const char *const vm_bnames[] = { 1210 "QEMU", /* QEMU */ 1211 "Plex86", /* Plex86 */ 1212 "Bochs", /* Bochs */ 1213 "Xen", /* Xen */ 1214 "BHYVE", /* bhyve */ 1215 "Seabios", /* KVM */ 1216 NULL 1217}; 1218 1219static const char *const vm_pnames[] = { 1220 "VMware Virtual Platform", /* VMWare VM */ 1221 "Virtual Machine", /* Microsoft VirtualPC */ 1222 "VirtualBox", /* Sun xVM VirtualBox */ 1223 "Parallels Virtual Platform", /* Parallels VM */ 1224 "KVM", /* KVM */ 1225 NULL 1226}; 1227 1228static void 1229identify_hypervisor(void) 1230{ 1231 u_int regs[4]; 1232 char *p; 1233 int i; 1234 1235 /* 1236 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1237 * http://lkml.org/lkml/2008/10/1/246 1238 * 1239 * KB1009458: Mechanisms to determine if software is running in 1240 * a VMware virtual machine 1241 * http://kb.vmware.com/kb/1009458 1242 */ 1243 if (cpu_feature2 & CPUID2_HV) { 1244 vm_guest = VM_GUEST_VM; 1245 do_cpuid(0x40000000, regs); 1246 if (regs[0] >= 0x40000000) { 1247 hv_high = regs[0]; 1248 ((u_int *)&hv_vendor)[0] = regs[1]; 1249 ((u_int *)&hv_vendor)[1] = regs[2]; 1250 ((u_int *)&hv_vendor)[2] = regs[3]; 1251 hv_vendor[12] = '\0'; 1252 if (strcmp(hv_vendor, "VMwareVMware") == 0) 1253 vm_guest = VM_GUEST_VMWARE; 1254 else if (strcmp(hv_vendor, "Microsoft Hv") == 0) 1255 vm_guest = VM_GUEST_HV; 1256 } 1257 return; 1258 } 1259 1260 /* 1261 * Examine SMBIOS strings for older hypervisors. 1262 */ 1263 p = getenv("smbios.system.serial"); 1264 if (p != NULL) { 1265 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) { 1266 vmware_hvcall(VMW_HVCMD_GETVERSION, regs); 1267 if (regs[1] == VMW_HVMAGIC) { 1268 vm_guest = VM_GUEST_VMWARE; 1269 freeenv(p); 1270 return; 1271 } 1272 } 1273 freeenv(p); 1274 } 1275 1276 /* 1277 * XXX: Some of these entries may not be needed since they were 1278 * added to FreeBSD before the checks above. 1279 */ 1280 p = getenv("smbios.bios.vendor"); 1281 if (p != NULL) { 1282 for (i = 0; vm_bnames[i] != NULL; i++) 1283 if (strcmp(p, vm_bnames[i]) == 0) { 1284 vm_guest = VM_GUEST_VM; 1285 freeenv(p); 1286 return; 1287 } 1288 freeenv(p); 1289 } 1290 p = getenv("smbios.system.product"); 1291 if (p != NULL) { 1292 for (i = 0; vm_pnames[i] != NULL; i++) 1293 if (strcmp(p, vm_pnames[i]) == 0) { 1294 vm_guest = VM_GUEST_VM; 1295 freeenv(p); 1296 return; 1297 } 1298 freeenv(p); 1299 } 1300} 1301#endif 1302 1303/* 1304 * Clear "Limit CPUID Maxval" bit and return true if the caller should 1305 * get the largest standard CPUID function number again if it is set 1306 * from BIOS. It is necessary for probing correct CPU topology later 1307 * and for the correct operation of the AVX-aware userspace. 1308 */ 1309bool 1310intel_fix_cpuid(void) 1311{ 1312 uint64_t msr; 1313 1314 if (cpu_vendor_id != CPU_VENDOR_INTEL) 1315 return (false); 1316 if ((CPUID_TO_FAMILY(cpu_id) == 0xf && 1317 CPUID_TO_MODEL(cpu_id) >= 0x3) || 1318 (CPUID_TO_FAMILY(cpu_id) == 0x6 && 1319 CPUID_TO_MODEL(cpu_id) >= 0xe)) { 1320 msr = rdmsr(MSR_IA32_MISC_ENABLE); 1321 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) { 1322 msr &= ~IA32_MISC_EN_LIMCPUID; 1323 wrmsr(MSR_IA32_MISC_ENABLE, msr); 1324 return (true); 1325 } 1326 } 1327 return (false); 1328} 1329 1330/* 1331 * Final stage of CPU identification. 1332 */ 1333#ifdef __i386__ 1334void 1335finishidentcpu(void) 1336#else 1337void 1338identify_cpu(void) 1339#endif 1340{ 1341 u_int regs[4], cpu_stdext_disable; 1342#ifdef __i386__ 1343 u_char ccr3; 1344#endif 1345 1346#ifdef __amd64__ 1347 do_cpuid(0, regs); 1348 cpu_high = regs[0]; 1349 ((u_int *)&cpu_vendor)[0] = regs[1]; 1350 ((u_int *)&cpu_vendor)[1] = regs[3]; 1351 ((u_int *)&cpu_vendor)[2] = regs[2]; 1352 cpu_vendor[12] = '\0'; 1353 1354 do_cpuid(1, regs); 1355 cpu_id = regs[0]; 1356 cpu_procinfo = regs[1]; 1357 cpu_feature = regs[3]; 1358 cpu_feature2 = regs[2]; 1359#endif 1360 1361#ifndef XEN 1362 identify_hypervisor(); 1363#endif 1364 cpu_vendor_id = find_cpu_vendor_id(); 1365 1366 if (intel_fix_cpuid()) { 1367 do_cpuid(0, regs); 1368 cpu_high = regs[0]; 1369 } 1370 1371 if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) { 1372 do_cpuid(5, regs); 1373 cpu_mon_mwait_flags = regs[2]; 1374 cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE; 1375 cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE; 1376 } 1377 1378 if (cpu_high >= 7) { 1379 cpuid_count(7, 0, regs); 1380 cpu_stdext_feature = regs[1]; 1381 1382 /* 1383 * Some hypervisors fail to filter out unsupported 1384 * extended features. For now, disable the 1385 * extensions, activation of which requires setting a 1386 * bit in CR4, and which VM monitors do not support. 1387 */ 1388 if (cpu_feature2 & CPUID2_HV) { 1389 cpu_stdext_disable = CPUID_STDEXT_FSGSBASE | 1390 CPUID_STDEXT_SMEP; 1391 } else 1392 cpu_stdext_disable = 0; 1393 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable); 1394 cpu_stdext_feature &= ~cpu_stdext_disable; 1395 cpu_stdext_feature2 = regs[2]; 1396 } 1397 1398#ifdef __i386__ 1399 if (cpu_high > 0 && 1400 (cpu_vendor_id == CPU_VENDOR_INTEL || 1401 cpu_vendor_id == CPU_VENDOR_AMD || 1402 cpu_vendor_id == CPU_VENDOR_TRANSMETA || 1403 cpu_vendor_id == CPU_VENDOR_CENTAUR || 1404 cpu_vendor_id == CPU_VENDOR_NSC)) { 1405 do_cpuid(0x80000000, regs); 1406 if (regs[0] >= 0x80000000) 1407 cpu_exthigh = regs[0]; 1408 } 1409#else 1410 if (cpu_vendor_id == CPU_VENDOR_INTEL || 1411 cpu_vendor_id == CPU_VENDOR_AMD || 1412 cpu_vendor_id == CPU_VENDOR_CENTAUR) { 1413 do_cpuid(0x80000000, regs); 1414 cpu_exthigh = regs[0]; 1415 } 1416#endif 1417 if (cpu_exthigh >= 0x80000001) { 1418 do_cpuid(0x80000001, regs); 1419 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff); 1420 amd_feature2 = regs[2]; 1421 } 1422 if (cpu_exthigh >= 0x80000007) { 1423 do_cpuid(0x80000007, regs); 1424 amd_pminfo = regs[3]; 1425 } 1426 if (cpu_exthigh >= 0x80000008) { 1427 do_cpuid(0x80000008, regs); 1428 cpu_maxphyaddr = regs[0] & 0xff; 1429 cpu_procinfo2 = regs[2]; 1430 } else { 1431 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32; 1432 } 1433 1434#ifdef __i386__ 1435 if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 1436 if (cpu == CPU_486) { 1437 /* 1438 * These conditions are equivalent to: 1439 * - CPU does not support cpuid instruction. 1440 * - Cyrix/IBM CPU is detected. 1441 */ 1442 if (identblue() == IDENTBLUE_IBMCPU) { 1443 strcpy(cpu_vendor, "IBM"); 1444 cpu_vendor_id = CPU_VENDOR_IBM; 1445 cpu = CPU_BLUE; 1446 return; 1447 } 1448 } 1449 switch (cpu_id & 0xf00) { 1450 case 0x600: 1451 /* 1452 * Cyrix's datasheet does not describe DIRs. 1453 * Therefor, I assume it does not have them 1454 * and use the result of the cpuid instruction. 1455 * XXX they seem to have it for now at least. -Peter 1456 */ 1457 identifycyrix(); 1458 cpu = CPU_M2; 1459 break; 1460 default: 1461 identifycyrix(); 1462 /* 1463 * This routine contains a trick. 1464 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now. 1465 */ 1466 switch (cyrix_did & 0x00f0) { 1467 case 0x00: 1468 case 0xf0: 1469 cpu = CPU_486DLC; 1470 break; 1471 case 0x10: 1472 cpu = CPU_CY486DX; 1473 break; 1474 case 0x20: 1475 if ((cyrix_did & 0x000f) < 8) 1476 cpu = CPU_M1; 1477 else 1478 cpu = CPU_M1SC; 1479 break; 1480 case 0x30: 1481 cpu = CPU_M1; 1482 break; 1483 case 0x40: 1484 /* MediaGX CPU */ 1485 cpu = CPU_M1SC; 1486 break; 1487 default: 1488 /* M2 and later CPUs are treated as M2. */ 1489 cpu = CPU_M2; 1490 1491 /* 1492 * enable cpuid instruction. 1493 */ 1494 ccr3 = read_cyrix_reg(CCR3); 1495 write_cyrix_reg(CCR3, CCR3_MAPEN0); 1496 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID); 1497 write_cyrix_reg(CCR3, ccr3); 1498 1499 do_cpuid(0, regs); 1500 cpu_high = regs[0]; /* eax */ 1501 do_cpuid(1, regs); 1502 cpu_id = regs[0]; /* eax */ 1503 cpu_feature = regs[3]; /* edx */ 1504 break; 1505 } 1506 } 1507 } else if (cpu == CPU_486 && *cpu_vendor == '\0') { 1508 /* 1509 * There are BlueLightning CPUs that do not change 1510 * undefined flags by dividing 5 by 2. In this case, 1511 * the CPU identification routine in locore.s leaves 1512 * cpu_vendor null string and puts CPU_486 into the 1513 * cpu. 1514 */ 1515 if (identblue() == IDENTBLUE_IBMCPU) { 1516 strcpy(cpu_vendor, "IBM"); 1517 cpu_vendor_id = CPU_VENDOR_IBM; 1518 cpu = CPU_BLUE; 1519 return; 1520 } 1521 } 1522#else 1523 /* XXX */ 1524 cpu = CPU_CLAWHAMMER; 1525#endif 1526} 1527 1528static u_int 1529find_cpu_vendor_id(void) 1530{ 1531 int i; 1532 1533 for (i = 0; i < sizeof(cpu_vendors) / sizeof(cpu_vendors[0]); i++) 1534 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0) 1535 return (cpu_vendors[i].vendor_id); 1536 return (0); 1537} 1538 1539static void 1540print_AMD_assoc(int i) 1541{ 1542 if (i == 255) 1543 printf(", fully associative\n"); 1544 else 1545 printf(", %d-way associative\n", i); 1546} 1547 1548static void 1549print_AMD_l2_assoc(int i) 1550{ 1551 switch (i & 0x0f) { 1552 case 0: printf(", disabled/not present\n"); break; 1553 case 1: printf(", direct mapped\n"); break; 1554 case 2: printf(", 2-way associative\n"); break; 1555 case 4: printf(", 4-way associative\n"); break; 1556 case 6: printf(", 8-way associative\n"); break; 1557 case 8: printf(", 16-way associative\n"); break; 1558 case 15: printf(", fully associative\n"); break; 1559 default: printf(", reserved configuration\n"); break; 1560 } 1561} 1562 1563static void 1564print_AMD_info(void) 1565{ 1566#ifdef __i386__ 1567 uint64_t amd_whcr; 1568#endif 1569 u_int regs[4]; 1570 1571 if (cpu_exthigh >= 0x80000005) { 1572 do_cpuid(0x80000005, regs); 1573 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff); 1574 print_AMD_assoc(regs[0] >> 24); 1575 1576 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff); 1577 print_AMD_assoc((regs[0] >> 8) & 0xff); 1578 1579 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff); 1580 print_AMD_assoc(regs[1] >> 24); 1581 1582 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff); 1583 print_AMD_assoc((regs[1] >> 8) & 0xff); 1584 1585 printf("L1 data cache: %d kbytes", regs[2] >> 24); 1586 printf(", %d bytes/line", regs[2] & 0xff); 1587 printf(", %d lines/tag", (regs[2] >> 8) & 0xff); 1588 print_AMD_assoc((regs[2] >> 16) & 0xff); 1589 1590 printf("L1 instruction cache: %d kbytes", regs[3] >> 24); 1591 printf(", %d bytes/line", regs[3] & 0xff); 1592 printf(", %d lines/tag", (regs[3] >> 8) & 0xff); 1593 print_AMD_assoc((regs[3] >> 16) & 0xff); 1594 } 1595 1596 if (cpu_exthigh >= 0x80000006) { 1597 do_cpuid(0x80000006, regs); 1598 if ((regs[0] >> 16) != 0) { 1599 printf("L2 2MB data TLB: %d entries", 1600 (regs[0] >> 16) & 0xfff); 1601 print_AMD_l2_assoc(regs[0] >> 28); 1602 printf("L2 2MB instruction TLB: %d entries", 1603 regs[0] & 0xfff); 1604 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 1605 } else { 1606 printf("L2 2MB unified TLB: %d entries", 1607 regs[0] & 0xfff); 1608 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 1609 } 1610 if ((regs[1] >> 16) != 0) { 1611 printf("L2 4KB data TLB: %d entries", 1612 (regs[1] >> 16) & 0xfff); 1613 print_AMD_l2_assoc(regs[1] >> 28); 1614 1615 printf("L2 4KB instruction TLB: %d entries", 1616 (regs[1] >> 16) & 0xfff); 1617 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 1618 } else { 1619 printf("L2 4KB unified TLB: %d entries", 1620 (regs[1] >> 16) & 0xfff); 1621 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 1622 } 1623 printf("L2 unified cache: %d kbytes", regs[2] >> 16); 1624 printf(", %d bytes/line", regs[2] & 0xff); 1625 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f); 1626 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f); 1627 } 1628 1629#ifdef __i386__ 1630 if (((cpu_id & 0xf00) == 0x500) 1631 && (((cpu_id & 0x0f0) > 0x80) 1632 || (((cpu_id & 0x0f0) == 0x80) 1633 && (cpu_id & 0x00f) > 0x07))) { 1634 /* K6-2(new core [Stepping 8-F]), K6-III or later */ 1635 amd_whcr = rdmsr(0xc0000082); 1636 if (!(amd_whcr & (0x3ff << 22))) { 1637 printf("Write Allocate Disable\n"); 1638 } else { 1639 printf("Write Allocate Enable Limit: %dM bytes\n", 1640 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4); 1641 printf("Write Allocate 15-16M bytes: %s\n", 1642 (amd_whcr & (1 << 16)) ? "Enable" : "Disable"); 1643 } 1644 } else if (((cpu_id & 0xf00) == 0x500) 1645 && ((cpu_id & 0x0f0) > 0x50)) { 1646 /* K6, K6-2(old core) */ 1647 amd_whcr = rdmsr(0xc0000082); 1648 if (!(amd_whcr & (0x7f << 1))) { 1649 printf("Write Allocate Disable\n"); 1650 } else { 1651 printf("Write Allocate Enable Limit: %dM bytes\n", 1652 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4); 1653 printf("Write Allocate 15-16M bytes: %s\n", 1654 (amd_whcr & 0x0001) ? "Enable" : "Disable"); 1655 printf("Hardware Write Allocate Control: %s\n", 1656 (amd_whcr & 0x0100) ? "Enable" : "Disable"); 1657 } 1658 } 1659#endif 1660 /* 1661 * Opteron Rev E shows a bug as in very rare occasions a read memory 1662 * barrier is not performed as expected if it is followed by a 1663 * non-atomic read-modify-write instruction. 1664 * As long as that bug pops up very rarely (intensive machine usage 1665 * on other operating systems generally generates one unexplainable 1666 * crash any 2 months) and as long as a model specific fix would be 1667 * impratical at this stage, print out a warning string if the broken 1668 * model and family are identified. 1669 */ 1670 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 && 1671 CPUID_TO_MODEL(cpu_id) <= 0x3f) 1672 printf("WARNING: This architecture revision has known SMP " 1673 "hardware bugs which may cause random instability\n"); 1674} 1675 1676static void 1677print_INTEL_info(void) 1678{ 1679 u_int regs[4]; 1680 u_int rounds, regnum; 1681 u_int nwaycode, nway; 1682 1683 if (cpu_high >= 2) { 1684 rounds = 0; 1685 do { 1686 do_cpuid(0x2, regs); 1687 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0) 1688 break; /* we have a buggy CPU */ 1689 1690 for (regnum = 0; regnum <= 3; ++regnum) { 1691 if (regs[regnum] & (1<<31)) 1692 continue; 1693 if (regnum != 0) 1694 print_INTEL_TLB(regs[regnum] & 0xff); 1695 print_INTEL_TLB((regs[regnum] >> 8) & 0xff); 1696 print_INTEL_TLB((regs[regnum] >> 16) & 0xff); 1697 print_INTEL_TLB((regs[regnum] >> 24) & 0xff); 1698 } 1699 } while (--rounds > 0); 1700 } 1701 1702 if (cpu_exthigh >= 0x80000006) { 1703 do_cpuid(0x80000006, regs); 1704 nwaycode = (regs[2] >> 12) & 0x0f; 1705 if (nwaycode >= 0x02 && nwaycode <= 0x08) 1706 nway = 1 << (nwaycode / 2); 1707 else 1708 nway = 0; 1709 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n", 1710 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff); 1711 } 1712} 1713 1714static void 1715print_INTEL_TLB(u_int data) 1716{ 1717 switch (data) { 1718 case 0x0: 1719 case 0x40: 1720 default: 1721 break; 1722 case 0x1: 1723 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n"); 1724 break; 1725 case 0x2: 1726 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n"); 1727 break; 1728 case 0x3: 1729 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n"); 1730 break; 1731 case 0x4: 1732 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n"); 1733 break; 1734 case 0x6: 1735 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n"); 1736 break; 1737 case 0x8: 1738 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n"); 1739 break; 1740 case 0x9: 1741 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n"); 1742 break; 1743 case 0xa: 1744 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n"); 1745 break; 1746 case 0xb: 1747 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n"); 1748 break; 1749 case 0xc: 1750 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n"); 1751 break; 1752 case 0xd: 1753 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size"); 1754 break; 1755 case 0xe: 1756 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n"); 1757 break; 1758 case 0x1d: 1759 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n"); 1760 break; 1761 case 0x21: 1762 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n"); 1763 break; 1764 case 0x22: 1765 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 1766 break; 1767 case 0x23: 1768 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 1769 break; 1770 case 0x24: 1771 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n"); 1772 break; 1773 case 0x25: 1774 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 1775 break; 1776 case 0x29: 1777 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 1778 break; 1779 case 0x2c: 1780 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n"); 1781 break; 1782 case 0x30: 1783 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n"); 1784 break; 1785 case 0x39: /* De-listed in SDM rev. 54 */ 1786 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 1787 break; 1788 case 0x3b: /* De-listed in SDM rev. 54 */ 1789 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n"); 1790 break; 1791 case 0x3c: /* De-listed in SDM rev. 54 */ 1792 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 1793 break; 1794 case 0x41: 1795 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n"); 1796 break; 1797 case 0x42: 1798 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n"); 1799 break; 1800 case 0x43: 1801 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n"); 1802 break; 1803 case 0x44: 1804 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n"); 1805 break; 1806 case 0x45: 1807 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n"); 1808 break; 1809 case 0x46: 1810 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n"); 1811 break; 1812 case 0x47: 1813 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n"); 1814 break; 1815 case 0x48: 1816 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n"); 1817 break; 1818 case 0x49: 1819 if (CPUID_TO_FAMILY(cpu_id) == 0xf && 1820 CPUID_TO_MODEL(cpu_id) == 0x6) 1821 printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n"); 1822 else 1823 printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size"); 1824 break; 1825 case 0x4a: 1826 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n"); 1827 break; 1828 case 0x4b: 1829 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n"); 1830 break; 1831 case 0x4c: 1832 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n"); 1833 break; 1834 case 0x4d: 1835 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n"); 1836 break; 1837 case 0x4e: 1838 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n"); 1839 break; 1840 case 0x4f: 1841 printf("Instruction TLB: 4 KByte pages, 32 entries\n"); 1842 break; 1843 case 0x50: 1844 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n"); 1845 break; 1846 case 0x51: 1847 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n"); 1848 break; 1849 case 0x52: 1850 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n"); 1851 break; 1852 case 0x55: 1853 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n"); 1854 break; 1855 case 0x56: 1856 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n"); 1857 break; 1858 case 0x57: 1859 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n"); 1860 break; 1861 case 0x59: 1862 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n"); 1863 break; 1864 case 0x5a: 1865 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n"); 1866 break; 1867 case 0x5b: 1868 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n"); 1869 break; 1870 case 0x5c: 1871 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n"); 1872 break; 1873 case 0x5d: 1874 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n"); 1875 break; 1876 case 0x60: 1877 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 1878 break; 1879 case 0x61: 1880 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n"); 1881 break; 1882 case 0x63: 1883 printf("Data TLB: 1 GByte pages, 4-way set associative, 4 entries\n"); 1884 break; 1885 case 0x66: 1886 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 1887 break; 1888 case 0x67: 1889 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 1890 break; 1891 case 0x68: 1892 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n"); 1893 break; 1894 case 0x6a: 1895 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n"); 1896 break; 1897 case 0x6b: 1898 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n"); 1899 break; 1900 case 0x6c: 1901 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n"); 1902 break; 1903 case 0x6d: 1904 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n"); 1905 break; 1906 case 0x70: 1907 printf("Trace cache: 12K-uops, 8-way set associative\n"); 1908 break; 1909 case 0x71: 1910 printf("Trace cache: 16K-uops, 8-way set associative\n"); 1911 break; 1912 case 0x72: 1913 printf("Trace cache: 32K-uops, 8-way set associative\n"); 1914 break; 1915 case 0x76: 1916 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n"); 1917 break; 1918 case 0x78: 1919 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n"); 1920 break; 1921 case 0x79: 1922 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 1923 break; 1924 case 0x7a: 1925 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 1926 break; 1927 case 0x7b: 1928 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 1929 break; 1930 case 0x7c: 1931 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 1932 break; 1933 case 0x7d: 1934 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n"); 1935 break; 1936 case 0x7f: 1937 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n"); 1938 break; 1939 case 0x80: 1940 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n"); 1941 break; 1942 case 0x82: 1943 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n"); 1944 break; 1945 case 0x83: 1946 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n"); 1947 break; 1948 case 0x84: 1949 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n"); 1950 break; 1951 case 0x85: 1952 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n"); 1953 break; 1954 case 0x86: 1955 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n"); 1956 break; 1957 case 0x87: 1958 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n"); 1959 break; 1960 case 0xa0: 1961 printf("DTLB: 4k pages, fully associative, 32 entries\n"); 1962 break; 1963 case 0xb0: 1964 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n"); 1965 break; 1966 case 0xb1: 1967 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n"); 1968 break; 1969 case 0xb2: 1970 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n"); 1971 break; 1972 case 0xb3: 1973 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n"); 1974 break; 1975 case 0xb4: 1976 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n"); 1977 break; 1978 case 0xb5: 1979 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n"); 1980 break; 1981 case 0xb6: 1982 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n"); 1983 break; 1984 case 0xba: 1985 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n"); 1986 break; 1987 case 0xc0: 1988 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n"); 1989 break; 1990 case 0xc1: 1991 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n"); 1992 break; 1993 case 0xc2: 1994 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n"); 1995 break; 1996 case 0xc3: 1997 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n"); 1998 break; 1999 case 0xca: 2000 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n"); 2001 break; 2002 case 0xd0: 2003 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n"); 2004 break; 2005 case 0xd1: 2006 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n"); 2007 break; 2008 case 0xd2: 2009 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n"); 2010 break; 2011 case 0xd6: 2012 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n"); 2013 break; 2014 case 0xd7: 2015 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n"); 2016 break; 2017 case 0xd8: 2018 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n"); 2019 break; 2020 case 0xdc: 2021 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n"); 2022 break; 2023 case 0xdd: 2024 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n"); 2025 break; 2026 case 0xde: 2027 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n"); 2028 break; 2029 case 0xe2: 2030 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n"); 2031 break; 2032 case 0xe3: 2033 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n"); 2034 break; 2035 case 0xe4: 2036 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n"); 2037 break; 2038 case 0xea: 2039 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n"); 2040 break; 2041 case 0xeb: 2042 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n"); 2043 break; 2044 case 0xec: 2045 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n"); 2046 break; 2047 case 0xf0: 2048 printf("64-Byte prefetching\n"); 2049 break; 2050 case 0xf1: 2051 printf("128-Byte prefetching\n"); 2052 break; 2053 } 2054} 2055 2056static void 2057print_svm_info(void) 2058{ 2059 u_int features, regs[4]; 2060 uint64_t msr; 2061 int comma; 2062 2063 printf("\n SVM: "); 2064 do_cpuid(0x8000000A, regs); 2065 features = regs[3]; 2066 2067 msr = rdmsr(MSR_VM_CR); 2068 if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS) 2069 printf("(disabled in BIOS) "); 2070 2071 if (!bootverbose) { 2072 comma = 0; 2073 if (features & (1 << 0)) { 2074 printf("%sNP", comma ? "," : ""); 2075 comma = 1; 2076 } 2077 if (features & (1 << 3)) { 2078 printf("%sNRIP", comma ? "," : ""); 2079 comma = 1; 2080 } 2081 if (features & (1 << 5)) { 2082 printf("%sVClean", comma ? "," : ""); 2083 comma = 1; 2084 } 2085 if (features & (1 << 6)) { 2086 printf("%sAFlush", comma ? "," : ""); 2087 comma = 1; 2088 } 2089 if (features & (1 << 7)) { 2090 printf("%sDAssist", comma ? "," : ""); 2091 comma = 1; 2092 } 2093 printf("%sNAsids=%d", comma ? "," : "", regs[1]); 2094 return; 2095 } 2096 2097 printf("Features=0x%b", features, 2098 "\020" 2099 "\001NP" /* Nested paging */ 2100 "\002LbrVirt" /* LBR virtualization */ 2101 "\003SVML" /* SVM lock */ 2102 "\004NRIPS" /* NRIP save */ 2103 "\005TscRateMsr" /* MSR based TSC rate control */ 2104 "\006VmcbClean" /* VMCB clean bits */ 2105 "\007FlushByAsid" /* Flush by ASID */ 2106 "\010DecodeAssist" /* Decode assist */ 2107 "\011<b8>" 2108 "\012<b9>" 2109 "\013PauseFilter" /* PAUSE intercept filter */ 2110 "\014<b11>" 2111 "\015PauseFilterThreshold" /* PAUSE filter threshold */ 2112 "\016AVIC" /* virtual interrupt controller */ 2113 ); 2114 printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]); 2115} 2116 2117#ifdef __i386__ 2118static void 2119print_transmeta_info(void) 2120{ 2121 u_int regs[4], nreg = 0; 2122 2123 do_cpuid(0x80860000, regs); 2124 nreg = regs[0]; 2125 if (nreg >= 0x80860001) { 2126 do_cpuid(0x80860001, regs); 2127 printf(" Processor revision %u.%u.%u.%u\n", 2128 (regs[1] >> 24) & 0xff, 2129 (regs[1] >> 16) & 0xff, 2130 (regs[1] >> 8) & 0xff, 2131 regs[1] & 0xff); 2132 } 2133 if (nreg >= 0x80860002) { 2134 do_cpuid(0x80860002, regs); 2135 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n", 2136 (regs[1] >> 24) & 0xff, 2137 (regs[1] >> 16) & 0xff, 2138 (regs[1] >> 8) & 0xff, 2139 regs[1] & 0xff, 2140 regs[2]); 2141 } 2142 if (nreg >= 0x80860006) { 2143 char info[65]; 2144 do_cpuid(0x80860003, (u_int*) &info[0]); 2145 do_cpuid(0x80860004, (u_int*) &info[16]); 2146 do_cpuid(0x80860005, (u_int*) &info[32]); 2147 do_cpuid(0x80860006, (u_int*) &info[48]); 2148 info[64] = 0; 2149 printf(" %s\n", info); 2150 } 2151} 2152#endif 2153 2154static void 2155print_via_padlock_info(void) 2156{ 2157 u_int regs[4]; 2158 2159 do_cpuid(0xc0000001, regs); 2160 printf("\n VIA Padlock Features=0x%b", regs[3], 2161 "\020" 2162 "\003RNG" /* RNG */ 2163 "\007AES" /* ACE */ 2164 "\011AES-CTR" /* ACE2 */ 2165 "\013SHA1,SHA256" /* PHE */ 2166 "\015RSA" /* PMM */ 2167 ); 2168} 2169 2170static uint32_t 2171vmx_settable(uint64_t basic, int msr, int true_msr) 2172{ 2173 uint64_t val; 2174 2175 if (basic & (1ULL << 55)) 2176 val = rdmsr(true_msr); 2177 else 2178 val = rdmsr(msr); 2179 2180 /* Just report the controls that can be set to 1. */ 2181 return (val >> 32); 2182} 2183 2184static void 2185print_vmx_info(void) 2186{ 2187 uint64_t basic, msr; 2188 uint32_t entry, exit, mask, pin, proc, proc2; 2189 int comma; 2190 2191 printf("\n VT-x: "); 2192 msr = rdmsr(MSR_IA32_FEATURE_CONTROL); 2193 if (!(msr & IA32_FEATURE_CONTROL_VMX_EN)) 2194 printf("(disabled in BIOS) "); 2195 basic = rdmsr(MSR_VMX_BASIC); 2196 pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS, 2197 MSR_VMX_TRUE_PINBASED_CTLS); 2198 proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS, 2199 MSR_VMX_TRUE_PROCBASED_CTLS); 2200 if (proc & PROCBASED_SECONDARY_CONTROLS) 2201 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2, 2202 MSR_VMX_PROCBASED_CTLS2); 2203 else 2204 proc2 = 0; 2205 exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS); 2206 entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS); 2207 2208 if (!bootverbose) { 2209 comma = 0; 2210 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT && 2211 entry & VM_ENTRY_LOAD_PAT) { 2212 printf("%sPAT", comma ? "," : ""); 2213 comma = 1; 2214 } 2215 if (proc & PROCBASED_HLT_EXITING) { 2216 printf("%sHLT", comma ? "," : ""); 2217 comma = 1; 2218 } 2219 if (proc & PROCBASED_MTF) { 2220 printf("%sMTF", comma ? "," : ""); 2221 comma = 1; 2222 } 2223 if (proc & PROCBASED_PAUSE_EXITING) { 2224 printf("%sPAUSE", comma ? "," : ""); 2225 comma = 1; 2226 } 2227 if (proc2 & PROCBASED2_ENABLE_EPT) { 2228 printf("%sEPT", comma ? "," : ""); 2229 comma = 1; 2230 } 2231 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) { 2232 printf("%sUG", comma ? "," : ""); 2233 comma = 1; 2234 } 2235 if (proc2 & PROCBASED2_ENABLE_VPID) { 2236 printf("%sVPID", comma ? "," : ""); 2237 comma = 1; 2238 } 2239 if (proc & PROCBASED_USE_TPR_SHADOW && 2240 proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES && 2241 proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE && 2242 proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION && 2243 proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) { 2244 printf("%sVID", comma ? "," : ""); 2245 comma = 1; 2246 if (pin & PINBASED_POSTED_INTERRUPT) 2247 printf(",PostIntr"); 2248 } 2249 return; 2250 } 2251 2252 mask = basic >> 32; 2253 printf("Basic Features=0x%b", mask, 2254 "\020" 2255 "\02132PA" /* 32-bit physical addresses */ 2256 "\022SMM" /* SMM dual-monitor */ 2257 "\027INS/OUTS" /* VM-exit info for INS and OUTS */ 2258 "\030TRUE" /* TRUE_CTLS MSRs */ 2259 ); 2260 printf("\n Pin-Based Controls=0x%b", pin, 2261 "\020" 2262 "\001ExtINT" /* External-interrupt exiting */ 2263 "\004NMI" /* NMI exiting */ 2264 "\006VNMI" /* Virtual NMIs */ 2265 "\007PreTmr" /* Activate VMX-preemption timer */ 2266 "\010PostIntr" /* Process posted interrupts */ 2267 ); 2268 printf("\n Primary Processor Controls=0x%b", proc, 2269 "\020" 2270 "\003INTWIN" /* Interrupt-window exiting */ 2271 "\004TSCOff" /* Use TSC offsetting */ 2272 "\010HLT" /* HLT exiting */ 2273 "\012INVLPG" /* INVLPG exiting */ 2274 "\013MWAIT" /* MWAIT exiting */ 2275 "\014RDPMC" /* RDPMC exiting */ 2276 "\015RDTSC" /* RDTSC exiting */ 2277 "\020CR3-LD" /* CR3-load exiting */ 2278 "\021CR3-ST" /* CR3-store exiting */ 2279 "\024CR8-LD" /* CR8-load exiting */ 2280 "\025CR8-ST" /* CR8-store exiting */ 2281 "\026TPR" /* Use TPR shadow */ 2282 "\027NMIWIN" /* NMI-window exiting */ 2283 "\030MOV-DR" /* MOV-DR exiting */ 2284 "\031IO" /* Unconditional I/O exiting */ 2285 "\032IOmap" /* Use I/O bitmaps */ 2286 "\034MTF" /* Monitor trap flag */ 2287 "\035MSRmap" /* Use MSR bitmaps */ 2288 "\036MONITOR" /* MONITOR exiting */ 2289 "\037PAUSE" /* PAUSE exiting */ 2290 ); 2291 if (proc & PROCBASED_SECONDARY_CONTROLS) 2292 printf("\n Secondary Processor Controls=0x%b", proc2, 2293 "\020" 2294 "\001APIC" /* Virtualize APIC accesses */ 2295 "\002EPT" /* Enable EPT */ 2296 "\003DT" /* Descriptor-table exiting */ 2297 "\004RDTSCP" /* Enable RDTSCP */ 2298 "\005x2APIC" /* Virtualize x2APIC mode */ 2299 "\006VPID" /* Enable VPID */ 2300 "\007WBINVD" /* WBINVD exiting */ 2301 "\010UG" /* Unrestricted guest */ 2302 "\011APIC-reg" /* APIC-register virtualization */ 2303 "\012VID" /* Virtual-interrupt delivery */ 2304 "\013PAUSE-loop" /* PAUSE-loop exiting */ 2305 "\014RDRAND" /* RDRAND exiting */ 2306 "\015INVPCID" /* Enable INVPCID */ 2307 "\016VMFUNC" /* Enable VM functions */ 2308 "\017VMCS" /* VMCS shadowing */ 2309 "\020EPT#VE" /* EPT-violation #VE */ 2310 "\021XSAVES" /* Enable XSAVES/XRSTORS */ 2311 ); 2312 printf("\n Exit Controls=0x%b", mask, 2313 "\020" 2314 "\003DR" /* Save debug controls */ 2315 /* Ignore Host address-space size */ 2316 "\015PERF" /* Load MSR_PERF_GLOBAL_CTRL */ 2317 "\020AckInt" /* Acknowledge interrupt on exit */ 2318 "\023PAT-SV" /* Save MSR_PAT */ 2319 "\024PAT-LD" /* Load MSR_PAT */ 2320 "\025EFER-SV" /* Save MSR_EFER */ 2321 "\026EFER-LD" /* Load MSR_EFER */ 2322 "\027PTMR-SV" /* Save VMX-preemption timer value */ 2323 ); 2324 printf("\n Entry Controls=0x%b", mask, 2325 "\020" 2326 "\003DR" /* Save debug controls */ 2327 /* Ignore IA-32e mode guest */ 2328 /* Ignore Entry to SMM */ 2329 /* Ignore Deactivate dual-monitor treatment */ 2330 "\016PERF" /* Load MSR_PERF_GLOBAL_CTRL */ 2331 "\017PAT" /* Load MSR_PAT */ 2332 "\020EFER" /* Load MSR_EFER */ 2333 ); 2334 if (proc & PROCBASED_SECONDARY_CONTROLS && 2335 (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) { 2336 msr = rdmsr(MSR_VMX_EPT_VPID_CAP); 2337 mask = msr; 2338 printf("\n EPT Features=0x%b", mask, 2339 "\020" 2340 "\001XO" /* Execute-only translations */ 2341 "\007PW4" /* Page-walk length of 4 */ 2342 "\011UC" /* EPT paging-structure mem can be UC */ 2343 "\017WB" /* EPT paging-structure mem can be WB */ 2344 "\0212M" /* EPT PDE can map a 2-Mbyte page */ 2345 "\0221G" /* EPT PDPTE can map a 1-Gbyte page */ 2346 "\025INVEPT" /* INVEPT is supported */ 2347 "\026AD" /* Accessed and dirty flags for EPT */ 2348 "\032single" /* INVEPT single-context type */ 2349 "\033all" /* INVEPT all-context type */ 2350 ); 2351 mask = msr >> 32; 2352 printf("\n VPID Features=0x%b", mask, 2353 "\020" 2354 "\001INVVPID" /* INVVPID is supported */ 2355 "\011individual" /* INVVPID individual-address type */ 2356 "\012single" /* INVVPID single-context type */ 2357 "\013all" /* INVVPID all-context type */ 2358 /* INVVPID single-context-retaining-globals type */ 2359 "\014single-globals" 2360 ); 2361 } 2362} 2363 2364static void 2365print_hypervisor_info(void) 2366{ 2367 2368 if (*hv_vendor) 2369 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor); 2370} 2371