identcpu.c revision 293195
1/*- 2 * Copyright (c) 1992 Terrence R. Lambert. 3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 4 * Copyright (c) 1997 KATO Takenori. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp 39 */ 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD: stable/10/sys/x86/x86/identcpu.c 293195 2016-01-05 13:05:38Z kib $"); 43 44#include "opt_cpu.h" 45 46#include <sys/param.h> 47#include <sys/bus.h> 48#include <sys/cpu.h> 49#include <sys/eventhandler.h> 50#include <sys/limits.h> 51#include <sys/systm.h> 52#include <sys/kernel.h> 53#include <sys/sysctl.h> 54#include <sys/power.h> 55 56#include <machine/asmacros.h> 57#include <machine/clock.h> 58#include <machine/cputypes.h> 59#include <machine/frame.h> 60#include <machine/intr_machdep.h> 61#include <machine/md_var.h> 62#include <machine/segments.h> 63#include <machine/specialreg.h> 64 65#include <amd64/vmm/intel/vmx_controls.h> 66#include <x86/isa/icu.h> 67#include <x86/vmware.h> 68 69#ifdef __i386__ 70#define IDENTBLUE_CYRIX486 0 71#define IDENTBLUE_IBMCPU 1 72#define IDENTBLUE_CYRIXM2 2 73 74static void identifycyrix(void); 75static void print_transmeta_info(void); 76#endif 77static u_int find_cpu_vendor_id(void); 78static void print_AMD_info(void); 79static void print_INTEL_info(void); 80static void print_INTEL_TLB(u_int data); 81static void print_hypervisor_info(void); 82static void print_svm_info(void); 83static void print_via_padlock_info(void); 84static void print_vmx_info(void); 85 86int cpu_class; 87char machine[] = MACHINE; 88 89#ifdef __amd64__ 90#ifdef SCTL_MASK32 91extern int adaptive_machine_arch; 92#endif 93 94static int 95sysctl_hw_machine(SYSCTL_HANDLER_ARGS) 96{ 97#ifdef SCTL_MASK32 98 static const char machine32[] = "i386"; 99#endif 100 int error; 101 102#ifdef SCTL_MASK32 103 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch) 104 error = SYSCTL_OUT(req, machine32, sizeof(machine32)); 105 else 106#endif 107 error = SYSCTL_OUT(req, machine, sizeof(machine)); 108 return (error); 109 110} 111SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD, 112 NULL, 0, sysctl_hw_machine, "A", "Machine class"); 113#else 114SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 115 machine, 0, "Machine class"); 116#endif 117 118static char cpu_model[128]; 119SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, 120 cpu_model, 0, "Machine model"); 121 122static int hw_clockrate; 123SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 124 &hw_clockrate, 0, "CPU instruction clock rate"); 125 126u_int hv_high; 127char hv_vendor[16]; 128SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD, hv_vendor, 0, 129 "Hypervisor vendor"); 130 131static eventhandler_tag tsc_post_tag; 132 133static char cpu_brand[48]; 134 135#ifdef __i386__ 136#define MAX_BRAND_INDEX 8 137 138static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = { 139 NULL, /* No brand */ 140 "Intel Celeron", 141 "Intel Pentium III", 142 "Intel Pentium III Xeon", 143 NULL, 144 NULL, 145 NULL, 146 NULL, 147 "Intel Pentium 4" 148}; 149#endif 150 151static struct { 152 char *cpu_name; 153 int cpu_class; 154} cpus[] = { 155#ifdef __i386__ 156 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */ 157 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */ 158 { "i386DX", CPUCLASS_386 }, /* CPU_386 */ 159 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */ 160 { "i486DX", CPUCLASS_486 }, /* CPU_486 */ 161 { "Pentium", CPUCLASS_586 }, /* CPU_586 */ 162 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */ 163 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */ 164 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */ 165 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */ 166 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */ 167 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */ 168 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */ 169 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */ 170 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */ 171 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */ 172 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */ 173#else 174 { "Clawhammer", CPUCLASS_K8 }, /* CPU_CLAWHAMMER */ 175 { "Sledgehammer", CPUCLASS_K8 }, /* CPU_SLEDGEHAMMER */ 176#endif 177}; 178 179static struct { 180 char *vendor; 181 u_int vendor_id; 182} cpu_vendors[] = { 183 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */ 184 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */ 185 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */ 186#ifdef __i386__ 187 { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */ 188 { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */ 189 { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */ 190 { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */ 191 { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */ 192 { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */ 193 { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */ 194#if 0 195 /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */ 196 { "TransmetaCPU", CPU_VENDOR_TRANSMETA }, 197#endif 198#endif 199}; 200 201void 202printcpuinfo(void) 203{ 204 u_int regs[4], i; 205 char *brand; 206 207 cpu_class = cpus[cpu].cpu_class; 208 printf("CPU: "); 209 strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model)); 210 211 /* Check for extended CPUID information and a processor name. */ 212 if (cpu_exthigh >= 0x80000004) { 213 brand = cpu_brand; 214 for (i = 0x80000002; i < 0x80000005; i++) { 215 do_cpuid(i, regs); 216 memcpy(brand, regs, sizeof(regs)); 217 brand += sizeof(regs); 218 } 219 } 220 221 switch (cpu_vendor_id) { 222 case CPU_VENDOR_INTEL: 223#ifdef __i386__ 224 if ((cpu_id & 0xf00) > 0x300) { 225 u_int brand_index; 226 227 cpu_model[0] = '\0'; 228 229 switch (cpu_id & 0x3000) { 230 case 0x1000: 231 strcpy(cpu_model, "Overdrive "); 232 break; 233 case 0x2000: 234 strcpy(cpu_model, "Dual "); 235 break; 236 } 237 238 switch (cpu_id & 0xf00) { 239 case 0x400: 240 strcat(cpu_model, "i486 "); 241 /* Check the particular flavor of 486 */ 242 switch (cpu_id & 0xf0) { 243 case 0x00: 244 case 0x10: 245 strcat(cpu_model, "DX"); 246 break; 247 case 0x20: 248 strcat(cpu_model, "SX"); 249 break; 250 case 0x30: 251 strcat(cpu_model, "DX2"); 252 break; 253 case 0x40: 254 strcat(cpu_model, "SL"); 255 break; 256 case 0x50: 257 strcat(cpu_model, "SX2"); 258 break; 259 case 0x70: 260 strcat(cpu_model, 261 "DX2 Write-Back Enhanced"); 262 break; 263 case 0x80: 264 strcat(cpu_model, "DX4"); 265 break; 266 } 267 break; 268 case 0x500: 269 /* Check the particular flavor of 586 */ 270 strcat(cpu_model, "Pentium"); 271 switch (cpu_id & 0xf0) { 272 case 0x00: 273 strcat(cpu_model, " A-step"); 274 break; 275 case 0x10: 276 strcat(cpu_model, "/P5"); 277 break; 278 case 0x20: 279 strcat(cpu_model, "/P54C"); 280 break; 281 case 0x30: 282 strcat(cpu_model, "/P24T"); 283 break; 284 case 0x40: 285 strcat(cpu_model, "/P55C"); 286 break; 287 case 0x70: 288 strcat(cpu_model, "/P54C"); 289 break; 290 case 0x80: 291 strcat(cpu_model, "/P55C (quarter-micron)"); 292 break; 293 default: 294 /* nothing */ 295 break; 296 } 297#if defined(I586_CPU) && !defined(NO_F00F_HACK) 298 /* 299 * XXX - If/when Intel fixes the bug, this 300 * should also check the version of the 301 * CPU, not just that it's a Pentium. 302 */ 303 has_f00f_bug = 1; 304#endif 305 break; 306 case 0x600: 307 /* Check the particular flavor of 686 */ 308 switch (cpu_id & 0xf0) { 309 case 0x00: 310 strcat(cpu_model, "Pentium Pro A-step"); 311 break; 312 case 0x10: 313 strcat(cpu_model, "Pentium Pro"); 314 break; 315 case 0x30: 316 case 0x50: 317 case 0x60: 318 strcat(cpu_model, 319 "Pentium II/Pentium II Xeon/Celeron"); 320 cpu = CPU_PII; 321 break; 322 case 0x70: 323 case 0x80: 324 case 0xa0: 325 case 0xb0: 326 strcat(cpu_model, 327 "Pentium III/Pentium III Xeon/Celeron"); 328 cpu = CPU_PIII; 329 break; 330 default: 331 strcat(cpu_model, "Unknown 80686"); 332 break; 333 } 334 break; 335 case 0xf00: 336 strcat(cpu_model, "Pentium 4"); 337 cpu = CPU_P4; 338 break; 339 default: 340 strcat(cpu_model, "unknown"); 341 break; 342 } 343 344 /* 345 * If we didn't get a brand name from the extended 346 * CPUID, try to look it up in the brand table. 347 */ 348 if (cpu_high > 0 && *cpu_brand == '\0') { 349 brand_index = cpu_procinfo & CPUID_BRAND_INDEX; 350 if (brand_index <= MAX_BRAND_INDEX && 351 cpu_brandtable[brand_index] != NULL) 352 strcpy(cpu_brand, 353 cpu_brandtable[brand_index]); 354 } 355 } 356#else 357 /* Please make up your mind folks! */ 358 strcat(cpu_model, "EM64T"); 359#endif 360 break; 361 case CPU_VENDOR_AMD: 362 /* 363 * Values taken from AMD Processor Recognition 364 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf 365 * (also describes ``Features'' encodings. 366 */ 367 strcpy(cpu_model, "AMD "); 368#ifdef __i386__ 369 switch (cpu_id & 0xFF0) { 370 case 0x410: 371 strcat(cpu_model, "Standard Am486DX"); 372 break; 373 case 0x430: 374 strcat(cpu_model, "Enhanced Am486DX2 Write-Through"); 375 break; 376 case 0x470: 377 strcat(cpu_model, "Enhanced Am486DX2 Write-Back"); 378 break; 379 case 0x480: 380 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through"); 381 break; 382 case 0x490: 383 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back"); 384 break; 385 case 0x4E0: 386 strcat(cpu_model, "Am5x86 Write-Through"); 387 break; 388 case 0x4F0: 389 strcat(cpu_model, "Am5x86 Write-Back"); 390 break; 391 case 0x500: 392 strcat(cpu_model, "K5 model 0"); 393 break; 394 case 0x510: 395 strcat(cpu_model, "K5 model 1"); 396 break; 397 case 0x520: 398 strcat(cpu_model, "K5 PR166 (model 2)"); 399 break; 400 case 0x530: 401 strcat(cpu_model, "K5 PR200 (model 3)"); 402 break; 403 case 0x560: 404 strcat(cpu_model, "K6"); 405 break; 406 case 0x570: 407 strcat(cpu_model, "K6 266 (model 1)"); 408 break; 409 case 0x580: 410 strcat(cpu_model, "K6-2"); 411 break; 412 case 0x590: 413 strcat(cpu_model, "K6-III"); 414 break; 415 case 0x5a0: 416 strcat(cpu_model, "Geode LX"); 417 break; 418 default: 419 strcat(cpu_model, "Unknown"); 420 break; 421 } 422#else 423 if ((cpu_id & 0xf00) == 0xf00) 424 strcat(cpu_model, "AMD64 Processor"); 425 else 426 strcat(cpu_model, "Unknown"); 427#endif 428 break; 429#ifdef __i386__ 430 case CPU_VENDOR_CYRIX: 431 strcpy(cpu_model, "Cyrix "); 432 switch (cpu_id & 0xff0) { 433 case 0x440: 434 strcat(cpu_model, "MediaGX"); 435 break; 436 case 0x520: 437 strcat(cpu_model, "6x86"); 438 break; 439 case 0x540: 440 cpu_class = CPUCLASS_586; 441 strcat(cpu_model, "GXm"); 442 break; 443 case 0x600: 444 strcat(cpu_model, "6x86MX"); 445 break; 446 default: 447 /* 448 * Even though CPU supports the cpuid 449 * instruction, it can be disabled. 450 * Therefore, this routine supports all Cyrix 451 * CPUs. 452 */ 453 switch (cyrix_did & 0xf0) { 454 case 0x00: 455 switch (cyrix_did & 0x0f) { 456 case 0x00: 457 strcat(cpu_model, "486SLC"); 458 break; 459 case 0x01: 460 strcat(cpu_model, "486DLC"); 461 break; 462 case 0x02: 463 strcat(cpu_model, "486SLC2"); 464 break; 465 case 0x03: 466 strcat(cpu_model, "486DLC2"); 467 break; 468 case 0x04: 469 strcat(cpu_model, "486SRx"); 470 break; 471 case 0x05: 472 strcat(cpu_model, "486DRx"); 473 break; 474 case 0x06: 475 strcat(cpu_model, "486SRx2"); 476 break; 477 case 0x07: 478 strcat(cpu_model, "486DRx2"); 479 break; 480 case 0x08: 481 strcat(cpu_model, "486SRu"); 482 break; 483 case 0x09: 484 strcat(cpu_model, "486DRu"); 485 break; 486 case 0x0a: 487 strcat(cpu_model, "486SRu2"); 488 break; 489 case 0x0b: 490 strcat(cpu_model, "486DRu2"); 491 break; 492 default: 493 strcat(cpu_model, "Unknown"); 494 break; 495 } 496 break; 497 case 0x10: 498 switch (cyrix_did & 0x0f) { 499 case 0x00: 500 strcat(cpu_model, "486S"); 501 break; 502 case 0x01: 503 strcat(cpu_model, "486S2"); 504 break; 505 case 0x02: 506 strcat(cpu_model, "486Se"); 507 break; 508 case 0x03: 509 strcat(cpu_model, "486S2e"); 510 break; 511 case 0x0a: 512 strcat(cpu_model, "486DX"); 513 break; 514 case 0x0b: 515 strcat(cpu_model, "486DX2"); 516 break; 517 case 0x0f: 518 strcat(cpu_model, "486DX4"); 519 break; 520 default: 521 strcat(cpu_model, "Unknown"); 522 break; 523 } 524 break; 525 case 0x20: 526 if ((cyrix_did & 0x0f) < 8) 527 strcat(cpu_model, "6x86"); /* Where did you get it? */ 528 else 529 strcat(cpu_model, "5x86"); 530 break; 531 case 0x30: 532 strcat(cpu_model, "6x86"); 533 break; 534 case 0x40: 535 if ((cyrix_did & 0xf000) == 0x3000) { 536 cpu_class = CPUCLASS_586; 537 strcat(cpu_model, "GXm"); 538 } else 539 strcat(cpu_model, "MediaGX"); 540 break; 541 case 0x50: 542 strcat(cpu_model, "6x86MX"); 543 break; 544 case 0xf0: 545 switch (cyrix_did & 0x0f) { 546 case 0x0d: 547 strcat(cpu_model, "Overdrive CPU"); 548 break; 549 case 0x0e: 550 strcpy(cpu_model, "Texas Instruments 486SXL"); 551 break; 552 case 0x0f: 553 strcat(cpu_model, "486SLC/DLC"); 554 break; 555 default: 556 strcat(cpu_model, "Unknown"); 557 break; 558 } 559 break; 560 default: 561 strcat(cpu_model, "Unknown"); 562 break; 563 } 564 break; 565 } 566 break; 567 case CPU_VENDOR_RISE: 568 strcpy(cpu_model, "Rise "); 569 switch (cpu_id & 0xff0) { 570 case 0x500: /* 6401 and 6441 (Kirin) */ 571 case 0x520: /* 6510 (Lynx) */ 572 strcat(cpu_model, "mP6"); 573 break; 574 default: 575 strcat(cpu_model, "Unknown"); 576 } 577 break; 578#endif 579 case CPU_VENDOR_CENTAUR: 580#ifdef __i386__ 581 switch (cpu_id & 0xff0) { 582 case 0x540: 583 strcpy(cpu_model, "IDT WinChip C6"); 584 break; 585 case 0x580: 586 strcpy(cpu_model, "IDT WinChip 2"); 587 break; 588 case 0x590: 589 strcpy(cpu_model, "IDT WinChip 3"); 590 break; 591 case 0x660: 592 strcpy(cpu_model, "VIA C3 Samuel"); 593 break; 594 case 0x670: 595 if (cpu_id & 0x8) 596 strcpy(cpu_model, "VIA C3 Ezra"); 597 else 598 strcpy(cpu_model, "VIA C3 Samuel 2"); 599 break; 600 case 0x680: 601 strcpy(cpu_model, "VIA C3 Ezra-T"); 602 break; 603 case 0x690: 604 strcpy(cpu_model, "VIA C3 Nehemiah"); 605 break; 606 case 0x6a0: 607 case 0x6d0: 608 strcpy(cpu_model, "VIA C7 Esther"); 609 break; 610 case 0x6f0: 611 strcpy(cpu_model, "VIA Nano"); 612 break; 613 default: 614 strcpy(cpu_model, "VIA/IDT Unknown"); 615 } 616#else 617 strcpy(cpu_model, "VIA "); 618 if ((cpu_id & 0xff0) == 0x6f0) 619 strcat(cpu_model, "Nano Processor"); 620 else 621 strcat(cpu_model, "Unknown"); 622#endif 623 break; 624#ifdef __i386__ 625 case CPU_VENDOR_IBM: 626 strcpy(cpu_model, "Blue Lightning CPU"); 627 break; 628 case CPU_VENDOR_NSC: 629 switch (cpu_id & 0xff0) { 630 case 0x540: 631 strcpy(cpu_model, "Geode SC1100"); 632 cpu = CPU_GEODE1100; 633 break; 634 default: 635 strcpy(cpu_model, "Geode/NSC unknown"); 636 break; 637 } 638 break; 639#endif 640 default: 641 strcat(cpu_model, "Unknown"); 642 break; 643 } 644 645 /* 646 * Replace cpu_model with cpu_brand minus leading spaces if 647 * we have one. 648 */ 649 brand = cpu_brand; 650 while (*brand == ' ') 651 ++brand; 652 if (*brand != '\0') 653 strcpy(cpu_model, brand); 654 655 printf("%s (", cpu_model); 656 if (tsc_freq != 0) { 657 hw_clockrate = (tsc_freq + 5000) / 1000000; 658 printf("%jd.%02d-MHz ", 659 (intmax_t)(tsc_freq + 4999) / 1000000, 660 (u_int)((tsc_freq + 4999) / 10000) % 100); 661 } 662 switch(cpu_class) { 663#ifdef __i386__ 664 case CPUCLASS_286: 665 printf("286"); 666 break; 667 case CPUCLASS_386: 668 printf("386"); 669 break; 670#if defined(I486_CPU) 671 case CPUCLASS_486: 672 printf("486"); 673 break; 674#endif 675#if defined(I586_CPU) 676 case CPUCLASS_586: 677 printf("586"); 678 break; 679#endif 680#if defined(I686_CPU) 681 case CPUCLASS_686: 682 printf("686"); 683 break; 684#endif 685#else 686 case CPUCLASS_K8: 687 printf("K8"); 688 break; 689#endif 690 default: 691 printf("Unknown"); /* will panic below... */ 692 } 693 printf("-class CPU)\n"); 694 if (*cpu_vendor) 695 printf(" Origin=\"%s\"", cpu_vendor); 696 if (cpu_id) 697 printf(" Id=0x%x", cpu_id); 698 699 if (cpu_vendor_id == CPU_VENDOR_INTEL || 700 cpu_vendor_id == CPU_VENDOR_AMD || 701 cpu_vendor_id == CPU_VENDOR_CENTAUR || 702#ifdef __i386__ 703 cpu_vendor_id == CPU_VENDOR_TRANSMETA || 704 cpu_vendor_id == CPU_VENDOR_RISE || 705 cpu_vendor_id == CPU_VENDOR_NSC || 706 (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) || 707#endif 708 0) { 709 printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id)); 710 printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id)); 711 printf(" Stepping=%u", cpu_id & CPUID_STEPPING); 712#ifdef __i386__ 713 if (cpu_vendor_id == CPU_VENDOR_CYRIX) 714 printf("\n DIR=0x%04x", cyrix_did); 715#endif 716 717 /* 718 * AMD CPUID Specification 719 * http://support.amd.com/us/Embedded_TechDocs/25481.pdf 720 * 721 * Intel Processor Identification and CPUID Instruction 722 * http://www.intel.com/assets/pdf/appnote/241618.pdf 723 */ 724 if (cpu_high > 0) { 725 726 /* 727 * Here we should probably set up flags indicating 728 * whether or not various features are available. 729 * The interesting ones are probably VME, PSE, PAE, 730 * and PGE. The code already assumes without bothering 731 * to check that all CPUs >= Pentium have a TSC and 732 * MSRs. 733 */ 734 printf("\n Features=0x%b", cpu_feature, 735 "\020" 736 "\001FPU" /* Integral FPU */ 737 "\002VME" /* Extended VM86 mode support */ 738 "\003DE" /* Debugging Extensions (CR4.DE) */ 739 "\004PSE" /* 4MByte page tables */ 740 "\005TSC" /* Timestamp counter */ 741 "\006MSR" /* Machine specific registers */ 742 "\007PAE" /* Physical address extension */ 743 "\010MCE" /* Machine Check support */ 744 "\011CX8" /* CMPEXCH8 instruction */ 745 "\012APIC" /* SMP local APIC */ 746 "\013oldMTRR" /* Previous implementation of MTRR */ 747 "\014SEP" /* Fast System Call */ 748 "\015MTRR" /* Memory Type Range Registers */ 749 "\016PGE" /* PG_G (global bit) support */ 750 "\017MCA" /* Machine Check Architecture */ 751 "\020CMOV" /* CMOV instruction */ 752 "\021PAT" /* Page attributes table */ 753 "\022PSE36" /* 36 bit address space support */ 754 "\023PN" /* Processor Serial number */ 755 "\024CLFLUSH" /* Has the CLFLUSH instruction */ 756 "\025<b20>" 757 "\026DTS" /* Debug Trace Store */ 758 "\027ACPI" /* ACPI support */ 759 "\030MMX" /* MMX instructions */ 760 "\031FXSR" /* FXSAVE/FXRSTOR */ 761 "\032SSE" /* Streaming SIMD Extensions */ 762 "\033SSE2" /* Streaming SIMD Extensions #2 */ 763 "\034SS" /* Self snoop */ 764 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */ 765 "\036TM" /* Thermal Monitor clock slowdown */ 766 "\037IA64" /* CPU can execute IA64 instructions */ 767 "\040PBE" /* Pending Break Enable */ 768 ); 769 770 if (cpu_feature2 != 0) { 771 printf("\n Features2=0x%b", cpu_feature2, 772 "\020" 773 "\001SSE3" /* SSE3 */ 774 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */ 775 "\003DTES64" /* 64-bit Debug Trace */ 776 "\004MON" /* MONITOR/MWAIT Instructions */ 777 "\005DS_CPL" /* CPL Qualified Debug Store */ 778 "\006VMX" /* Virtual Machine Extensions */ 779 "\007SMX" /* Safer Mode Extensions */ 780 "\010EST" /* Enhanced SpeedStep */ 781 "\011TM2" /* Thermal Monitor 2 */ 782 "\012SSSE3" /* SSSE3 */ 783 "\013CNXT-ID" /* L1 context ID available */ 784 "\014SDBG" /* IA32 silicon debug */ 785 "\015FMA" /* Fused Multiply Add */ 786 "\016CX16" /* CMPXCHG16B Instruction */ 787 "\017xTPR" /* Send Task Priority Messages*/ 788 "\020PDCM" /* Perf/Debug Capability MSR */ 789 "\021<b16>" 790 "\022PCID" /* Process-context Identifiers*/ 791 "\023DCA" /* Direct Cache Access */ 792 "\024SSE4.1" /* SSE 4.1 */ 793 "\025SSE4.2" /* SSE 4.2 */ 794 "\026x2APIC" /* xAPIC Extensions */ 795 "\027MOVBE" /* MOVBE Instruction */ 796 "\030POPCNT" /* POPCNT Instruction */ 797 "\031TSCDLT" /* TSC-Deadline Timer */ 798 "\032AESNI" /* AES Crypto */ 799 "\033XSAVE" /* XSAVE/XRSTOR States */ 800 "\034OSXSAVE" /* OS-Enabled State Management*/ 801 "\035AVX" /* Advanced Vector Extensions */ 802 "\036F16C" /* Half-precision conversions */ 803 "\037RDRAND" /* RDRAND Instruction */ 804 "\040HV" /* Hypervisor */ 805 ); 806 } 807 808 if (amd_feature != 0) { 809 printf("\n AMD Features=0x%b", amd_feature, 810 "\020" /* in hex */ 811 "\001<s0>" /* Same */ 812 "\002<s1>" /* Same */ 813 "\003<s2>" /* Same */ 814 "\004<s3>" /* Same */ 815 "\005<s4>" /* Same */ 816 "\006<s5>" /* Same */ 817 "\007<s6>" /* Same */ 818 "\010<s7>" /* Same */ 819 "\011<s8>" /* Same */ 820 "\012<s9>" /* Same */ 821 "\013<b10>" /* Undefined */ 822 "\014SYSCALL" /* Have SYSCALL/SYSRET */ 823 "\015<s12>" /* Same */ 824 "\016<s13>" /* Same */ 825 "\017<s14>" /* Same */ 826 "\020<s15>" /* Same */ 827 "\021<s16>" /* Same */ 828 "\022<s17>" /* Same */ 829 "\023<b18>" /* Reserved, unknown */ 830 "\024MP" /* Multiprocessor Capable */ 831 "\025NX" /* Has EFER.NXE, NX */ 832 "\026<b21>" /* Undefined */ 833 "\027MMX+" /* AMD MMX Extensions */ 834 "\030<s23>" /* Same */ 835 "\031<s24>" /* Same */ 836 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */ 837 "\033Page1GB" /* 1-GB large page support */ 838 "\034RDTSCP" /* RDTSCP */ 839 "\035<b28>" /* Undefined */ 840 "\036LM" /* 64 bit long mode */ 841 "\0373DNow!+" /* AMD 3DNow! Extensions */ 842 "\0403DNow!" /* AMD 3DNow! */ 843 ); 844 } 845 846 if (amd_feature2 != 0) { 847 printf("\n AMD Features2=0x%b", amd_feature2, 848 "\020" 849 "\001LAHF" /* LAHF/SAHF in long mode */ 850 "\002CMP" /* CMP legacy */ 851 "\003SVM" /* Secure Virtual Mode */ 852 "\004ExtAPIC" /* Extended APIC register */ 853 "\005CR8" /* CR8 in legacy mode */ 854 "\006ABM" /* LZCNT instruction */ 855 "\007SSE4A" /* SSE4A */ 856 "\010MAS" /* Misaligned SSE mode */ 857 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */ 858 "\012OSVW" /* OS visible workaround */ 859 "\013IBS" /* Instruction based sampling */ 860 "\014XOP" /* XOP extended instructions */ 861 "\015SKINIT" /* SKINIT/STGI */ 862 "\016WDT" /* Watchdog timer */ 863 "\017<b14>" 864 "\020LWP" /* Lightweight Profiling */ 865 "\021FMA4" /* 4-operand FMA instructions */ 866 "\022TCE" /* Translation Cache Extension */ 867 "\023<b18>" 868 "\024NodeId" /* NodeId MSR support */ 869 "\025<b20>" 870 "\026TBM" /* Trailing Bit Manipulation */ 871 "\027Topology" /* Topology Extensions */ 872 "\030PCXC" /* Core perf count */ 873 "\031PNXC" /* NB perf count */ 874 "\032<b25>" 875 "\033DBE" /* Data Breakpoint extension */ 876 "\034PTSC" /* Performance TSC */ 877 "\035PL2I" /* L2I perf count */ 878 "\036<b29>" 879 "\037<b30>" 880 "\040<b31>" 881 ); 882 } 883 884 if (cpu_stdext_feature != 0) { 885 printf("\n Structured Extended Features=0x%b", 886 cpu_stdext_feature, 887 "\020" 888 /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ 889 "\001FSGSBASE" 890 "\002TSCADJ" 891 /* Bit Manipulation Instructions */ 892 "\004BMI1" 893 /* Hardware Lock Elision */ 894 "\005HLE" 895 /* Advanced Vector Instructions 2 */ 896 "\006AVX2" 897 /* FDP_EXCPTN_ONLY */ 898 "\007FDPEXC" 899 /* Supervisor Mode Execution Prot. */ 900 "\010SMEP" 901 /* Bit Manipulation Instructions */ 902 "\011BMI2" 903 "\012ERMS" 904 /* Invalidate Processor Context ID */ 905 "\013INVPCID" 906 /* Restricted Transactional Memory */ 907 "\014RTM" 908 "\015PQM" 909 "\016NFPUSG" 910 "\020PQE" 911 /* Intel Memory Protection Extensions */ 912 "\017MPX" 913 /* AVX512 Foundation */ 914 "\021AVX512F" 915 /* Enhanced NRBG */ 916 "\023RDSEED" 917 /* ADCX + ADOX */ 918 "\024ADX" 919 /* Supervisor Mode Access Prevention */ 920 "\025SMAP" 921 "\030CLFLUSHOPT" 922 "\032PROCTRACE" 923 "\033AVX512PF" 924 "\034AVX512ER" 925 "\035AVX512CD" 926 "\036SHA" 927 ); 928 } 929 930 if (cpu_stdext_feature2 != 0) { 931 printf("\n Structured Extended Features2=0x%b", 932 cpu_stdext_feature2, 933 "\020" 934 "\001PREFETCHWT1" 935 "\004PKU" 936 "\005OSPKE" 937 ); 938 } 939 940 if ((cpu_feature2 & CPUID2_XSAVE) != 0) { 941 cpuid_count(0xd, 0x1, regs); 942 if (regs[0] != 0) { 943 printf("\n XSAVE Features=0x%b", 944 regs[0], 945 "\020" 946 "\001XSAVEOPT" 947 "\002XSAVEC" 948 "\003XINUSE" 949 "\004XSAVES"); 950 } 951 } 952 953 if (via_feature_rng != 0 || via_feature_xcrypt != 0) 954 print_via_padlock_info(); 955 956 if (cpu_feature2 & CPUID2_VMX) 957 print_vmx_info(); 958 959 if (amd_feature2 & AMDID2_SVM) 960 print_svm_info(); 961 962 if ((cpu_feature & CPUID_HTT) && 963 cpu_vendor_id == CPU_VENDOR_AMD) 964 cpu_feature &= ~CPUID_HTT; 965 966 /* 967 * If this CPU supports P-state invariant TSC then 968 * mention the capability. 969 */ 970 if (tsc_is_invariant) { 971 printf("\n TSC: P-state invariant"); 972 if (tsc_perf_stat) 973 printf(", performance statistics"); 974 } 975 } 976#ifdef __i386__ 977 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 978 printf(" DIR=0x%04x", cyrix_did); 979 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12); 980 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8); 981#ifndef CYRIX_CACHE_REALLY_WORKS 982 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700) 983 printf("\n CPU cache: write-through mode"); 984#endif 985#endif 986 } 987 988 /* Avoid ugly blank lines: only print newline when we have to. */ 989 if (*cpu_vendor || cpu_id) 990 printf("\n"); 991 992 if (bootverbose) { 993 if (cpu_vendor_id == CPU_VENDOR_AMD) 994 print_AMD_info(); 995 else if (cpu_vendor_id == CPU_VENDOR_INTEL) 996 print_INTEL_info(); 997#ifdef __i386__ 998 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA) 999 print_transmeta_info(); 1000#endif 1001 } 1002 1003 print_hypervisor_info(); 1004} 1005 1006void 1007panicifcpuunsupported(void) 1008{ 1009 1010#ifdef __i386__ 1011#if !defined(lint) 1012#if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU) 1013#error This kernel is not configured for one of the supported CPUs 1014#endif 1015#else /* lint */ 1016#endif /* lint */ 1017#else /* __amd64__ */ 1018#ifndef HAMMER 1019#error "You need to specify a cpu type" 1020#endif 1021#endif 1022 /* 1023 * Now that we have told the user what they have, 1024 * let them know if that machine type isn't configured. 1025 */ 1026 switch (cpu_class) { 1027#ifdef __i386__ 1028 case CPUCLASS_286: /* a 286 should not make it this far, anyway */ 1029 case CPUCLASS_386: 1030#if !defined(I486_CPU) 1031 case CPUCLASS_486: 1032#endif 1033#if !defined(I586_CPU) 1034 case CPUCLASS_586: 1035#endif 1036#if !defined(I686_CPU) 1037 case CPUCLASS_686: 1038#endif 1039#else /* __amd64__ */ 1040 case CPUCLASS_X86: 1041#ifndef HAMMER 1042 case CPUCLASS_K8: 1043#endif 1044#endif 1045 panic("CPU class not configured"); 1046 default: 1047 break; 1048 } 1049} 1050 1051#ifdef __i386__ 1052static volatile u_int trap_by_rdmsr; 1053 1054/* 1055 * Special exception 6 handler. 1056 * The rdmsr instruction generates invalid opcodes fault on 486-class 1057 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the 1058 * function identblue() when this handler is called. Stacked eip should 1059 * be advanced. 1060 */ 1061inthand_t bluetrap6; 1062#ifdef __GNUCLIKE_ASM 1063__asm 1064(" \n\ 1065 .text \n\ 1066 .p2align 2,0x90 \n\ 1067 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\ 1068" __XSTRING(CNAME(bluetrap6)) ": \n\ 1069 ss \n\ 1070 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ 1071 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ 1072 iret \n\ 1073"); 1074#endif 1075 1076/* 1077 * Special exception 13 handler. 1078 * Accessing non-existent MSR generates general protection fault. 1079 */ 1080inthand_t bluetrap13; 1081#ifdef __GNUCLIKE_ASM 1082__asm 1083(" \n\ 1084 .text \n\ 1085 .p2align 2,0x90 \n\ 1086 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\ 1087" __XSTRING(CNAME(bluetrap13)) ": \n\ 1088 ss \n\ 1089 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ 1090 popl %eax /* discard error code */ \n\ 1091 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ 1092 iret \n\ 1093"); 1094#endif 1095 1096/* 1097 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not 1098 * support cpuid instruction. This function should be called after 1099 * loading interrupt descriptor table register. 1100 * 1101 * I don't like this method that handles fault, but I couldn't get 1102 * information for any other methods. Does blue giant know? 1103 */ 1104static int 1105identblue(void) 1106{ 1107 1108 trap_by_rdmsr = 0; 1109 1110 /* 1111 * Cyrix 486-class CPU does not support rdmsr instruction. 1112 * The rdmsr instruction generates invalid opcode fault, and exception 1113 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The 1114 * bluetrap6() set the magic number to trap_by_rdmsr. 1115 */ 1116 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL, 1117 GSEL(GCODE_SEL, SEL_KPL)); 1118 1119 /* 1120 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU. 1121 * In this case, rdmsr generates general protection fault, and 1122 * exception will be trapped by bluetrap13(). 1123 */ 1124 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL, 1125 GSEL(GCODE_SEL, SEL_KPL)); 1126 1127 rdmsr(0x1002); /* Cyrix CPU generates fault. */ 1128 1129 if (trap_by_rdmsr == 0xa8c1d) 1130 return IDENTBLUE_CYRIX486; 1131 else if (trap_by_rdmsr == 0xa89c4) 1132 return IDENTBLUE_CYRIXM2; 1133 return IDENTBLUE_IBMCPU; 1134} 1135 1136 1137/* 1138 * identifycyrix() set lower 16 bits of cyrix_did as follows: 1139 * 1140 * F E D C B A 9 8 7 6 5 4 3 2 1 0 1141 * +-------+-------+---------------+ 1142 * | SID | RID | Device ID | 1143 * | (DIR 1) | (DIR 0) | 1144 * +-------+-------+---------------+ 1145 */ 1146static void 1147identifycyrix(void) 1148{ 1149 register_t saveintr; 1150 int ccr2_test = 0, dir_test = 0; 1151 u_char ccr2, ccr3; 1152 1153 saveintr = intr_disable(); 1154 1155 ccr2 = read_cyrix_reg(CCR2); 1156 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW); 1157 read_cyrix_reg(CCR2); 1158 if (read_cyrix_reg(CCR2) != ccr2) 1159 ccr2_test = 1; 1160 write_cyrix_reg(CCR2, ccr2); 1161 1162 ccr3 = read_cyrix_reg(CCR3); 1163 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3); 1164 read_cyrix_reg(CCR3); 1165 if (read_cyrix_reg(CCR3) != ccr3) 1166 dir_test = 1; /* CPU supports DIRs. */ 1167 write_cyrix_reg(CCR3, ccr3); 1168 1169 if (dir_test) { 1170 /* Device ID registers are available. */ 1171 cyrix_did = read_cyrix_reg(DIR1) << 8; 1172 cyrix_did += read_cyrix_reg(DIR0); 1173 } else if (ccr2_test) 1174 cyrix_did = 0x0010; /* 486S A-step */ 1175 else 1176 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */ 1177 1178 intr_restore(saveintr); 1179} 1180#endif 1181 1182/* Update TSC freq with the value indicated by the caller. */ 1183static void 1184tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status) 1185{ 1186 1187 /* If there was an error during the transition, don't do anything. */ 1188 if (status != 0) 1189 return; 1190 1191 /* Total setting for this level gives the new frequency in MHz. */ 1192 hw_clockrate = level->total_set.freq; 1193} 1194 1195static void 1196hook_tsc_freq(void *arg __unused) 1197{ 1198 1199 if (tsc_is_invariant) 1200 return; 1201 1202 tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change, 1203 tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY); 1204} 1205 1206SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL); 1207 1208#ifndef XEN 1209static const char *const vm_bnames[] = { 1210 "QEMU", /* QEMU */ 1211 "Plex86", /* Plex86 */ 1212 "Bochs", /* Bochs */ 1213 "Xen", /* Xen */ 1214 "BHYVE", /* bhyve */ 1215 "Seabios", /* KVM */ 1216 NULL 1217}; 1218 1219static const char *const vm_pnames[] = { 1220 "VMware Virtual Platform", /* VMWare VM */ 1221 "Virtual Machine", /* Microsoft VirtualPC */ 1222 "VirtualBox", /* Sun xVM VirtualBox */ 1223 "Parallels Virtual Platform", /* Parallels VM */ 1224 "KVM", /* KVM */ 1225 NULL 1226}; 1227 1228static void 1229identify_hypervisor(void) 1230{ 1231 u_int regs[4]; 1232 char *p; 1233 int i; 1234 1235 /* 1236 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1237 * http://lkml.org/lkml/2008/10/1/246 1238 * 1239 * KB1009458: Mechanisms to determine if software is running in 1240 * a VMware virtual machine 1241 * http://kb.vmware.com/kb/1009458 1242 */ 1243 if (cpu_feature2 & CPUID2_HV) { 1244 vm_guest = VM_GUEST_VM; 1245 do_cpuid(0x40000000, regs); 1246 if (regs[0] >= 0x40000000) { 1247 hv_high = regs[0]; 1248 ((u_int *)&hv_vendor)[0] = regs[1]; 1249 ((u_int *)&hv_vendor)[1] = regs[2]; 1250 ((u_int *)&hv_vendor)[2] = regs[3]; 1251 hv_vendor[12] = '\0'; 1252 if (strcmp(hv_vendor, "VMwareVMware") == 0) 1253 vm_guest = VM_GUEST_VMWARE; 1254 } 1255 return; 1256 } 1257 1258 /* 1259 * Examine SMBIOS strings for older hypervisors. 1260 */ 1261 p = getenv("smbios.system.serial"); 1262 if (p != NULL) { 1263 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) { 1264 vmware_hvcall(VMW_HVCMD_GETVERSION, regs); 1265 if (regs[1] == VMW_HVMAGIC) { 1266 vm_guest = VM_GUEST_VMWARE; 1267 freeenv(p); 1268 return; 1269 } 1270 } 1271 freeenv(p); 1272 } 1273 1274 /* 1275 * XXX: Some of these entries may not be needed since they were 1276 * added to FreeBSD before the checks above. 1277 */ 1278 p = getenv("smbios.bios.vendor"); 1279 if (p != NULL) { 1280 for (i = 0; vm_bnames[i] != NULL; i++) 1281 if (strcmp(p, vm_bnames[i]) == 0) { 1282 vm_guest = VM_GUEST_VM; 1283 freeenv(p); 1284 return; 1285 } 1286 freeenv(p); 1287 } 1288 p = getenv("smbios.system.product"); 1289 if (p != NULL) { 1290 for (i = 0; vm_pnames[i] != NULL; i++) 1291 if (strcmp(p, vm_pnames[i]) == 0) { 1292 vm_guest = VM_GUEST_VM; 1293 freeenv(p); 1294 return; 1295 } 1296 freeenv(p); 1297 } 1298} 1299#endif 1300 1301/* 1302 * Clear "Limit CPUID Maxval" bit and return true if the caller should 1303 * get the largest standard CPUID function number again if it is set 1304 * from BIOS. It is necessary for probing correct CPU topology later 1305 * and for the correct operation of the AVX-aware userspace. 1306 */ 1307bool 1308intel_fix_cpuid(void) 1309{ 1310 uint64_t msr; 1311 1312 if (cpu_vendor_id != CPU_VENDOR_INTEL) 1313 return (false); 1314 if ((CPUID_TO_FAMILY(cpu_id) == 0xf && 1315 CPUID_TO_MODEL(cpu_id) >= 0x3) || 1316 (CPUID_TO_FAMILY(cpu_id) == 0x6 && 1317 CPUID_TO_MODEL(cpu_id) >= 0xe)) { 1318 msr = rdmsr(MSR_IA32_MISC_ENABLE); 1319 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) { 1320 msr &= ~IA32_MISC_EN_LIMCPUID; 1321 wrmsr(MSR_IA32_MISC_ENABLE, msr); 1322 return (true); 1323 } 1324 } 1325 return (false); 1326} 1327 1328/* 1329 * Final stage of CPU identification. 1330 */ 1331#ifdef __i386__ 1332void 1333finishidentcpu(void) 1334#else 1335void 1336identify_cpu(void) 1337#endif 1338{ 1339 u_int regs[4], cpu_stdext_disable; 1340#ifdef __i386__ 1341 u_char ccr3; 1342#endif 1343 1344#ifdef __amd64__ 1345 do_cpuid(0, regs); 1346 cpu_high = regs[0]; 1347 ((u_int *)&cpu_vendor)[0] = regs[1]; 1348 ((u_int *)&cpu_vendor)[1] = regs[3]; 1349 ((u_int *)&cpu_vendor)[2] = regs[2]; 1350 cpu_vendor[12] = '\0'; 1351 1352 do_cpuid(1, regs); 1353 cpu_id = regs[0]; 1354 cpu_procinfo = regs[1]; 1355 cpu_feature = regs[3]; 1356 cpu_feature2 = regs[2]; 1357#endif 1358 1359#ifndef XEN 1360 identify_hypervisor(); 1361#endif 1362 cpu_vendor_id = find_cpu_vendor_id(); 1363 1364 if (intel_fix_cpuid()) { 1365 do_cpuid(0, regs); 1366 cpu_high = regs[0]; 1367 } 1368 1369 if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) { 1370 do_cpuid(5, regs); 1371 cpu_mon_mwait_flags = regs[2]; 1372 cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE; 1373 cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE; 1374 } 1375 1376 if (cpu_high >= 7) { 1377 cpuid_count(7, 0, regs); 1378 cpu_stdext_feature = regs[1]; 1379 1380 /* 1381 * Some hypervisors fail to filter out unsupported 1382 * extended features. For now, disable the 1383 * extensions, activation of which requires setting a 1384 * bit in CR4, and which VM monitors do not support. 1385 */ 1386 if (cpu_feature2 & CPUID2_HV) { 1387 cpu_stdext_disable = CPUID_STDEXT_FSGSBASE | 1388 CPUID_STDEXT_SMEP; 1389 } else 1390 cpu_stdext_disable = 0; 1391 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable); 1392 cpu_stdext_feature &= ~cpu_stdext_disable; 1393 cpu_stdext_feature2 = regs[2]; 1394 } 1395 1396#ifdef __i386__ 1397 if (cpu_high > 0 && 1398 (cpu_vendor_id == CPU_VENDOR_INTEL || 1399 cpu_vendor_id == CPU_VENDOR_AMD || 1400 cpu_vendor_id == CPU_VENDOR_TRANSMETA || 1401 cpu_vendor_id == CPU_VENDOR_CENTAUR || 1402 cpu_vendor_id == CPU_VENDOR_NSC)) { 1403 do_cpuid(0x80000000, regs); 1404 if (regs[0] >= 0x80000000) 1405 cpu_exthigh = regs[0]; 1406 } 1407#else 1408 if (cpu_vendor_id == CPU_VENDOR_INTEL || 1409 cpu_vendor_id == CPU_VENDOR_AMD || 1410 cpu_vendor_id == CPU_VENDOR_CENTAUR) { 1411 do_cpuid(0x80000000, regs); 1412 cpu_exthigh = regs[0]; 1413 } 1414#endif 1415 if (cpu_exthigh >= 0x80000001) { 1416 do_cpuid(0x80000001, regs); 1417 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff); 1418 amd_feature2 = regs[2]; 1419 } 1420 if (cpu_exthigh >= 0x80000007) { 1421 do_cpuid(0x80000007, regs); 1422 amd_pminfo = regs[3]; 1423 } 1424 if (cpu_exthigh >= 0x80000008) { 1425 do_cpuid(0x80000008, regs); 1426 cpu_maxphyaddr = regs[0] & 0xff; 1427 cpu_procinfo2 = regs[2]; 1428 } else { 1429 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32; 1430 } 1431 1432#ifdef __i386__ 1433 if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 1434 if (cpu == CPU_486) { 1435 /* 1436 * These conditions are equivalent to: 1437 * - CPU does not support cpuid instruction. 1438 * - Cyrix/IBM CPU is detected. 1439 */ 1440 if (identblue() == IDENTBLUE_IBMCPU) { 1441 strcpy(cpu_vendor, "IBM"); 1442 cpu_vendor_id = CPU_VENDOR_IBM; 1443 cpu = CPU_BLUE; 1444 return; 1445 } 1446 } 1447 switch (cpu_id & 0xf00) { 1448 case 0x600: 1449 /* 1450 * Cyrix's datasheet does not describe DIRs. 1451 * Therefor, I assume it does not have them 1452 * and use the result of the cpuid instruction. 1453 * XXX they seem to have it for now at least. -Peter 1454 */ 1455 identifycyrix(); 1456 cpu = CPU_M2; 1457 break; 1458 default: 1459 identifycyrix(); 1460 /* 1461 * This routine contains a trick. 1462 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now. 1463 */ 1464 switch (cyrix_did & 0x00f0) { 1465 case 0x00: 1466 case 0xf0: 1467 cpu = CPU_486DLC; 1468 break; 1469 case 0x10: 1470 cpu = CPU_CY486DX; 1471 break; 1472 case 0x20: 1473 if ((cyrix_did & 0x000f) < 8) 1474 cpu = CPU_M1; 1475 else 1476 cpu = CPU_M1SC; 1477 break; 1478 case 0x30: 1479 cpu = CPU_M1; 1480 break; 1481 case 0x40: 1482 /* MediaGX CPU */ 1483 cpu = CPU_M1SC; 1484 break; 1485 default: 1486 /* M2 and later CPUs are treated as M2. */ 1487 cpu = CPU_M2; 1488 1489 /* 1490 * enable cpuid instruction. 1491 */ 1492 ccr3 = read_cyrix_reg(CCR3); 1493 write_cyrix_reg(CCR3, CCR3_MAPEN0); 1494 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID); 1495 write_cyrix_reg(CCR3, ccr3); 1496 1497 do_cpuid(0, regs); 1498 cpu_high = regs[0]; /* eax */ 1499 do_cpuid(1, regs); 1500 cpu_id = regs[0]; /* eax */ 1501 cpu_feature = regs[3]; /* edx */ 1502 break; 1503 } 1504 } 1505 } else if (cpu == CPU_486 && *cpu_vendor == '\0') { 1506 /* 1507 * There are BlueLightning CPUs that do not change 1508 * undefined flags by dividing 5 by 2. In this case, 1509 * the CPU identification routine in locore.s leaves 1510 * cpu_vendor null string and puts CPU_486 into the 1511 * cpu. 1512 */ 1513 if (identblue() == IDENTBLUE_IBMCPU) { 1514 strcpy(cpu_vendor, "IBM"); 1515 cpu_vendor_id = CPU_VENDOR_IBM; 1516 cpu = CPU_BLUE; 1517 return; 1518 } 1519 } 1520#else 1521 /* XXX */ 1522 cpu = CPU_CLAWHAMMER; 1523#endif 1524} 1525 1526static u_int 1527find_cpu_vendor_id(void) 1528{ 1529 int i; 1530 1531 for (i = 0; i < sizeof(cpu_vendors) / sizeof(cpu_vendors[0]); i++) 1532 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0) 1533 return (cpu_vendors[i].vendor_id); 1534 return (0); 1535} 1536 1537static void 1538print_AMD_assoc(int i) 1539{ 1540 if (i == 255) 1541 printf(", fully associative\n"); 1542 else 1543 printf(", %d-way associative\n", i); 1544} 1545 1546static void 1547print_AMD_l2_assoc(int i) 1548{ 1549 switch (i & 0x0f) { 1550 case 0: printf(", disabled/not present\n"); break; 1551 case 1: printf(", direct mapped\n"); break; 1552 case 2: printf(", 2-way associative\n"); break; 1553 case 4: printf(", 4-way associative\n"); break; 1554 case 6: printf(", 8-way associative\n"); break; 1555 case 8: printf(", 16-way associative\n"); break; 1556 case 15: printf(", fully associative\n"); break; 1557 default: printf(", reserved configuration\n"); break; 1558 } 1559} 1560 1561static void 1562print_AMD_info(void) 1563{ 1564#ifdef __i386__ 1565 uint64_t amd_whcr; 1566#endif 1567 u_int regs[4]; 1568 1569 if (cpu_exthigh >= 0x80000005) { 1570 do_cpuid(0x80000005, regs); 1571 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff); 1572 print_AMD_assoc(regs[0] >> 24); 1573 1574 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff); 1575 print_AMD_assoc((regs[0] >> 8) & 0xff); 1576 1577 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff); 1578 print_AMD_assoc(regs[1] >> 24); 1579 1580 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff); 1581 print_AMD_assoc((regs[1] >> 8) & 0xff); 1582 1583 printf("L1 data cache: %d kbytes", regs[2] >> 24); 1584 printf(", %d bytes/line", regs[2] & 0xff); 1585 printf(", %d lines/tag", (regs[2] >> 8) & 0xff); 1586 print_AMD_assoc((regs[2] >> 16) & 0xff); 1587 1588 printf("L1 instruction cache: %d kbytes", regs[3] >> 24); 1589 printf(", %d bytes/line", regs[3] & 0xff); 1590 printf(", %d lines/tag", (regs[3] >> 8) & 0xff); 1591 print_AMD_assoc((regs[3] >> 16) & 0xff); 1592 } 1593 1594 if (cpu_exthigh >= 0x80000006) { 1595 do_cpuid(0x80000006, regs); 1596 if ((regs[0] >> 16) != 0) { 1597 printf("L2 2MB data TLB: %d entries", 1598 (regs[0] >> 16) & 0xfff); 1599 print_AMD_l2_assoc(regs[0] >> 28); 1600 printf("L2 2MB instruction TLB: %d entries", 1601 regs[0] & 0xfff); 1602 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 1603 } else { 1604 printf("L2 2MB unified TLB: %d entries", 1605 regs[0] & 0xfff); 1606 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 1607 } 1608 if ((regs[1] >> 16) != 0) { 1609 printf("L2 4KB data TLB: %d entries", 1610 (regs[1] >> 16) & 0xfff); 1611 print_AMD_l2_assoc(regs[1] >> 28); 1612 1613 printf("L2 4KB instruction TLB: %d entries", 1614 (regs[1] >> 16) & 0xfff); 1615 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 1616 } else { 1617 printf("L2 4KB unified TLB: %d entries", 1618 (regs[1] >> 16) & 0xfff); 1619 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 1620 } 1621 printf("L2 unified cache: %d kbytes", regs[2] >> 16); 1622 printf(", %d bytes/line", regs[2] & 0xff); 1623 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f); 1624 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f); 1625 } 1626 1627#ifdef __i386__ 1628 if (((cpu_id & 0xf00) == 0x500) 1629 && (((cpu_id & 0x0f0) > 0x80) 1630 || (((cpu_id & 0x0f0) == 0x80) 1631 && (cpu_id & 0x00f) > 0x07))) { 1632 /* K6-2(new core [Stepping 8-F]), K6-III or later */ 1633 amd_whcr = rdmsr(0xc0000082); 1634 if (!(amd_whcr & (0x3ff << 22))) { 1635 printf("Write Allocate Disable\n"); 1636 } else { 1637 printf("Write Allocate Enable Limit: %dM bytes\n", 1638 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4); 1639 printf("Write Allocate 15-16M bytes: %s\n", 1640 (amd_whcr & (1 << 16)) ? "Enable" : "Disable"); 1641 } 1642 } else if (((cpu_id & 0xf00) == 0x500) 1643 && ((cpu_id & 0x0f0) > 0x50)) { 1644 /* K6, K6-2(old core) */ 1645 amd_whcr = rdmsr(0xc0000082); 1646 if (!(amd_whcr & (0x7f << 1))) { 1647 printf("Write Allocate Disable\n"); 1648 } else { 1649 printf("Write Allocate Enable Limit: %dM bytes\n", 1650 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4); 1651 printf("Write Allocate 15-16M bytes: %s\n", 1652 (amd_whcr & 0x0001) ? "Enable" : "Disable"); 1653 printf("Hardware Write Allocate Control: %s\n", 1654 (amd_whcr & 0x0100) ? "Enable" : "Disable"); 1655 } 1656 } 1657#endif 1658 /* 1659 * Opteron Rev E shows a bug as in very rare occasions a read memory 1660 * barrier is not performed as expected if it is followed by a 1661 * non-atomic read-modify-write instruction. 1662 * As long as that bug pops up very rarely (intensive machine usage 1663 * on other operating systems generally generates one unexplainable 1664 * crash any 2 months) and as long as a model specific fix would be 1665 * impratical at this stage, print out a warning string if the broken 1666 * model and family are identified. 1667 */ 1668 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 && 1669 CPUID_TO_MODEL(cpu_id) <= 0x3f) 1670 printf("WARNING: This architecture revision has known SMP " 1671 "hardware bugs which may cause random instability\n"); 1672} 1673 1674static void 1675print_INTEL_info(void) 1676{ 1677 u_int regs[4]; 1678 u_int rounds, regnum; 1679 u_int nwaycode, nway; 1680 1681 if (cpu_high >= 2) { 1682 rounds = 0; 1683 do { 1684 do_cpuid(0x2, regs); 1685 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0) 1686 break; /* we have a buggy CPU */ 1687 1688 for (regnum = 0; regnum <= 3; ++regnum) { 1689 if (regs[regnum] & (1<<31)) 1690 continue; 1691 if (regnum != 0) 1692 print_INTEL_TLB(regs[regnum] & 0xff); 1693 print_INTEL_TLB((regs[regnum] >> 8) & 0xff); 1694 print_INTEL_TLB((regs[regnum] >> 16) & 0xff); 1695 print_INTEL_TLB((regs[regnum] >> 24) & 0xff); 1696 } 1697 } while (--rounds > 0); 1698 } 1699 1700 if (cpu_exthigh >= 0x80000006) { 1701 do_cpuid(0x80000006, regs); 1702 nwaycode = (regs[2] >> 12) & 0x0f; 1703 if (nwaycode >= 0x02 && nwaycode <= 0x08) 1704 nway = 1 << (nwaycode / 2); 1705 else 1706 nway = 0; 1707 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n", 1708 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff); 1709 } 1710} 1711 1712static void 1713print_INTEL_TLB(u_int data) 1714{ 1715 switch (data) { 1716 case 0x0: 1717 case 0x40: 1718 default: 1719 break; 1720 case 0x1: 1721 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n"); 1722 break; 1723 case 0x2: 1724 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n"); 1725 break; 1726 case 0x3: 1727 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n"); 1728 break; 1729 case 0x4: 1730 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n"); 1731 break; 1732 case 0x6: 1733 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n"); 1734 break; 1735 case 0x8: 1736 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n"); 1737 break; 1738 case 0x9: 1739 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n"); 1740 break; 1741 case 0xa: 1742 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n"); 1743 break; 1744 case 0xb: 1745 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n"); 1746 break; 1747 case 0xc: 1748 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n"); 1749 break; 1750 case 0xd: 1751 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size"); 1752 break; 1753 case 0xe: 1754 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n"); 1755 break; 1756 case 0x1d: 1757 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n"); 1758 break; 1759 case 0x21: 1760 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n"); 1761 break; 1762 case 0x22: 1763 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 1764 break; 1765 case 0x23: 1766 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 1767 break; 1768 case 0x24: 1769 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n"); 1770 break; 1771 case 0x25: 1772 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 1773 break; 1774 case 0x29: 1775 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 1776 break; 1777 case 0x2c: 1778 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n"); 1779 break; 1780 case 0x30: 1781 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n"); 1782 break; 1783 case 0x39: /* De-listed in SDM rev. 54 */ 1784 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 1785 break; 1786 case 0x3b: /* De-listed in SDM rev. 54 */ 1787 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n"); 1788 break; 1789 case 0x3c: /* De-listed in SDM rev. 54 */ 1790 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 1791 break; 1792 case 0x41: 1793 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n"); 1794 break; 1795 case 0x42: 1796 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n"); 1797 break; 1798 case 0x43: 1799 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n"); 1800 break; 1801 case 0x44: 1802 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n"); 1803 break; 1804 case 0x45: 1805 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n"); 1806 break; 1807 case 0x46: 1808 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n"); 1809 break; 1810 case 0x47: 1811 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n"); 1812 break; 1813 case 0x48: 1814 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n"); 1815 break; 1816 case 0x49: 1817 if (CPUID_TO_FAMILY(cpu_id) == 0xf && 1818 CPUID_TO_MODEL(cpu_id) == 0x6) 1819 printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n"); 1820 else 1821 printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size"); 1822 break; 1823 case 0x4a: 1824 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n"); 1825 break; 1826 case 0x4b: 1827 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n"); 1828 break; 1829 case 0x4c: 1830 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n"); 1831 break; 1832 case 0x4d: 1833 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n"); 1834 break; 1835 case 0x4e: 1836 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n"); 1837 break; 1838 case 0x4f: 1839 printf("Instruction TLB: 4 KByte pages, 32 entries\n"); 1840 break; 1841 case 0x50: 1842 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n"); 1843 break; 1844 case 0x51: 1845 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n"); 1846 break; 1847 case 0x52: 1848 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n"); 1849 break; 1850 case 0x55: 1851 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n"); 1852 break; 1853 case 0x56: 1854 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n"); 1855 break; 1856 case 0x57: 1857 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n"); 1858 break; 1859 case 0x59: 1860 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n"); 1861 break; 1862 case 0x5a: 1863 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n"); 1864 break; 1865 case 0x5b: 1866 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n"); 1867 break; 1868 case 0x5c: 1869 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n"); 1870 break; 1871 case 0x5d: 1872 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n"); 1873 break; 1874 case 0x60: 1875 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 1876 break; 1877 case 0x61: 1878 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n"); 1879 break; 1880 case 0x63: 1881 printf("Data TLB: 1 GByte pages, 4-way set associative, 4 entries\n"); 1882 break; 1883 case 0x66: 1884 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 1885 break; 1886 case 0x67: 1887 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 1888 break; 1889 case 0x68: 1890 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n"); 1891 break; 1892 case 0x6a: 1893 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n"); 1894 break; 1895 case 0x6b: 1896 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n"); 1897 break; 1898 case 0x6c: 1899 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n"); 1900 break; 1901 case 0x6d: 1902 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n"); 1903 break; 1904 case 0x70: 1905 printf("Trace cache: 12K-uops, 8-way set associative\n"); 1906 break; 1907 case 0x71: 1908 printf("Trace cache: 16K-uops, 8-way set associative\n"); 1909 break; 1910 case 0x72: 1911 printf("Trace cache: 32K-uops, 8-way set associative\n"); 1912 break; 1913 case 0x76: 1914 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n"); 1915 break; 1916 case 0x78: 1917 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n"); 1918 break; 1919 case 0x79: 1920 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 1921 break; 1922 case 0x7a: 1923 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 1924 break; 1925 case 0x7b: 1926 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 1927 break; 1928 case 0x7c: 1929 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 1930 break; 1931 case 0x7d: 1932 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n"); 1933 break; 1934 case 0x7f: 1935 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n"); 1936 break; 1937 case 0x80: 1938 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n"); 1939 break; 1940 case 0x82: 1941 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n"); 1942 break; 1943 case 0x83: 1944 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n"); 1945 break; 1946 case 0x84: 1947 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n"); 1948 break; 1949 case 0x85: 1950 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n"); 1951 break; 1952 case 0x86: 1953 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n"); 1954 break; 1955 case 0x87: 1956 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n"); 1957 break; 1958 case 0xa0: 1959 printf("DTLB: 4k pages, fully associative, 32 entries\n"); 1960 break; 1961 case 0xb0: 1962 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n"); 1963 break; 1964 case 0xb1: 1965 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n"); 1966 break; 1967 case 0xb2: 1968 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n"); 1969 break; 1970 case 0xb3: 1971 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n"); 1972 break; 1973 case 0xb4: 1974 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n"); 1975 break; 1976 case 0xb5: 1977 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n"); 1978 break; 1979 case 0xb6: 1980 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n"); 1981 break; 1982 case 0xba: 1983 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n"); 1984 break; 1985 case 0xc0: 1986 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n"); 1987 break; 1988 case 0xc1: 1989 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n"); 1990 break; 1991 case 0xc2: 1992 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n"); 1993 break; 1994 case 0xc3: 1995 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n"); 1996 break; 1997 case 0xca: 1998 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n"); 1999 break; 2000 case 0xd0: 2001 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n"); 2002 break; 2003 case 0xd1: 2004 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n"); 2005 break; 2006 case 0xd2: 2007 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n"); 2008 break; 2009 case 0xd6: 2010 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n"); 2011 break; 2012 case 0xd7: 2013 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n"); 2014 break; 2015 case 0xd8: 2016 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n"); 2017 break; 2018 case 0xdc: 2019 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n"); 2020 break; 2021 case 0xdd: 2022 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n"); 2023 break; 2024 case 0xde: 2025 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n"); 2026 break; 2027 case 0xe2: 2028 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n"); 2029 break; 2030 case 0xe3: 2031 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n"); 2032 break; 2033 case 0xe4: 2034 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n"); 2035 break; 2036 case 0xea: 2037 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n"); 2038 break; 2039 case 0xeb: 2040 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n"); 2041 break; 2042 case 0xec: 2043 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n"); 2044 break; 2045 case 0xf0: 2046 printf("64-Byte prefetching\n"); 2047 break; 2048 case 0xf1: 2049 printf("128-Byte prefetching\n"); 2050 break; 2051 } 2052} 2053 2054static void 2055print_svm_info(void) 2056{ 2057 u_int features, regs[4]; 2058 uint64_t msr; 2059 int comma; 2060 2061 printf("\n SVM: "); 2062 do_cpuid(0x8000000A, regs); 2063 features = regs[3]; 2064 2065 msr = rdmsr(MSR_VM_CR); 2066 if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS) 2067 printf("(disabled in BIOS) "); 2068 2069 if (!bootverbose) { 2070 comma = 0; 2071 if (features & (1 << 0)) { 2072 printf("%sNP", comma ? "," : ""); 2073 comma = 1; 2074 } 2075 if (features & (1 << 3)) { 2076 printf("%sNRIP", comma ? "," : ""); 2077 comma = 1; 2078 } 2079 if (features & (1 << 5)) { 2080 printf("%sVClean", comma ? "," : ""); 2081 comma = 1; 2082 } 2083 if (features & (1 << 6)) { 2084 printf("%sAFlush", comma ? "," : ""); 2085 comma = 1; 2086 } 2087 if (features & (1 << 7)) { 2088 printf("%sDAssist", comma ? "," : ""); 2089 comma = 1; 2090 } 2091 printf("%sNAsids=%d", comma ? "," : "", regs[1]); 2092 return; 2093 } 2094 2095 printf("Features=0x%b", features, 2096 "\020" 2097 "\001NP" /* Nested paging */ 2098 "\002LbrVirt" /* LBR virtualization */ 2099 "\003SVML" /* SVM lock */ 2100 "\004NRIPS" /* NRIP save */ 2101 "\005TscRateMsr" /* MSR based TSC rate control */ 2102 "\006VmcbClean" /* VMCB clean bits */ 2103 "\007FlushByAsid" /* Flush by ASID */ 2104 "\010DecodeAssist" /* Decode assist */ 2105 "\011<b8>" 2106 "\012<b9>" 2107 "\013PauseFilter" /* PAUSE intercept filter */ 2108 "\014<b11>" 2109 "\015PauseFilterThreshold" /* PAUSE filter threshold */ 2110 "\016AVIC" /* virtual interrupt controller */ 2111 ); 2112 printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]); 2113} 2114 2115#ifdef __i386__ 2116static void 2117print_transmeta_info(void) 2118{ 2119 u_int regs[4], nreg = 0; 2120 2121 do_cpuid(0x80860000, regs); 2122 nreg = regs[0]; 2123 if (nreg >= 0x80860001) { 2124 do_cpuid(0x80860001, regs); 2125 printf(" Processor revision %u.%u.%u.%u\n", 2126 (regs[1] >> 24) & 0xff, 2127 (regs[1] >> 16) & 0xff, 2128 (regs[1] >> 8) & 0xff, 2129 regs[1] & 0xff); 2130 } 2131 if (nreg >= 0x80860002) { 2132 do_cpuid(0x80860002, regs); 2133 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n", 2134 (regs[1] >> 24) & 0xff, 2135 (regs[1] >> 16) & 0xff, 2136 (regs[1] >> 8) & 0xff, 2137 regs[1] & 0xff, 2138 regs[2]); 2139 } 2140 if (nreg >= 0x80860006) { 2141 char info[65]; 2142 do_cpuid(0x80860003, (u_int*) &info[0]); 2143 do_cpuid(0x80860004, (u_int*) &info[16]); 2144 do_cpuid(0x80860005, (u_int*) &info[32]); 2145 do_cpuid(0x80860006, (u_int*) &info[48]); 2146 info[64] = 0; 2147 printf(" %s\n", info); 2148 } 2149} 2150#endif 2151 2152static void 2153print_via_padlock_info(void) 2154{ 2155 u_int regs[4]; 2156 2157 do_cpuid(0xc0000001, regs); 2158 printf("\n VIA Padlock Features=0x%b", regs[3], 2159 "\020" 2160 "\003RNG" /* RNG */ 2161 "\007AES" /* ACE */ 2162 "\011AES-CTR" /* ACE2 */ 2163 "\013SHA1,SHA256" /* PHE */ 2164 "\015RSA" /* PMM */ 2165 ); 2166} 2167 2168static uint32_t 2169vmx_settable(uint64_t basic, int msr, int true_msr) 2170{ 2171 uint64_t val; 2172 2173 if (basic & (1ULL << 55)) 2174 val = rdmsr(true_msr); 2175 else 2176 val = rdmsr(msr); 2177 2178 /* Just report the controls that can be set to 1. */ 2179 return (val >> 32); 2180} 2181 2182static void 2183print_vmx_info(void) 2184{ 2185 uint64_t basic, msr; 2186 uint32_t entry, exit, mask, pin, proc, proc2; 2187 int comma; 2188 2189 printf("\n VT-x: "); 2190 msr = rdmsr(MSR_IA32_FEATURE_CONTROL); 2191 if (!(msr & IA32_FEATURE_CONTROL_VMX_EN)) 2192 printf("(disabled in BIOS) "); 2193 basic = rdmsr(MSR_VMX_BASIC); 2194 pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS, 2195 MSR_VMX_TRUE_PINBASED_CTLS); 2196 proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS, 2197 MSR_VMX_TRUE_PROCBASED_CTLS); 2198 if (proc & PROCBASED_SECONDARY_CONTROLS) 2199 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2, 2200 MSR_VMX_PROCBASED_CTLS2); 2201 else 2202 proc2 = 0; 2203 exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS); 2204 entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS); 2205 2206 if (!bootverbose) { 2207 comma = 0; 2208 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT && 2209 entry & VM_ENTRY_LOAD_PAT) { 2210 printf("%sPAT", comma ? "," : ""); 2211 comma = 1; 2212 } 2213 if (proc & PROCBASED_HLT_EXITING) { 2214 printf("%sHLT", comma ? "," : ""); 2215 comma = 1; 2216 } 2217 if (proc & PROCBASED_MTF) { 2218 printf("%sMTF", comma ? "," : ""); 2219 comma = 1; 2220 } 2221 if (proc & PROCBASED_PAUSE_EXITING) { 2222 printf("%sPAUSE", comma ? "," : ""); 2223 comma = 1; 2224 } 2225 if (proc2 & PROCBASED2_ENABLE_EPT) { 2226 printf("%sEPT", comma ? "," : ""); 2227 comma = 1; 2228 } 2229 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) { 2230 printf("%sUG", comma ? "," : ""); 2231 comma = 1; 2232 } 2233 if (proc2 & PROCBASED2_ENABLE_VPID) { 2234 printf("%sVPID", comma ? "," : ""); 2235 comma = 1; 2236 } 2237 if (proc & PROCBASED_USE_TPR_SHADOW && 2238 proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES && 2239 proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE && 2240 proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION && 2241 proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) { 2242 printf("%sVID", comma ? "," : ""); 2243 comma = 1; 2244 if (pin & PINBASED_POSTED_INTERRUPT) 2245 printf(",PostIntr"); 2246 } 2247 return; 2248 } 2249 2250 mask = basic >> 32; 2251 printf("Basic Features=0x%b", mask, 2252 "\020" 2253 "\02132PA" /* 32-bit physical addresses */ 2254 "\022SMM" /* SMM dual-monitor */ 2255 "\027INS/OUTS" /* VM-exit info for INS and OUTS */ 2256 "\030TRUE" /* TRUE_CTLS MSRs */ 2257 ); 2258 printf("\n Pin-Based Controls=0x%b", pin, 2259 "\020" 2260 "\001ExtINT" /* External-interrupt exiting */ 2261 "\004NMI" /* NMI exiting */ 2262 "\006VNMI" /* Virtual NMIs */ 2263 "\007PreTmr" /* Activate VMX-preemption timer */ 2264 "\010PostIntr" /* Process posted interrupts */ 2265 ); 2266 printf("\n Primary Processor Controls=0x%b", proc, 2267 "\020" 2268 "\003INTWIN" /* Interrupt-window exiting */ 2269 "\004TSCOff" /* Use TSC offsetting */ 2270 "\010HLT" /* HLT exiting */ 2271 "\012INVLPG" /* INVLPG exiting */ 2272 "\013MWAIT" /* MWAIT exiting */ 2273 "\014RDPMC" /* RDPMC exiting */ 2274 "\015RDTSC" /* RDTSC exiting */ 2275 "\020CR3-LD" /* CR3-load exiting */ 2276 "\021CR3-ST" /* CR3-store exiting */ 2277 "\024CR8-LD" /* CR8-load exiting */ 2278 "\025CR8-ST" /* CR8-store exiting */ 2279 "\026TPR" /* Use TPR shadow */ 2280 "\027NMIWIN" /* NMI-window exiting */ 2281 "\030MOV-DR" /* MOV-DR exiting */ 2282 "\031IO" /* Unconditional I/O exiting */ 2283 "\032IOmap" /* Use I/O bitmaps */ 2284 "\034MTF" /* Monitor trap flag */ 2285 "\035MSRmap" /* Use MSR bitmaps */ 2286 "\036MONITOR" /* MONITOR exiting */ 2287 "\037PAUSE" /* PAUSE exiting */ 2288 ); 2289 if (proc & PROCBASED_SECONDARY_CONTROLS) 2290 printf("\n Secondary Processor Controls=0x%b", proc2, 2291 "\020" 2292 "\001APIC" /* Virtualize APIC accesses */ 2293 "\002EPT" /* Enable EPT */ 2294 "\003DT" /* Descriptor-table exiting */ 2295 "\004RDTSCP" /* Enable RDTSCP */ 2296 "\005x2APIC" /* Virtualize x2APIC mode */ 2297 "\006VPID" /* Enable VPID */ 2298 "\007WBINVD" /* WBINVD exiting */ 2299 "\010UG" /* Unrestricted guest */ 2300 "\011APIC-reg" /* APIC-register virtualization */ 2301 "\012VID" /* Virtual-interrupt delivery */ 2302 "\013PAUSE-loop" /* PAUSE-loop exiting */ 2303 "\014RDRAND" /* RDRAND exiting */ 2304 "\015INVPCID" /* Enable INVPCID */ 2305 "\016VMFUNC" /* Enable VM functions */ 2306 "\017VMCS" /* VMCS shadowing */ 2307 "\020EPT#VE" /* EPT-violation #VE */ 2308 "\021XSAVES" /* Enable XSAVES/XRSTORS */ 2309 ); 2310 printf("\n Exit Controls=0x%b", mask, 2311 "\020" 2312 "\003DR" /* Save debug controls */ 2313 /* Ignore Host address-space size */ 2314 "\015PERF" /* Load MSR_PERF_GLOBAL_CTRL */ 2315 "\020AckInt" /* Acknowledge interrupt on exit */ 2316 "\023PAT-SV" /* Save MSR_PAT */ 2317 "\024PAT-LD" /* Load MSR_PAT */ 2318 "\025EFER-SV" /* Save MSR_EFER */ 2319 "\026EFER-LD" /* Load MSR_EFER */ 2320 "\027PTMR-SV" /* Save VMX-preemption timer value */ 2321 ); 2322 printf("\n Entry Controls=0x%b", mask, 2323 "\020" 2324 "\003DR" /* Save debug controls */ 2325 /* Ignore IA-32e mode guest */ 2326 /* Ignore Entry to SMM */ 2327 /* Ignore Deactivate dual-monitor treatment */ 2328 "\016PERF" /* Load MSR_PERF_GLOBAL_CTRL */ 2329 "\017PAT" /* Load MSR_PAT */ 2330 "\020EFER" /* Load MSR_EFER */ 2331 ); 2332 if (proc & PROCBASED_SECONDARY_CONTROLS && 2333 (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) { 2334 msr = rdmsr(MSR_VMX_EPT_VPID_CAP); 2335 mask = msr; 2336 printf("\n EPT Features=0x%b", mask, 2337 "\020" 2338 "\001XO" /* Execute-only translations */ 2339 "\007PW4" /* Page-walk length of 4 */ 2340 "\011UC" /* EPT paging-structure mem can be UC */ 2341 "\017WB" /* EPT paging-structure mem can be WB */ 2342 "\0212M" /* EPT PDE can map a 2-Mbyte page */ 2343 "\0221G" /* EPT PDPTE can map a 1-Gbyte page */ 2344 "\025INVEPT" /* INVEPT is supported */ 2345 "\026AD" /* Accessed and dirty flags for EPT */ 2346 "\032single" /* INVEPT single-context type */ 2347 "\033all" /* INVEPT all-context type */ 2348 ); 2349 mask = msr >> 32; 2350 printf("\n VPID Features=0x%b", mask, 2351 "\020" 2352 "\001INVVPID" /* INVVPID is supported */ 2353 "\011individual" /* INVVPID individual-address type */ 2354 "\012single" /* INVVPID single-context type */ 2355 "\013all" /* INVVPID all-context type */ 2356 /* INVVPID single-context-retaining-globals type */ 2357 "\014single-globals" 2358 ); 2359 } 2360} 2361 2362static void 2363print_hypervisor_info(void) 2364{ 2365 2366 if (*hv_vendor) 2367 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor); 2368} 2369