identcpu.c revision 276482
1/*- 2 * Copyright (c) 1992 Terrence R. Lambert. 3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 4 * Copyright (c) 1997 KATO Takenori. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp 39 */ 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD: stable/10/sys/x86/x86/identcpu.c 276482 2014-12-31 22:15:28Z neel $"); 43 44#include "opt_cpu.h" 45 46#include <sys/param.h> 47#include <sys/bus.h> 48#include <sys/cpu.h> 49#include <sys/eventhandler.h> 50#include <sys/systm.h> 51#include <sys/kernel.h> 52#include <sys/sysctl.h> 53#include <sys/power.h> 54 55#include <machine/asmacros.h> 56#include <machine/clock.h> 57#include <machine/cputypes.h> 58#include <machine/frame.h> 59#include <machine/intr_machdep.h> 60#include <machine/md_var.h> 61#include <machine/segments.h> 62#include <machine/specialreg.h> 63 64#include <amd64/vmm/intel/vmx_controls.h> 65#include <x86/isa/icu.h> 66 67#ifdef __i386__ 68#define IDENTBLUE_CYRIX486 0 69#define IDENTBLUE_IBMCPU 1 70#define IDENTBLUE_CYRIXM2 2 71 72static void identifycyrix(void); 73static void print_transmeta_info(void); 74#endif 75static u_int find_cpu_vendor_id(void); 76static void print_AMD_info(void); 77static void print_INTEL_info(void); 78static void print_INTEL_TLB(u_int data); 79static void print_svm_info(void); 80static void print_via_padlock_info(void); 81static void print_vmx_info(void); 82 83int cpu_class; 84char machine[] = MACHINE; 85 86#ifdef __amd64__ 87#ifdef SCTL_MASK32 88extern int adaptive_machine_arch; 89#endif 90 91static int 92sysctl_hw_machine(SYSCTL_HANDLER_ARGS) 93{ 94#ifdef SCTL_MASK32 95 static const char machine32[] = "i386"; 96#endif 97 int error; 98 99#ifdef SCTL_MASK32 100 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch) 101 error = SYSCTL_OUT(req, machine32, sizeof(machine32)); 102 else 103#endif 104 error = SYSCTL_OUT(req, machine, sizeof(machine)); 105 return (error); 106 107} 108SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD, 109 NULL, 0, sysctl_hw_machine, "A", "Machine class"); 110#else 111SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 112 machine, 0, "Machine class"); 113#endif 114 115static char cpu_model[128]; 116SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, 117 cpu_model, 0, "Machine model"); 118 119static int hw_clockrate; 120SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 121 &hw_clockrate, 0, "CPU instruction clock rate"); 122 123static eventhandler_tag tsc_post_tag; 124 125static char cpu_brand[48]; 126 127#ifdef __i386__ 128#define MAX_BRAND_INDEX 8 129 130static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = { 131 NULL, /* No brand */ 132 "Intel Celeron", 133 "Intel Pentium III", 134 "Intel Pentium III Xeon", 135 NULL, 136 NULL, 137 NULL, 138 NULL, 139 "Intel Pentium 4" 140}; 141#endif 142 143static struct { 144 char *cpu_name; 145 int cpu_class; 146} cpus[] = { 147#ifdef __i386__ 148 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */ 149 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */ 150 { "i386DX", CPUCLASS_386 }, /* CPU_386 */ 151 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */ 152 { "i486DX", CPUCLASS_486 }, /* CPU_486 */ 153 { "Pentium", CPUCLASS_586 }, /* CPU_586 */ 154 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */ 155 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */ 156 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */ 157 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */ 158 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */ 159 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */ 160 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */ 161 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */ 162 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */ 163 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */ 164 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */ 165#else 166 { "Clawhammer", CPUCLASS_K8 }, /* CPU_CLAWHAMMER */ 167 { "Sledgehammer", CPUCLASS_K8 }, /* CPU_SLEDGEHAMMER */ 168#endif 169}; 170 171static struct { 172 char *vendor; 173 u_int vendor_id; 174} cpu_vendors[] = { 175 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */ 176 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */ 177 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */ 178#ifdef __i386__ 179 { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */ 180 { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */ 181 { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */ 182 { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */ 183 { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */ 184 { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */ 185 { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */ 186#if 0 187 /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */ 188 { "TransmetaCPU", CPU_VENDOR_TRANSMETA }, 189#endif 190#endif 191}; 192 193void 194printcpuinfo(void) 195{ 196 u_int regs[4], i; 197 char *brand; 198 199 cpu_class = cpus[cpu].cpu_class; 200 printf("CPU: "); 201 strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model)); 202 203 /* Check for extended CPUID information and a processor name. */ 204 if (cpu_exthigh >= 0x80000004) { 205 brand = cpu_brand; 206 for (i = 0x80000002; i < 0x80000005; i++) { 207 do_cpuid(i, regs); 208 memcpy(brand, regs, sizeof(regs)); 209 brand += sizeof(regs); 210 } 211 } 212 213 switch (cpu_vendor_id) { 214 case CPU_VENDOR_INTEL: 215#ifdef __i386__ 216 if ((cpu_id & 0xf00) > 0x300) { 217 u_int brand_index; 218 219 cpu_model[0] = '\0'; 220 221 switch (cpu_id & 0x3000) { 222 case 0x1000: 223 strcpy(cpu_model, "Overdrive "); 224 break; 225 case 0x2000: 226 strcpy(cpu_model, "Dual "); 227 break; 228 } 229 230 switch (cpu_id & 0xf00) { 231 case 0x400: 232 strcat(cpu_model, "i486 "); 233 /* Check the particular flavor of 486 */ 234 switch (cpu_id & 0xf0) { 235 case 0x00: 236 case 0x10: 237 strcat(cpu_model, "DX"); 238 break; 239 case 0x20: 240 strcat(cpu_model, "SX"); 241 break; 242 case 0x30: 243 strcat(cpu_model, "DX2"); 244 break; 245 case 0x40: 246 strcat(cpu_model, "SL"); 247 break; 248 case 0x50: 249 strcat(cpu_model, "SX2"); 250 break; 251 case 0x70: 252 strcat(cpu_model, 253 "DX2 Write-Back Enhanced"); 254 break; 255 case 0x80: 256 strcat(cpu_model, "DX4"); 257 break; 258 } 259 break; 260 case 0x500: 261 /* Check the particular flavor of 586 */ 262 strcat(cpu_model, "Pentium"); 263 switch (cpu_id & 0xf0) { 264 case 0x00: 265 strcat(cpu_model, " A-step"); 266 break; 267 case 0x10: 268 strcat(cpu_model, "/P5"); 269 break; 270 case 0x20: 271 strcat(cpu_model, "/P54C"); 272 break; 273 case 0x30: 274 strcat(cpu_model, "/P24T"); 275 break; 276 case 0x40: 277 strcat(cpu_model, "/P55C"); 278 break; 279 case 0x70: 280 strcat(cpu_model, "/P54C"); 281 break; 282 case 0x80: 283 strcat(cpu_model, "/P55C (quarter-micron)"); 284 break; 285 default: 286 /* nothing */ 287 break; 288 } 289#if defined(I586_CPU) && !defined(NO_F00F_HACK) 290 /* 291 * XXX - If/when Intel fixes the bug, this 292 * should also check the version of the 293 * CPU, not just that it's a Pentium. 294 */ 295 has_f00f_bug = 1; 296#endif 297 break; 298 case 0x600: 299 /* Check the particular flavor of 686 */ 300 switch (cpu_id & 0xf0) { 301 case 0x00: 302 strcat(cpu_model, "Pentium Pro A-step"); 303 break; 304 case 0x10: 305 strcat(cpu_model, "Pentium Pro"); 306 break; 307 case 0x30: 308 case 0x50: 309 case 0x60: 310 strcat(cpu_model, 311 "Pentium II/Pentium II Xeon/Celeron"); 312 cpu = CPU_PII; 313 break; 314 case 0x70: 315 case 0x80: 316 case 0xa0: 317 case 0xb0: 318 strcat(cpu_model, 319 "Pentium III/Pentium III Xeon/Celeron"); 320 cpu = CPU_PIII; 321 break; 322 default: 323 strcat(cpu_model, "Unknown 80686"); 324 break; 325 } 326 break; 327 case 0xf00: 328 strcat(cpu_model, "Pentium 4"); 329 cpu = CPU_P4; 330 break; 331 default: 332 strcat(cpu_model, "unknown"); 333 break; 334 } 335 336 /* 337 * If we didn't get a brand name from the extended 338 * CPUID, try to look it up in the brand table. 339 */ 340 if (cpu_high > 0 && *cpu_brand == '\0') { 341 brand_index = cpu_procinfo & CPUID_BRAND_INDEX; 342 if (brand_index <= MAX_BRAND_INDEX && 343 cpu_brandtable[brand_index] != NULL) 344 strcpy(cpu_brand, 345 cpu_brandtable[brand_index]); 346 } 347 } 348#else 349 /* Please make up your mind folks! */ 350 strcat(cpu_model, "EM64T"); 351#endif 352 break; 353 case CPU_VENDOR_AMD: 354 /* 355 * Values taken from AMD Processor Recognition 356 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf 357 * (also describes ``Features'' encodings. 358 */ 359 strcpy(cpu_model, "AMD "); 360#ifdef __i386__ 361 switch (cpu_id & 0xFF0) { 362 case 0x410: 363 strcat(cpu_model, "Standard Am486DX"); 364 break; 365 case 0x430: 366 strcat(cpu_model, "Enhanced Am486DX2 Write-Through"); 367 break; 368 case 0x470: 369 strcat(cpu_model, "Enhanced Am486DX2 Write-Back"); 370 break; 371 case 0x480: 372 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through"); 373 break; 374 case 0x490: 375 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back"); 376 break; 377 case 0x4E0: 378 strcat(cpu_model, "Am5x86 Write-Through"); 379 break; 380 case 0x4F0: 381 strcat(cpu_model, "Am5x86 Write-Back"); 382 break; 383 case 0x500: 384 strcat(cpu_model, "K5 model 0"); 385 break; 386 case 0x510: 387 strcat(cpu_model, "K5 model 1"); 388 break; 389 case 0x520: 390 strcat(cpu_model, "K5 PR166 (model 2)"); 391 break; 392 case 0x530: 393 strcat(cpu_model, "K5 PR200 (model 3)"); 394 break; 395 case 0x560: 396 strcat(cpu_model, "K6"); 397 break; 398 case 0x570: 399 strcat(cpu_model, "K6 266 (model 1)"); 400 break; 401 case 0x580: 402 strcat(cpu_model, "K6-2"); 403 break; 404 case 0x590: 405 strcat(cpu_model, "K6-III"); 406 break; 407 case 0x5a0: 408 strcat(cpu_model, "Geode LX"); 409 break; 410 default: 411 strcat(cpu_model, "Unknown"); 412 break; 413 } 414#else 415 if ((cpu_id & 0xf00) == 0xf00) 416 strcat(cpu_model, "AMD64 Processor"); 417 else 418 strcat(cpu_model, "Unknown"); 419#endif 420 break; 421#ifdef __i386__ 422 case CPU_VENDOR_CYRIX: 423 strcpy(cpu_model, "Cyrix "); 424 switch (cpu_id & 0xff0) { 425 case 0x440: 426 strcat(cpu_model, "MediaGX"); 427 break; 428 case 0x520: 429 strcat(cpu_model, "6x86"); 430 break; 431 case 0x540: 432 cpu_class = CPUCLASS_586; 433 strcat(cpu_model, "GXm"); 434 break; 435 case 0x600: 436 strcat(cpu_model, "6x86MX"); 437 break; 438 default: 439 /* 440 * Even though CPU supports the cpuid 441 * instruction, it can be disabled. 442 * Therefore, this routine supports all Cyrix 443 * CPUs. 444 */ 445 switch (cyrix_did & 0xf0) { 446 case 0x00: 447 switch (cyrix_did & 0x0f) { 448 case 0x00: 449 strcat(cpu_model, "486SLC"); 450 break; 451 case 0x01: 452 strcat(cpu_model, "486DLC"); 453 break; 454 case 0x02: 455 strcat(cpu_model, "486SLC2"); 456 break; 457 case 0x03: 458 strcat(cpu_model, "486DLC2"); 459 break; 460 case 0x04: 461 strcat(cpu_model, "486SRx"); 462 break; 463 case 0x05: 464 strcat(cpu_model, "486DRx"); 465 break; 466 case 0x06: 467 strcat(cpu_model, "486SRx2"); 468 break; 469 case 0x07: 470 strcat(cpu_model, "486DRx2"); 471 break; 472 case 0x08: 473 strcat(cpu_model, "486SRu"); 474 break; 475 case 0x09: 476 strcat(cpu_model, "486DRu"); 477 break; 478 case 0x0a: 479 strcat(cpu_model, "486SRu2"); 480 break; 481 case 0x0b: 482 strcat(cpu_model, "486DRu2"); 483 break; 484 default: 485 strcat(cpu_model, "Unknown"); 486 break; 487 } 488 break; 489 case 0x10: 490 switch (cyrix_did & 0x0f) { 491 case 0x00: 492 strcat(cpu_model, "486S"); 493 break; 494 case 0x01: 495 strcat(cpu_model, "486S2"); 496 break; 497 case 0x02: 498 strcat(cpu_model, "486Se"); 499 break; 500 case 0x03: 501 strcat(cpu_model, "486S2e"); 502 break; 503 case 0x0a: 504 strcat(cpu_model, "486DX"); 505 break; 506 case 0x0b: 507 strcat(cpu_model, "486DX2"); 508 break; 509 case 0x0f: 510 strcat(cpu_model, "486DX4"); 511 break; 512 default: 513 strcat(cpu_model, "Unknown"); 514 break; 515 } 516 break; 517 case 0x20: 518 if ((cyrix_did & 0x0f) < 8) 519 strcat(cpu_model, "6x86"); /* Where did you get it? */ 520 else 521 strcat(cpu_model, "5x86"); 522 break; 523 case 0x30: 524 strcat(cpu_model, "6x86"); 525 break; 526 case 0x40: 527 if ((cyrix_did & 0xf000) == 0x3000) { 528 cpu_class = CPUCLASS_586; 529 strcat(cpu_model, "GXm"); 530 } else 531 strcat(cpu_model, "MediaGX"); 532 break; 533 case 0x50: 534 strcat(cpu_model, "6x86MX"); 535 break; 536 case 0xf0: 537 switch (cyrix_did & 0x0f) { 538 case 0x0d: 539 strcat(cpu_model, "Overdrive CPU"); 540 break; 541 case 0x0e: 542 strcpy(cpu_model, "Texas Instruments 486SXL"); 543 break; 544 case 0x0f: 545 strcat(cpu_model, "486SLC/DLC"); 546 break; 547 default: 548 strcat(cpu_model, "Unknown"); 549 break; 550 } 551 break; 552 default: 553 strcat(cpu_model, "Unknown"); 554 break; 555 } 556 break; 557 } 558 break; 559 case CPU_VENDOR_RISE: 560 strcpy(cpu_model, "Rise "); 561 switch (cpu_id & 0xff0) { 562 case 0x500: /* 6401 and 6441 (Kirin) */ 563 case 0x520: /* 6510 (Lynx) */ 564 strcat(cpu_model, "mP6"); 565 break; 566 default: 567 strcat(cpu_model, "Unknown"); 568 } 569 break; 570#endif 571 case CPU_VENDOR_CENTAUR: 572#ifdef __i386__ 573 switch (cpu_id & 0xff0) { 574 case 0x540: 575 strcpy(cpu_model, "IDT WinChip C6"); 576 break; 577 case 0x580: 578 strcpy(cpu_model, "IDT WinChip 2"); 579 break; 580 case 0x590: 581 strcpy(cpu_model, "IDT WinChip 3"); 582 break; 583 case 0x660: 584 strcpy(cpu_model, "VIA C3 Samuel"); 585 break; 586 case 0x670: 587 if (cpu_id & 0x8) 588 strcpy(cpu_model, "VIA C3 Ezra"); 589 else 590 strcpy(cpu_model, "VIA C3 Samuel 2"); 591 break; 592 case 0x680: 593 strcpy(cpu_model, "VIA C3 Ezra-T"); 594 break; 595 case 0x690: 596 strcpy(cpu_model, "VIA C3 Nehemiah"); 597 break; 598 case 0x6a0: 599 case 0x6d0: 600 strcpy(cpu_model, "VIA C7 Esther"); 601 break; 602 case 0x6f0: 603 strcpy(cpu_model, "VIA Nano"); 604 break; 605 default: 606 strcpy(cpu_model, "VIA/IDT Unknown"); 607 } 608#else 609 strcpy(cpu_model, "VIA "); 610 if ((cpu_id & 0xff0) == 0x6f0) 611 strcat(cpu_model, "Nano Processor"); 612 else 613 strcat(cpu_model, "Unknown"); 614#endif 615 break; 616#ifdef __i386__ 617 case CPU_VENDOR_IBM: 618 strcpy(cpu_model, "Blue Lightning CPU"); 619 break; 620 case CPU_VENDOR_NSC: 621 switch (cpu_id & 0xff0) { 622 case 0x540: 623 strcpy(cpu_model, "Geode SC1100"); 624 cpu = CPU_GEODE1100; 625 break; 626 default: 627 strcpy(cpu_model, "Geode/NSC unknown"); 628 break; 629 } 630 break; 631#endif 632 default: 633 strcat(cpu_model, "Unknown"); 634 break; 635 } 636 637 /* 638 * Replace cpu_model with cpu_brand minus leading spaces if 639 * we have one. 640 */ 641 brand = cpu_brand; 642 while (*brand == ' ') 643 ++brand; 644 if (*brand != '\0') 645 strcpy(cpu_model, brand); 646 647 printf("%s (", cpu_model); 648 if (tsc_freq != 0) { 649 hw_clockrate = (tsc_freq + 5000) / 1000000; 650 printf("%jd.%02d-MHz ", 651 (intmax_t)(tsc_freq + 4999) / 1000000, 652 (u_int)((tsc_freq + 4999) / 10000) % 100); 653 } 654 switch(cpu_class) { 655#ifdef __i386__ 656 case CPUCLASS_286: 657 printf("286"); 658 break; 659 case CPUCLASS_386: 660 printf("386"); 661 break; 662#if defined(I486_CPU) 663 case CPUCLASS_486: 664 printf("486"); 665 break; 666#endif 667#if defined(I586_CPU) 668 case CPUCLASS_586: 669 printf("586"); 670 break; 671#endif 672#if defined(I686_CPU) 673 case CPUCLASS_686: 674 printf("686"); 675 break; 676#endif 677#else 678 case CPUCLASS_K8: 679 printf("K8"); 680 break; 681#endif 682 default: 683 printf("Unknown"); /* will panic below... */ 684 } 685 printf("-class CPU)\n"); 686 if (*cpu_vendor) 687 printf(" Origin=\"%s\"", cpu_vendor); 688 if (cpu_id) 689 printf(" Id=0x%x", cpu_id); 690 691 if (cpu_vendor_id == CPU_VENDOR_INTEL || 692 cpu_vendor_id == CPU_VENDOR_AMD || 693 cpu_vendor_id == CPU_VENDOR_CENTAUR || 694#ifdef __i386__ 695 cpu_vendor_id == CPU_VENDOR_TRANSMETA || 696 cpu_vendor_id == CPU_VENDOR_RISE || 697 cpu_vendor_id == CPU_VENDOR_NSC || 698 (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) || 699#endif 700 0) { 701 printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id)); 702 printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id)); 703 printf(" Stepping=%u", cpu_id & CPUID_STEPPING); 704#ifdef __i386__ 705 if (cpu_vendor_id == CPU_VENDOR_CYRIX) 706 printf("\n DIR=0x%04x", cyrix_did); 707#endif 708 709 /* 710 * AMD CPUID Specification 711 * http://support.amd.com/us/Embedded_TechDocs/25481.pdf 712 * 713 * Intel Processor Identification and CPUID Instruction 714 * http://www.intel.com/assets/pdf/appnote/241618.pdf 715 */ 716 if (cpu_high > 0) { 717 718 /* 719 * Here we should probably set up flags indicating 720 * whether or not various features are available. 721 * The interesting ones are probably VME, PSE, PAE, 722 * and PGE. The code already assumes without bothering 723 * to check that all CPUs >= Pentium have a TSC and 724 * MSRs. 725 */ 726 printf("\n Features=0x%b", cpu_feature, 727 "\020" 728 "\001FPU" /* Integral FPU */ 729 "\002VME" /* Extended VM86 mode support */ 730 "\003DE" /* Debugging Extensions (CR4.DE) */ 731 "\004PSE" /* 4MByte page tables */ 732 "\005TSC" /* Timestamp counter */ 733 "\006MSR" /* Machine specific registers */ 734 "\007PAE" /* Physical address extension */ 735 "\010MCE" /* Machine Check support */ 736 "\011CX8" /* CMPEXCH8 instruction */ 737 "\012APIC" /* SMP local APIC */ 738 "\013oldMTRR" /* Previous implementation of MTRR */ 739 "\014SEP" /* Fast System Call */ 740 "\015MTRR" /* Memory Type Range Registers */ 741 "\016PGE" /* PG_G (global bit) support */ 742 "\017MCA" /* Machine Check Architecture */ 743 "\020CMOV" /* CMOV instruction */ 744 "\021PAT" /* Page attributes table */ 745 "\022PSE36" /* 36 bit address space support */ 746 "\023PN" /* Processor Serial number */ 747 "\024CLFLUSH" /* Has the CLFLUSH instruction */ 748 "\025<b20>" 749 "\026DTS" /* Debug Trace Store */ 750 "\027ACPI" /* ACPI support */ 751 "\030MMX" /* MMX instructions */ 752 "\031FXSR" /* FXSAVE/FXRSTOR */ 753 "\032SSE" /* Streaming SIMD Extensions */ 754 "\033SSE2" /* Streaming SIMD Extensions #2 */ 755 "\034SS" /* Self snoop */ 756 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */ 757 "\036TM" /* Thermal Monitor clock slowdown */ 758 "\037IA64" /* CPU can execute IA64 instructions */ 759 "\040PBE" /* Pending Break Enable */ 760 ); 761 762 if (cpu_feature2 != 0) { 763 printf("\n Features2=0x%b", cpu_feature2, 764 "\020" 765 "\001SSE3" /* SSE3 */ 766 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */ 767 "\003DTES64" /* 64-bit Debug Trace */ 768 "\004MON" /* MONITOR/MWAIT Instructions */ 769 "\005DS_CPL" /* CPL Qualified Debug Store */ 770 "\006VMX" /* Virtual Machine Extensions */ 771 "\007SMX" /* Safer Mode Extensions */ 772 "\010EST" /* Enhanced SpeedStep */ 773 "\011TM2" /* Thermal Monitor 2 */ 774 "\012SSSE3" /* SSSE3 */ 775 "\013CNXT-ID" /* L1 context ID available */ 776 "\014<b11>" 777 "\015FMA" /* Fused Multiply Add */ 778 "\016CX16" /* CMPXCHG16B Instruction */ 779 "\017xTPR" /* Send Task Priority Messages*/ 780 "\020PDCM" /* Perf/Debug Capability MSR */ 781 "\021<b16>" 782 "\022PCID" /* Process-context Identifiers*/ 783 "\023DCA" /* Direct Cache Access */ 784 "\024SSE4.1" /* SSE 4.1 */ 785 "\025SSE4.2" /* SSE 4.2 */ 786 "\026x2APIC" /* xAPIC Extensions */ 787 "\027MOVBE" /* MOVBE Instruction */ 788 "\030POPCNT" /* POPCNT Instruction */ 789 "\031TSCDLT" /* TSC-Deadline Timer */ 790 "\032AESNI" /* AES Crypto */ 791 "\033XSAVE" /* XSAVE/XRSTOR States */ 792 "\034OSXSAVE" /* OS-Enabled State Management*/ 793 "\035AVX" /* Advanced Vector Extensions */ 794 "\036F16C" /* Half-precision conversions */ 795 "\037RDRAND" /* RDRAND Instruction */ 796 "\040HV" /* Hypervisor */ 797 ); 798 } 799 800 if (amd_feature != 0) { 801 printf("\n AMD Features=0x%b", amd_feature, 802 "\020" /* in hex */ 803 "\001<s0>" /* Same */ 804 "\002<s1>" /* Same */ 805 "\003<s2>" /* Same */ 806 "\004<s3>" /* Same */ 807 "\005<s4>" /* Same */ 808 "\006<s5>" /* Same */ 809 "\007<s6>" /* Same */ 810 "\010<s7>" /* Same */ 811 "\011<s8>" /* Same */ 812 "\012<s9>" /* Same */ 813 "\013<b10>" /* Undefined */ 814 "\014SYSCALL" /* Have SYSCALL/SYSRET */ 815 "\015<s12>" /* Same */ 816 "\016<s13>" /* Same */ 817 "\017<s14>" /* Same */ 818 "\020<s15>" /* Same */ 819 "\021<s16>" /* Same */ 820 "\022<s17>" /* Same */ 821 "\023<b18>" /* Reserved, unknown */ 822 "\024MP" /* Multiprocessor Capable */ 823 "\025NX" /* Has EFER.NXE, NX */ 824 "\026<b21>" /* Undefined */ 825 "\027MMX+" /* AMD MMX Extensions */ 826 "\030<s23>" /* Same */ 827 "\031<s24>" /* Same */ 828 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */ 829 "\033Page1GB" /* 1-GB large page support */ 830 "\034RDTSCP" /* RDTSCP */ 831 "\035<b28>" /* Undefined */ 832 "\036LM" /* 64 bit long mode */ 833 "\0373DNow!+" /* AMD 3DNow! Extensions */ 834 "\0403DNow!" /* AMD 3DNow! */ 835 ); 836 } 837 838 if (amd_feature2 != 0) { 839 printf("\n AMD Features2=0x%b", amd_feature2, 840 "\020" 841 "\001LAHF" /* LAHF/SAHF in long mode */ 842 "\002CMP" /* CMP legacy */ 843 "\003SVM" /* Secure Virtual Mode */ 844 "\004ExtAPIC" /* Extended APIC register */ 845 "\005CR8" /* CR8 in legacy mode */ 846 "\006ABM" /* LZCNT instruction */ 847 "\007SSE4A" /* SSE4A */ 848 "\010MAS" /* Misaligned SSE mode */ 849 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */ 850 "\012OSVW" /* OS visible workaround */ 851 "\013IBS" /* Instruction based sampling */ 852 "\014XOP" /* XOP extended instructions */ 853 "\015SKINIT" /* SKINIT/STGI */ 854 "\016WDT" /* Watchdog timer */ 855 "\017<b14>" 856 "\020LWP" /* Lightweight Profiling */ 857 "\021FMA4" /* 4-operand FMA instructions */ 858 "\022TCE" /* Translation Cache Extension */ 859 "\023<b18>" 860 "\024NodeId" /* NodeId MSR support */ 861 "\025<b20>" 862 "\026TBM" /* Trailing Bit Manipulation */ 863 "\027Topology" /* Topology Extensions */ 864 "\030PCXC" /* Core perf count */ 865 "\031PNXC" /* NB perf count */ 866 "\032<b25>" 867 "\033DBE" /* Data Breakpoint extension */ 868 "\034PTSC" /* Performance TSC */ 869 "\035PL2I" /* L2I perf count */ 870 "\036<b29>" 871 "\037<b30>" 872 "\040<b31>" 873 ); 874 } 875 876 if (cpu_stdext_feature != 0) { 877 printf("\n Structured Extended Features=0x%b", 878 cpu_stdext_feature, 879 "\020" 880 /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ 881 "\001FSGSBASE" 882 "\002TSCADJ" 883 /* Bit Manipulation Instructions */ 884 "\004BMI1" 885 /* Hardware Lock Elision */ 886 "\005HLE" 887 /* Advanced Vector Instructions 2 */ 888 "\006AVX2" 889 /* Supervisor Mode Execution Prot. */ 890 "\010SMEP" 891 /* Bit Manipulation Instructions */ 892 "\011BMI2" 893 "\012ERMS" 894 /* Invalidate Processor Context ID */ 895 "\013INVPCID" 896 /* Restricted Transactional Memory */ 897 "\014RTM" 898 /* Intel Memory Protection Extensions */ 899 "\017MPX" 900 /* AVX512 Foundation */ 901 "\021AVX512F" 902 /* Enhanced NRBG */ 903 "\023RDSEED" 904 /* ADCX + ADOX */ 905 "\024ADX" 906 /* Supervisor Mode Access Prevention */ 907 "\025SMAP" 908 "\030CLFLUSHOPT" 909 "\032PROCTRACE" 910 "\033AVX512PF" 911 "\034AVX512ER" 912 "\035AVX512CD" 913 "\036SHA" 914 ); 915 } 916 917 if ((cpu_feature2 & CPUID2_XSAVE) != 0) { 918 cpuid_count(0xd, 0x1, regs); 919 if (regs[0] != 0) { 920 printf("\n XSAVE Features=0x%b", 921 regs[0], 922 "\020" 923 "\001XSAVEOPT" 924 "\002XSAVEC" 925 "\003XINUSE" 926 "\004XSAVES"); 927 } 928 } 929 930 if (via_feature_rng != 0 || via_feature_xcrypt != 0) 931 print_via_padlock_info(); 932 933 if (cpu_feature2 & CPUID2_VMX) 934 print_vmx_info(); 935 936 if (amd_feature2 & AMDID2_SVM) 937 print_svm_info(); 938 939 if ((cpu_feature & CPUID_HTT) && 940 cpu_vendor_id == CPU_VENDOR_AMD) 941 cpu_feature &= ~CPUID_HTT; 942 943 /* 944 * If this CPU supports P-state invariant TSC then 945 * mention the capability. 946 */ 947 if (tsc_is_invariant) { 948 printf("\n TSC: P-state invariant"); 949 if (tsc_perf_stat) 950 printf(", performance statistics"); 951 } 952 953 } 954#ifdef __i386__ 955 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 956 printf(" DIR=0x%04x", cyrix_did); 957 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12); 958 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8); 959#ifndef CYRIX_CACHE_REALLY_WORKS 960 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700) 961 printf("\n CPU cache: write-through mode"); 962#endif 963#endif 964 } 965 966 /* Avoid ugly blank lines: only print newline when we have to. */ 967 if (*cpu_vendor || cpu_id) 968 printf("\n"); 969 970 if (!bootverbose) 971 return; 972 973 if (cpu_vendor_id == CPU_VENDOR_AMD) 974 print_AMD_info(); 975 else if (cpu_vendor_id == CPU_VENDOR_INTEL) 976 print_INTEL_info(); 977#ifdef __i386__ 978 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA) 979 print_transmeta_info(); 980#endif 981} 982 983void 984panicifcpuunsupported(void) 985{ 986 987#ifdef __i386__ 988#if !defined(lint) 989#if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU) 990#error This kernel is not configured for one of the supported CPUs 991#endif 992#else /* lint */ 993#endif /* lint */ 994#else /* __amd64__ */ 995#ifndef HAMMER 996#error "You need to specify a cpu type" 997#endif 998#endif 999 /* 1000 * Now that we have told the user what they have, 1001 * let them know if that machine type isn't configured. 1002 */ 1003 switch (cpu_class) { 1004#ifdef __i386__ 1005 case CPUCLASS_286: /* a 286 should not make it this far, anyway */ 1006 case CPUCLASS_386: 1007#if !defined(I486_CPU) 1008 case CPUCLASS_486: 1009#endif 1010#if !defined(I586_CPU) 1011 case CPUCLASS_586: 1012#endif 1013#if !defined(I686_CPU) 1014 case CPUCLASS_686: 1015#endif 1016#else /* __amd64__ */ 1017 case CPUCLASS_X86: 1018#ifndef HAMMER 1019 case CPUCLASS_K8: 1020#endif 1021#endif 1022 panic("CPU class not configured"); 1023 default: 1024 break; 1025 } 1026} 1027 1028#ifdef __i386__ 1029static volatile u_int trap_by_rdmsr; 1030 1031/* 1032 * Special exception 6 handler. 1033 * The rdmsr instruction generates invalid opcodes fault on 486-class 1034 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the 1035 * function identblue() when this handler is called. Stacked eip should 1036 * be advanced. 1037 */ 1038inthand_t bluetrap6; 1039#ifdef __GNUCLIKE_ASM 1040__asm 1041(" \n\ 1042 .text \n\ 1043 .p2align 2,0x90 \n\ 1044 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\ 1045" __XSTRING(CNAME(bluetrap6)) ": \n\ 1046 ss \n\ 1047 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ 1048 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ 1049 iret \n\ 1050"); 1051#endif 1052 1053/* 1054 * Special exception 13 handler. 1055 * Accessing non-existent MSR generates general protection fault. 1056 */ 1057inthand_t bluetrap13; 1058#ifdef __GNUCLIKE_ASM 1059__asm 1060(" \n\ 1061 .text \n\ 1062 .p2align 2,0x90 \n\ 1063 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\ 1064" __XSTRING(CNAME(bluetrap13)) ": \n\ 1065 ss \n\ 1066 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ 1067 popl %eax /* discard error code */ \n\ 1068 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ 1069 iret \n\ 1070"); 1071#endif 1072 1073/* 1074 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not 1075 * support cpuid instruction. This function should be called after 1076 * loading interrupt descriptor table register. 1077 * 1078 * I don't like this method that handles fault, but I couldn't get 1079 * information for any other methods. Does blue giant know? 1080 */ 1081static int 1082identblue(void) 1083{ 1084 1085 trap_by_rdmsr = 0; 1086 1087 /* 1088 * Cyrix 486-class CPU does not support rdmsr instruction. 1089 * The rdmsr instruction generates invalid opcode fault, and exception 1090 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The 1091 * bluetrap6() set the magic number to trap_by_rdmsr. 1092 */ 1093 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL, 1094 GSEL(GCODE_SEL, SEL_KPL)); 1095 1096 /* 1097 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU. 1098 * In this case, rdmsr generates general protection fault, and 1099 * exception will be trapped by bluetrap13(). 1100 */ 1101 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL, 1102 GSEL(GCODE_SEL, SEL_KPL)); 1103 1104 rdmsr(0x1002); /* Cyrix CPU generates fault. */ 1105 1106 if (trap_by_rdmsr == 0xa8c1d) 1107 return IDENTBLUE_CYRIX486; 1108 else if (trap_by_rdmsr == 0xa89c4) 1109 return IDENTBLUE_CYRIXM2; 1110 return IDENTBLUE_IBMCPU; 1111} 1112 1113 1114/* 1115 * identifycyrix() set lower 16 bits of cyrix_did as follows: 1116 * 1117 * F E D C B A 9 8 7 6 5 4 3 2 1 0 1118 * +-------+-------+---------------+ 1119 * | SID | RID | Device ID | 1120 * | (DIR 1) | (DIR 0) | 1121 * +-------+-------+---------------+ 1122 */ 1123static void 1124identifycyrix(void) 1125{ 1126 register_t saveintr; 1127 int ccr2_test = 0, dir_test = 0; 1128 u_char ccr2, ccr3; 1129 1130 saveintr = intr_disable(); 1131 1132 ccr2 = read_cyrix_reg(CCR2); 1133 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW); 1134 read_cyrix_reg(CCR2); 1135 if (read_cyrix_reg(CCR2) != ccr2) 1136 ccr2_test = 1; 1137 write_cyrix_reg(CCR2, ccr2); 1138 1139 ccr3 = read_cyrix_reg(CCR3); 1140 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3); 1141 read_cyrix_reg(CCR3); 1142 if (read_cyrix_reg(CCR3) != ccr3) 1143 dir_test = 1; /* CPU supports DIRs. */ 1144 write_cyrix_reg(CCR3, ccr3); 1145 1146 if (dir_test) { 1147 /* Device ID registers are available. */ 1148 cyrix_did = read_cyrix_reg(DIR1) << 8; 1149 cyrix_did += read_cyrix_reg(DIR0); 1150 } else if (ccr2_test) 1151 cyrix_did = 0x0010; /* 486S A-step */ 1152 else 1153 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */ 1154 1155 intr_restore(saveintr); 1156} 1157#endif 1158 1159/* Update TSC freq with the value indicated by the caller. */ 1160static void 1161tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status) 1162{ 1163 1164 /* If there was an error during the transition, don't do anything. */ 1165 if (status != 0) 1166 return; 1167 1168 /* Total setting for this level gives the new frequency in MHz. */ 1169 hw_clockrate = level->total_set.freq; 1170} 1171 1172static void 1173hook_tsc_freq(void *arg __unused) 1174{ 1175 1176 if (tsc_is_invariant) 1177 return; 1178 1179 tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change, 1180 tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY); 1181} 1182 1183SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL); 1184 1185/* 1186 * Final stage of CPU identification. 1187 */ 1188#ifdef __i386__ 1189void 1190finishidentcpu(void) 1191#else 1192void 1193identify_cpu(void) 1194#endif 1195{ 1196 u_int regs[4], cpu_stdext_disable; 1197#ifdef __i386__ 1198 u_char ccr3; 1199#endif 1200 1201#ifdef __amd64__ 1202 do_cpuid(0, regs); 1203 cpu_high = regs[0]; 1204 ((u_int *)&cpu_vendor)[0] = regs[1]; 1205 ((u_int *)&cpu_vendor)[1] = regs[3]; 1206 ((u_int *)&cpu_vendor)[2] = regs[2]; 1207 cpu_vendor[12] = '\0'; 1208 1209 do_cpuid(1, regs); 1210 cpu_id = regs[0]; 1211 cpu_procinfo = regs[1]; 1212 cpu_feature = regs[3]; 1213 cpu_feature2 = regs[2]; 1214#endif 1215 1216 cpu_vendor_id = find_cpu_vendor_id(); 1217 1218 /* 1219 * Clear "Limit CPUID Maxval" bit and get the largest standard CPUID 1220 * function number again if it is set from BIOS. It is necessary 1221 * for probing correct CPU topology later. 1222 * XXX This is only done on the BSP package. 1223 */ 1224 if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_high > 0 && cpu_high < 4 && 1225 ((CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x3) || 1226 (CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) >= 0xe))) { 1227 uint64_t msr; 1228 msr = rdmsr(MSR_IA32_MISC_ENABLE); 1229 if ((msr & 0x400000ULL) != 0) { 1230 wrmsr(MSR_IA32_MISC_ENABLE, msr & ~0x400000ULL); 1231 do_cpuid(0, regs); 1232 cpu_high = regs[0]; 1233 } 1234 } 1235 1236 if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) { 1237 do_cpuid(5, regs); 1238 cpu_mon_mwait_flags = regs[2]; 1239 cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE; 1240 cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE; 1241 } 1242 1243 if (cpu_high >= 7) { 1244 cpuid_count(7, 0, regs); 1245 cpu_stdext_feature = regs[1]; 1246 1247 /* 1248 * Some hypervisors fail to filter out unsupported 1249 * extended features. For now, disable the 1250 * extensions, activation of which requires setting a 1251 * bit in CR4, and which VM monitors do not support. 1252 */ 1253 if (cpu_feature2 & CPUID2_HV) { 1254 cpu_stdext_disable = CPUID_STDEXT_FSGSBASE | 1255 CPUID_STDEXT_SMEP; 1256 } else 1257 cpu_stdext_disable = 0; 1258 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable); 1259 cpu_stdext_feature &= ~cpu_stdext_disable; 1260 } 1261 1262#ifdef __i386__ 1263 if (cpu_high > 0 && 1264 (cpu_vendor_id == CPU_VENDOR_INTEL || 1265 cpu_vendor_id == CPU_VENDOR_AMD || 1266 cpu_vendor_id == CPU_VENDOR_TRANSMETA || 1267 cpu_vendor_id == CPU_VENDOR_CENTAUR || 1268 cpu_vendor_id == CPU_VENDOR_NSC)) { 1269 do_cpuid(0x80000000, regs); 1270 if (regs[0] >= 0x80000000) 1271 cpu_exthigh = regs[0]; 1272 } 1273#else 1274 if (cpu_vendor_id == CPU_VENDOR_INTEL || 1275 cpu_vendor_id == CPU_VENDOR_AMD || 1276 cpu_vendor_id == CPU_VENDOR_CENTAUR) { 1277 do_cpuid(0x80000000, regs); 1278 cpu_exthigh = regs[0]; 1279 } 1280#endif 1281 if (cpu_exthigh >= 0x80000001) { 1282 do_cpuid(0x80000001, regs); 1283 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff); 1284 amd_feature2 = regs[2]; 1285 } 1286 if (cpu_exthigh >= 0x80000007) { 1287 do_cpuid(0x80000007, regs); 1288 amd_pminfo = regs[3]; 1289 } 1290 if (cpu_exthigh >= 0x80000008) { 1291 do_cpuid(0x80000008, regs); 1292 cpu_procinfo2 = regs[2]; 1293 } 1294 1295#ifdef __i386__ 1296 if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 1297 if (cpu == CPU_486) { 1298 /* 1299 * These conditions are equivalent to: 1300 * - CPU does not support cpuid instruction. 1301 * - Cyrix/IBM CPU is detected. 1302 */ 1303 if (identblue() == IDENTBLUE_IBMCPU) { 1304 strcpy(cpu_vendor, "IBM"); 1305 cpu_vendor_id = CPU_VENDOR_IBM; 1306 cpu = CPU_BLUE; 1307 return; 1308 } 1309 } 1310 switch (cpu_id & 0xf00) { 1311 case 0x600: 1312 /* 1313 * Cyrix's datasheet does not describe DIRs. 1314 * Therefor, I assume it does not have them 1315 * and use the result of the cpuid instruction. 1316 * XXX they seem to have it for now at least. -Peter 1317 */ 1318 identifycyrix(); 1319 cpu = CPU_M2; 1320 break; 1321 default: 1322 identifycyrix(); 1323 /* 1324 * This routine contains a trick. 1325 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now. 1326 */ 1327 switch (cyrix_did & 0x00f0) { 1328 case 0x00: 1329 case 0xf0: 1330 cpu = CPU_486DLC; 1331 break; 1332 case 0x10: 1333 cpu = CPU_CY486DX; 1334 break; 1335 case 0x20: 1336 if ((cyrix_did & 0x000f) < 8) 1337 cpu = CPU_M1; 1338 else 1339 cpu = CPU_M1SC; 1340 break; 1341 case 0x30: 1342 cpu = CPU_M1; 1343 break; 1344 case 0x40: 1345 /* MediaGX CPU */ 1346 cpu = CPU_M1SC; 1347 break; 1348 default: 1349 /* M2 and later CPUs are treated as M2. */ 1350 cpu = CPU_M2; 1351 1352 /* 1353 * enable cpuid instruction. 1354 */ 1355 ccr3 = read_cyrix_reg(CCR3); 1356 write_cyrix_reg(CCR3, CCR3_MAPEN0); 1357 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID); 1358 write_cyrix_reg(CCR3, ccr3); 1359 1360 do_cpuid(0, regs); 1361 cpu_high = regs[0]; /* eax */ 1362 do_cpuid(1, regs); 1363 cpu_id = regs[0]; /* eax */ 1364 cpu_feature = regs[3]; /* edx */ 1365 break; 1366 } 1367 } 1368 } else if (cpu == CPU_486 && *cpu_vendor == '\0') { 1369 /* 1370 * There are BlueLightning CPUs that do not change 1371 * undefined flags by dividing 5 by 2. In this case, 1372 * the CPU identification routine in locore.s leaves 1373 * cpu_vendor null string and puts CPU_486 into the 1374 * cpu. 1375 */ 1376 if (identblue() == IDENTBLUE_IBMCPU) { 1377 strcpy(cpu_vendor, "IBM"); 1378 cpu_vendor_id = CPU_VENDOR_IBM; 1379 cpu = CPU_BLUE; 1380 return; 1381 } 1382 } 1383#else 1384 /* XXX */ 1385 cpu = CPU_CLAWHAMMER; 1386#endif 1387} 1388 1389static u_int 1390find_cpu_vendor_id(void) 1391{ 1392 int i; 1393 1394 for (i = 0; i < sizeof(cpu_vendors) / sizeof(cpu_vendors[0]); i++) 1395 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0) 1396 return (cpu_vendors[i].vendor_id); 1397 return (0); 1398} 1399 1400static void 1401print_AMD_assoc(int i) 1402{ 1403 if (i == 255) 1404 printf(", fully associative\n"); 1405 else 1406 printf(", %d-way associative\n", i); 1407} 1408 1409static void 1410print_AMD_l2_assoc(int i) 1411{ 1412 switch (i & 0x0f) { 1413 case 0: printf(", disabled/not present\n"); break; 1414 case 1: printf(", direct mapped\n"); break; 1415 case 2: printf(", 2-way associative\n"); break; 1416 case 4: printf(", 4-way associative\n"); break; 1417 case 6: printf(", 8-way associative\n"); break; 1418 case 8: printf(", 16-way associative\n"); break; 1419 case 15: printf(", fully associative\n"); break; 1420 default: printf(", reserved configuration\n"); break; 1421 } 1422} 1423 1424static void 1425print_AMD_info(void) 1426{ 1427#ifdef __i386__ 1428 uint64_t amd_whcr; 1429#endif 1430 u_int regs[4]; 1431 1432 if (cpu_exthigh >= 0x80000005) { 1433 do_cpuid(0x80000005, regs); 1434 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff); 1435 print_AMD_assoc(regs[0] >> 24); 1436 1437 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff); 1438 print_AMD_assoc((regs[0] >> 8) & 0xff); 1439 1440 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff); 1441 print_AMD_assoc(regs[1] >> 24); 1442 1443 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff); 1444 print_AMD_assoc((regs[1] >> 8) & 0xff); 1445 1446 printf("L1 data cache: %d kbytes", regs[2] >> 24); 1447 printf(", %d bytes/line", regs[2] & 0xff); 1448 printf(", %d lines/tag", (regs[2] >> 8) & 0xff); 1449 print_AMD_assoc((regs[2] >> 16) & 0xff); 1450 1451 printf("L1 instruction cache: %d kbytes", regs[3] >> 24); 1452 printf(", %d bytes/line", regs[3] & 0xff); 1453 printf(", %d lines/tag", (regs[3] >> 8) & 0xff); 1454 print_AMD_assoc((regs[3] >> 16) & 0xff); 1455 } 1456 1457 if (cpu_exthigh >= 0x80000006) { 1458 do_cpuid(0x80000006, regs); 1459 if ((regs[0] >> 16) != 0) { 1460 printf("L2 2MB data TLB: %d entries", 1461 (regs[0] >> 16) & 0xfff); 1462 print_AMD_l2_assoc(regs[0] >> 28); 1463 printf("L2 2MB instruction TLB: %d entries", 1464 regs[0] & 0xfff); 1465 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 1466 } else { 1467 printf("L2 2MB unified TLB: %d entries", 1468 regs[0] & 0xfff); 1469 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 1470 } 1471 if ((regs[1] >> 16) != 0) { 1472 printf("L2 4KB data TLB: %d entries", 1473 (regs[1] >> 16) & 0xfff); 1474 print_AMD_l2_assoc(regs[1] >> 28); 1475 1476 printf("L2 4KB instruction TLB: %d entries", 1477 (regs[1] >> 16) & 0xfff); 1478 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 1479 } else { 1480 printf("L2 4KB unified TLB: %d entries", 1481 (regs[1] >> 16) & 0xfff); 1482 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 1483 } 1484 printf("L2 unified cache: %d kbytes", regs[2] >> 16); 1485 printf(", %d bytes/line", regs[2] & 0xff); 1486 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f); 1487 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f); 1488 } 1489 1490#ifdef __i386__ 1491 if (((cpu_id & 0xf00) == 0x500) 1492 && (((cpu_id & 0x0f0) > 0x80) 1493 || (((cpu_id & 0x0f0) == 0x80) 1494 && (cpu_id & 0x00f) > 0x07))) { 1495 /* K6-2(new core [Stepping 8-F]), K6-III or later */ 1496 amd_whcr = rdmsr(0xc0000082); 1497 if (!(amd_whcr & (0x3ff << 22))) { 1498 printf("Write Allocate Disable\n"); 1499 } else { 1500 printf("Write Allocate Enable Limit: %dM bytes\n", 1501 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4); 1502 printf("Write Allocate 15-16M bytes: %s\n", 1503 (amd_whcr & (1 << 16)) ? "Enable" : "Disable"); 1504 } 1505 } else if (((cpu_id & 0xf00) == 0x500) 1506 && ((cpu_id & 0x0f0) > 0x50)) { 1507 /* K6, K6-2(old core) */ 1508 amd_whcr = rdmsr(0xc0000082); 1509 if (!(amd_whcr & (0x7f << 1))) { 1510 printf("Write Allocate Disable\n"); 1511 } else { 1512 printf("Write Allocate Enable Limit: %dM bytes\n", 1513 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4); 1514 printf("Write Allocate 15-16M bytes: %s\n", 1515 (amd_whcr & 0x0001) ? "Enable" : "Disable"); 1516 printf("Hardware Write Allocate Control: %s\n", 1517 (amd_whcr & 0x0100) ? "Enable" : "Disable"); 1518 } 1519 } 1520#endif 1521 /* 1522 * Opteron Rev E shows a bug as in very rare occasions a read memory 1523 * barrier is not performed as expected if it is followed by a 1524 * non-atomic read-modify-write instruction. 1525 * As long as that bug pops up very rarely (intensive machine usage 1526 * on other operating systems generally generates one unexplainable 1527 * crash any 2 months) and as long as a model specific fix would be 1528 * impratical at this stage, print out a warning string if the broken 1529 * model and family are identified. 1530 */ 1531 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 && 1532 CPUID_TO_MODEL(cpu_id) <= 0x3f) 1533 printf("WARNING: This architecture revision has known SMP " 1534 "hardware bugs which may cause random instability\n"); 1535} 1536 1537static void 1538print_INTEL_info(void) 1539{ 1540 u_int regs[4]; 1541 u_int rounds, regnum; 1542 u_int nwaycode, nway; 1543 1544 if (cpu_high >= 2) { 1545 rounds = 0; 1546 do { 1547 do_cpuid(0x2, regs); 1548 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0) 1549 break; /* we have a buggy CPU */ 1550 1551 for (regnum = 0; regnum <= 3; ++regnum) { 1552 if (regs[regnum] & (1<<31)) 1553 continue; 1554 if (regnum != 0) 1555 print_INTEL_TLB(regs[regnum] & 0xff); 1556 print_INTEL_TLB((regs[regnum] >> 8) & 0xff); 1557 print_INTEL_TLB((regs[regnum] >> 16) & 0xff); 1558 print_INTEL_TLB((regs[regnum] >> 24) & 0xff); 1559 } 1560 } while (--rounds > 0); 1561 } 1562 1563 if (cpu_exthigh >= 0x80000006) { 1564 do_cpuid(0x80000006, regs); 1565 nwaycode = (regs[2] >> 12) & 0x0f; 1566 if (nwaycode >= 0x02 && nwaycode <= 0x08) 1567 nway = 1 << (nwaycode / 2); 1568 else 1569 nway = 0; 1570 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n", 1571 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff); 1572 } 1573} 1574 1575static void 1576print_INTEL_TLB(u_int data) 1577{ 1578 switch (data) { 1579 case 0x0: 1580 case 0x40: 1581 default: 1582 break; 1583 case 0x1: 1584 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n"); 1585 break; 1586 case 0x2: 1587 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n"); 1588 break; 1589 case 0x3: 1590 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n"); 1591 break; 1592 case 0x4: 1593 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n"); 1594 break; 1595 case 0x6: 1596 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n"); 1597 break; 1598 case 0x8: 1599 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n"); 1600 break; 1601 case 0xa: 1602 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n"); 1603 break; 1604 case 0xc: 1605 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n"); 1606 break; 1607 case 0x22: 1608 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 1609 break; 1610 case 0x23: 1611 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 1612 break; 1613 case 0x25: 1614 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 1615 break; 1616 case 0x29: 1617 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 1618 break; 1619 case 0x2c: 1620 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n"); 1621 break; 1622 case 0x30: 1623 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n"); 1624 break; 1625 case 0x39: 1626 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 1627 break; 1628 case 0x3b: 1629 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n"); 1630 break; 1631 case 0x3c: 1632 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 1633 break; 1634 case 0x41: 1635 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n"); 1636 break; 1637 case 0x42: 1638 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n"); 1639 break; 1640 case 0x43: 1641 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n"); 1642 break; 1643 case 0x44: 1644 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n"); 1645 break; 1646 case 0x45: 1647 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n"); 1648 break; 1649 case 0x46: 1650 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n"); 1651 break; 1652 case 0x47: 1653 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n"); 1654 break; 1655 case 0x50: 1656 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n"); 1657 break; 1658 case 0x51: 1659 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n"); 1660 break; 1661 case 0x52: 1662 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n"); 1663 break; 1664 case 0x5b: 1665 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n"); 1666 break; 1667 case 0x5c: 1668 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n"); 1669 break; 1670 case 0x5d: 1671 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n"); 1672 break; 1673 case 0x60: 1674 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 1675 break; 1676 case 0x66: 1677 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 1678 break; 1679 case 0x67: 1680 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 1681 break; 1682 case 0x68: 1683 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n"); 1684 break; 1685 case 0x70: 1686 printf("Trace cache: 12K-uops, 8-way set associative\n"); 1687 break; 1688 case 0x71: 1689 printf("Trace cache: 16K-uops, 8-way set associative\n"); 1690 break; 1691 case 0x72: 1692 printf("Trace cache: 32K-uops, 8-way set associative\n"); 1693 break; 1694 case 0x78: 1695 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n"); 1696 break; 1697 case 0x79: 1698 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 1699 break; 1700 case 0x7a: 1701 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 1702 break; 1703 case 0x7b: 1704 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 1705 break; 1706 case 0x7c: 1707 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 1708 break; 1709 case 0x7d: 1710 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n"); 1711 break; 1712 case 0x7f: 1713 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n"); 1714 break; 1715 case 0x82: 1716 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n"); 1717 break; 1718 case 0x83: 1719 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n"); 1720 break; 1721 case 0x84: 1722 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n"); 1723 break; 1724 case 0x85: 1725 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n"); 1726 break; 1727 case 0x86: 1728 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n"); 1729 break; 1730 case 0x87: 1731 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n"); 1732 break; 1733 case 0xb0: 1734 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n"); 1735 break; 1736 case 0xb3: 1737 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n"); 1738 break; 1739 } 1740} 1741 1742static void 1743print_svm_info(void) 1744{ 1745 u_int features, regs[4]; 1746 uint64_t msr; 1747 int comma; 1748 1749 printf("\n SVM: "); 1750 do_cpuid(0x8000000A, regs); 1751 features = regs[3]; 1752 1753 msr = rdmsr(MSR_VM_CR); 1754 if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS) 1755 printf("(disabled in BIOS) "); 1756 1757 if (!bootverbose) { 1758 comma = 0; 1759 if (features & (1 << 0)) { 1760 printf("%sNP", comma ? "," : ""); 1761 comma = 1; 1762 } 1763 if (features & (1 << 3)) { 1764 printf("%sNRIP", comma ? "," : ""); 1765 comma = 1; 1766 } 1767 if (features & (1 << 5)) { 1768 printf("%sVClean", comma ? "," : ""); 1769 comma = 1; 1770 } 1771 if (features & (1 << 6)) { 1772 printf("%sAFlush", comma ? "," : ""); 1773 comma = 1; 1774 } 1775 if (features & (1 << 7)) { 1776 printf("%sDAssist", comma ? "," : ""); 1777 comma = 1; 1778 } 1779 printf("%sNAsids=%d", comma ? "," : "", regs[1]); 1780 return; 1781 } 1782 1783 printf("Features=0x%b", features, 1784 "\020" 1785 "\001NP" /* Nested paging */ 1786 "\002LbrVirt" /* LBR virtualization */ 1787 "\003SVML" /* SVM lock */ 1788 "\004NRIPS" /* NRIP save */ 1789 "\005TscRateMsr" /* MSR based TSC rate control */ 1790 "\006VmcbClean" /* VMCB clean bits */ 1791 "\007FlushByAsid" /* Flush by ASID */ 1792 "\010DecodeAssist" /* Decode assist */ 1793 "\011<b8>" 1794 "\012<b9>" 1795 "\013PauseFilter" /* PAUSE intercept filter */ 1796 "\014<b11>" 1797 "\015PauseFilterThreshold" /* PAUSE filter threshold */ 1798 "\016AVIC" /* virtual interrupt controller */ 1799 ); 1800 printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]); 1801} 1802 1803#ifdef __i386__ 1804static void 1805print_transmeta_info(void) 1806{ 1807 u_int regs[4], nreg = 0; 1808 1809 do_cpuid(0x80860000, regs); 1810 nreg = regs[0]; 1811 if (nreg >= 0x80860001) { 1812 do_cpuid(0x80860001, regs); 1813 printf(" Processor revision %u.%u.%u.%u\n", 1814 (regs[1] >> 24) & 0xff, 1815 (regs[1] >> 16) & 0xff, 1816 (regs[1] >> 8) & 0xff, 1817 regs[1] & 0xff); 1818 } 1819 if (nreg >= 0x80860002) { 1820 do_cpuid(0x80860002, regs); 1821 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n", 1822 (regs[1] >> 24) & 0xff, 1823 (regs[1] >> 16) & 0xff, 1824 (regs[1] >> 8) & 0xff, 1825 regs[1] & 0xff, 1826 regs[2]); 1827 } 1828 if (nreg >= 0x80860006) { 1829 char info[65]; 1830 do_cpuid(0x80860003, (u_int*) &info[0]); 1831 do_cpuid(0x80860004, (u_int*) &info[16]); 1832 do_cpuid(0x80860005, (u_int*) &info[32]); 1833 do_cpuid(0x80860006, (u_int*) &info[48]); 1834 info[64] = 0; 1835 printf(" %s\n", info); 1836 } 1837} 1838#endif 1839 1840static void 1841print_via_padlock_info(void) 1842{ 1843 u_int regs[4]; 1844 1845 do_cpuid(0xc0000001, regs); 1846 printf("\n VIA Padlock Features=0x%b", regs[3], 1847 "\020" 1848 "\003RNG" /* RNG */ 1849 "\007AES" /* ACE */ 1850 "\011AES-CTR" /* ACE2 */ 1851 "\013SHA1,SHA256" /* PHE */ 1852 "\015RSA" /* PMM */ 1853 ); 1854} 1855 1856static uint32_t 1857vmx_settable(uint64_t basic, int msr, int true_msr) 1858{ 1859 uint64_t val; 1860 1861 if (basic & (1ULL << 55)) 1862 val = rdmsr(true_msr); 1863 else 1864 val = rdmsr(msr); 1865 1866 /* Just report the controls that can be set to 1. */ 1867 return (val >> 32); 1868} 1869 1870static void 1871print_vmx_info(void) 1872{ 1873 uint64_t basic, msr; 1874 uint32_t entry, exit, mask, pin, proc, proc2; 1875 int comma; 1876 1877 printf("\n VT-x: "); 1878 msr = rdmsr(MSR_IA32_FEATURE_CONTROL); 1879 if (!(msr & IA32_FEATURE_CONTROL_VMX_EN)) 1880 printf("(disabled in BIOS) "); 1881 basic = rdmsr(MSR_VMX_BASIC); 1882 pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS, 1883 MSR_VMX_TRUE_PINBASED_CTLS); 1884 proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS, 1885 MSR_VMX_TRUE_PROCBASED_CTLS); 1886 if (proc & PROCBASED_SECONDARY_CONTROLS) 1887 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2, 1888 MSR_VMX_PROCBASED_CTLS2); 1889 else 1890 proc2 = 0; 1891 exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS); 1892 entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS); 1893 1894 if (!bootverbose) { 1895 comma = 0; 1896 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT && 1897 entry & VM_ENTRY_LOAD_PAT) { 1898 printf("%sPAT", comma ? "," : ""); 1899 comma = 1; 1900 } 1901 if (proc & PROCBASED_HLT_EXITING) { 1902 printf("%sHLT", comma ? "," : ""); 1903 comma = 1; 1904 } 1905 if (proc & PROCBASED_MTF) { 1906 printf("%sMTF", comma ? "," : ""); 1907 comma = 1; 1908 } 1909 if (proc & PROCBASED_PAUSE_EXITING) { 1910 printf("%sPAUSE", comma ? "," : ""); 1911 comma = 1; 1912 } 1913 if (proc2 & PROCBASED2_ENABLE_EPT) { 1914 printf("%sEPT", comma ? "," : ""); 1915 comma = 1; 1916 } 1917 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) { 1918 printf("%sUG", comma ? "," : ""); 1919 comma = 1; 1920 } 1921 if (proc2 & PROCBASED2_ENABLE_VPID) { 1922 printf("%sVPID", comma ? "," : ""); 1923 comma = 1; 1924 } 1925 if (proc & PROCBASED_USE_TPR_SHADOW && 1926 proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES && 1927 proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE && 1928 proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION && 1929 proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) { 1930 printf("%sVID", comma ? "," : ""); 1931 comma = 1; 1932 if (pin & PINBASED_POSTED_INTERRUPT) 1933 printf(",PostIntr"); 1934 } 1935 return; 1936 } 1937 1938 mask = basic >> 32; 1939 printf("Basic Features=0x%b", mask, 1940 "\020" 1941 "\02132PA" /* 32-bit physical addresses */ 1942 "\022SMM" /* SMM dual-monitor */ 1943 "\027INS/OUTS" /* VM-exit info for INS and OUTS */ 1944 "\030TRUE" /* TRUE_CTLS MSRs */ 1945 ); 1946 printf("\n Pin-Based Controls=0x%b", pin, 1947 "\020" 1948 "\001ExtINT" /* External-interrupt exiting */ 1949 "\004NMI" /* NMI exiting */ 1950 "\006VNMI" /* Virtual NMIs */ 1951 "\007PreTmr" /* Activate VMX-preemption timer */ 1952 "\010PostIntr" /* Process posted interrupts */ 1953 ); 1954 printf("\n Primary Processor Controls=0x%b", proc, 1955 "\020" 1956 "\003INTWIN" /* Interrupt-window exiting */ 1957 "\004TSCOff" /* Use TSC offsetting */ 1958 "\010HLT" /* HLT exiting */ 1959 "\012INVLPG" /* INVLPG exiting */ 1960 "\013MWAIT" /* MWAIT exiting */ 1961 "\014RDPMC" /* RDPMC exiting */ 1962 "\015RDTSC" /* RDTSC exiting */ 1963 "\020CR3-LD" /* CR3-load exiting */ 1964 "\021CR3-ST" /* CR3-store exiting */ 1965 "\024CR8-LD" /* CR8-load exiting */ 1966 "\025CR8-ST" /* CR8-store exiting */ 1967 "\026TPR" /* Use TPR shadow */ 1968 "\027NMIWIN" /* NMI-window exiting */ 1969 "\030MOV-DR" /* MOV-DR exiting */ 1970 "\031IO" /* Unconditional I/O exiting */ 1971 "\032IOmap" /* Use I/O bitmaps */ 1972 "\034MTF" /* Monitor trap flag */ 1973 "\035MSRmap" /* Use MSR bitmaps */ 1974 "\036MONITOR" /* MONITOR exiting */ 1975 "\037PAUSE" /* PAUSE exiting */ 1976 ); 1977 if (proc & PROCBASED_SECONDARY_CONTROLS) 1978 printf("\n Secondary Processor Controls=0x%b", proc2, 1979 "\020" 1980 "\001APIC" /* Virtualize APIC accesses */ 1981 "\002EPT" /* Enable EPT */ 1982 "\003DT" /* Descriptor-table exiting */ 1983 "\004RDTSCP" /* Enable RDTSCP */ 1984 "\005x2APIC" /* Virtualize x2APIC mode */ 1985 "\006VPID" /* Enable VPID */ 1986 "\007WBINVD" /* WBINVD exiting */ 1987 "\010UG" /* Unrestricted guest */ 1988 "\011APIC-reg" /* APIC-register virtualization */ 1989 "\012VID" /* Virtual-interrupt delivery */ 1990 "\013PAUSE-loop" /* PAUSE-loop exiting */ 1991 "\014RDRAND" /* RDRAND exiting */ 1992 "\015INVPCID" /* Enable INVPCID */ 1993 "\016VMFUNC" /* Enable VM functions */ 1994 "\017VMCS" /* VMCS shadowing */ 1995 "\020EPT#VE" /* EPT-violation #VE */ 1996 "\021XSAVES" /* Enable XSAVES/XRSTORS */ 1997 ); 1998 printf("\n Exit Controls=0x%b", mask, 1999 "\020" 2000 "\003DR" /* Save debug controls */ 2001 /* Ignore Host address-space size */ 2002 "\015PERF" /* Load MSR_PERF_GLOBAL_CTRL */ 2003 "\020AckInt" /* Acknowledge interrupt on exit */ 2004 "\023PAT-SV" /* Save MSR_PAT */ 2005 "\024PAT-LD" /* Load MSR_PAT */ 2006 "\025EFER-SV" /* Save MSR_EFER */ 2007 "\026EFER-LD" /* Load MSR_EFER */ 2008 "\027PTMR-SV" /* Save VMX-preemption timer value */ 2009 ); 2010 printf("\n Entry Controls=0x%b", mask, 2011 "\020" 2012 "\003DR" /* Save debug controls */ 2013 /* Ignore IA-32e mode guest */ 2014 /* Ignore Entry to SMM */ 2015 /* Ignore Deactivate dual-monitor treatment */ 2016 "\016PERF" /* Load MSR_PERF_GLOBAL_CTRL */ 2017 "\017PAT" /* Load MSR_PAT */ 2018 "\020EFER" /* Load MSR_EFER */ 2019 ); 2020 if (proc & PROCBASED_SECONDARY_CONTROLS && 2021 (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) { 2022 msr = rdmsr(MSR_VMX_EPT_VPID_CAP); 2023 mask = msr; 2024 printf("\n EPT Features=0x%b", mask, 2025 "\020" 2026 "\001XO" /* Execute-only translations */ 2027 "\007PW4" /* Page-walk length of 4 */ 2028 "\011UC" /* EPT paging-structure mem can be UC */ 2029 "\017WB" /* EPT paging-structure mem can be WB */ 2030 "\0212M" /* EPT PDE can map a 2-Mbyte page */ 2031 "\0221G" /* EPT PDPTE can map a 1-Gbyte page */ 2032 "\025INVEPT" /* INVEPT is supported */ 2033 "\026AD" /* Accessed and dirty flags for EPT */ 2034 "\032single" /* INVEPT single-context type */ 2035 "\033all" /* INVEPT all-context type */ 2036 ); 2037 mask = msr >> 32; 2038 printf("\n VPID Features=0x%b", mask, 2039 "\020" 2040 "\001INVVPID" /* INVVPID is supported */ 2041 "\011individual" /* INVVPID individual-address type */ 2042 "\012single" /* INVVPID single-context type */ 2043 "\013all" /* INVVPID all-context type */ 2044 /* INVVPID single-context-retaining-globals type */ 2045 "\014single-globals" 2046 ); 2047 } 2048} 2049