intel_reg.h revision 280343
1321964Ssjg/*- 2246149Ssjg * Copyright (c) 2013-2015 The FreeBSD Foundation 3249033Ssjg * All rights reserved. 4249033Ssjg * 5246149Ssjg * This software was developed by Konstantin Belousov <kib@FreeBSD.org> 6246149Ssjg * under sponsorship from the FreeBSD Foundation. 7246149Ssjg * 8246149Ssjg * Redistribution and use in source and binary forms, with or without 9246149Ssjg * modification, are permitted provided that the following conditions 10246149Ssjg * are met: 11246149Ssjg * 1. Redistributions of source code must retain the above copyright 12246149Ssjg * notice, this list of conditions and the following disclaimer. 13246149Ssjg * 2. Redistributions in binary form must reproduce the above copyright 14246149Ssjg * notice, this list of conditions and the following disclaimer in the 15246149Ssjg * documentation and/or other materials provided with the distribution. 16246149Ssjg * 17246149Ssjg * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18246149Ssjg * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19246149Ssjg * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20246149Ssjg * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21246149Ssjg * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22246149Ssjg * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23246149Ssjg * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24246149Ssjg * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25246149Ssjg * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26246149Ssjg * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27246149Ssjg * SUCH DAMAGE. 28246149Ssjg * 29246149Ssjg * $FreeBSD: stable/10/sys/x86/iommu/intel_reg.h 280343 2015-03-22 09:12:44Z kib $ 30246149Ssjg */ 31246149Ssjg 32246149Ssjg#ifndef __X86_IOMMU_INTEL_REG_H 33246149Ssjg#define __X86_IOMMU_INTEL_REG_H 34246149Ssjg 35246149Ssjg#define DMAR_PAGE_SIZE PAGE_SIZE 36246149Ssjg#define DMAR_PAGE_MASK (DMAR_PAGE_SIZE - 1) 37249033Ssjg#define DMAR_PAGE_SHIFT PAGE_SHIFT 38249033Ssjg#define DMAR_NPTEPG (DMAR_PAGE_SIZE / sizeof(dmar_pte_t)) 39246149Ssjg#define DMAR_NPTEPGSHIFT 9 40249033Ssjg#define DMAR_PTEMASK (DMAR_NPTEPG - 1) 41249033Ssjg 42246149Ssjgtypedef struct dmar_root_entry { 43249033Ssjg uint64_t r1; 44249033Ssjg uint64_t r2; 45249033Ssjg} dmar_root_entry_t; 46249033Ssjg#define DMAR_ROOT_R1_P 1 /* Present */ 47276305Sngie#define DMAR_ROOT_R1_CTP_MASK 0xfffffffffffff000 /* Mask for Context-Entry 48246149Ssjg Table Pointer */ 49246149Ssjg 50249033Ssjg#define DMAR_CTX_CNT (DMAR_PAGE_SIZE / sizeof(dmar_root_entry_t)) 51249033Ssjg 52249033Ssjgtypedef struct dmar_ctx_entry { 53249033Ssjg uint64_t ctx1; 54249033Ssjg uint64_t ctx2; 55249033Ssjg} dmar_ctx_entry_t; 56249033Ssjg#define DMAR_CTX1_P 1 /* Present */ 57249033Ssjg#define DMAR_CTX1_FPD 2 /* Fault Processing Disable */ 58249033Ssjg /* Translation Type: */ 59321964Ssjg#define DMAR_CTX1_T_UNTR 0 /* only Untranslated */ 60321964Ssjg#define DMAR_CTX1_T_TR 4 /* both Untranslated 61321964Ssjg and Translated */ 62321964Ssjg#define DMAR_CTX1_T_PASS 8 /* Pass-Through */ 63321964Ssjg#define DMAR_CTX1_ASR_MASK 0xfffffffffffff000 /* Mask for the Address 64321964Ssjg Space Root */ 65246149Ssjg#define DMAR_CTX2_AW_2LVL 0 /* 2-level page tables */ 66246149Ssjg#define DMAR_CTX2_AW_3LVL 1 /* 3-level page tables */ 67246149Ssjg#define DMAR_CTX2_AW_4LVL 2 /* 4-level page tables */ 68246149Ssjg#define DMAR_CTX2_AW_5LVL 3 /* 5-level page tables */ 69246149Ssjg#define DMAR_CTX2_AW_6LVL 4 /* 6-level page tables */ 70246149Ssjg#define DMAR_CTX2_DID(x) ((x) << 8) /* Domain Identifier */ 71246149Ssjg 72249033Ssjgtypedef struct dmar_pte { 73249033Ssjg uint64_t pte; 74246149Ssjg} dmar_pte_t; 75246149Ssjg#define DMAR_PTE_R 1 /* Read */ 76249033Ssjg#define DMAR_PTE_W (1 << 1) /* Write */ 77276305Sngie#define DMAR_PTE_SP (1 << 7) /* Super Page */ 78249033Ssjg#define DMAR_PTE_SNP (1 << 11) /* Snoop Behaviour */ 79249033Ssjg#define DMAR_PTE_ADDR_MASK 0xffffffffff000 /* Address Mask */ 80246149Ssjg#define DMAR_PTE_TM (1ULL << 62) /* Transient Mapping */ 81249033Ssjg 82246149Ssjgtypedef struct dmar_irte { 83249033Ssjg uint64_t irte1; 84249033Ssjg uint64_t irte2; 85249033Ssjg} dmar_irte_t; 86249033Ssjg/* Source Validation Type */ 87246149Ssjg#define DMAR_IRTE2_SVT_NONE (0ULL << (82 - 64)) 88249033Ssjg#define DMAR_IRTE2_SVT_RID (1ULL << (82 - 64)) 89246149Ssjg#define DMAR_IRTE2_SVT_BUS (2ULL << (82 - 64)) 90246149Ssjg/* Source-id Qualifier */ 91246149Ssjg#define DMAR_IRTE2_SQ_RID (0ULL << (80 - 64)) 92249033Ssjg#define DMAR_IRTE2_SQ_RID_N2 (1ULL << (80 - 64)) 93249033Ssjg#define DMAR_IRTE2_SQ_RID_N21 (2ULL << (80 - 64)) 94246149Ssjg#define DMAR_IRTE2_SQ_RID_N210 (3ULL << (80 - 64)) 95246149Ssjg/* Source Identifier */ 96246149Ssjg#define DMAR_IRTE2_SID_RID(x) ((uint64_t)(x)) 97246149Ssjg#define DMAR_IRTE2_SID_BUS(start, end) ((((uint64_t)(start)) << 8) | (end)) 98246149Ssjg/* Destination Id */ 99246149Ssjg#define DMAR_IRTE1_DST_xAPIC(x) (((uint64_t)(x)) << 40) 100249033Ssjg#define DMAR_IRTE1_DST_x2APIC(x) (((uint64_t)(x)) << 32) 101249033Ssjg/* Vector */ 102249033Ssjg#define DMAR_IRTE1_V(x) (((uint64_t)x) << 16) 103249033Ssjg#define DMAR_IRTE1_IM_POSTED (1ULL << 15) /* Posted */ 104249033Ssjg/* Delivery Mode */ 105249033Ssjg#define DMAR_IRTE1_DLM_FM (0ULL << 5) 106246149Ssjg#define DMAR_IRTE1_DLM_LP (1ULL << 5) 107246149Ssjg#define DMAR_IRTE1_DLM_SMI (2ULL << 5) 108246149Ssjg#define DMAR_IRTE1_DLM_NMI (4ULL << 5) 109246149Ssjg#define DMAR_IRTE1_DLM_INIT (5ULL << 5) 110246149Ssjg#define DMAR_IRTE1_DLM_ExtINT (7ULL << 5) 111246149Ssjg/* Trigger Mode */ 112249033Ssjg#define DMAR_IRTE1_TM_EDGE (0ULL << 4) 113249033Ssjg#define DMAR_IRTE1_TM_LEVEL (1ULL << 4) 114249033Ssjg/* Redirection Hint */ 115246149Ssjg#define DMAR_IRTE1_RH_DIRECT (0ULL << 3) 116321964Ssjg#define DMAR_IRTE1_RH_SELECT (1ULL << 3) 117321964Ssjg/* Destination Mode */ 118321964Ssjg#define DMAR_IRTE1_DM_PHYSICAL (0ULL << 2) 119321964Ssjg#define DMAR_IRTE1_DM_LOGICAL (1ULL << 2) 120321964Ssjg#define DMAR_IRTE1_FPD (1ULL << 1) /* Fault Processing Disable */ 121321964Ssjg#define DMAR_IRTE1_P (1ULL) /* Present */ 122321964Ssjg 123321964Ssjg/* Version register */ 124321964Ssjg#define DMAR_VER_REG 0 125321964Ssjg#define DMAR_MAJOR_VER(x) (((x) >> 4) & 0xf) 126321964Ssjg#define DMAR_MINOR_VER(x) ((x) & 0xf) 127321964Ssjg 128321964Ssjg/* Capabilities register */ 129321964Ssjg#define DMAR_CAP_REG 0x8 130321964Ssjg#define DMAR_CAP_PI (1ULL << 59) /* Posted Interrupts */ 131321964Ssjg#define DMAR_CAP_FL1GP (1ULL << 56) /* First Level 1GByte Page */ 132321964Ssjg#define DMAR_CAP_DRD (1ULL << 55) /* DMA Read Draining */ 133321964Ssjg#define DMAR_CAP_DWD (1ULL << 54) /* DMA Write Draining */ 134321964Ssjg#define DMAR_CAP_MAMV(x) ((u_int)(((x) >> 48) & 0x3f)) 135321964Ssjg /* Maximum Address Mask */ 136321964Ssjg#define DMAR_CAP_NFR(x) ((u_int)(((x) >> 40) & 0xff) + 1) 137321964Ssjg /* Num of Fault-recording regs */ 138321964Ssjg#define DMAR_CAP_PSI (1ULL << 39) /* Page Selective Invalidation */ 139246149Ssjg#define DMAR_CAP_SPS(x) ((u_int)(((x) >> 34) & 0xf)) /* Super-Page Support */ 140321964Ssjg#define DMAR_CAP_SPS_2M 0x1 141321964Ssjg#define DMAR_CAP_SPS_1G 0x2 142321964Ssjg#define DMAR_CAP_SPS_512G 0x4 143321964Ssjg#define DMAR_CAP_SPS_1T 0x8 144321964Ssjg#define DMAR_CAP_FRO(x) ((u_int)(((x) >> 24) & 0x1ff)) 145321964Ssjg /* Fault-recording reg offset */ 146321964Ssjg#define DMAR_CAP_ISOCH (1 << 23) /* Isochrony */ 147321964Ssjg#define DMAR_CAP_ZLR (1 << 22) /* Zero-length reads */ 148292068Ssjg#define DMAR_CAP_MGAW(x) ((u_int)(((x) >> 16) & 0x3f)) 149292068Ssjg /* Max Guest Address Width */ 150292068Ssjg#define DMAR_CAP_SAGAW(x) ((u_int)(((x) >> 8) & 0x1f)) 151246149Ssjg /* Adjusted Guest Address Width */ 152246149Ssjg#define DMAR_CAP_SAGAW_2LVL 0x01 153321964Ssjg#define DMAR_CAP_SAGAW_3LVL 0x02 154246149Ssjg#define DMAR_CAP_SAGAW_4LVL 0x04 155246149Ssjg#define DMAR_CAP_SAGAW_5LVL 0x08 156246149Ssjg#define DMAR_CAP_SAGAW_6LVL 0x10 157292068Ssjg#define DMAR_CAP_CM (1 << 7) /* Caching mode */ 158246149Ssjg#define DMAR_CAP_PHMR (1 << 6) /* Protected High-mem Region */ 159292068Ssjg#define DMAR_CAP_PLMR (1 << 5) /* Protected Low-mem Region */ 160292068Ssjg#define DMAR_CAP_RWBF (1 << 4) /* Required Write-Buffer Flushing */ 161292068Ssjg#define DMAR_CAP_AFL (1 << 3) /* Advanced Fault Logging */ 162292068Ssjg#define DMAR_CAP_ND(x) ((u_int)((x) & 0x3)) /* Number of domains */ 163292068Ssjg 164321964Ssjg/* Extended Capabilities register */ 165321964Ssjg#define DMAR_ECAP_REG 0x10 166321964Ssjg#define DMAR_ECAP_PSS(x) (((x) >> 35) & 0xf) /* PASID Size Supported */ 167321964Ssjg#define DMAR_ECAP_EAFS (1ULL << 34) /* Extended Accessed Flag */ 168321964Ssjg#define DMAR_ECAP_NWFS (1ULL << 33) /* No Write Flag */ 169321964Ssjg#define DMAR_ECAP_SRS (1ULL << 31) /* Supervisor Request */ 170321964Ssjg#define DMAR_ECAP_ERS (1ULL << 30) /* Execute Request */ 171321964Ssjg#define DMAR_ECAP_PRS (1ULL << 29) /* Page Request */ 172321964Ssjg#define DMAR_ECAP_PASID (1ULL << 28) /* Process Address Space Id */ 173321964Ssjg#define DMAR_ECAP_DIS (1ULL << 27) /* Deferred Invalidate */ 174321964Ssjg#define DMAR_ECAP_NEST (1ULL << 26) /* Nested Translation */ 175321964Ssjg#define DMAR_ECAP_MTS (1ULL << 25) /* Memory Type */ 176321964Ssjg#define DMAR_ECAP_ECS (1ULL << 24) /* Extended Context */ 177321964Ssjg#define DMAR_ECAP_MHMV(x) ((u_int)(((x) >> 20) & 0xf)) 178321964Ssjg /* Maximum Handle Mask Value */ 179321964Ssjg#define DMAR_ECAP_IRO(x) ((u_int)(((x) >> 8) & 0x3ff)) 180321964Ssjg /* IOTLB Register Offset */ 181321964Ssjg#define DMAR_ECAP_SC (1 << 7) /* Snoop Control */ 182321964Ssjg#define DMAR_ECAP_PT (1 << 6) /* Pass Through */ 183321964Ssjg#define DMAR_ECAP_EIM (1 << 4) /* Extended Interrupt Mode */ 184321964Ssjg#define DMAR_ECAP_IR (1 << 3) /* Interrupt Remapping */ 185321964Ssjg#define DMAR_ECAP_DI (1 << 2) /* Device IOTLB */ 186249033Ssjg#define DMAR_ECAP_QI (1 << 1) /* Queued Invalidation */ 187249033Ssjg#define DMAR_ECAP_C (1 << 0) /* Coherency */ 188249033Ssjg 189246149Ssjg/* Global Command register */ 190246149Ssjg#define DMAR_GCMD_REG 0x18 191246149Ssjg#define DMAR_GCMD_TE (1U << 31) /* Translation Enable */ 192246149Ssjg#define DMAR_GCMD_SRTP (1 << 30) /* Set Root Table Pointer */ 193249033Ssjg#define DMAR_GCMD_SFL (1 << 29) /* Set Fault Log */ 194246149Ssjg#define DMAR_GCMD_EAFL (1 << 28) /* Enable Advanced Fault Logging */ 195249033Ssjg#define DMAR_GCMD_WBF (1 << 27) /* Write Buffer Flush */ 196249033Ssjg#define DMAR_GCMD_QIE (1 << 26) /* Queued Invalidation Enable */ 197249033Ssjg#define DMAR_GCMD_IRE (1 << 25) /* Interrupt Remapping Enable */ 198249033Ssjg#define DMAR_GCMD_SIRTP (1 << 24) /* Set Interrupt Remap Table Pointer */ 199249033Ssjg#define DMAR_GCMD_CFI (1 << 23) /* Compatibility Format Interrupt */ 200249033Ssjg 201246149Ssjg/* Global Status register */ 202249033Ssjg#define DMAR_GSTS_REG 0x1c 203249033Ssjg#define DMAR_GSTS_TES (1U << 31) /* Translation Enable Status */ 204249033Ssjg#define DMAR_GSTS_RTPS (1 << 30) /* Root Table Pointer Status */ 205249033Ssjg#define DMAR_GSTS_FLS (1 << 29) /* Fault Log Status */ 206249033Ssjg#define DMAR_GSTS_AFLS (1 << 28) /* Advanced Fault Logging Status */ 207249033Ssjg#define DMAR_GSTS_WBFS (1 << 27) /* Write Buffer Flush Status */ 208321964Ssjg#define DMAR_GSTS_QIES (1 << 26) /* Queued Invalidation Enable Status */ 209321964Ssjg#define DMAR_GSTS_IRES (1 << 25) /* Interrupt Remapping Enable Status */ 210321964Ssjg#define DMAR_GSTS_IRTPS (1 << 24) /* Interrupt Remapping Table 211321964Ssjg Pointer Status */ 212321964Ssjg#define DMAR_GSTS_CFIS (1 << 23) /* Compatibility Format 213321964Ssjg Interrupt Status */ 214321964Ssjg 215321964Ssjg/* Root-Entry Table Address register */ 216321964Ssjg#define DMAR_RTADDR_REG 0x20 217249033Ssjg 218276305Sngie/* Context Command register */ 219249033Ssjg#define DMAR_CCMD_REG 0x28 220249033Ssjg#define DMAR_CCMD_ICC (1ULL << 63) /* Invalidate Context-Cache */ 221249033Ssjg#define DMAR_CCMD_ICC32 (1U << 31) 222276305Sngie#define DMAR_CCMD_CIRG_MASK (0x3ULL << 61) /* Context Invalidation 223249033Ssjg Request Granularity */ 224249033Ssjg#define DMAR_CCMD_CIRG_GLOB (0x1ULL << 61) /* Global */ 225249033Ssjg#define DMAR_CCMD_CIRG_DOM (0x2ULL << 61) /* Domain */ 226249033Ssjg#define DMAR_CCMD_CIRG_DEV (0x3ULL << 61) /* Device */ 227249033Ssjg#define DMAR_CCMD_CAIG(x) (((x) >> 59) & 0x3) /* Context Actual 228249033Ssjg Invalidation Granularity */ 229249033Ssjg#define DMAR_CCMD_CAIG_GLOB 0x1 /* Global */ 230246149Ssjg#define DMAR_CCMD_CAIG_DOM 0x2 /* Domain */ 231249033Ssjg#define DMAR_CCMD_CAIG_DEV 0x3 /* Device */ 232249033Ssjg#define DMAR_CCMD_FM (0x3UUL << 32) /* Function Mask */ 233246149Ssjg#define DMAR_CCMD_SID(x) (((x) & 0xffff) << 16) /* Source-ID */ 234246149Ssjg#define DMAR_CCMD_DID(x) ((x) & 0xffff) /* Domain-ID */ 235246149Ssjg 236246149Ssjg/* Invalidate Address register */ 237246149Ssjg#define DMAR_IVA_REG_OFF 0 238246149Ssjg#define DMAR_IVA_IH (1 << 6) /* Invalidation Hint */ 239246149Ssjg#define DMAR_IVA_AM(x) ((x) & 0x1f) /* Address Mask */ 240246149Ssjg#define DMAR_IVA_ADDR(x) ((x) & ~0xfffULL) /* Address */ 241246149Ssjg 242246149Ssjg/* IOTLB Invalidate register */ 243249033Ssjg#define DMAR_IOTLB_REG_OFF 0x8 244246149Ssjg#define DMAR_IOTLB_IVT (1ULL << 63) /* Invalidate IOTLB */ 245246149Ssjg#define DMAR_IOTLB_IVT32 (1U << 31) 246246149Ssjg#define DMAR_IOTLB_IIRG_MASK (0x3ULL << 60) /* Invalidation Request 247246149Ssjg Granularity */ 248249033Ssjg#define DMAR_IOTLB_IIRG_GLB (0x1ULL << 60) /* Global */ 249246149Ssjg#define DMAR_IOTLB_IIRG_DOM (0x2ULL << 60) /* Domain-selective */ 250246149Ssjg#define DMAR_IOTLB_IIRG_PAGE (0x3ULL << 60) /* Page-selective */ 251246149Ssjg#define DMAR_IOTLB_IAIG_MASK (0x3ULL << 57) /* Actual Invalidation 252246149Ssjg Granularity */ 253246149Ssjg#define DMAR_IOTLB_IAIG_INVLD 0 /* Hw detected error */ 254246149Ssjg#define DMAR_IOTLB_IAIG_GLB (0x1ULL << 57) /* Global */ 255246149Ssjg#define DMAR_IOTLB_IAIG_DOM (0x2ULL << 57) /* Domain-selective */ 256246149Ssjg#define DMAR_IOTLB_IAIG_PAGE (0x3ULL << 57) /* Page-selective */ 257246149Ssjg#define DMAR_IOTLB_DR (0x1ULL << 49) /* Drain Reads */ 258249033Ssjg#define DMAR_IOTLB_DW (0x1ULL << 48) /* Drain Writes */ 259246149Ssjg#define DMAR_IOTLB_DID(x) (((uint64_t)(x) & 0xffff) << 32) /* Domain Id */ 260246149Ssjg 261246149Ssjg/* Fault Status register */ 262321964Ssjg#define DMAR_FSTS_REG 0x34 263321964Ssjg#define DMAR_FSTS_FRI(x) (((x) >> 8) & 0xff) /* Fault Record Index */ 264321964Ssjg#define DMAR_FSTS_ITE (1 << 6) /* Invalidation Time-out */ 265321964Ssjg#define DMAR_FSTS_ICE (1 << 5) /* Invalidation Completion */ 266249033Ssjg#define DMAR_FSTS_IQE (1 << 4) /* Invalidation Queue */ 267249033Ssjg#define DMAR_FSTS_APF (1 << 3) /* Advanced Pending Fault */ 268249033Ssjg#define DMAR_FSTS_AFO (1 << 2) /* Advanced Fault Overflow */ 269276305Sngie#define DMAR_FSTS_PPF (1 << 1) /* Primary Pending Fault */ 270276305Sngie#define DMAR_FSTS_PFO 1 /* Fault Overflow */ 271276305Sngie 272246149Ssjg/* Fault Event Control register */ 273276305Sngie#define DMAR_FECTL_REG 0x38 274292068Ssjg#define DMAR_FECTL_IM (1U << 31) /* Interrupt Mask */ 275249033Ssjg#define DMAR_FECTL_IP (1 << 30) /* Interrupt Pending */ 276249033Ssjg 277246149Ssjg/* Fault Event Data register */ 278249033Ssjg#define DMAR_FEDATA_REG 0x3c 279249033Ssjg 280249033Ssjg/* Fault Event Address register */ 281249033Ssjg#define DMAR_FEADDR_REG 0x40 282246149Ssjg 283249033Ssjg/* Fault Event Upper Address register */ 284246149Ssjg#define DMAR_FEUADDR_REG 0x44 285249033Ssjg 286249033Ssjg/* Advanced Fault Log register */ 287321964Ssjg#define DMAR_AFLOG_REG 0x58 288249033Ssjg 289249033Ssjg/* Fault Recording Register, also usable for Advanced Fault Log records */ 290246149Ssjg#define DMAR_FRCD2_F (1ULL << 63) /* Fault */ 291249033Ssjg#define DMAR_FRCD2_F32 (1U << 31) 292249033Ssjg#define DMAR_FRCD2_T(x) ((int)((x >> 62) & 1)) /* Type */ 293249033Ssjg#define DMAR_FRCD2_T_W 0 /* Write request */ 294249033Ssjg#define DMAR_FRCD2_T_R 1 /* Read or AtomicOp */ 295249033Ssjg#define DMAR_FRCD2_AT(x) ((int)((x >> 60) & 0x3)) /* Address Type */ 296249033Ssjg#define DMAR_FRCD2_FR(x) ((int)((x >> 32) & 0xff)) /* Fault Reason */ 297249033Ssjg#define DMAR_FRCD2_SID(x) ((int)(x & 0xffff)) /* Source Identifier */ 298249033Ssjg#define DMAR_FRCS1_FI_MASK 0xffffffffff000 /* Fault Info, Address Mask */ 299249033Ssjg 300249033Ssjg/* Protected Memory Enable register */ 301249033Ssjg#define DMAR_PMEN_REG 0x64 302249033Ssjg#define DMAR_PMEN_EPM (1U << 31) /* Enable Protected Memory */ 303249033Ssjg#define DMAR_PMEN_PRS 1 /* Protected Region Status */ 304249033Ssjg 305249033Ssjg/* Protected Low-Memory Base register */ 306249033Ssjg#define DMAR_PLMBASE_REG 0x68 307321964Ssjg 308321964Ssjg/* Protected Low-Memory Limit register */ 309292068Ssjg#define DMAR_PLMLIMIT_REG 0x6c 310246149Ssjg 311246149Ssjg/* Protected High-Memory Base register */ 312246149Ssjg#define DMAR_PHMBASE_REG 0x70 313246149Ssjg 314276305Sngie/* Protected High-Memory Limit register */ 315276305Sngie#define DMAR_PHMLIMIT_REG 0x78 316246149Ssjg 317246149Ssjg/* Queued Invalidation Descriptors */ 318246149Ssjg#define DMAR_IQ_DESCR_SZ_SHIFT 4 /* Shift for descriptor count 319246149Ssjg to ring offset */ 320246149Ssjg#define DMAR_IQ_DESCR_SZ (1 << DMAR_IQ_DESCR_SZ_SHIFT) 321246149Ssjg /* Descriptor size */ 322246149Ssjg 323246149Ssjg#define DMAR_IQ_DESCR_CTX_INV 0x1 /* Context-cache Invalidate 324246149Ssjg Descriptor */ 325246149Ssjg#define DMAR_IQ_DESCR_CTX_GLOB (0x1 << 4) /* Granularity: Global */ 326246149Ssjg#define DMAR_IQ_DESCR_CTX_DOM (0x2 << 4) /* Granularity: Domain */ 327246149Ssjg#define DMAR_IQ_DESCR_CTX_DEV (0x3 << 4) /* Granularity: Device */ 328321964Ssjg#define DMAR_IQ_DESCR_CTX_DID(x) (((uint32_t)(x)) << 16) /* Domain Id */ 329321964Ssjg#define DMAR_IQ_DESCR_CTX_SRC(x) (((uint64_t)(x)) << 32) /* Source Id */ 330321964Ssjg#define DMAR_IQ_DESCR_CTX_FM(x) (((uint64_t)(x)) << 48) /* Function Mask */ 331321964Ssjg 332321964Ssjg#define DMAR_IQ_DESCR_IOTLB_INV 0x2 /* IOTLB Invalidate Descriptor */ 333321964Ssjg#define DMAR_IQ_DESCR_IOTLB_GLOB (0x1 << 4) /* Granularity: Global */ 334321964Ssjg#define DMAR_IQ_DESCR_IOTLB_DOM (0x2 << 4) /* Granularity: Domain */ 335321964Ssjg#define DMAR_IQ_DESCR_IOTLB_PAGE (0x3 << 4) /* Granularity: Page */ 336321964Ssjg#define DMAR_IQ_DESCR_IOTLB_DW (1 << 6) /* Drain Writes */ 337321964Ssjg#define DMAR_IQ_DESCR_IOTLB_DR (1 << 7) /* Drain Reads */ 338321964Ssjg#define DMAR_IQ_DESCR_IOTLB_DID(x) (((uint32_t)(x)) << 16) /* Domain Id */ 339321964Ssjg 340321964Ssjg#define DMAR_IQ_DESCR_IEC_INV 0x4 /* Invalidate Interrupt Entry Cache */ 341321964Ssjg#define DMAR_IQ_DESCR_IEC_IDX (1 << 4) /* Index-Selective Invalidation */ 342321964Ssjg#define DMAR_IQ_DESCR_IEC_IIDX(x) (((uint64_t)x) << 32) /* Interrupt Index */ 343321964Ssjg#define DMAR_IQ_DESCR_IEC_IM(x) ((x) << 27) /* Index Mask */ 344321964Ssjg 345321964Ssjg#define DMAR_IQ_DESCR_WAIT_ID 0x5 /* Invalidation Wait Descriptor */ 346321964Ssjg#define DMAR_IQ_DESCR_WAIT_IF (1 << 4) /* Interrupt Flag */ 347321964Ssjg#define DMAR_IQ_DESCR_WAIT_SW (1 << 5) /* Status Write */ 348246149Ssjg#define DMAR_IQ_DESCR_WAIT_FN (1 << 6) /* Fence */ 349246149Ssjg#define DMAR_IQ_DESCR_WAIT_SD(x) (((uint64_t)(x)) << 32) /* Status Data */ 350246149Ssjg 351292068Ssjg/* Invalidation Queue Head register */ 352246149Ssjg#define DMAR_IQH_REG 0x80 353246149Ssjg#define DMAR_IQH_MASK 0x7fff0 /* Next cmd index mask */ 354246149Ssjg 355246149Ssjg/* Invalidation Queue Tail register */ 356249033Ssjg#define DMAR_IQT_REG 0x88 357246149Ssjg#define DMAR_IQT_MASK 0x7fff0 358249033Ssjg 359249033Ssjg/* Invalidation Queue Address register */ 360321964Ssjg#define DMAR_IQA_REG 0x90 361321964Ssjg#define DMAR_IQA_IQA_MASK 0xfffffffffffff000 /* Invalidation Queue 362321964Ssjg Base Address mask */ 363246149Ssjg#define DMAR_IQA_QS_MASK 0x7 /* Queue Size in pages */ 364321964Ssjg#define DMAR_IQA_QS_MAX 0x7 /* Max Queue size */ 365249033Ssjg#define DMAR_IQA_QS_DEF 3 366246149Ssjg 367321964Ssjg /* Invalidation Completion Status register */ 368321964Ssjg#define DMAR_ICS_REG 0x9c 369321964Ssjg#define DMAR_ICS_IWC 1 /* Invalidation Wait 370321964Ssjg Descriptor Complete */ 371321964Ssjg 372321964Ssjg/* Invalidation Event Control register */ 373321964Ssjg#define DMAR_IECTL_REG 0xa0 374321964Ssjg#define DMAR_IECTL_IM (1U << 31) /* Interrupt Mask */ 375246149Ssjg#define DMAR_IECTL_IP (1 << 30) /* Interrupt Pending */ 376321964Ssjg 377321964Ssjg/* Invalidation Event Data register */ 378246149Ssjg#define DMAR_IEDATA_REG 0xa4 379246149Ssjg 380276305Sngie/* Invalidation Event Address register */ 381276305Sngie#define DMAR_IEADDR_REG 0xa8 382276305Sngie 383276305Sngie/* Invalidation Event Upper Address register */ 384246149Ssjg#define DMAR_IEUADDR_REG 0xac 385249033Ssjg 386249033Ssjg/* Interrupt Remapping Table Address register */ 387246149Ssjg#define DMAR_IRTA_REG 0xb8 388246149Ssjg#define DMAR_IRTA_EIME (1 << 11) /* Extended Interrupt Mode 389246149Ssjg Enable */ 390246149Ssjg#define DMAR_IRTA_S_MASK 0xf /* Size Mask */ 391249033Ssjg 392246149Ssjg#endif 393249033Ssjg