specialreg.h revision 276386
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 4. Neither the name of the University nor the names of its contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 30 * $FreeBSD: stable/10/sys/x86/include/specialreg.h 276386 2014-12-30 00:00:42Z neel $ 31 */ 32 33#ifndef _MACHINE_SPECIALREG_H_ 34#define _MACHINE_SPECIALREG_H_ 35 36/* 37 * Bits in 386 special registers: 38 */ 39#define CR0_PE 0x00000001 /* Protected mode Enable */ 40#define CR0_MP 0x00000002 /* "Math" (fpu) Present */ 41#define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ 42#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 43#define CR0_PG 0x80000000 /* PaGing enable */ 44 45/* 46 * Bits in 486 special registers: 47 */ 48#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 49#define CR0_WP 0x00010000 /* Write Protect (honor page protect in 50 all modes) */ 51#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 52#define CR0_NW 0x20000000 /* Not Write-through */ 53#define CR0_CD 0x40000000 /* Cache Disable */ 54 55#define CR3_PCID_SAVE 0x8000000000000000 56 57/* 58 * Bits in PPro special registers 59 */ 60#define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ 61#define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ 62#define CR4_TSD 0x00000004 /* Time stamp disable */ 63#define CR4_DE 0x00000008 /* Debugging extensions */ 64#define CR4_PSE 0x00000010 /* Page size extensions */ 65#define CR4_PAE 0x00000020 /* Physical address extension */ 66#define CR4_MCE 0x00000040 /* Machine check enable */ 67#define CR4_PGE 0x00000080 /* Page global enable */ 68#define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ 69#define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ 70#define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ 71#define CR4_VMXE 0x00002000 /* enable VMX operation (Intel-specific) */ 72#define CR4_FSGSBASE 0x00010000 /* Enable FS/GS BASE accessing instructions */ 73#define CR4_PCIDE 0x00020000 /* Enable Context ID */ 74#define CR4_XSAVE 0x00040000 /* XSETBV/XGETBV */ 75#define CR4_SMEP 0x00100000 /* Supervisor-Mode Execution Prevention */ 76 77/* 78 * Bits in AMD64 special registers. EFER is 64 bits wide. 79 */ 80#define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */ 81#define EFER_LME 0x000000100 /* Long mode enable (R/W) */ 82#define EFER_LMA 0x000000400 /* Long mode active (R) */ 83#define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ 84#define EFER_SVM 0x000001000 /* SVM enable bit for AMD, reserved for Intel */ 85 86/* 87 * Intel Extended Features registers 88 */ 89#define XCR0 0 /* XFEATURE_ENABLED_MASK register */ 90 91#define XFEATURE_ENABLED_X87 0x00000001 92#define XFEATURE_ENABLED_SSE 0x00000002 93#define XFEATURE_ENABLED_YMM_HI128 0x00000004 94#define XFEATURE_ENABLED_AVX XFEATURE_ENABLED_YMM_HI128 95#define XFEATURE_ENABLED_BNDREGS 0x00000008 96#define XFEATURE_ENABLED_BNDCSR 0x00000010 97#define XFEATURE_ENABLED_OPMASK 0x00000020 98#define XFEATURE_ENABLED_ZMM_HI256 0x00000040 99#define XFEATURE_ENABLED_HI16_ZMM 0x00000080 100 101#define XFEATURE_AVX \ 102 (XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE | XFEATURE_ENABLED_AVX) 103#define XFEATURE_AVX512 \ 104 (XFEATURE_ENABLED_OPMASK | XFEATURE_ENABLED_ZMM_HI256 | \ 105 XFEATURE_ENABLED_HI16_ZMM) 106#define XFEATURE_MPX \ 107 (XFEATURE_ENABLED_BNDREGS | XFEATURE_ENABLED_BNDCSR) 108 109/* 110 * CPUID instruction features register 111 */ 112#define CPUID_FPU 0x00000001 113#define CPUID_VME 0x00000002 114#define CPUID_DE 0x00000004 115#define CPUID_PSE 0x00000008 116#define CPUID_TSC 0x00000010 117#define CPUID_MSR 0x00000020 118#define CPUID_PAE 0x00000040 119#define CPUID_MCE 0x00000080 120#define CPUID_CX8 0x00000100 121#define CPUID_APIC 0x00000200 122#define CPUID_B10 0x00000400 123#define CPUID_SEP 0x00000800 124#define CPUID_MTRR 0x00001000 125#define CPUID_PGE 0x00002000 126#define CPUID_MCA 0x00004000 127#define CPUID_CMOV 0x00008000 128#define CPUID_PAT 0x00010000 129#define CPUID_PSE36 0x00020000 130#define CPUID_PSN 0x00040000 131#define CPUID_CLFSH 0x00080000 132#define CPUID_B20 0x00100000 133#define CPUID_DS 0x00200000 134#define CPUID_ACPI 0x00400000 135#define CPUID_MMX 0x00800000 136#define CPUID_FXSR 0x01000000 137#define CPUID_SSE 0x02000000 138#define CPUID_XMM 0x02000000 139#define CPUID_SSE2 0x04000000 140#define CPUID_SS 0x08000000 141#define CPUID_HTT 0x10000000 142#define CPUID_TM 0x20000000 143#define CPUID_IA64 0x40000000 144#define CPUID_PBE 0x80000000 145 146#define CPUID2_SSE3 0x00000001 147#define CPUID2_PCLMULQDQ 0x00000002 148#define CPUID2_DTES64 0x00000004 149#define CPUID2_MON 0x00000008 150#define CPUID2_DS_CPL 0x00000010 151#define CPUID2_VMX 0x00000020 152#define CPUID2_SMX 0x00000040 153#define CPUID2_EST 0x00000080 154#define CPUID2_TM2 0x00000100 155#define CPUID2_SSSE3 0x00000200 156#define CPUID2_CNXTID 0x00000400 157#define CPUID2_FMA 0x00001000 158#define CPUID2_CX16 0x00002000 159#define CPUID2_XTPR 0x00004000 160#define CPUID2_PDCM 0x00008000 161#define CPUID2_PCID 0x00020000 162#define CPUID2_DCA 0x00040000 163#define CPUID2_SSE41 0x00080000 164#define CPUID2_SSE42 0x00100000 165#define CPUID2_X2APIC 0x00200000 166#define CPUID2_MOVBE 0x00400000 167#define CPUID2_POPCNT 0x00800000 168#define CPUID2_TSCDLT 0x01000000 169#define CPUID2_AESNI 0x02000000 170#define CPUID2_XSAVE 0x04000000 171#define CPUID2_OSXSAVE 0x08000000 172#define CPUID2_AVX 0x10000000 173#define CPUID2_F16C 0x20000000 174#define CPUID2_RDRAND 0x40000000 175#define CPUID2_HV 0x80000000 176 177/* 178 * Important bits in the Thermal and Power Management flags 179 * CPUID.6 EAX and ECX. 180 */ 181#define CPUTPM1_SENSOR 0x00000001 182#define CPUTPM1_TURBO 0x00000002 183#define CPUTPM1_ARAT 0x00000004 184#define CPUTPM2_EFFREQ 0x00000001 185 186/* 187 * Important bits in the AMD extended cpuid flags 188 */ 189#define AMDID_SYSCALL 0x00000800 190#define AMDID_MP 0x00080000 191#define AMDID_NX 0x00100000 192#define AMDID_EXT_MMX 0x00400000 193#define AMDID_FFXSR 0x01000000 194#define AMDID_PAGE1GB 0x04000000 195#define AMDID_RDTSCP 0x08000000 196#define AMDID_LM 0x20000000 197#define AMDID_EXT_3DNOW 0x40000000 198#define AMDID_3DNOW 0x80000000 199 200#define AMDID2_LAHF 0x00000001 201#define AMDID2_CMP 0x00000002 202#define AMDID2_SVM 0x00000004 203#define AMDID2_EXT_APIC 0x00000008 204#define AMDID2_CR8 0x00000010 205#define AMDID2_ABM 0x00000020 206#define AMDID2_SSE4A 0x00000040 207#define AMDID2_MAS 0x00000080 208#define AMDID2_PREFETCH 0x00000100 209#define AMDID2_OSVW 0x00000200 210#define AMDID2_IBS 0x00000400 211#define AMDID2_XOP 0x00000800 212#define AMDID2_SKINIT 0x00001000 213#define AMDID2_WDT 0x00002000 214#define AMDID2_LWP 0x00008000 215#define AMDID2_FMA4 0x00010000 216#define AMDID2_TCE 0x00020000 217#define AMDID2_NODE_ID 0x00080000 218#define AMDID2_TBM 0x00200000 219#define AMDID2_TOPOLOGY 0x00400000 220#define AMDID2_PCXC 0x00800000 221#define AMDID2_PNXC 0x01000000 222#define AMDID2_DBE 0x04000000 223#define AMDID2_PTSC 0x08000000 224#define AMDID2_PTSCEL2I 0x10000000 225 226/* 227 * CPUID instruction 1 eax info 228 */ 229#define CPUID_STEPPING 0x0000000f 230#define CPUID_MODEL 0x000000f0 231#define CPUID_FAMILY 0x00000f00 232#define CPUID_EXT_MODEL 0x000f0000 233#define CPUID_EXT_FAMILY 0x0ff00000 234#ifdef __i386__ 235#define CPUID_TO_MODEL(id) \ 236 ((((id) & CPUID_MODEL) >> 4) | \ 237 ((((id) & CPUID_FAMILY) >= 0x600) ? \ 238 (((id) & CPUID_EXT_MODEL) >> 12) : 0)) 239#define CPUID_TO_FAMILY(id) \ 240 ((((id) & CPUID_FAMILY) >> 8) + \ 241 ((((id) & CPUID_FAMILY) == 0xf00) ? \ 242 (((id) & CPUID_EXT_FAMILY) >> 20) : 0)) 243#else 244#define CPUID_TO_MODEL(id) \ 245 ((((id) & CPUID_MODEL) >> 4) | \ 246 (((id) & CPUID_EXT_MODEL) >> 12)) 247#define CPUID_TO_FAMILY(id) \ 248 ((((id) & CPUID_FAMILY) >> 8) + \ 249 (((id) & CPUID_EXT_FAMILY) >> 20)) 250#endif 251 252/* 253 * CPUID instruction 1 ebx info 254 */ 255#define CPUID_BRAND_INDEX 0x000000ff 256#define CPUID_CLFUSH_SIZE 0x0000ff00 257#define CPUID_HTT_CORES 0x00ff0000 258#define CPUID_LOCAL_APIC_ID 0xff000000 259 260/* 261 * CPUID instruction 5 info 262 */ 263#define CPUID5_MON_MIN_SIZE 0x0000ffff /* eax */ 264#define CPUID5_MON_MAX_SIZE 0x0000ffff /* ebx */ 265#define CPUID5_MON_MWAIT_EXT 0x00000001 /* ecx */ 266#define CPUID5_MWAIT_INTRBREAK 0x00000002 /* ecx */ 267 268/* 269 * MWAIT cpu power states. Lower 4 bits are sub-states. 270 */ 271#define MWAIT_C0 0xf0 272#define MWAIT_C1 0x00 273#define MWAIT_C2 0x10 274#define MWAIT_C3 0x20 275#define MWAIT_C4 0x30 276 277/* 278 * MWAIT extensions. 279 */ 280/* Interrupt breaks MWAIT even when masked. */ 281#define MWAIT_INTRBREAK 0x00000001 282 283/* 284 * CPUID instruction 6 ecx info 285 */ 286#define CPUID_PERF_STAT 0x00000001 287#define CPUID_PERF_BIAS 0x00000008 288 289/* 290 * CPUID instruction 0xb ebx info. 291 */ 292#define CPUID_TYPE_INVAL 0 293#define CPUID_TYPE_SMT 1 294#define CPUID_TYPE_CORE 2 295 296/* 297 * CPUID instruction 0xd Processor Extended State Enumeration Sub-leaf 1 298 */ 299#define CPUID_EXTSTATE_XSAVEOPT 0x00000001 300#define CPUID_EXTSTATE_XSAVEC 0x00000002 301#define CPUID_EXTSTATE_XINUSE 0x00000004 302#define CPUID_EXTSTATE_XSAVES 0x00000008 303 304/* 305 * AMD extended function 8000_0007h edx info 306 */ 307#define AMDPM_TS 0x00000001 308#define AMDPM_FID 0x00000002 309#define AMDPM_VID 0x00000004 310#define AMDPM_TTP 0x00000008 311#define AMDPM_TM 0x00000010 312#define AMDPM_STC 0x00000020 313#define AMDPM_100MHZ_STEPS 0x00000040 314#define AMDPM_HW_PSTATE 0x00000080 315#define AMDPM_TSC_INVARIANT 0x00000100 316#define AMDPM_CPB 0x00000200 317 318/* 319 * AMD extended function 8000_0008h ecx info 320 */ 321#define AMDID_CMP_CORES 0x000000ff 322#define AMDID_COREID_SIZE 0x0000f000 323#define AMDID_COREID_SIZE_SHIFT 12 324 325/* 326 * CPUID instruction 7 Structured Extended Features, leaf 0 ebx info 327 */ 328#define CPUID_STDEXT_FSGSBASE 0x00000001 329#define CPUID_STDEXT_TSC_ADJUST 0x00000002 330#define CPUID_STDEXT_BMI1 0x00000008 331#define CPUID_STDEXT_HLE 0x00000010 332#define CPUID_STDEXT_AVX2 0x00000020 333#define CPUID_STDEXT_SMEP 0x00000080 334#define CPUID_STDEXT_BMI2 0x00000100 335#define CPUID_STDEXT_ERMS 0x00000200 336#define CPUID_STDEXT_INVPCID 0x00000400 337#define CPUID_STDEXT_RTM 0x00000800 338#define CPUID_STDEXT_MPX 0x00004000 339#define CPUID_STDEXT_AVX512F 0x00010000 340#define CPUID_STDEXT_RDSEED 0x00040000 341#define CPUID_STDEXT_ADX 0x00080000 342#define CPUID_STDEXT_SMAP 0x00100000 343#define CPUID_STDEXT_CLFLUSHOPT 0x00800000 344#define CPUID_STDEXT_PROCTRACE 0x02000000 345#define CPUID_STDEXT_AVX512PF 0x04000000 346#define CPUID_STDEXT_AVX512ER 0x08000000 347#define CPUID_STDEXT_AVX512CD 0x10000000 348#define CPUID_STDEXT_SHA 0x20000000 349 350/* 351 * CPUID manufacturers identifiers 352 */ 353#define AMD_VENDOR_ID "AuthenticAMD" 354#define CENTAUR_VENDOR_ID "CentaurHauls" 355#define CYRIX_VENDOR_ID "CyrixInstead" 356#define INTEL_VENDOR_ID "GenuineIntel" 357#define NEXGEN_VENDOR_ID "NexGenDriven" 358#define NSC_VENDOR_ID "Geode by NSC" 359#define RISE_VENDOR_ID "RiseRiseRise" 360#define SIS_VENDOR_ID "SiS SiS SiS " 361#define TRANSMETA_VENDOR_ID "GenuineTMx86" 362#define UMC_VENDOR_ID "UMC UMC UMC " 363 364/* 365 * Model-specific registers for the i386 family 366 */ 367#define MSR_P5_MC_ADDR 0x000 368#define MSR_P5_MC_TYPE 0x001 369#define MSR_TSC 0x010 370#define MSR_P5_CESR 0x011 371#define MSR_P5_CTR0 0x012 372#define MSR_P5_CTR1 0x013 373#define MSR_IA32_PLATFORM_ID 0x017 374#define MSR_APICBASE 0x01b 375#define MSR_EBL_CR_POWERON 0x02a 376#define MSR_TEST_CTL 0x033 377#define MSR_IA32_FEATURE_CONTROL 0x03a 378#define MSR_BIOS_UPDT_TRIG 0x079 379#define MSR_BBL_CR_D0 0x088 380#define MSR_BBL_CR_D1 0x089 381#define MSR_BBL_CR_D2 0x08a 382#define MSR_BIOS_SIGN 0x08b 383#define MSR_PERFCTR0 0x0c1 384#define MSR_PERFCTR1 0x0c2 385#define MSR_PLATFORM_INFO 0x0ce 386#define MSR_MPERF 0x0e7 387#define MSR_APERF 0x0e8 388#define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 389#define MSR_MTRRcap 0x0fe 390#define MSR_BBL_CR_ADDR 0x116 391#define MSR_BBL_CR_DECC 0x118 392#define MSR_BBL_CR_CTL 0x119 393#define MSR_BBL_CR_TRIG 0x11a 394#define MSR_BBL_CR_BUSY 0x11b 395#define MSR_BBL_CR_CTL3 0x11e 396#define MSR_SYSENTER_CS_MSR 0x174 397#define MSR_SYSENTER_ESP_MSR 0x175 398#define MSR_SYSENTER_EIP_MSR 0x176 399#define MSR_MCG_CAP 0x179 400#define MSR_MCG_STATUS 0x17a 401#define MSR_MCG_CTL 0x17b 402#define MSR_EVNTSEL0 0x186 403#define MSR_EVNTSEL1 0x187 404#define MSR_THERM_CONTROL 0x19a 405#define MSR_THERM_INTERRUPT 0x19b 406#define MSR_THERM_STATUS 0x19c 407#define MSR_IA32_MISC_ENABLE 0x1a0 408#define MSR_IA32_TEMPERATURE_TARGET 0x1a2 409#define MSR_TURBO_RATIO_LIMIT 0x1ad 410#define MSR_TURBO_RATIO_LIMIT1 0x1ae 411#define MSR_DEBUGCTLMSR 0x1d9 412#define MSR_LASTBRANCHFROMIP 0x1db 413#define MSR_LASTBRANCHTOIP 0x1dc 414#define MSR_LASTINTFROMIP 0x1dd 415#define MSR_LASTINTTOIP 0x1de 416#define MSR_ROB_CR_BKUPTMPDR6 0x1e0 417#define MSR_MTRRVarBase 0x200 418#define MSR_MTRR64kBase 0x250 419#define MSR_MTRR16kBase 0x258 420#define MSR_MTRR4kBase 0x268 421#define MSR_PAT 0x277 422#define MSR_MC0_CTL2 0x280 423#define MSR_MTRRdefType 0x2ff 424#define MSR_MC0_CTL 0x400 425#define MSR_MC0_STATUS 0x401 426#define MSR_MC0_ADDR 0x402 427#define MSR_MC0_MISC 0x403 428#define MSR_MC1_CTL 0x404 429#define MSR_MC1_STATUS 0x405 430#define MSR_MC1_ADDR 0x406 431#define MSR_MC1_MISC 0x407 432#define MSR_MC2_CTL 0x408 433#define MSR_MC2_STATUS 0x409 434#define MSR_MC2_ADDR 0x40a 435#define MSR_MC2_MISC 0x40b 436#define MSR_MC3_CTL 0x40c 437#define MSR_MC3_STATUS 0x40d 438#define MSR_MC3_ADDR 0x40e 439#define MSR_MC3_MISC 0x40f 440#define MSR_MC4_CTL 0x410 441#define MSR_MC4_STATUS 0x411 442#define MSR_MC4_ADDR 0x412 443#define MSR_MC4_MISC 0x413 444#define MSR_RAPL_POWER_UNIT 0x606 445#define MSR_PKG_ENERGY_STATUS 0x611 446#define MSR_DRAM_ENERGY_STATUS 0x619 447#define MSR_PP0_ENERGY_STATUS 0x639 448#define MSR_PP1_ENERGY_STATUS 0x641 449 450/* 451 * VMX MSRs 452 */ 453#define MSR_VMX_BASIC 0x480 454#define MSR_VMX_PINBASED_CTLS 0x481 455#define MSR_VMX_PROCBASED_CTLS 0x482 456#define MSR_VMX_EXIT_CTLS 0x483 457#define MSR_VMX_ENTRY_CTLS 0x484 458#define MSR_VMX_CR0_FIXED0 0x486 459#define MSR_VMX_CR0_FIXED1 0x487 460#define MSR_VMX_CR4_FIXED0 0x488 461#define MSR_VMX_CR4_FIXED1 0x489 462#define MSR_VMX_PROCBASED_CTLS2 0x48b 463#define MSR_VMX_EPT_VPID_CAP 0x48c 464#define MSR_VMX_TRUE_PINBASED_CTLS 0x48d 465#define MSR_VMX_TRUE_PROCBASED_CTLS 0x48e 466#define MSR_VMX_TRUE_EXIT_CTLS 0x48f 467#define MSR_VMX_TRUE_ENTRY_CTLS 0x490 468 469/* 470 * X2APIC MSRs 471 */ 472#define MSR_APIC_ID 0x802 473#define MSR_APIC_VERSION 0x803 474#define MSR_APIC_TPR 0x808 475#define MSR_APIC_EOI 0x80b 476#define MSR_APIC_LDR 0x80d 477#define MSR_APIC_SVR 0x80f 478#define MSR_APIC_ISR0 0x810 479#define MSR_APIC_ISR1 0x811 480#define MSR_APIC_ISR2 0x812 481#define MSR_APIC_ISR3 0x813 482#define MSR_APIC_ISR4 0x814 483#define MSR_APIC_ISR5 0x815 484#define MSR_APIC_ISR6 0x816 485#define MSR_APIC_ISR7 0x817 486#define MSR_APIC_TMR0 0x818 487#define MSR_APIC_IRR0 0x820 488#define MSR_APIC_ESR 0x828 489#define MSR_APIC_LVT_CMCI 0x82F 490#define MSR_APIC_ICR 0x830 491#define MSR_APIC_LVT_TIMER 0x832 492#define MSR_APIC_LVT_THERMAL 0x833 493#define MSR_APIC_LVT_PCINT 0x834 494#define MSR_APIC_LVT_LINT0 0x835 495#define MSR_APIC_LVT_LINT1 0x836 496#define MSR_APIC_LVT_ERROR 0x837 497#define MSR_APIC_ICR_TIMER 0x838 498#define MSR_APIC_CCR_TIMER 0x839 499#define MSR_APIC_DCR_TIMER 0x83e 500#define MSR_APIC_SELF_IPI 0x83f 501 502#define MSR_IA32_XSS 0xda0 503 504/* 505 * Constants related to MSR's. 506 */ 507#define APICBASE_RESERVED 0x000002ff 508#define APICBASE_BSP 0x00000100 509#define APICBASE_X2APIC 0x00000400 510#define APICBASE_ENABLED 0x00000800 511#define APICBASE_ADDRESS 0xfffff000 512 513/* MSR_IA32_FEATURE_CONTROL related */ 514#define IA32_FEATURE_CONTROL_LOCK 0x01 /* lock bit */ 515#define IA32_FEATURE_CONTROL_SMX_EN 0x02 /* enable VMX inside SMX */ 516#define IA32_FEATURE_CONTROL_VMX_EN 0x04 /* enable VMX outside SMX */ 517 518/* 519 * PAT modes. 520 */ 521#define PAT_UNCACHEABLE 0x00 522#define PAT_WRITE_COMBINING 0x01 523#define PAT_WRITE_THROUGH 0x04 524#define PAT_WRITE_PROTECTED 0x05 525#define PAT_WRITE_BACK 0x06 526#define PAT_UNCACHED 0x07 527#define PAT_VALUE(i, m) ((long long)(m) << (8 * (i))) 528#define PAT_MASK(i) PAT_VALUE(i, 0xff) 529 530/* 531 * Constants related to MTRRs 532 */ 533#define MTRR_UNCACHEABLE 0x00 534#define MTRR_WRITE_COMBINING 0x01 535#define MTRR_WRITE_THROUGH 0x04 536#define MTRR_WRITE_PROTECTED 0x05 537#define MTRR_WRITE_BACK 0x06 538#define MTRR_N64K 8 /* numbers of fixed-size entries */ 539#define MTRR_N16K 16 540#define MTRR_N4K 64 541#define MTRR_CAP_WC 0x0000000000000400 542#define MTRR_CAP_FIXED 0x0000000000000100 543#define MTRR_CAP_VCNT 0x00000000000000ff 544#define MTRR_DEF_ENABLE 0x0000000000000800 545#define MTRR_DEF_FIXED_ENABLE 0x0000000000000400 546#define MTRR_DEF_TYPE 0x00000000000000ff 547#define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000 548#define MTRR_PHYSBASE_TYPE 0x00000000000000ff 549#define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000 550#define MTRR_PHYSMASK_VALID 0x0000000000000800 551 552/* 553 * Cyrix configuration registers, accessible as IO ports. 554 */ 555#define CCR0 0xc0 /* Configuration control register 0 */ 556#define CCR0_NC0 0x01 /* First 64K of each 1M memory region is 557 non-cacheable */ 558#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 559#define CCR0_A20M 0x04 /* Enables A20M# input pin */ 560#define CCR0_KEN 0x08 /* Enables KEN# input pin */ 561#define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */ 562#define CCR0_BARB 0x20 /* Flushes internal cache when entering hold 563 state */ 564#define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set 565 assoc */ 566#define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */ 567 568#define CCR1 0xc1 /* Configuration control register 1 */ 569#define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */ 570#define CCR1_SMI 0x02 /* Enables SMM pins */ 571#define CCR1_SMAC 0x04 /* System management memory access */ 572#define CCR1_MMAC 0x08 /* Main memory access */ 573#define CCR1_NO_LOCK 0x10 /* Negate LOCK# */ 574#define CCR1_SM3 0x80 /* SMM address space address region 3 */ 575 576#define CCR2 0xc2 577#define CCR2_WB 0x02 /* Enables WB cache interface pins */ 578#define CCR2_SADS 0x02 /* Slow ADS */ 579#define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */ 580#define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */ 581#define CCR2_WT1 0x10 /* WT region 1 */ 582#define CCR2_WPR1 0x10 /* Write-protect region 1 */ 583#define CCR2_BARB 0x20 /* Flushes write-back cache when entering 584 hold state. */ 585#define CCR2_BWRT 0x40 /* Enables burst write cycles */ 586#define CCR2_USE_SUSP 0x80 /* Enables suspend pins */ 587 588#define CCR3 0xc3 589#define CCR3_SMILOCK 0x01 /* SMM register lock */ 590#define CCR3_NMI 0x02 /* Enables NMI during SMM */ 591#define CCR3_LINBRST 0x04 /* Linear address burst cycles */ 592#define CCR3_SMMMODE 0x08 /* SMM Mode */ 593#define CCR3_MAPEN0 0x10 /* Enables Map0 */ 594#define CCR3_MAPEN1 0x20 /* Enables Map1 */ 595#define CCR3_MAPEN2 0x40 /* Enables Map2 */ 596#define CCR3_MAPEN3 0x80 /* Enables Map3 */ 597 598#define CCR4 0xe8 599#define CCR4_IOMASK 0x07 600#define CCR4_MEM 0x08 /* Enables momory bypassing */ 601#define CCR4_DTE 0x10 /* Enables directory table entry cache */ 602#define CCR4_FASTFPE 0x20 /* Fast FPU exception */ 603#define CCR4_CPUID 0x80 /* Enables CPUID instruction */ 604 605#define CCR5 0xe9 606#define CCR5_WT_ALLOC 0x01 /* Write-through allocate */ 607#define CCR5_SLOP 0x02 /* LOOP instruction slowed down */ 608#define CCR5_LBR1 0x10 /* Local bus region 1 */ 609#define CCR5_ARREN 0x20 /* Enables ARR region */ 610 611#define CCR6 0xea 612 613#define CCR7 0xeb 614 615/* Performance Control Register (5x86 only). */ 616#define PCR0 0x20 617#define PCR0_RSTK 0x01 /* Enables return stack */ 618#define PCR0_BTB 0x02 /* Enables branch target buffer */ 619#define PCR0_LOOP 0x04 /* Enables loop */ 620#define PCR0_AIS 0x08 /* Enables all instrcutions stalled to 621 serialize pipe. */ 622#define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ 623#define PCR0_BTBRT 0x40 /* Enables BTB test register. */ 624#define PCR0_LSSER 0x80 /* Disable reorder */ 625 626/* Device Identification Registers */ 627#define DIR0 0xfe 628#define DIR1 0xff 629 630/* 631 * Machine Check register constants. 632 */ 633#define MCG_CAP_COUNT 0x000000ff 634#define MCG_CAP_CTL_P 0x00000100 635#define MCG_CAP_EXT_P 0x00000200 636#define MCG_CAP_CMCI_P 0x00000400 637#define MCG_CAP_TES_P 0x00000800 638#define MCG_CAP_EXT_CNT 0x00ff0000 639#define MCG_CAP_SER_P 0x01000000 640#define MCG_STATUS_RIPV 0x00000001 641#define MCG_STATUS_EIPV 0x00000002 642#define MCG_STATUS_MCIP 0x00000004 643#define MCG_CTL_ENABLE 0xffffffffffffffff 644#define MCG_CTL_DISABLE 0x0000000000000000 645#define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4) 646#define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4) 647#define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4) 648#define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4) 649#define MSR_MC_CTL2(x) (MSR_MC0_CTL2 + (x)) /* If MCG_CAP_CMCI_P */ 650#define MC_STATUS_MCA_ERROR 0x000000000000ffff 651#define MC_STATUS_MODEL_ERROR 0x00000000ffff0000 652#define MC_STATUS_OTHER_INFO 0x01ffffff00000000 653#define MC_STATUS_COR_COUNT 0x001fffc000000000 /* If MCG_CAP_CMCI_P */ 654#define MC_STATUS_TES_STATUS 0x0060000000000000 /* If MCG_CAP_TES_P */ 655#define MC_STATUS_AR 0x0080000000000000 /* If MCG_CAP_TES_P */ 656#define MC_STATUS_S 0x0100000000000000 /* If MCG_CAP_TES_P */ 657#define MC_STATUS_PCC 0x0200000000000000 658#define MC_STATUS_ADDRV 0x0400000000000000 659#define MC_STATUS_MISCV 0x0800000000000000 660#define MC_STATUS_EN 0x1000000000000000 661#define MC_STATUS_UC 0x2000000000000000 662#define MC_STATUS_OVER 0x4000000000000000 663#define MC_STATUS_VAL 0x8000000000000000 664#define MC_MISC_RA_LSB 0x000000000000003f /* If MCG_CAP_SER_P */ 665#define MC_MISC_ADDRESS_MODE 0x00000000000001c0 /* If MCG_CAP_SER_P */ 666#define MC_CTL2_THRESHOLD 0x0000000000007fff 667#define MC_CTL2_CMCI_EN 0x0000000040000000 668 669/* 670 * The following four 3-byte registers control the non-cacheable regions. 671 * These registers must be written as three separate bytes. 672 * 673 * NCRx+0: A31-A24 of starting address 674 * NCRx+1: A23-A16 of starting address 675 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 676 * 677 * The non-cacheable region's starting address must be aligned to the 678 * size indicated by the NCR_SIZE_xx field. 679 */ 680#define NCR1 0xc4 681#define NCR2 0xc7 682#define NCR3 0xca 683#define NCR4 0xcd 684 685#define NCR_SIZE_0K 0 686#define NCR_SIZE_4K 1 687#define NCR_SIZE_8K 2 688#define NCR_SIZE_16K 3 689#define NCR_SIZE_32K 4 690#define NCR_SIZE_64K 5 691#define NCR_SIZE_128K 6 692#define NCR_SIZE_256K 7 693#define NCR_SIZE_512K 8 694#define NCR_SIZE_1M 9 695#define NCR_SIZE_2M 10 696#define NCR_SIZE_4M 11 697#define NCR_SIZE_8M 12 698#define NCR_SIZE_16M 13 699#define NCR_SIZE_32M 14 700#define NCR_SIZE_4G 15 701 702/* 703 * The address region registers are used to specify the location and 704 * size for the eight address regions. 705 * 706 * ARRx + 0: A31-A24 of start address 707 * ARRx + 1: A23-A16 of start address 708 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx 709 */ 710#define ARR0 0xc4 711#define ARR1 0xc7 712#define ARR2 0xca 713#define ARR3 0xcd 714#define ARR4 0xd0 715#define ARR5 0xd3 716#define ARR6 0xd6 717#define ARR7 0xd9 718 719#define ARR_SIZE_0K 0 720#define ARR_SIZE_4K 1 721#define ARR_SIZE_8K 2 722#define ARR_SIZE_16K 3 723#define ARR_SIZE_32K 4 724#define ARR_SIZE_64K 5 725#define ARR_SIZE_128K 6 726#define ARR_SIZE_256K 7 727#define ARR_SIZE_512K 8 728#define ARR_SIZE_1M 9 729#define ARR_SIZE_2M 10 730#define ARR_SIZE_4M 11 731#define ARR_SIZE_8M 12 732#define ARR_SIZE_16M 13 733#define ARR_SIZE_32M 14 734#define ARR_SIZE_4G 15 735 736/* 737 * The region control registers specify the attributes associated with 738 * the ARRx addres regions. 739 */ 740#define RCR0 0xdc 741#define RCR1 0xdd 742#define RCR2 0xde 743#define RCR3 0xdf 744#define RCR4 0xe0 745#define RCR5 0xe1 746#define RCR6 0xe2 747#define RCR7 0xe3 748 749#define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 750#define RCR_RCE 0x01 /* Enables caching for ARR7. */ 751#define RCR_WWO 0x02 /* Weak write ordering. */ 752#define RCR_WL 0x04 /* Weak locking. */ 753#define RCR_WG 0x08 /* Write gathering. */ 754#define RCR_WT 0x10 /* Write-through. */ 755#define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 756 757/* AMD Write Allocate Top-Of-Memory and Control Register */ 758#define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 759#define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 760#define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ 761 762/* AMD64 MSR's */ 763#define MSR_EFER 0xc0000080 /* extended features */ 764#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */ 765#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */ 766#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */ 767#define MSR_SF_MASK 0xc0000084 /* syscall flags mask */ 768#define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */ 769#define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */ 770#define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */ 771#define MSR_PERFEVSEL0 0xc0010000 772#define MSR_PERFEVSEL1 0xc0010001 773#define MSR_PERFEVSEL2 0xc0010002 774#define MSR_PERFEVSEL3 0xc0010003 775#define MSR_K7_PERFCTR0 0xc0010004 776#define MSR_K7_PERFCTR1 0xc0010005 777#define MSR_K7_PERFCTR2 0xc0010006 778#define MSR_K7_PERFCTR3 0xc0010007 779#define MSR_SYSCFG 0xc0010010 780#define MSR_HWCR 0xc0010015 781#define MSR_IORRBASE0 0xc0010016 782#define MSR_IORRMASK0 0xc0010017 783#define MSR_IORRBASE1 0xc0010018 784#define MSR_IORRMASK1 0xc0010019 785#define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */ 786#define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */ 787#define MSR_NB_CFG1 0xc001001f /* NB configuration 1 */ 788#define MSR_P_STATE_LIMIT 0xc0010061 /* P-state Current Limit Register */ 789#define MSR_P_STATE_CONTROL 0xc0010062 /* P-state Control Register */ 790#define MSR_P_STATE_STATUS 0xc0010063 /* P-state Status Register */ 791#define MSR_P_STATE_CONFIG(n) (0xc0010064 + (n)) /* P-state Config */ 792#define MSR_SMM_ADDR 0xc0010112 /* SMM TSEG base address */ 793#define MSR_SMM_MASK 0xc0010113 /* SMM TSEG address mask */ 794#define MSR_IC_CFG 0xc0011021 /* Instruction Cache Configuration */ 795#define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */ 796#define MSR_MC0_CTL_MASK 0xc0010044 797#define MSR_VM_CR 0xc0010114 /* SVM: feature control */ 798#define MSR_VM_HSAVE_PA 0xc0010117 /* SVM: host save area address */ 799 800/* MSR_VM_CR related */ 801#define VM_CR_SVMDIS 0x10 /* SVM: disabled by BIOS */ 802 803/* VIA ACE crypto featureset: for via_feature_rng */ 804#define VIA_HAS_RNG 1 /* cpu has RNG */ 805 806/* VIA ACE crypto featureset: for via_feature_xcrypt */ 807#define VIA_HAS_AES 1 /* cpu has AES */ 808#define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ 809#define VIA_HAS_MM 4 /* cpu has RSA instructions */ 810#define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ 811 812/* Centaur Extended Feature flags */ 813#define VIA_CPUID_HAS_RNG 0x000004 814#define VIA_CPUID_DO_RNG 0x000008 815#define VIA_CPUID_HAS_ACE 0x000040 816#define VIA_CPUID_DO_ACE 0x000080 817#define VIA_CPUID_HAS_ACE2 0x000100 818#define VIA_CPUID_DO_ACE2 0x000200 819#define VIA_CPUID_HAS_PHE 0x000400 820#define VIA_CPUID_DO_PHE 0x000800 821#define VIA_CPUID_HAS_PMM 0x001000 822#define VIA_CPUID_DO_PMM 0x002000 823 824/* VIA ACE xcrypt-* instruction context control options */ 825#define VIA_CRYPT_CWLO_ROUND_M 0x0000000f 826#define VIA_CRYPT_CWLO_ALG_M 0x00000070 827#define VIA_CRYPT_CWLO_ALG_AES 0x00000000 828#define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080 829#define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000 830#define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080 831#define VIA_CRYPT_CWLO_NORMAL 0x00000000 832#define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100 833#define VIA_CRYPT_CWLO_ENCRYPT 0x00000000 834#define VIA_CRYPT_CWLO_DECRYPT 0x00000200 835#define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */ 836#define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */ 837#define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */ 838 839#endif /* !_MACHINE_SPECIALREG_H_ */ 840