specialreg.h revision 258159
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 4. Neither the name of the University nor the names of its contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 30 * $FreeBSD: stable/10/sys/x86/include/specialreg.h 258159 2013-11-15 07:10:42Z kib $ 31 */ 32 33#ifndef _MACHINE_SPECIALREG_H_ 34#define _MACHINE_SPECIALREG_H_ 35 36/* 37 * Bits in 386 special registers: 38 */ 39#define CR0_PE 0x00000001 /* Protected mode Enable */ 40#define CR0_MP 0x00000002 /* "Math" (fpu) Present */ 41#define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ 42#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 43#define CR0_PG 0x80000000 /* PaGing enable */ 44 45/* 46 * Bits in 486 special registers: 47 */ 48#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 49#define CR0_WP 0x00010000 /* Write Protect (honor page protect in 50 all modes) */ 51#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 52#define CR0_NW 0x20000000 /* Not Write-through */ 53#define CR0_CD 0x40000000 /* Cache Disable */ 54 55#define CR3_PCID_SAVE 0x8000000000000000 56 57/* 58 * Bits in PPro special registers 59 */ 60#define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ 61#define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ 62#define CR4_TSD 0x00000004 /* Time stamp disable */ 63#define CR4_DE 0x00000008 /* Debugging extensions */ 64#define CR4_PSE 0x00000010 /* Page size extensions */ 65#define CR4_PAE 0x00000020 /* Physical address extension */ 66#define CR4_MCE 0x00000040 /* Machine check enable */ 67#define CR4_PGE 0x00000080 /* Page global enable */ 68#define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ 69#define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ 70#define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ 71#define CR4_VMXE 0x00002000 /* enable VMX operation (Intel-specific) */ 72#define CR4_FSGSBASE 0x00010000 /* Enable FS/GS BASE accessing instructions */ 73#define CR4_PCIDE 0x00020000 /* Enable Context ID */ 74#define CR4_XSAVE 0x00040000 /* XSETBV/XGETBV */ 75#define CR4_SMEP 0x00100000 /* Supervisor-Mode Execution Prevention */ 76 77/* 78 * Bits in AMD64 special registers. EFER is 64 bits wide. 79 */ 80#define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */ 81#define EFER_LME 0x000000100 /* Long mode enable (R/W) */ 82#define EFER_LMA 0x000000400 /* Long mode active (R) */ 83#define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ 84 85/* 86 * Intel Extended Features registers 87 */ 88#define XCR0 0 /* XFEATURE_ENABLED_MASK register */ 89 90#define XFEATURE_ENABLED_X87 0x00000001 91#define XFEATURE_ENABLED_SSE 0x00000002 92#define XFEATURE_ENABLED_AVX 0x00000004 93 94#define XFEATURE_AVX \ 95 (XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE | XFEATURE_ENABLED_AVX) 96 97/* 98 * CPUID instruction features register 99 */ 100#define CPUID_FPU 0x00000001 101#define CPUID_VME 0x00000002 102#define CPUID_DE 0x00000004 103#define CPUID_PSE 0x00000008 104#define CPUID_TSC 0x00000010 105#define CPUID_MSR 0x00000020 106#define CPUID_PAE 0x00000040 107#define CPUID_MCE 0x00000080 108#define CPUID_CX8 0x00000100 109#define CPUID_APIC 0x00000200 110#define CPUID_B10 0x00000400 111#define CPUID_SEP 0x00000800 112#define CPUID_MTRR 0x00001000 113#define CPUID_PGE 0x00002000 114#define CPUID_MCA 0x00004000 115#define CPUID_CMOV 0x00008000 116#define CPUID_PAT 0x00010000 117#define CPUID_PSE36 0x00020000 118#define CPUID_PSN 0x00040000 119#define CPUID_CLFSH 0x00080000 120#define CPUID_B20 0x00100000 121#define CPUID_DS 0x00200000 122#define CPUID_ACPI 0x00400000 123#define CPUID_MMX 0x00800000 124#define CPUID_FXSR 0x01000000 125#define CPUID_SSE 0x02000000 126#define CPUID_XMM 0x02000000 127#define CPUID_SSE2 0x04000000 128#define CPUID_SS 0x08000000 129#define CPUID_HTT 0x10000000 130#define CPUID_TM 0x20000000 131#define CPUID_IA64 0x40000000 132#define CPUID_PBE 0x80000000 133 134#define CPUID2_SSE3 0x00000001 135#define CPUID2_PCLMULQDQ 0x00000002 136#define CPUID2_DTES64 0x00000004 137#define CPUID2_MON 0x00000008 138#define CPUID2_DS_CPL 0x00000010 139#define CPUID2_VMX 0x00000020 140#define CPUID2_SMX 0x00000040 141#define CPUID2_EST 0x00000080 142#define CPUID2_TM2 0x00000100 143#define CPUID2_SSSE3 0x00000200 144#define CPUID2_CNXTID 0x00000400 145#define CPUID2_FMA 0x00001000 146#define CPUID2_CX16 0x00002000 147#define CPUID2_XTPR 0x00004000 148#define CPUID2_PDCM 0x00008000 149#define CPUID2_PCID 0x00020000 150#define CPUID2_DCA 0x00040000 151#define CPUID2_SSE41 0x00080000 152#define CPUID2_SSE42 0x00100000 153#define CPUID2_X2APIC 0x00200000 154#define CPUID2_MOVBE 0x00400000 155#define CPUID2_POPCNT 0x00800000 156#define CPUID2_TSCDLT 0x01000000 157#define CPUID2_AESNI 0x02000000 158#define CPUID2_XSAVE 0x04000000 159#define CPUID2_OSXSAVE 0x08000000 160#define CPUID2_AVX 0x10000000 161#define CPUID2_F16C 0x20000000 162#define CPUID2_RDRAND 0x40000000 163#define CPUID2_HV 0x80000000 164 165/* 166 * Important bits in the Thermal and Power Management flags 167 * CPUID.6 EAX and ECX. 168 */ 169#define CPUTPM1_SENSOR 0x00000001 170#define CPUTPM1_TURBO 0x00000002 171#define CPUTPM1_ARAT 0x00000004 172#define CPUTPM2_EFFREQ 0x00000001 173 174/* 175 * Important bits in the AMD extended cpuid flags 176 */ 177#define AMDID_SYSCALL 0x00000800 178#define AMDID_MP 0x00080000 179#define AMDID_NX 0x00100000 180#define AMDID_EXT_MMX 0x00400000 181#define AMDID_FFXSR 0x01000000 182#define AMDID_PAGE1GB 0x04000000 183#define AMDID_RDTSCP 0x08000000 184#define AMDID_LM 0x20000000 185#define AMDID_EXT_3DNOW 0x40000000 186#define AMDID_3DNOW 0x80000000 187 188#define AMDID2_LAHF 0x00000001 189#define AMDID2_CMP 0x00000002 190#define AMDID2_SVM 0x00000004 191#define AMDID2_EXT_APIC 0x00000008 192#define AMDID2_CR8 0x00000010 193#define AMDID2_ABM 0x00000020 194#define AMDID2_SSE4A 0x00000040 195#define AMDID2_MAS 0x00000080 196#define AMDID2_PREFETCH 0x00000100 197#define AMDID2_OSVW 0x00000200 198#define AMDID2_IBS 0x00000400 199#define AMDID2_XOP 0x00000800 200#define AMDID2_SKINIT 0x00001000 201#define AMDID2_WDT 0x00002000 202#define AMDID2_LWP 0x00008000 203#define AMDID2_FMA4 0x00010000 204#define AMDID2_TCE 0x00020000 205#define AMDID2_NODE_ID 0x00080000 206#define AMDID2_TBM 0x00200000 207#define AMDID2_TOPOLOGY 0x00400000 208#define AMDID2_PCXC 0x00800000 209#define AMDID2_PNXC 0x01000000 210#define AMDID2_DBE 0x04000000 211#define AMDID2_PTSC 0x08000000 212#define AMDID2_PTSCEL2I 0x10000000 213 214/* 215 * CPUID instruction 1 eax info 216 */ 217#define CPUID_STEPPING 0x0000000f 218#define CPUID_MODEL 0x000000f0 219#define CPUID_FAMILY 0x00000f00 220#define CPUID_EXT_MODEL 0x000f0000 221#define CPUID_EXT_FAMILY 0x0ff00000 222#ifdef __i386__ 223#define CPUID_TO_MODEL(id) \ 224 ((((id) & CPUID_MODEL) >> 4) | \ 225 ((((id) & CPUID_FAMILY) >= 0x600) ? \ 226 (((id) & CPUID_EXT_MODEL) >> 12) : 0)) 227#define CPUID_TO_FAMILY(id) \ 228 ((((id) & CPUID_FAMILY) >> 8) + \ 229 ((((id) & CPUID_FAMILY) == 0xf00) ? \ 230 (((id) & CPUID_EXT_FAMILY) >> 20) : 0)) 231#else 232#define CPUID_TO_MODEL(id) \ 233 ((((id) & CPUID_MODEL) >> 4) | \ 234 (((id) & CPUID_EXT_MODEL) >> 12)) 235#define CPUID_TO_FAMILY(id) \ 236 ((((id) & CPUID_FAMILY) >> 8) + \ 237 (((id) & CPUID_EXT_FAMILY) >> 20)) 238#endif 239 240/* 241 * CPUID instruction 1 ebx info 242 */ 243#define CPUID_BRAND_INDEX 0x000000ff 244#define CPUID_CLFUSH_SIZE 0x0000ff00 245#define CPUID_HTT_CORES 0x00ff0000 246#define CPUID_LOCAL_APIC_ID 0xff000000 247 248/* 249 * CPUID instruction 5 info 250 */ 251#define CPUID5_MON_MIN_SIZE 0x0000ffff /* eax */ 252#define CPUID5_MON_MAX_SIZE 0x0000ffff /* ebx */ 253#define CPUID5_MON_MWAIT_EXT 0x00000001 /* ecx */ 254#define CPUID5_MWAIT_INTRBREAK 0x00000002 /* ecx */ 255 256/* 257 * MWAIT cpu power states. Lower 4 bits are sub-states. 258 */ 259#define MWAIT_C0 0xf0 260#define MWAIT_C1 0x00 261#define MWAIT_C2 0x10 262#define MWAIT_C3 0x20 263#define MWAIT_C4 0x30 264 265/* 266 * MWAIT extensions. 267 */ 268/* Interrupt breaks MWAIT even when masked. */ 269#define MWAIT_INTRBREAK 0x00000001 270 271/* 272 * CPUID instruction 6 ecx info 273 */ 274#define CPUID_PERF_STAT 0x00000001 275#define CPUID_PERF_BIAS 0x00000008 276 277/* 278 * CPUID instruction 0xb ebx info. 279 */ 280#define CPUID_TYPE_INVAL 0 281#define CPUID_TYPE_SMT 1 282#define CPUID_TYPE_CORE 2 283 284/* 285 * CPUID instruction 0xd Processor Extended State Enumeration Sub-leaf 1 286 */ 287#define CPUID_EXTSTATE_XSAVEOPT 0x00000001 288 289/* 290 * AMD extended function 8000_0007h edx info 291 */ 292#define AMDPM_TS 0x00000001 293#define AMDPM_FID 0x00000002 294#define AMDPM_VID 0x00000004 295#define AMDPM_TTP 0x00000008 296#define AMDPM_TM 0x00000010 297#define AMDPM_STC 0x00000020 298#define AMDPM_100MHZ_STEPS 0x00000040 299#define AMDPM_HW_PSTATE 0x00000080 300#define AMDPM_TSC_INVARIANT 0x00000100 301#define AMDPM_CPB 0x00000200 302 303/* 304 * AMD extended function 8000_0008h ecx info 305 */ 306#define AMDID_CMP_CORES 0x000000ff 307#define AMDID_COREID_SIZE 0x0000f000 308#define AMDID_COREID_SIZE_SHIFT 12 309 310/* 311 * Structured Extended Features 312 */ 313#define CPUID_STDEXT_FSGSBASE 0x00000001 314#define CPUID_STDEXT_TSC_ADJUST 0x00000002 315#define CPUID_STDEXT_BMI1 0x00000008 316#define CPUID_STDEXT_HLE 0x00000010 317#define CPUID_STDEXT_AVX2 0x00000020 318#define CPUID_STDEXT_SMEP 0x00000080 319#define CPUID_STDEXT_BMI2 0x00000100 320#define CPUID_STDEXT_ENH_MOVSB 0x00000200 321#define CPUID_STDEXT_RTM 0x00000800 322#define CPUID_STDEXT_INVPCID 0x00000400 323#define CPUID_STDEXT_RDSEED 0x00040000 324#define CPUID_STDEXT_ADX 0x00080000 325#define CPUID_STDEXT_SMAP 0x00100000 326 327/* 328 * CPUID manufacturers identifiers 329 */ 330#define AMD_VENDOR_ID "AuthenticAMD" 331#define CENTAUR_VENDOR_ID "CentaurHauls" 332#define CYRIX_VENDOR_ID "CyrixInstead" 333#define INTEL_VENDOR_ID "GenuineIntel" 334#define NEXGEN_VENDOR_ID "NexGenDriven" 335#define NSC_VENDOR_ID "Geode by NSC" 336#define RISE_VENDOR_ID "RiseRiseRise" 337#define SIS_VENDOR_ID "SiS SiS SiS " 338#define TRANSMETA_VENDOR_ID "GenuineTMx86" 339#define UMC_VENDOR_ID "UMC UMC UMC " 340 341/* 342 * Model-specific registers for the i386 family 343 */ 344#define MSR_P5_MC_ADDR 0x000 345#define MSR_P5_MC_TYPE 0x001 346#define MSR_TSC 0x010 347#define MSR_P5_CESR 0x011 348#define MSR_P5_CTR0 0x012 349#define MSR_P5_CTR1 0x013 350#define MSR_IA32_PLATFORM_ID 0x017 351#define MSR_APICBASE 0x01b 352#define MSR_EBL_CR_POWERON 0x02a 353#define MSR_TEST_CTL 0x033 354#define MSR_IA32_FEATURE_CONTROL 0x03a 355#define MSR_BIOS_UPDT_TRIG 0x079 356#define MSR_BBL_CR_D0 0x088 357#define MSR_BBL_CR_D1 0x089 358#define MSR_BBL_CR_D2 0x08a 359#define MSR_BIOS_SIGN 0x08b 360#define MSR_PERFCTR0 0x0c1 361#define MSR_PERFCTR1 0x0c2 362#define MSR_MPERF 0x0e7 363#define MSR_APERF 0x0e8 364#define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 365#define MSR_MTRRcap 0x0fe 366#define MSR_BBL_CR_ADDR 0x116 367#define MSR_BBL_CR_DECC 0x118 368#define MSR_BBL_CR_CTL 0x119 369#define MSR_BBL_CR_TRIG 0x11a 370#define MSR_BBL_CR_BUSY 0x11b 371#define MSR_BBL_CR_CTL3 0x11e 372#define MSR_SYSENTER_CS_MSR 0x174 373#define MSR_SYSENTER_ESP_MSR 0x175 374#define MSR_SYSENTER_EIP_MSR 0x176 375#define MSR_MCG_CAP 0x179 376#define MSR_MCG_STATUS 0x17a 377#define MSR_MCG_CTL 0x17b 378#define MSR_EVNTSEL0 0x186 379#define MSR_EVNTSEL1 0x187 380#define MSR_THERM_CONTROL 0x19a 381#define MSR_THERM_INTERRUPT 0x19b 382#define MSR_THERM_STATUS 0x19c 383#define MSR_IA32_MISC_ENABLE 0x1a0 384#define MSR_IA32_TEMPERATURE_TARGET 0x1a2 385#define MSR_DEBUGCTLMSR 0x1d9 386#define MSR_LASTBRANCHFROMIP 0x1db 387#define MSR_LASTBRANCHTOIP 0x1dc 388#define MSR_LASTINTFROMIP 0x1dd 389#define MSR_LASTINTTOIP 0x1de 390#define MSR_ROB_CR_BKUPTMPDR6 0x1e0 391#define MSR_MTRRVarBase 0x200 392#define MSR_MTRR64kBase 0x250 393#define MSR_MTRR16kBase 0x258 394#define MSR_MTRR4kBase 0x268 395#define MSR_PAT 0x277 396#define MSR_MC0_CTL2 0x280 397#define MSR_MTRRdefType 0x2ff 398#define MSR_MC0_CTL 0x400 399#define MSR_MC0_STATUS 0x401 400#define MSR_MC0_ADDR 0x402 401#define MSR_MC0_MISC 0x403 402#define MSR_MC1_CTL 0x404 403#define MSR_MC1_STATUS 0x405 404#define MSR_MC1_ADDR 0x406 405#define MSR_MC1_MISC 0x407 406#define MSR_MC2_CTL 0x408 407#define MSR_MC2_STATUS 0x409 408#define MSR_MC2_ADDR 0x40a 409#define MSR_MC2_MISC 0x40b 410#define MSR_MC3_CTL 0x40c 411#define MSR_MC3_STATUS 0x40d 412#define MSR_MC3_ADDR 0x40e 413#define MSR_MC3_MISC 0x40f 414#define MSR_MC4_CTL 0x410 415#define MSR_MC4_STATUS 0x411 416#define MSR_MC4_ADDR 0x412 417#define MSR_MC4_MISC 0x413 418 419/* 420 * X2APIC MSRs 421 */ 422#define MSR_APIC_ID 0x802 423#define MSR_APIC_VERSION 0x803 424#define MSR_APIC_TPR 0x808 425#define MSR_APIC_EOI 0x80b 426#define MSR_APIC_LDR 0x80d 427#define MSR_APIC_SVR 0x80f 428#define MSR_APIC_ISR0 0x810 429#define MSR_APIC_ISR1 0x811 430#define MSR_APIC_ISR2 0x812 431#define MSR_APIC_ISR3 0x813 432#define MSR_APIC_ISR4 0x814 433#define MSR_APIC_ISR5 0x815 434#define MSR_APIC_ISR6 0x816 435#define MSR_APIC_ISR7 0x817 436#define MSR_APIC_TMR0 0x818 437#define MSR_APIC_IRR0 0x820 438#define MSR_APIC_ESR 0x828 439#define MSR_APIC_LVT_CMCI 0x82F 440#define MSR_APIC_ICR 0x830 441#define MSR_APIC_LVT_TIMER 0x832 442#define MSR_APIC_LVT_THERMAL 0x833 443#define MSR_APIC_LVT_PCINT 0x834 444#define MSR_APIC_LVT_LINT0 0x835 445#define MSR_APIC_LVT_LINT1 0x836 446#define MSR_APIC_LVT_ERROR 0x837 447#define MSR_APIC_ICR_TIMER 0x838 448#define MSR_APIC_CCR_TIMER 0x839 449#define MSR_APIC_DCR_TIMER 0x83e 450#define MSR_APIC_SELF_IPI 0x83f 451 452/* 453 * Constants related to MSR's. 454 */ 455#define APICBASE_RESERVED 0x000002ff 456#define APICBASE_BSP 0x00000100 457#define APICBASE_X2APIC 0x00000400 458#define APICBASE_ENABLED 0x00000800 459#define APICBASE_ADDRESS 0xfffff000 460 461/* MSR_IA32_FEATURE_CONTROL related */ 462#define IA32_FEATURE_CONTROL_LOCK 0x01 /* lock bit */ 463#define IA32_FEATURE_CONTROL_SMX_EN 0x02 /* enable VMX inside SMX */ 464#define IA32_FEATURE_CONTROL_VMX_EN 0x04 /* enable VMX outside SMX */ 465 466/* 467 * PAT modes. 468 */ 469#define PAT_UNCACHEABLE 0x00 470#define PAT_WRITE_COMBINING 0x01 471#define PAT_WRITE_THROUGH 0x04 472#define PAT_WRITE_PROTECTED 0x05 473#define PAT_WRITE_BACK 0x06 474#define PAT_UNCACHED 0x07 475#define PAT_VALUE(i, m) ((long long)(m) << (8 * (i))) 476#define PAT_MASK(i) PAT_VALUE(i, 0xff) 477 478/* 479 * Constants related to MTRRs 480 */ 481#define MTRR_UNCACHEABLE 0x00 482#define MTRR_WRITE_COMBINING 0x01 483#define MTRR_WRITE_THROUGH 0x04 484#define MTRR_WRITE_PROTECTED 0x05 485#define MTRR_WRITE_BACK 0x06 486#define MTRR_N64K 8 /* numbers of fixed-size entries */ 487#define MTRR_N16K 16 488#define MTRR_N4K 64 489#define MTRR_CAP_WC 0x0000000000000400 490#define MTRR_CAP_FIXED 0x0000000000000100 491#define MTRR_CAP_VCNT 0x00000000000000ff 492#define MTRR_DEF_ENABLE 0x0000000000000800 493#define MTRR_DEF_FIXED_ENABLE 0x0000000000000400 494#define MTRR_DEF_TYPE 0x00000000000000ff 495#define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000 496#define MTRR_PHYSBASE_TYPE 0x00000000000000ff 497#define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000 498#define MTRR_PHYSMASK_VALID 0x0000000000000800 499 500/* 501 * Cyrix configuration registers, accessible as IO ports. 502 */ 503#define CCR0 0xc0 /* Configuration control register 0 */ 504#define CCR0_NC0 0x01 /* First 64K of each 1M memory region is 505 non-cacheable */ 506#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 507#define CCR0_A20M 0x04 /* Enables A20M# input pin */ 508#define CCR0_KEN 0x08 /* Enables KEN# input pin */ 509#define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */ 510#define CCR0_BARB 0x20 /* Flushes internal cache when entering hold 511 state */ 512#define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set 513 assoc */ 514#define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */ 515 516#define CCR1 0xc1 /* Configuration control register 1 */ 517#define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */ 518#define CCR1_SMI 0x02 /* Enables SMM pins */ 519#define CCR1_SMAC 0x04 /* System management memory access */ 520#define CCR1_MMAC 0x08 /* Main memory access */ 521#define CCR1_NO_LOCK 0x10 /* Negate LOCK# */ 522#define CCR1_SM3 0x80 /* SMM address space address region 3 */ 523 524#define CCR2 0xc2 525#define CCR2_WB 0x02 /* Enables WB cache interface pins */ 526#define CCR2_SADS 0x02 /* Slow ADS */ 527#define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */ 528#define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */ 529#define CCR2_WT1 0x10 /* WT region 1 */ 530#define CCR2_WPR1 0x10 /* Write-protect region 1 */ 531#define CCR2_BARB 0x20 /* Flushes write-back cache when entering 532 hold state. */ 533#define CCR2_BWRT 0x40 /* Enables burst write cycles */ 534#define CCR2_USE_SUSP 0x80 /* Enables suspend pins */ 535 536#define CCR3 0xc3 537#define CCR3_SMILOCK 0x01 /* SMM register lock */ 538#define CCR3_NMI 0x02 /* Enables NMI during SMM */ 539#define CCR3_LINBRST 0x04 /* Linear address burst cycles */ 540#define CCR3_SMMMODE 0x08 /* SMM Mode */ 541#define CCR3_MAPEN0 0x10 /* Enables Map0 */ 542#define CCR3_MAPEN1 0x20 /* Enables Map1 */ 543#define CCR3_MAPEN2 0x40 /* Enables Map2 */ 544#define CCR3_MAPEN3 0x80 /* Enables Map3 */ 545 546#define CCR4 0xe8 547#define CCR4_IOMASK 0x07 548#define CCR4_MEM 0x08 /* Enables momory bypassing */ 549#define CCR4_DTE 0x10 /* Enables directory table entry cache */ 550#define CCR4_FASTFPE 0x20 /* Fast FPU exception */ 551#define CCR4_CPUID 0x80 /* Enables CPUID instruction */ 552 553#define CCR5 0xe9 554#define CCR5_WT_ALLOC 0x01 /* Write-through allocate */ 555#define CCR5_SLOP 0x02 /* LOOP instruction slowed down */ 556#define CCR5_LBR1 0x10 /* Local bus region 1 */ 557#define CCR5_ARREN 0x20 /* Enables ARR region */ 558 559#define CCR6 0xea 560 561#define CCR7 0xeb 562 563/* Performance Control Register (5x86 only). */ 564#define PCR0 0x20 565#define PCR0_RSTK 0x01 /* Enables return stack */ 566#define PCR0_BTB 0x02 /* Enables branch target buffer */ 567#define PCR0_LOOP 0x04 /* Enables loop */ 568#define PCR0_AIS 0x08 /* Enables all instrcutions stalled to 569 serialize pipe. */ 570#define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ 571#define PCR0_BTBRT 0x40 /* Enables BTB test register. */ 572#define PCR0_LSSER 0x80 /* Disable reorder */ 573 574/* Device Identification Registers */ 575#define DIR0 0xfe 576#define DIR1 0xff 577 578/* 579 * Machine Check register constants. 580 */ 581#define MCG_CAP_COUNT 0x000000ff 582#define MCG_CAP_CTL_P 0x00000100 583#define MCG_CAP_EXT_P 0x00000200 584#define MCG_CAP_CMCI_P 0x00000400 585#define MCG_CAP_TES_P 0x00000800 586#define MCG_CAP_EXT_CNT 0x00ff0000 587#define MCG_CAP_SER_P 0x01000000 588#define MCG_STATUS_RIPV 0x00000001 589#define MCG_STATUS_EIPV 0x00000002 590#define MCG_STATUS_MCIP 0x00000004 591#define MCG_CTL_ENABLE 0xffffffffffffffff 592#define MCG_CTL_DISABLE 0x0000000000000000 593#define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4) 594#define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4) 595#define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4) 596#define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4) 597#define MSR_MC_CTL2(x) (MSR_MC0_CTL2 + (x)) /* If MCG_CAP_CMCI_P */ 598#define MC_STATUS_MCA_ERROR 0x000000000000ffff 599#define MC_STATUS_MODEL_ERROR 0x00000000ffff0000 600#define MC_STATUS_OTHER_INFO 0x01ffffff00000000 601#define MC_STATUS_COR_COUNT 0x001fffc000000000 /* If MCG_CAP_CMCI_P */ 602#define MC_STATUS_TES_STATUS 0x0060000000000000 /* If MCG_CAP_TES_P */ 603#define MC_STATUS_AR 0x0080000000000000 /* If MCG_CAP_TES_P */ 604#define MC_STATUS_S 0x0100000000000000 /* If MCG_CAP_TES_P */ 605#define MC_STATUS_PCC 0x0200000000000000 606#define MC_STATUS_ADDRV 0x0400000000000000 607#define MC_STATUS_MISCV 0x0800000000000000 608#define MC_STATUS_EN 0x1000000000000000 609#define MC_STATUS_UC 0x2000000000000000 610#define MC_STATUS_OVER 0x4000000000000000 611#define MC_STATUS_VAL 0x8000000000000000 612#define MC_MISC_RA_LSB 0x000000000000003f /* If MCG_CAP_SER_P */ 613#define MC_MISC_ADDRESS_MODE 0x00000000000001c0 /* If MCG_CAP_SER_P */ 614#define MC_CTL2_THRESHOLD 0x0000000000007fff 615#define MC_CTL2_CMCI_EN 0x0000000040000000 616 617/* 618 * The following four 3-byte registers control the non-cacheable regions. 619 * These registers must be written as three separate bytes. 620 * 621 * NCRx+0: A31-A24 of starting address 622 * NCRx+1: A23-A16 of starting address 623 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 624 * 625 * The non-cacheable region's starting address must be aligned to the 626 * size indicated by the NCR_SIZE_xx field. 627 */ 628#define NCR1 0xc4 629#define NCR2 0xc7 630#define NCR3 0xca 631#define NCR4 0xcd 632 633#define NCR_SIZE_0K 0 634#define NCR_SIZE_4K 1 635#define NCR_SIZE_8K 2 636#define NCR_SIZE_16K 3 637#define NCR_SIZE_32K 4 638#define NCR_SIZE_64K 5 639#define NCR_SIZE_128K 6 640#define NCR_SIZE_256K 7 641#define NCR_SIZE_512K 8 642#define NCR_SIZE_1M 9 643#define NCR_SIZE_2M 10 644#define NCR_SIZE_4M 11 645#define NCR_SIZE_8M 12 646#define NCR_SIZE_16M 13 647#define NCR_SIZE_32M 14 648#define NCR_SIZE_4G 15 649 650/* 651 * The address region registers are used to specify the location and 652 * size for the eight address regions. 653 * 654 * ARRx + 0: A31-A24 of start address 655 * ARRx + 1: A23-A16 of start address 656 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx 657 */ 658#define ARR0 0xc4 659#define ARR1 0xc7 660#define ARR2 0xca 661#define ARR3 0xcd 662#define ARR4 0xd0 663#define ARR5 0xd3 664#define ARR6 0xd6 665#define ARR7 0xd9 666 667#define ARR_SIZE_0K 0 668#define ARR_SIZE_4K 1 669#define ARR_SIZE_8K 2 670#define ARR_SIZE_16K 3 671#define ARR_SIZE_32K 4 672#define ARR_SIZE_64K 5 673#define ARR_SIZE_128K 6 674#define ARR_SIZE_256K 7 675#define ARR_SIZE_512K 8 676#define ARR_SIZE_1M 9 677#define ARR_SIZE_2M 10 678#define ARR_SIZE_4M 11 679#define ARR_SIZE_8M 12 680#define ARR_SIZE_16M 13 681#define ARR_SIZE_32M 14 682#define ARR_SIZE_4G 15 683 684/* 685 * The region control registers specify the attributes associated with 686 * the ARRx addres regions. 687 */ 688#define RCR0 0xdc 689#define RCR1 0xdd 690#define RCR2 0xde 691#define RCR3 0xdf 692#define RCR4 0xe0 693#define RCR5 0xe1 694#define RCR6 0xe2 695#define RCR7 0xe3 696 697#define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 698#define RCR_RCE 0x01 /* Enables caching for ARR7. */ 699#define RCR_WWO 0x02 /* Weak write ordering. */ 700#define RCR_WL 0x04 /* Weak locking. */ 701#define RCR_WG 0x08 /* Write gathering. */ 702#define RCR_WT 0x10 /* Write-through. */ 703#define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 704 705/* AMD Write Allocate Top-Of-Memory and Control Register */ 706#define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 707#define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 708#define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ 709 710/* AMD64 MSR's */ 711#define MSR_EFER 0xc0000080 /* extended features */ 712#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */ 713#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */ 714#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */ 715#define MSR_SF_MASK 0xc0000084 /* syscall flags mask */ 716#define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */ 717#define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */ 718#define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */ 719#define MSR_PERFEVSEL0 0xc0010000 720#define MSR_PERFEVSEL1 0xc0010001 721#define MSR_PERFEVSEL2 0xc0010002 722#define MSR_PERFEVSEL3 0xc0010003 723#undef MSR_PERFCTR0 724#undef MSR_PERFCTR1 725#define MSR_PERFCTR0 0xc0010004 726#define MSR_PERFCTR1 0xc0010005 727#define MSR_PERFCTR2 0xc0010006 728#define MSR_PERFCTR3 0xc0010007 729#define MSR_SYSCFG 0xc0010010 730#define MSR_HWCR 0xc0010015 731#define MSR_IORRBASE0 0xc0010016 732#define MSR_IORRMASK0 0xc0010017 733#define MSR_IORRBASE1 0xc0010018 734#define MSR_IORRMASK1 0xc0010019 735#define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */ 736#define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */ 737#define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */ 738#define MSR_MC0_CTL_MASK 0xc0010044 739 740/* VIA ACE crypto featureset: for via_feature_rng */ 741#define VIA_HAS_RNG 1 /* cpu has RNG */ 742 743/* VIA ACE crypto featureset: for via_feature_xcrypt */ 744#define VIA_HAS_AES 1 /* cpu has AES */ 745#define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ 746#define VIA_HAS_MM 4 /* cpu has RSA instructions */ 747#define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ 748 749/* Centaur Extended Feature flags */ 750#define VIA_CPUID_HAS_RNG 0x000004 751#define VIA_CPUID_DO_RNG 0x000008 752#define VIA_CPUID_HAS_ACE 0x000040 753#define VIA_CPUID_DO_ACE 0x000080 754#define VIA_CPUID_HAS_ACE2 0x000100 755#define VIA_CPUID_DO_ACE2 0x000200 756#define VIA_CPUID_HAS_PHE 0x000400 757#define VIA_CPUID_DO_PHE 0x000800 758#define VIA_CPUID_HAS_PMM 0x001000 759#define VIA_CPUID_DO_PMM 0x002000 760 761/* VIA ACE xcrypt-* instruction context control options */ 762#define VIA_CRYPT_CWLO_ROUND_M 0x0000000f 763#define VIA_CRYPT_CWLO_ALG_M 0x00000070 764#define VIA_CRYPT_CWLO_ALG_AES 0x00000000 765#define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080 766#define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000 767#define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080 768#define VIA_CRYPT_CWLO_NORMAL 0x00000000 769#define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100 770#define VIA_CRYPT_CWLO_ENCRYPT 0x00000000 771#define VIA_CRYPT_CWLO_DECRYPT 0x00000200 772#define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */ 773#define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */ 774#define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */ 775 776#endif /* !_MACHINE_SPECIALREG_H_ */ 777