hwpstate.c revision 258994
1/*- 2 * Copyright (c) 2005 Nate Lawson 3 * Copyright (c) 2004 Colin Percival 4 * Copyright (c) 2004-2005 Bruno Durcot 5 * Copyright (c) 2004 FUKUDA Nobuhiko 6 * Copyright (c) 2009 Michael Reifenberger 7 * Copyright (c) 2009 Norikatsu Shigemura 8 * Copyright (c) 2008-2009 Gen Otsuji 9 * 10 * This code is depending on kern_cpu.c, est.c, powernow.c, p4tcc.c, smist.c 11 * in various parts. The authors of these files are Nate Lawson, 12 * Colin Percival, Bruno Durcot, and FUKUDA Nobuhiko. 13 * This code contains patches by Michael Reifenberger and Norikatsu Shigemura. 14 * Thank you. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted providing that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 29 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 33 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 34 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38/* 39 * For more info: 40 * BIOS and Kernel Developer's Guide(BKDG) for AMD Family 10h Processors 41 * 31116 Rev 3.20 February 04, 2009 42 * BIOS and Kernel Developer's Guide(BKDG) for AMD Family 11h Processors 43 * 41256 Rev 3.00 - July 07, 2008 44 */ 45 46#include <sys/cdefs.h> 47__FBSDID("$FreeBSD: stable/10/sys/x86/cpufreq/hwpstate.c 258994 2013-12-05 17:57:51Z sbruno $"); 48 49#include <sys/param.h> 50#include <sys/bus.h> 51#include <sys/cpu.h> 52#include <sys/kernel.h> 53#include <sys/module.h> 54#include <sys/malloc.h> 55#include <sys/proc.h> 56#include <sys/pcpu.h> 57#include <sys/smp.h> 58#include <sys/sched.h> 59 60#include <machine/md_var.h> 61#include <machine/cputypes.h> 62#include <machine/specialreg.h> 63 64#include <contrib/dev/acpica/include/acpi.h> 65 66#include <dev/acpica/acpivar.h> 67 68#include "acpi_if.h" 69#include "cpufreq_if.h" 70 71#define MSR_AMD_10H_11H_LIMIT 0xc0010061 72#define MSR_AMD_10H_11H_CONTROL 0xc0010062 73#define MSR_AMD_10H_11H_STATUS 0xc0010063 74#define MSR_AMD_10H_11H_CONFIG 0xc0010064 75 76#define AMD_10H_11H_MAX_STATES 16 77 78/* for MSR_AMD_10H_11H_LIMIT C001_0061 */ 79#define AMD_10H_11H_GET_PSTATE_MAX_VAL(msr) (((msr) >> 4) & 0x7) 80#define AMD_10H_11H_GET_PSTATE_LIMIT(msr) (((msr)) & 0x7) 81/* for MSR_AMD_10H_11H_CONFIG 10h:C001_0064:68 / 11h:C001_0064:6B */ 82#define AMD_10H_11H_CUR_VID(msr) (((msr) >> 9) & 0x7F) 83#define AMD_10H_11H_CUR_DID(msr) (((msr) >> 6) & 0x07) 84#define AMD_10H_11H_CUR_FID(msr) ((msr) & 0x3F) 85 86#define HWPSTATE_DEBUG(dev, msg...) \ 87 do{ \ 88 if(hwpstate_verbose) \ 89 device_printf(dev, msg); \ 90 }while(0) 91 92struct hwpstate_setting { 93 int freq; /* CPU clock in Mhz or 100ths of a percent. */ 94 int volts; /* Voltage in mV. */ 95 int power; /* Power consumed in mW. */ 96 int lat; /* Transition latency in us. */ 97 int pstate_id; /* P-State id */ 98}; 99 100struct hwpstate_softc { 101 device_t dev; 102 struct hwpstate_setting hwpstate_settings[AMD_10H_11H_MAX_STATES]; 103 int cfnum; 104}; 105 106static void hwpstate_identify(driver_t *driver, device_t parent); 107static int hwpstate_probe(device_t dev); 108static int hwpstate_attach(device_t dev); 109static int hwpstate_detach(device_t dev); 110static int hwpstate_set(device_t dev, const struct cf_setting *cf); 111static int hwpstate_get(device_t dev, struct cf_setting *cf); 112static int hwpstate_settings(device_t dev, struct cf_setting *sets, int *count); 113static int hwpstate_type(device_t dev, int *type); 114static int hwpstate_shutdown(device_t dev); 115static int hwpstate_features(driver_t *driver, u_int *features); 116static int hwpstate_get_info_from_acpi_perf(device_t dev, device_t perf_dev); 117static int hwpstate_get_info_from_msr(device_t dev); 118static int hwpstate_goto_pstate(device_t dev, int pstate_id); 119 120static int hwpstate_verbose = 0; 121SYSCTL_INT(_debug, OID_AUTO, hwpstate_verbose, CTLFLAG_RW | CTLFLAG_TUN, 122 &hwpstate_verbose, 0, "Debug hwpstate"); 123TUNABLE_INT("debug.hwpstate_verbose", &hwpstate_verbose); 124 125static device_method_t hwpstate_methods[] = { 126 /* Device interface */ 127 DEVMETHOD(device_identify, hwpstate_identify), 128 DEVMETHOD(device_probe, hwpstate_probe), 129 DEVMETHOD(device_attach, hwpstate_attach), 130 DEVMETHOD(device_detach, hwpstate_detach), 131 DEVMETHOD(device_shutdown, hwpstate_shutdown), 132 133 /* cpufreq interface */ 134 DEVMETHOD(cpufreq_drv_set, hwpstate_set), 135 DEVMETHOD(cpufreq_drv_get, hwpstate_get), 136 DEVMETHOD(cpufreq_drv_settings, hwpstate_settings), 137 DEVMETHOD(cpufreq_drv_type, hwpstate_type), 138 139 /* ACPI interface */ 140 DEVMETHOD(acpi_get_features, hwpstate_features), 141 142 {0, 0} 143}; 144 145static devclass_t hwpstate_devclass; 146static driver_t hwpstate_driver = { 147 "hwpstate", 148 hwpstate_methods, 149 sizeof(struct hwpstate_softc), 150}; 151 152DRIVER_MODULE(hwpstate, cpu, hwpstate_driver, hwpstate_devclass, 0, 0); 153 154/* 155 * Go to Px-state on all cpus considering the limit. 156 */ 157static int 158hwpstate_goto_pstate(device_t dev, int pstate) 159{ 160 int i; 161 uint64_t msr; 162 int j; 163 int limit; 164 int id = pstate; 165 int error; 166 167 /* get the current pstate limit */ 168 msr = rdmsr(MSR_AMD_10H_11H_LIMIT); 169 limit = AMD_10H_11H_GET_PSTATE_LIMIT(msr); 170 if(limit > id) 171 id = limit; 172 173 /* 174 * We are going to the same Px-state on all cpus. 175 * Probably should take _PSD into account. 176 */ 177 error = 0; 178 CPU_FOREACH(i) { 179 /* Bind to each cpu. */ 180 thread_lock(curthread); 181 sched_bind(curthread, i); 182 thread_unlock(curthread); 183 HWPSTATE_DEBUG(dev, "setting P%d-state on cpu%d\n", 184 id, PCPU_GET(cpuid)); 185 /* Go To Px-state */ 186 wrmsr(MSR_AMD_10H_11H_CONTROL, id); 187 } 188 CPU_FOREACH(i) { 189 /* Bind to each cpu. */ 190 thread_lock(curthread); 191 sched_bind(curthread, i); 192 thread_unlock(curthread); 193 /* wait loop (100*100 usec is enough ?) */ 194 for(j = 0; j < 100; j++){ 195 /* get the result. not assure msr=id */ 196 msr = rdmsr(MSR_AMD_10H_11H_STATUS); 197 if(msr == id){ 198 break; 199 } 200 DELAY(100); 201 } 202 HWPSTATE_DEBUG(dev, "result P%d-state on cpu%d\n", 203 (int)msr, PCPU_GET(cpuid)); 204 if (msr != id) { 205 HWPSTATE_DEBUG(dev, "error: loop is not enough.\n"); 206 error = ENXIO; 207 } 208 } 209 thread_lock(curthread); 210 sched_unbind(curthread); 211 thread_unlock(curthread); 212 return (error); 213} 214 215static int 216hwpstate_set(device_t dev, const struct cf_setting *cf) 217{ 218 struct hwpstate_softc *sc; 219 struct hwpstate_setting *set; 220 int i; 221 222 if (cf == NULL) 223 return (EINVAL); 224 sc = device_get_softc(dev); 225 set = sc->hwpstate_settings; 226 for (i = 0; i < sc->cfnum; i++) 227 if (CPUFREQ_CMP(cf->freq, set[i].freq)) 228 break; 229 if (i == sc->cfnum) 230 return (EINVAL); 231 232 return (hwpstate_goto_pstate(dev, set[i].pstate_id)); 233} 234 235static int 236hwpstate_get(device_t dev, struct cf_setting *cf) 237{ 238 struct hwpstate_softc *sc; 239 struct hwpstate_setting set; 240 uint64_t msr; 241 242 sc = device_get_softc(dev); 243 if (cf == NULL) 244 return (EINVAL); 245 msr = rdmsr(MSR_AMD_10H_11H_STATUS); 246 if(msr >= sc->cfnum) 247 return (EINVAL); 248 set = sc->hwpstate_settings[msr]; 249 250 cf->freq = set.freq; 251 cf->volts = set.volts; 252 cf->power = set.power; 253 cf->lat = set.lat; 254 cf->dev = dev; 255 return (0); 256} 257 258static int 259hwpstate_settings(device_t dev, struct cf_setting *sets, int *count) 260{ 261 struct hwpstate_softc *sc; 262 struct hwpstate_setting set; 263 int i; 264 265 if (sets == NULL || count == NULL) 266 return (EINVAL); 267 sc = device_get_softc(dev); 268 if (*count < sc->cfnum) 269 return (E2BIG); 270 for (i = 0; i < sc->cfnum; i++, sets++) { 271 set = sc->hwpstate_settings[i]; 272 sets->freq = set.freq; 273 sets->volts = set.volts; 274 sets->power = set.power; 275 sets->lat = set.lat; 276 sets->dev = dev; 277 } 278 *count = sc->cfnum; 279 280 return (0); 281} 282 283static int 284hwpstate_type(device_t dev, int *type) 285{ 286 287 if (type == NULL) 288 return (EINVAL); 289 290 *type = CPUFREQ_TYPE_ABSOLUTE; 291 return (0); 292} 293 294static void 295hwpstate_identify(driver_t *driver, device_t parent) 296{ 297 298 if (device_find_child(parent, "hwpstate", -1) != NULL) 299 return; 300 301 if (cpu_vendor_id != CPU_VENDOR_AMD || CPUID_TO_FAMILY(cpu_id) < 0x10) 302 return; 303 304 /* 305 * Check if hardware pstate enable bit is set. 306 */ 307 if ((amd_pminfo & AMDPM_HW_PSTATE) == 0) { 308 HWPSTATE_DEBUG(parent, "hwpstate enable bit is not set.\n"); 309 return; 310 } 311 312 if (resource_disabled("hwpstate", 0)) 313 return; 314 315 if (BUS_ADD_CHILD(parent, 10, "hwpstate", -1) == NULL) 316 device_printf(parent, "hwpstate: add child failed\n"); 317} 318 319static int 320hwpstate_probe(device_t dev) 321{ 322 struct hwpstate_softc *sc; 323 device_t perf_dev; 324 uint64_t msr; 325 int error, type; 326 327 /* 328 * Only hwpstate0. 329 * It goes well with acpi_throttle. 330 */ 331 if (device_get_unit(dev) != 0) 332 return (ENXIO); 333 334 sc = device_get_softc(dev); 335 sc->dev = dev; 336 337 /* 338 * Check if acpi_perf has INFO only flag. 339 */ 340 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1); 341 error = TRUE; 342 if (perf_dev && device_is_attached(perf_dev)) { 343 error = CPUFREQ_DRV_TYPE(perf_dev, &type); 344 if (error == 0) { 345 if ((type & CPUFREQ_FLAG_INFO_ONLY) == 0) { 346 /* 347 * If acpi_perf doesn't have INFO_ONLY flag, 348 * it will take care of pstate transitions. 349 */ 350 HWPSTATE_DEBUG(dev, "acpi_perf will take care of pstate transitions.\n"); 351 return (ENXIO); 352 } else { 353 /* 354 * If acpi_perf has INFO_ONLY flag, (_PCT has FFixedHW) 355 * we can get _PSS info from acpi_perf 356 * without going into ACPI. 357 */ 358 HWPSTATE_DEBUG(dev, "going to fetch info from acpi_perf\n"); 359 error = hwpstate_get_info_from_acpi_perf(dev, perf_dev); 360 } 361 } 362 } 363 364 if (error == 0) { 365 /* 366 * Now we get _PSS info from acpi_perf without error. 367 * Let's check it. 368 */ 369 msr = rdmsr(MSR_AMD_10H_11H_LIMIT); 370 if (sc->cfnum != 1 + AMD_10H_11H_GET_PSTATE_MAX_VAL(msr)) { 371 HWPSTATE_DEBUG(dev, "msr and acpi _PSS count mismatch.\n"); 372 error = TRUE; 373 } 374 } 375 376 /* 377 * If we cannot get info from acpi_perf, 378 * Let's get info from MSRs. 379 */ 380 if (error) 381 error = hwpstate_get_info_from_msr(dev); 382 if (error) 383 return (error); 384 385 device_set_desc(dev, "Cool`n'Quiet 2.0"); 386 return (0); 387} 388 389static int 390hwpstate_attach(device_t dev) 391{ 392 393 return (cpufreq_register(dev)); 394} 395 396static int 397hwpstate_get_info_from_msr(device_t dev) 398{ 399 struct hwpstate_softc *sc; 400 struct hwpstate_setting *hwpstate_set; 401 uint64_t msr; 402 int family, i, fid, did; 403 404 family = CPUID_TO_FAMILY(cpu_id); 405 sc = device_get_softc(dev); 406 /* Get pstate count */ 407 msr = rdmsr(MSR_AMD_10H_11H_LIMIT); 408 sc->cfnum = 1 + AMD_10H_11H_GET_PSTATE_MAX_VAL(msr); 409 hwpstate_set = sc->hwpstate_settings; 410 for (i = 0; i < sc->cfnum; i++) { 411 msr = rdmsr(MSR_AMD_10H_11H_CONFIG + i); 412 if ((msr & ((uint64_t)1 << 63)) != ((uint64_t)1 << 63)) { 413 HWPSTATE_DEBUG(dev, "msr is not valid.\n"); 414 return (ENXIO); 415 } 416 did = AMD_10H_11H_CUR_DID(msr); 417 fid = AMD_10H_11H_CUR_FID(msr); 418 switch(family) { 419 case 0x11: 420 /* fid/did to frequency */ 421 hwpstate_set[i].freq = 100 * (fid + 0x08) / (1 << did); 422 break; 423 case 0x10: 424 /* fid/did to frequency */ 425 hwpstate_set[i].freq = 100 * (fid + 0x10) / (1 << did); 426 break; 427 default: 428 HWPSTATE_DEBUG(dev, "get_info_from_msr: AMD family %d CPU's are not implemented yet. sorry.\n", family); 429 return (ENXIO); 430 break; 431 } 432 hwpstate_set[i].pstate_id = i; 433 /* There was volts calculation, but deleted it. */ 434 hwpstate_set[i].volts = CPUFREQ_VAL_UNKNOWN; 435 hwpstate_set[i].power = CPUFREQ_VAL_UNKNOWN; 436 hwpstate_set[i].lat = CPUFREQ_VAL_UNKNOWN; 437 } 438 return (0); 439} 440 441static int 442hwpstate_get_info_from_acpi_perf(device_t dev, device_t perf_dev) 443{ 444 struct hwpstate_softc *sc; 445 struct cf_setting *perf_set; 446 struct hwpstate_setting *hwpstate_set; 447 int count, error, i; 448 449 perf_set = malloc(MAX_SETTINGS * sizeof(*perf_set), M_TEMP, M_NOWAIT); 450 if (perf_set == NULL) { 451 HWPSTATE_DEBUG(dev, "nomem\n"); 452 return (ENOMEM); 453 } 454 /* 455 * Fetch settings from acpi_perf. 456 * Now it is attached, and has info only flag. 457 */ 458 count = MAX_SETTINGS; 459 error = CPUFREQ_DRV_SETTINGS(perf_dev, perf_set, &count); 460 if (error) { 461 HWPSTATE_DEBUG(dev, "error: CPUFREQ_DRV_SETTINGS.\n"); 462 goto out; 463 } 464 sc = device_get_softc(dev); 465 sc->cfnum = count; 466 hwpstate_set = sc->hwpstate_settings; 467 for (i = 0; i < count; i++) { 468 if (i == perf_set[i].spec[0]) { 469 hwpstate_set[i].pstate_id = i; 470 hwpstate_set[i].freq = perf_set[i].freq; 471 hwpstate_set[i].volts = perf_set[i].volts; 472 hwpstate_set[i].power = perf_set[i].power; 473 hwpstate_set[i].lat = perf_set[i].lat; 474 } else { 475 HWPSTATE_DEBUG(dev, "ACPI _PSS object mismatch.\n"); 476 error = ENXIO; 477 goto out; 478 } 479 } 480out: 481 if (perf_set) 482 free(perf_set, M_TEMP); 483 return (error); 484} 485 486static int 487hwpstate_detach(device_t dev) 488{ 489 490 hwpstate_goto_pstate(dev, 0); 491 return (cpufreq_unregister(dev)); 492} 493 494static int 495hwpstate_shutdown(device_t dev) 496{ 497 498 /* hwpstate_goto_pstate(dev, 0); */ 499 return (0); 500} 501 502static int 503hwpstate_features(driver_t *driver, u_int *features) 504{ 505 506 /* Notify the ACPI CPU that we support direct access to MSRs */ 507 *features = ACPI_CAP_PERF_MSRS; 508 return (0); 509} 510