ata_macio.c revision 256857
1/*- 2 * Copyright 2002 by Peter Grehan. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. The name of the author may not be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: stable/10/sys/powerpc/powermac/ata_macio.c 256857 2013-10-21 19:11:15Z andreast $"); 30 31/* 32 * Mac-io ATA controller 33 */ 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/kernel.h> 37#include <sys/module.h> 38#include <sys/bus.h> 39#include <sys/malloc.h> 40#include <sys/sema.h> 41#include <sys/taskqueue.h> 42#include <vm/uma.h> 43#include <machine/stdarg.h> 44#include <machine/resource.h> 45#include <machine/bus.h> 46#include <sys/rman.h> 47#include <sys/ata.h> 48#include <dev/ata/ata-all.h> 49#include <ata_if.h> 50 51#include <dev/ofw/ofw_bus.h> 52 53#include "ata_dbdma.h" 54 55/* 56 * Offset to control registers from base 57 */ 58#define ATA_MACIO_ALTOFFSET 0x160 59 60/* 61 * Define the gap between registers 62 */ 63#define ATA_MACIO_REGGAP 16 64 65/* 66 * Whether or not to bind to the DBDMA IRQ 67 */ 68#define USE_DBDMA_IRQ 0 69 70/* 71 * Timing register 72 */ 73#define ATA_MACIO_TIMINGREG 0x200 74 75#define ATA_TIME_TO_TICK(rev,time) howmany(time, (rev == 4) ? 15 : 30) 76#define PIO_REC_OFFSET 4 77#define PIO_REC_MIN 1 78#define PIO_ACT_MIN 1 79#define DMA_REC_OFFSET 1 80#define DMA_REC_MIN 1 81#define DMA_ACT_MIN 1 82 83struct ide_timings { 84 int cycle; /* minimum cycle time [ns] */ 85 int active; /* minimum command active time [ns] */ 86}; 87 88static const struct ide_timings pio_timings[5] = { 89 { 600, 180 }, /* PIO 0 */ 90 { 390, 150 }, /* PIO 1 */ 91 { 240, 105 }, /* PIO 2 */ 92 { 180, 90 }, /* PIO 3 */ 93 { 120, 75 } /* PIO 4 */ 94}; 95 96static const struct ide_timings dma_timings[3] = { 97 { 480, 240 }, /* WDMA 0 */ 98 { 165, 90 }, /* WDMA 1 */ 99 { 120, 75 } /* WDMA 2 */ 100}; 101 102static const struct ide_timings udma_timings[5] = { 103 { 120, 180 }, /* UDMA 0 */ 104 { 90, 150 }, /* UDMA 1 */ 105 { 60, 120 }, /* UDMA 2 */ 106 { 45, 90 }, /* UDMA 3 */ 107 { 30, 90 } /* UDMA 4 */ 108}; 109 110/* 111 * Define the macio ata bus attachment. 112 */ 113static int ata_macio_probe(device_t dev); 114static int ata_macio_setmode(device_t dev, int target, int mode); 115static int ata_macio_attach(device_t dev); 116static int ata_macio_begin_transaction(struct ata_request *request); 117 118static device_method_t ata_macio_methods[] = { 119 /* Device interface */ 120 DEVMETHOD(device_probe, ata_macio_probe), 121 DEVMETHOD(device_attach, ata_macio_attach), 122 123 /* ATA interface */ 124 DEVMETHOD(ata_setmode, ata_macio_setmode), 125 DEVMETHOD_END 126}; 127 128struct ata_macio_softc { 129 struct ata_dbdma_channel sc_ch; 130 131 int rev; 132 int max_mode; 133 struct resource *sc_mem; 134 135 uint32_t udmaconf[2]; 136 uint32_t wdmaconf[2]; 137 uint32_t pioconf[2]; 138}; 139 140static driver_t ata_macio_driver = { 141 "ata", 142 ata_macio_methods, 143 sizeof(struct ata_macio_softc), 144}; 145 146DRIVER_MODULE(ata, macio, ata_macio_driver, ata_devclass, NULL, NULL); 147MODULE_DEPEND(ata, ata, 1, 1, 1); 148 149static int 150ata_macio_probe(device_t dev) 151{ 152 const char *type = ofw_bus_get_type(dev); 153 const char *name = ofw_bus_get_name(dev); 154 struct ata_macio_softc *sc; 155 156 if (strcmp(type, "ata") != 0 && 157 strcmp(type, "ide") != 0) 158 return (ENXIO); 159 160 sc = device_get_softc(dev); 161 bzero(sc, sizeof(struct ata_macio_softc)); 162 163 if (strcmp(name,"ata-4") == 0) { 164 device_set_desc(dev,"Apple MacIO Ultra ATA Controller"); 165 sc->rev = 4; 166 sc->max_mode = ATA_UDMA4; 167 } else { 168 device_set_desc(dev,"Apple MacIO ATA Controller"); 169 sc->rev = 3; 170 sc->max_mode = ATA_WDMA2; 171 } 172 173 return (ata_probe(dev)); 174} 175 176static int 177ata_macio_attach(device_t dev) 178{ 179 struct ata_macio_softc *sc = device_get_softc(dev); 180 uint32_t timingreg; 181 struct ata_channel *ch; 182 int rid, i; 183 184 /* 185 * Allocate resources 186 */ 187 188 rid = 0; 189 ch = &sc->sc_ch.sc_ch; 190 sc->sc_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 191 RF_ACTIVE); 192 if (sc->sc_mem == NULL) { 193 device_printf(dev, "could not allocate memory\n"); 194 return (ENXIO); 195 } 196 197 /* 198 * Set up the resource vectors 199 */ 200 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 201 ch->r_io[i].res = sc->sc_mem; 202 ch->r_io[i].offset = i * ATA_MACIO_REGGAP; 203 } 204 ch->r_io[ATA_CONTROL].res = sc->sc_mem; 205 ch->r_io[ATA_CONTROL].offset = ATA_MACIO_ALTOFFSET; 206 ata_default_registers(dev); 207 208 ch->unit = 0; 209 ch->flags |= ATA_USE_16BIT | ATA_NO_ATAPI_DMA; 210 ata_generic_hw(dev); 211 212#if USE_DBDMA_IRQ 213 int dbdma_irq_rid = 1; 214 struct resource *dbdma_irq; 215 void *cookie; 216#endif 217 218 /* Init DMA engine */ 219 220 sc->sc_ch.dbdma_rid = 1; 221 sc->sc_ch.dbdma_regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 222 &sc->sc_ch.dbdma_rid, RF_ACTIVE); 223 224 ata_dbdma_dmainit(dev); 225 226 /* Configure initial timings */ 227 timingreg = bus_read_4(sc->sc_mem, ATA_MACIO_TIMINGREG); 228 if (sc->rev == 4) { 229 sc->udmaconf[0] = sc->udmaconf[1] = timingreg & 0x1ff00000; 230 sc->wdmaconf[0] = sc->wdmaconf[1] = timingreg & 0x001ffc00; 231 sc->pioconf[0] = sc->pioconf[1] = timingreg & 0x000003ff; 232 } else { 233 sc->udmaconf[0] = sc->udmaconf[1] = 0; 234 sc->wdmaconf[0] = sc->wdmaconf[1] = timingreg & 0xfffff800; 235 sc->pioconf[0] = sc->pioconf[1] = timingreg & 0x000007ff; 236 } 237 238#if USE_DBDMA_IRQ 239 /* Bind to DBDMA interrupt as well */ 240 241 if ((dbdma_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 242 &dbdma_irq_rid, RF_SHAREABLE | RF_ACTIVE)) != NULL) { 243 bus_setup_intr(dev, dbdma_irq, ATA_INTR_FLAGS, NULL, 244 (driver_intr_t *)ata_interrupt, sc,&cookie); 245 } 246#endif 247 248 /* Set begin_transaction */ 249 sc->sc_ch.sc_ch.hw.begin_transaction = ata_macio_begin_transaction; 250 251 return ata_attach(dev); 252} 253 254static int 255ata_macio_setmode(device_t dev, int target, int mode) 256{ 257 struct ata_macio_softc *sc = device_get_softc(dev); 258 259 int min_cycle = 0, min_active = 0; 260 int cycle_tick = 0, act_tick = 0, inact_tick = 0, half_tick; 261 262 mode = min(mode, sc->max_mode); 263 264 if ((mode & ATA_DMA_MASK) == ATA_UDMA0) { 265 min_cycle = udma_timings[mode & ATA_MODE_MASK].cycle; 266 min_active = udma_timings[mode & ATA_MODE_MASK].active; 267 268 cycle_tick = ATA_TIME_TO_TICK(sc->rev,min_cycle); 269 act_tick = ATA_TIME_TO_TICK(sc->rev,min_active); 270 271 /* mask: 0x1ff00000 */ 272 sc->udmaconf[target] = 273 (cycle_tick << 21) | (act_tick << 25) | 0x100000; 274 } else if ((mode & ATA_DMA_MASK) == ATA_WDMA0) { 275 min_cycle = dma_timings[mode & ATA_MODE_MASK].cycle; 276 min_active = dma_timings[mode & ATA_MODE_MASK].active; 277 278 cycle_tick = ATA_TIME_TO_TICK(sc->rev,min_cycle); 279 act_tick = ATA_TIME_TO_TICK(sc->rev,min_active); 280 281 if (sc->rev == 4) { 282 inact_tick = cycle_tick - act_tick; 283 /* mask: 0x001ffc00 */ 284 sc->wdmaconf[target] = 285 (act_tick << 10) | (inact_tick << 15); 286 } else { 287 inact_tick = cycle_tick - act_tick - DMA_REC_OFFSET; 288 if (inact_tick < DMA_REC_MIN) 289 inact_tick = DMA_REC_MIN; 290 half_tick = 0; /* XXX */ 291 292 /* mask: 0xfffff800 */ 293 sc->wdmaconf[target] = (half_tick << 21) 294 | (inact_tick << 16) | (act_tick << 11); 295 } 296 } else { 297 min_cycle = 298 pio_timings[(mode & ATA_MODE_MASK) - ATA_PIO0].cycle; 299 min_active = 300 pio_timings[(mode & ATA_MODE_MASK) - ATA_PIO0].active; 301 302 cycle_tick = ATA_TIME_TO_TICK(sc->rev,min_cycle); 303 act_tick = ATA_TIME_TO_TICK(sc->rev,min_active); 304 305 if (sc->rev == 4) { 306 inact_tick = cycle_tick - act_tick; 307 308 /* mask: 0x000003ff */ 309 sc->pioconf[target] = 310 (inact_tick << 5) | act_tick; 311 } else { 312 if (act_tick < PIO_ACT_MIN) 313 act_tick = PIO_ACT_MIN; 314 315 inact_tick = cycle_tick - act_tick - PIO_REC_OFFSET; 316 if (inact_tick < PIO_REC_MIN) 317 inact_tick = PIO_REC_MIN; 318 319 /* mask: 0x000007ff */ 320 sc->pioconf[target] = 321 (inact_tick << 5) | act_tick; 322 } 323 } 324 325 return (mode); 326} 327 328static int 329ata_macio_begin_transaction(struct ata_request *request) 330{ 331 struct ata_macio_softc *sc = device_get_softc(request->parent); 332 333 bus_write_4(sc->sc_mem, ATA_MACIO_TIMINGREG, 334 sc->udmaconf[request->unit] | sc->wdmaconf[request->unit] 335 | sc->pioconf[request->unit]); 336 337 return ata_begin_transaction(request); 338} 339