dbdma.h revision 260674
1275970Scy/*- 2275970Scy * Copyright (c) 2008 Nathan Whitehorn 3275970Scy * All rights reserved 4275970Scy * 5275970Scy * Redistribution and use in source and binary forms, with or without 6275970Scy * modification, are permitted provided that the following conditions 7275970Scy * are met: 8275970Scy * 1. Redistributions of source code must retain the above copyright 9275970Scy * notice, this list of conditions and the following disclaimer. 10275970Scy * 2. Redistributions in binary form must reproduce the above copyright 11275970Scy * notice, this list of conditions and the following disclaimer in the 12275970Scy * documentation and/or other materials provided with the distribution. 13275970Scy * 14275970Scy * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15275970Scy * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16275970Scy * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17285612Sdelphij * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18275970Scy * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19275970Scy * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20275970Scy * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21275970Scy * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22275970Scy * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23275970Scy * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24275970Scy * SUCH DAMAGE. 25275970Scy * 26275970Scy * $FreeBSD: stable/10/sys/powerpc/include/dbdma.h 260674 2014-01-15 06:17:15Z jhibbits $ 27275970Scy */ 28275970Scy 29275970Scy#ifndef _MACHINE_DBDMA_H_ 30275970Scy#define _MACHINE_DBDMA_H_ 31275970Scy 32275970Scy#include <sys/param.h> 33275970Scy#include <machine/bus.h> 34275970Scy 35275970Scy/* 36275970Scy * Apple's DBDMA (Descriptor-based DMA) interface is a common DMA engine 37275970Scy * used by a variety of custom Apple ASICs. It is described in the CHRP 38275970Scy * specification and in the book Macintosh Technology in the Common 39275970Scy * Hardware Reference Platform, copyright 1995 Apple Computer. 40275970Scy */ 41275970Scy 42275970Scy/* DBDMA Command Values */ 43275970Scy 44275970Scyenum { 45275970Scy DBDMA_OUTPUT_MORE = 0, 46275970Scy DBDMA_OUTPUT_LAST = 1, 47275970Scy DBDMA_INPUT_MORE = 2, 48275970Scy DBDMA_INPUT_LAST = 3, 49275970Scy 50275970Scy DBDMA_STORE_QUAD = 4, 51275970Scy DBDMA_LOAD_QUAD = 5, 52275970Scy DBDMA_NOP = 6, 53275970Scy DBDMA_STOP = 7 54275970Scy}; 55275970Scy 56275970Scy/* These codes are for the interrupt, branch, and wait flags */ 57275970Scy 58275970Scyenum { 59275970Scy DBDMA_NEVER = 0, 60275970Scy DBDMA_COND_TRUE = 1, 61275970Scy DBDMA_COND_FALSE = 2, 62275970Scy DBDMA_ALWAYS = 3 63275970Scy}; 64275970Scy 65275970Scy/* Channel status bits */ 66275970Scy#define DBDMA_STATUS_RUN (0x01 << 15) 67275970Scy#define DBDMA_STATUS_PAUSE (0x01 << 14) 68275970Scy#define DBDMA_STATUS_FLUSH (0x01 << 13) 69275970Scy#define DBDMA_STATUS_WAKE (0x01 << 12) 70275970Scy#define DBDMA_STATUS_DEAD (0x01 << 11) 71275970Scy#define DBDMA_STATUS_ACTIVE (0x01 << 10) 72275970Scy 73275970Scy/* Set by hardware if a branch was taken */ 74275970Scy#define DBDMA_STATUS_BRANCH 8 75275970Scy 76275970Scystruct dbdma_command; 77275970Scytypedef struct dbdma_command dbdma_command_t; 78275970Scystruct dbdma_channel; 79275970Scytypedef struct dbdma_channel dbdma_channel_t; 80275970Scy 81275970Scyint dbdma_allocate_channel(struct resource *dbdma_regs, u_int offset, 82275970Scy bus_dma_tag_t parent_dma, int slots, dbdma_channel_t **chan); 83275970Scy 84275970Scyint dbdma_resize_channel(dbdma_channel_t *chan, int newslots); 85275970Scyint dbdma_free_channel(dbdma_channel_t *chan); 86275970Scy 87275970Scyvoid dbdma_run(dbdma_channel_t *chan); 88275970Scyvoid dbdma_stop(dbdma_channel_t *chan); 89275970Scyvoid dbdma_reset(dbdma_channel_t *chan); 90275970Scyvoid dbdma_set_current_cmd(dbdma_channel_t *chan, int slot); 91275970Scy 92275970Scyvoid dbdma_pause(dbdma_channel_t *chan); 93275970Scyvoid dbdma_wake(dbdma_channel_t *chan); 94275970Scy 95275970Scy/* 96275970Scy * DBDMA uses a 16 bit channel control register to describe the current 97275970Scy * state of DMA on the channel. The high-order bits (8-15) contain information 98275970Scy * on the run state and are listed in the DBDMA_STATUS_* constants above. These 99275970Scy * are manipulated with the dbdma_run/stop/reset() routines above. 100275970Scy * 101275970Scy * The low order bits (0-7) are device dependent status bits. These can be set 102275970Scy * and read by both hardware and software. The mask is the set of bits to 103275970Scy * modify; if mask is 0x03 and value is 0, the lowest order 2 bits will be 104275970Scy * zeroed. 105275970Scy */ 106275970Scy 107275970Scyuint16_t dbdma_get_chan_status(dbdma_channel_t *chan); 108275970Scy 109275970Scyuint8_t dbdma_get_device_status(dbdma_channel_t *chan); 110275970Scyvoid dbdma_set_device_status(dbdma_channel_t *chan, uint8_t mask, 111275970Scy uint8_t value); 112275970Scy 113275970Scy/* 114275970Scy * Each DBDMA command word has the current channel status register and the 115275970Scy * number of residual bytes (requested - actually transferred) written to it 116275970Scy * at time of command completion. 117275970Scy */ 118275970Scy 119275970Scyuint16_t dbdma_get_cmd_status(dbdma_channel_t *chan, int slot); 120275970Scyuint16_t dbdma_get_residuals(dbdma_channel_t *chan, int slot); 121275970Scy 122275970Scyvoid dbdma_clear_cmd_status(dbdma_channel_t *chan, int slot); 123275970Scy 124275970Scy/* 125275970Scy * The interrupt/branch/wait selector let you specify a set of values 126275970Scy * of the device dependent status bits that will cause intterupt/branch/wait 127275970Scy * conditions to be taken if the flags for these are set to one of the 128275970Scy * DBDMA_COND_* values. 129275970Scy * 130275970Scy * The condition is considered true if (status & mask) == value. 131275970Scy */ 132275970Scy 133275970Scyvoid dbdma_set_interrupt_selector(dbdma_channel_t *chan, uint8_t mask, 134275970Scy uint8_t value); 135275970Scyvoid dbdma_set_branch_selector(dbdma_channel_t *chan, uint8_t mask, 136275970Scy uint8_t value); 137275970Scyvoid dbdma_set_wait_selector(dbdma_channel_t *chan, uint8_t mask, 138275970Scy uint8_t value); 139275970Scy 140275970Scyvoid dbdma_insert_command(dbdma_channel_t *chan, int slot, int command, 141275970Scy int stream, bus_addr_t data, size_t count, uint8_t interrupt, 142275970Scy uint8_t branch, uint8_t wait, uint32_t branch_slot); 143275970Scy 144275970Scyvoid dbdma_insert_stop(dbdma_channel_t *chan, int slot); 145275970Scyvoid dbdma_insert_nop(dbdma_channel_t *chan, int slot); 146275970Scyvoid dbdma_insert_branch(dbdma_channel_t *chan, int slot, int to_slot); 147275970Scy 148275970Scyvoid dbdma_sync_commands(dbdma_channel_t *chan, bus_dmasync_op_t op); 149275970Scy 150275970Scyvoid dbdma_save_state(dbdma_channel_t *chan); 151275970Scyvoid dbdma_restore_state(dbdma_channel_t *chan); 152275970Scy 153275970Scy#endif /* _MACHINE_DBDMA_H_ */ 154275970Scy