pmap.c revision 266001
1/*- 2 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * Some hw specific parts of this pmap were derived or influenced 27 * by NetBSD's ibm4xx pmap module. More generic code is shared with 28 * a few other pmap modules from the FreeBSD tree. 29 */ 30 31 /* 32 * VM layout notes: 33 * 34 * Kernel and user threads run within one common virtual address space 35 * defined by AS=0. 36 * 37 * Virtual address space layout: 38 * ----------------------------- 39 * 0x0000_0000 - 0xafff_ffff : user process 40 * 0xb000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.) 41 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved 42 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc. 43 * 0xc100_0000 - 0xfeef_ffff : KVA 44 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy 45 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs 46 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0 47 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space 48 * 0xfef0_0000 - 0xffff_ffff : I/O devices region 49 */ 50 51#include <sys/cdefs.h> 52__FBSDID("$FreeBSD: stable/10/sys/powerpc/booke/pmap.c 266001 2014-05-14 03:09:37Z ian $"); 53 54#include <sys/param.h> 55#include <sys/malloc.h> 56#include <sys/ktr.h> 57#include <sys/proc.h> 58#include <sys/user.h> 59#include <sys/queue.h> 60#include <sys/systm.h> 61#include <sys/kernel.h> 62#include <sys/linker.h> 63#include <sys/msgbuf.h> 64#include <sys/lock.h> 65#include <sys/mutex.h> 66#include <sys/rwlock.h> 67#include <sys/sched.h> 68#include <sys/smp.h> 69#include <sys/vmmeter.h> 70 71#include <vm/vm.h> 72#include <vm/vm_page.h> 73#include <vm/vm_kern.h> 74#include <vm/vm_pageout.h> 75#include <vm/vm_extern.h> 76#include <vm/vm_object.h> 77#include <vm/vm_param.h> 78#include <vm/vm_map.h> 79#include <vm/vm_pager.h> 80#include <vm/uma.h> 81 82#include <machine/cpu.h> 83#include <machine/pcb.h> 84#include <machine/platform.h> 85 86#include <machine/tlb.h> 87#include <machine/spr.h> 88#include <machine/md_var.h> 89#include <machine/mmuvar.h> 90#include <machine/pmap.h> 91#include <machine/pte.h> 92 93#include "mmu_if.h" 94 95#ifdef DEBUG 96#define debugf(fmt, args...) printf(fmt, ##args) 97#else 98#define debugf(fmt, args...) 99#endif 100 101#define TODO panic("%s: not implemented", __func__); 102 103extern int dumpsys_minidump; 104 105extern unsigned char _etext[]; 106extern unsigned char _end[]; 107 108extern uint32_t *bootinfo; 109 110#ifdef SMP 111extern uint32_t bp_ntlb1s; 112#endif 113 114vm_paddr_t kernload; 115vm_offset_t kernstart; 116vm_size_t kernsize; 117 118/* Message buffer and tables. */ 119static vm_offset_t data_start; 120static vm_size_t data_end; 121 122/* Phys/avail memory regions. */ 123static struct mem_region *availmem_regions; 124static int availmem_regions_sz; 125static struct mem_region *physmem_regions; 126static int physmem_regions_sz; 127 128/* Reserved KVA space and mutex for mmu_booke_zero_page. */ 129static vm_offset_t zero_page_va; 130static struct mtx zero_page_mutex; 131 132static struct mtx tlbivax_mutex; 133 134/* 135 * Reserved KVA space for mmu_booke_zero_page_idle. This is used 136 * by idle thred only, no lock required. 137 */ 138static vm_offset_t zero_page_idle_va; 139 140/* Reserved KVA space and mutex for mmu_booke_copy_page. */ 141static vm_offset_t copy_page_src_va; 142static vm_offset_t copy_page_dst_va; 143static struct mtx copy_page_mutex; 144 145/**************************************************************************/ 146/* PMAP */ 147/**************************************************************************/ 148 149static void mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t, 150 vm_prot_t, boolean_t); 151 152unsigned int kptbl_min; /* Index of the first kernel ptbl. */ 153unsigned int kernel_ptbls; /* Number of KVA ptbls. */ 154 155/* 156 * If user pmap is processed with mmu_booke_remove and the resident count 157 * drops to 0, there are no more pages to remove, so we need not continue. 158 */ 159#define PMAP_REMOVE_DONE(pmap) \ 160 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0) 161 162extern void tid_flush(tlbtid_t); 163 164/**************************************************************************/ 165/* TLB and TID handling */ 166/**************************************************************************/ 167 168/* Translation ID busy table */ 169static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1]; 170 171/* 172 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500 173 * core revisions and should be read from h/w registers during early config. 174 */ 175uint32_t tlb0_entries; 176uint32_t tlb0_ways; 177uint32_t tlb0_entries_per_way; 178 179#define TLB0_ENTRIES (tlb0_entries) 180#define TLB0_WAYS (tlb0_ways) 181#define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way) 182 183#define TLB1_ENTRIES 16 184 185/* In-ram copy of the TLB1 */ 186static tlb_entry_t tlb1[TLB1_ENTRIES]; 187 188/* Next free entry in the TLB1 */ 189static unsigned int tlb1_idx; 190static vm_offset_t tlb1_map_base = VM_MAX_KERNEL_ADDRESS; 191 192static tlbtid_t tid_alloc(struct pmap *); 193 194static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t); 195 196static int tlb1_set_entry(vm_offset_t, vm_offset_t, vm_size_t, uint32_t); 197static void tlb1_write_entry(unsigned int); 198static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *); 199static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t); 200 201static vm_size_t tsize2size(unsigned int); 202static unsigned int size2tsize(vm_size_t); 203static unsigned int ilog2(unsigned int); 204 205static void set_mas4_defaults(void); 206 207static inline void tlb0_flush_entry(vm_offset_t); 208static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int); 209 210/**************************************************************************/ 211/* Page table management */ 212/**************************************************************************/ 213 214static struct rwlock_padalign pvh_global_lock; 215 216/* Data for the pv entry allocation mechanism */ 217static uma_zone_t pvzone; 218static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 219 220#define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */ 221 222#ifndef PMAP_SHPGPERPROC 223#define PMAP_SHPGPERPROC 200 224#endif 225 226static void ptbl_init(void); 227static struct ptbl_buf *ptbl_buf_alloc(void); 228static void ptbl_buf_free(struct ptbl_buf *); 229static void ptbl_free_pmap_ptbl(pmap_t, pte_t *); 230 231static pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int); 232static void ptbl_free(mmu_t, pmap_t, unsigned int); 233static void ptbl_hold(mmu_t, pmap_t, unsigned int); 234static int ptbl_unhold(mmu_t, pmap_t, unsigned int); 235 236static vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t); 237static pte_t *pte_find(mmu_t, pmap_t, vm_offset_t); 238static void pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t); 239static int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t); 240 241static pv_entry_t pv_alloc(void); 242static void pv_free(pv_entry_t); 243static void pv_insert(pmap_t, vm_offset_t, vm_page_t); 244static void pv_remove(pmap_t, vm_offset_t, vm_page_t); 245 246/* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */ 247#define PTBL_BUFS (128 * 16) 248 249struct ptbl_buf { 250 TAILQ_ENTRY(ptbl_buf) link; /* list link */ 251 vm_offset_t kva; /* va of mapping */ 252}; 253 254/* ptbl free list and a lock used for access synchronization. */ 255static TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist; 256static struct mtx ptbl_buf_freelist_lock; 257 258/* Base address of kva space allocated fot ptbl bufs. */ 259static vm_offset_t ptbl_buf_pool_vabase; 260 261/* Pointer to ptbl_buf structures. */ 262static struct ptbl_buf *ptbl_bufs; 263 264void pmap_bootstrap_ap(volatile uint32_t *); 265 266/* 267 * Kernel MMU interface 268 */ 269static void mmu_booke_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 270static void mmu_booke_clear_modify(mmu_t, vm_page_t); 271static void mmu_booke_copy(mmu_t, pmap_t, pmap_t, vm_offset_t, 272 vm_size_t, vm_offset_t); 273static void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t); 274static void mmu_booke_copy_pages(mmu_t, vm_page_t *, 275 vm_offset_t, vm_page_t *, vm_offset_t, int); 276static void mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, 277 vm_prot_t, boolean_t); 278static void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 279 vm_page_t, vm_prot_t); 280static void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, 281 vm_prot_t); 282static vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t); 283static vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t, 284 vm_prot_t); 285static void mmu_booke_init(mmu_t); 286static boolean_t mmu_booke_is_modified(mmu_t, vm_page_t); 287static boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 288static boolean_t mmu_booke_is_referenced(mmu_t, vm_page_t); 289static int mmu_booke_ts_referenced(mmu_t, vm_page_t); 290static vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, 291 int); 292static int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t, 293 vm_paddr_t *); 294static void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t, 295 vm_object_t, vm_pindex_t, vm_size_t); 296static boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t); 297static void mmu_booke_page_init(mmu_t, vm_page_t); 298static int mmu_booke_page_wired_mappings(mmu_t, vm_page_t); 299static void mmu_booke_pinit(mmu_t, pmap_t); 300static void mmu_booke_pinit0(mmu_t, pmap_t); 301static void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 302 vm_prot_t); 303static void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 304static void mmu_booke_qremove(mmu_t, vm_offset_t, int); 305static void mmu_booke_release(mmu_t, pmap_t); 306static void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 307static void mmu_booke_remove_all(mmu_t, vm_page_t); 308static void mmu_booke_remove_write(mmu_t, vm_page_t); 309static void mmu_booke_zero_page(mmu_t, vm_page_t); 310static void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int); 311static void mmu_booke_zero_page_idle(mmu_t, vm_page_t); 312static void mmu_booke_activate(mmu_t, struct thread *); 313static void mmu_booke_deactivate(mmu_t, struct thread *); 314static void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 315static void *mmu_booke_mapdev(mmu_t, vm_paddr_t, vm_size_t); 316static void *mmu_booke_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t); 317static void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t); 318static vm_paddr_t mmu_booke_kextract(mmu_t, vm_offset_t); 319static void mmu_booke_kenter(mmu_t, vm_offset_t, vm_paddr_t); 320static void mmu_booke_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t); 321static void mmu_booke_kremove(mmu_t, vm_offset_t); 322static boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 323static void mmu_booke_sync_icache(mmu_t, pmap_t, vm_offset_t, 324 vm_size_t); 325static vm_offset_t mmu_booke_dumpsys_map(mmu_t, struct pmap_md *, 326 vm_size_t, vm_size_t *); 327static void mmu_booke_dumpsys_unmap(mmu_t, struct pmap_md *, 328 vm_size_t, vm_offset_t); 329static struct pmap_md *mmu_booke_scan_md(mmu_t, struct pmap_md *); 330 331static mmu_method_t mmu_booke_methods[] = { 332 /* pmap dispatcher interface */ 333 MMUMETHOD(mmu_change_wiring, mmu_booke_change_wiring), 334 MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify), 335 MMUMETHOD(mmu_copy, mmu_booke_copy), 336 MMUMETHOD(mmu_copy_page, mmu_booke_copy_page), 337 MMUMETHOD(mmu_copy_pages, mmu_booke_copy_pages), 338 MMUMETHOD(mmu_enter, mmu_booke_enter), 339 MMUMETHOD(mmu_enter_object, mmu_booke_enter_object), 340 MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick), 341 MMUMETHOD(mmu_extract, mmu_booke_extract), 342 MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold), 343 MMUMETHOD(mmu_init, mmu_booke_init), 344 MMUMETHOD(mmu_is_modified, mmu_booke_is_modified), 345 MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable), 346 MMUMETHOD(mmu_is_referenced, mmu_booke_is_referenced), 347 MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced), 348 MMUMETHOD(mmu_map, mmu_booke_map), 349 MMUMETHOD(mmu_mincore, mmu_booke_mincore), 350 MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt), 351 MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick), 352 MMUMETHOD(mmu_page_init, mmu_booke_page_init), 353 MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings), 354 MMUMETHOD(mmu_pinit, mmu_booke_pinit), 355 MMUMETHOD(mmu_pinit0, mmu_booke_pinit0), 356 MMUMETHOD(mmu_protect, mmu_booke_protect), 357 MMUMETHOD(mmu_qenter, mmu_booke_qenter), 358 MMUMETHOD(mmu_qremove, mmu_booke_qremove), 359 MMUMETHOD(mmu_release, mmu_booke_release), 360 MMUMETHOD(mmu_remove, mmu_booke_remove), 361 MMUMETHOD(mmu_remove_all, mmu_booke_remove_all), 362 MMUMETHOD(mmu_remove_write, mmu_booke_remove_write), 363 MMUMETHOD(mmu_sync_icache, mmu_booke_sync_icache), 364 MMUMETHOD(mmu_zero_page, mmu_booke_zero_page), 365 MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area), 366 MMUMETHOD(mmu_zero_page_idle, mmu_booke_zero_page_idle), 367 MMUMETHOD(mmu_activate, mmu_booke_activate), 368 MMUMETHOD(mmu_deactivate, mmu_booke_deactivate), 369 370 /* Internal interfaces */ 371 MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap), 372 MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped), 373 MMUMETHOD(mmu_mapdev, mmu_booke_mapdev), 374 MMUMETHOD(mmu_mapdev_attr, mmu_booke_mapdev_attr), 375 MMUMETHOD(mmu_kenter, mmu_booke_kenter), 376 MMUMETHOD(mmu_kenter_attr, mmu_booke_kenter_attr), 377 MMUMETHOD(mmu_kextract, mmu_booke_kextract), 378/* MMUMETHOD(mmu_kremove, mmu_booke_kremove), */ 379 MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev), 380 381 /* dumpsys() support */ 382 MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map), 383 MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap), 384 MMUMETHOD(mmu_scan_md, mmu_booke_scan_md), 385 386 { 0, 0 } 387}; 388 389MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods, 0); 390 391static __inline uint32_t 392tlb_calc_wimg(vm_offset_t pa, vm_memattr_t ma) 393{ 394 uint32_t attrib; 395 int i; 396 397 if (ma != VM_MEMATTR_DEFAULT) { 398 switch (ma) { 399 case VM_MEMATTR_UNCACHEABLE: 400 return (PTE_I | PTE_G); 401 case VM_MEMATTR_WRITE_COMBINING: 402 case VM_MEMATTR_WRITE_BACK: 403 case VM_MEMATTR_PREFETCHABLE: 404 return (PTE_I); 405 case VM_MEMATTR_WRITE_THROUGH: 406 return (PTE_W | PTE_M); 407 } 408 } 409 410 /* 411 * Assume the page is cache inhibited and access is guarded unless 412 * it's in our available memory array. 413 */ 414 attrib = _TLB_ENTRY_IO; 415 for (i = 0; i < physmem_regions_sz; i++) { 416 if ((pa >= physmem_regions[i].mr_start) && 417 (pa < (physmem_regions[i].mr_start + 418 physmem_regions[i].mr_size))) { 419 attrib = _TLB_ENTRY_MEM; 420 break; 421 } 422 } 423 424 return (attrib); 425} 426 427static inline void 428tlb_miss_lock(void) 429{ 430#ifdef SMP 431 struct pcpu *pc; 432 433 if (!smp_started) 434 return; 435 436 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 437 if (pc != pcpup) { 438 439 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, " 440 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke_tlb_lock); 441 442 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)), 443 ("tlb_miss_lock: tried to lock self")); 444 445 tlb_lock(pc->pc_booke_tlb_lock); 446 447 CTR1(KTR_PMAP, "%s: locked", __func__); 448 } 449 } 450#endif 451} 452 453static inline void 454tlb_miss_unlock(void) 455{ 456#ifdef SMP 457 struct pcpu *pc; 458 459 if (!smp_started) 460 return; 461 462 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 463 if (pc != pcpup) { 464 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d", 465 __func__, pc->pc_cpuid); 466 467 tlb_unlock(pc->pc_booke_tlb_lock); 468 469 CTR1(KTR_PMAP, "%s: unlocked", __func__); 470 } 471 } 472#endif 473} 474 475/* Return number of entries in TLB0. */ 476static __inline void 477tlb0_get_tlbconf(void) 478{ 479 uint32_t tlb0_cfg; 480 481 tlb0_cfg = mfspr(SPR_TLB0CFG); 482 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK; 483 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT; 484 tlb0_entries_per_way = tlb0_entries / tlb0_ways; 485} 486 487/* Initialize pool of kva ptbl buffers. */ 488static void 489ptbl_init(void) 490{ 491 int i; 492 493 CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__, 494 (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS); 495 CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)", 496 __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE); 497 498 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF); 499 TAILQ_INIT(&ptbl_buf_freelist); 500 501 for (i = 0; i < PTBL_BUFS; i++) { 502 ptbl_bufs[i].kva = ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE; 503 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link); 504 } 505} 506 507/* Get a ptbl_buf from the freelist. */ 508static struct ptbl_buf * 509ptbl_buf_alloc(void) 510{ 511 struct ptbl_buf *buf; 512 513 mtx_lock(&ptbl_buf_freelist_lock); 514 buf = TAILQ_FIRST(&ptbl_buf_freelist); 515 if (buf != NULL) 516 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link); 517 mtx_unlock(&ptbl_buf_freelist_lock); 518 519 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 520 521 return (buf); 522} 523 524/* Return ptbl buff to free pool. */ 525static void 526ptbl_buf_free(struct ptbl_buf *buf) 527{ 528 529 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 530 531 mtx_lock(&ptbl_buf_freelist_lock); 532 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link); 533 mtx_unlock(&ptbl_buf_freelist_lock); 534} 535 536/* 537 * Search the list of allocated ptbl bufs and find on list of allocated ptbls 538 */ 539static void 540ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl) 541{ 542 struct ptbl_buf *pbuf; 543 544 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 545 546 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 547 548 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link) 549 if (pbuf->kva == (vm_offset_t)ptbl) { 550 /* Remove from pmap ptbl buf list. */ 551 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link); 552 553 /* Free corresponding ptbl buf. */ 554 ptbl_buf_free(pbuf); 555 break; 556 } 557} 558 559/* Allocate page table. */ 560static pte_t * 561ptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 562{ 563 vm_page_t mtbl[PTBL_PAGES]; 564 vm_page_t m; 565 struct ptbl_buf *pbuf; 566 unsigned int pidx; 567 pte_t *ptbl; 568 int i; 569 570 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 571 (pmap == kernel_pmap), pdir_idx); 572 573 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 574 ("ptbl_alloc: invalid pdir_idx")); 575 KASSERT((pmap->pm_pdir[pdir_idx] == NULL), 576 ("pte_alloc: valid ptbl entry exists!")); 577 578 pbuf = ptbl_buf_alloc(); 579 if (pbuf == NULL) 580 panic("pte_alloc: couldn't alloc kernel virtual memory"); 581 582 ptbl = (pte_t *)pbuf->kva; 583 584 CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl); 585 586 /* Allocate ptbl pages, this will sleep! */ 587 for (i = 0; i < PTBL_PAGES; i++) { 588 pidx = (PTBL_PAGES * pdir_idx) + i; 589 while ((m = vm_page_alloc(NULL, pidx, 590 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 591 592 PMAP_UNLOCK(pmap); 593 rw_wunlock(&pvh_global_lock); 594 VM_WAIT; 595 rw_wlock(&pvh_global_lock); 596 PMAP_LOCK(pmap); 597 } 598 mtbl[i] = m; 599 } 600 601 /* Map allocated pages into kernel_pmap. */ 602 mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES); 603 604 /* Zero whole ptbl. */ 605 bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE); 606 607 /* Add pbuf to the pmap ptbl bufs list. */ 608 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link); 609 610 return (ptbl); 611} 612 613/* Free ptbl pages and invalidate pdir entry. */ 614static void 615ptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 616{ 617 pte_t *ptbl; 618 vm_paddr_t pa; 619 vm_offset_t va; 620 vm_page_t m; 621 int i; 622 623 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 624 (pmap == kernel_pmap), pdir_idx); 625 626 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 627 ("ptbl_free: invalid pdir_idx")); 628 629 ptbl = pmap->pm_pdir[pdir_idx]; 630 631 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 632 633 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl")); 634 635 /* 636 * Invalidate the pdir entry as soon as possible, so that other CPUs 637 * don't attempt to look up the page tables we are releasing. 638 */ 639 mtx_lock_spin(&tlbivax_mutex); 640 tlb_miss_lock(); 641 642 pmap->pm_pdir[pdir_idx] = NULL; 643 644 tlb_miss_unlock(); 645 mtx_unlock_spin(&tlbivax_mutex); 646 647 for (i = 0; i < PTBL_PAGES; i++) { 648 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE)); 649 pa = pte_vatopa(mmu, kernel_pmap, va); 650 m = PHYS_TO_VM_PAGE(pa); 651 vm_page_free_zero(m); 652 atomic_subtract_int(&cnt.v_wire_count, 1); 653 mmu_booke_kremove(mmu, va); 654 } 655 656 ptbl_free_pmap_ptbl(pmap, ptbl); 657} 658 659/* 660 * Decrement ptbl pages hold count and attempt to free ptbl pages. 661 * Called when removing pte entry from ptbl. 662 * 663 * Return 1 if ptbl pages were freed. 664 */ 665static int 666ptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 667{ 668 pte_t *ptbl; 669 vm_paddr_t pa; 670 vm_page_t m; 671 int i; 672 673 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 674 (pmap == kernel_pmap), pdir_idx); 675 676 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 677 ("ptbl_unhold: invalid pdir_idx")); 678 KASSERT((pmap != kernel_pmap), 679 ("ptbl_unhold: unholding kernel ptbl!")); 680 681 ptbl = pmap->pm_pdir[pdir_idx]; 682 683 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl); 684 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS), 685 ("ptbl_unhold: non kva ptbl")); 686 687 /* decrement hold count */ 688 for (i = 0; i < PTBL_PAGES; i++) { 689 pa = pte_vatopa(mmu, kernel_pmap, 690 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 691 m = PHYS_TO_VM_PAGE(pa); 692 m->wire_count--; 693 } 694 695 /* 696 * Free ptbl pages if there are no pte etries in this ptbl. 697 * wire_count has the same value for all ptbl pages, so check the last 698 * page. 699 */ 700 if (m->wire_count == 0) { 701 ptbl_free(mmu, pmap, pdir_idx); 702 703 //debugf("ptbl_unhold: e (freed ptbl)\n"); 704 return (1); 705 } 706 707 return (0); 708} 709 710/* 711 * Increment hold count for ptbl pages. This routine is used when a new pte 712 * entry is being inserted into the ptbl. 713 */ 714static void 715ptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 716{ 717 vm_paddr_t pa; 718 pte_t *ptbl; 719 vm_page_t m; 720 int i; 721 722 CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap, 723 pdir_idx); 724 725 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 726 ("ptbl_hold: invalid pdir_idx")); 727 KASSERT((pmap != kernel_pmap), 728 ("ptbl_hold: holding kernel ptbl!")); 729 730 ptbl = pmap->pm_pdir[pdir_idx]; 731 732 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl")); 733 734 for (i = 0; i < PTBL_PAGES; i++) { 735 pa = pte_vatopa(mmu, kernel_pmap, 736 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 737 m = PHYS_TO_VM_PAGE(pa); 738 m->wire_count++; 739 } 740} 741 742/* Allocate pv_entry structure. */ 743pv_entry_t 744pv_alloc(void) 745{ 746 pv_entry_t pv; 747 748 pv_entry_count++; 749 if (pv_entry_count > pv_entry_high_water) 750 pagedaemon_wakeup(); 751 pv = uma_zalloc(pvzone, M_NOWAIT); 752 753 return (pv); 754} 755 756/* Free pv_entry structure. */ 757static __inline void 758pv_free(pv_entry_t pve) 759{ 760 761 pv_entry_count--; 762 uma_zfree(pvzone, pve); 763} 764 765 766/* Allocate and initialize pv_entry structure. */ 767static void 768pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m) 769{ 770 pv_entry_t pve; 771 772 //int su = (pmap == kernel_pmap); 773 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su, 774 // (u_int32_t)pmap, va, (u_int32_t)m); 775 776 pve = pv_alloc(); 777 if (pve == NULL) 778 panic("pv_insert: no pv entries!"); 779 780 pve->pv_pmap = pmap; 781 pve->pv_va = va; 782 783 /* add to pv_list */ 784 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 785 rw_assert(&pvh_global_lock, RA_WLOCKED); 786 787 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link); 788 789 //debugf("pv_insert: e\n"); 790} 791 792/* Destroy pv entry. */ 793static void 794pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m) 795{ 796 pv_entry_t pve; 797 798 //int su = (pmap == kernel_pmap); 799 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va); 800 801 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 802 rw_assert(&pvh_global_lock, RA_WLOCKED); 803 804 /* find pv entry */ 805 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) { 806 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 807 /* remove from pv_list */ 808 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link); 809 if (TAILQ_EMPTY(&m->md.pv_list)) 810 vm_page_aflag_clear(m, PGA_WRITEABLE); 811 812 /* free pv entry struct */ 813 pv_free(pve); 814 break; 815 } 816 } 817 818 //debugf("pv_remove: e\n"); 819} 820 821/* 822 * Clean pte entry, try to free page table page if requested. 823 * 824 * Return 1 if ptbl pages were freed, otherwise return 0. 825 */ 826static int 827pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags) 828{ 829 unsigned int pdir_idx = PDIR_IDX(va); 830 unsigned int ptbl_idx = PTBL_IDX(va); 831 vm_page_t m; 832 pte_t *ptbl; 833 pte_t *pte; 834 835 //int su = (pmap == kernel_pmap); 836 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n", 837 // su, (u_int32_t)pmap, va, flags); 838 839 ptbl = pmap->pm_pdir[pdir_idx]; 840 KASSERT(ptbl, ("pte_remove: null ptbl")); 841 842 pte = &ptbl[ptbl_idx]; 843 844 if (pte == NULL || !PTE_ISVALID(pte)) 845 return (0); 846 847 if (PTE_ISWIRED(pte)) 848 pmap->pm_stats.wired_count--; 849 850 /* Handle managed entry. */ 851 if (PTE_ISMANAGED(pte)) { 852 /* Get vm_page_t for mapped pte. */ 853 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 854 855 if (PTE_ISMODIFIED(pte)) 856 vm_page_dirty(m); 857 858 if (PTE_ISREFERENCED(pte)) 859 vm_page_aflag_set(m, PGA_REFERENCED); 860 861 pv_remove(pmap, va, m); 862 } 863 864 mtx_lock_spin(&tlbivax_mutex); 865 tlb_miss_lock(); 866 867 tlb0_flush_entry(va); 868 pte->flags = 0; 869 pte->rpn = 0; 870 871 tlb_miss_unlock(); 872 mtx_unlock_spin(&tlbivax_mutex); 873 874 pmap->pm_stats.resident_count--; 875 876 if (flags & PTBL_UNHOLD) { 877 //debugf("pte_remove: e (unhold)\n"); 878 return (ptbl_unhold(mmu, pmap, pdir_idx)); 879 } 880 881 //debugf("pte_remove: e\n"); 882 return (0); 883} 884 885/* 886 * Insert PTE for a given page and virtual address. 887 */ 888static void 889pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags) 890{ 891 unsigned int pdir_idx = PDIR_IDX(va); 892 unsigned int ptbl_idx = PTBL_IDX(va); 893 pte_t *ptbl, *pte; 894 895 CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__, 896 pmap == kernel_pmap, pmap, va); 897 898 /* Get the page table pointer. */ 899 ptbl = pmap->pm_pdir[pdir_idx]; 900 901 if (ptbl == NULL) { 902 /* Allocate page table pages. */ 903 ptbl = ptbl_alloc(mmu, pmap, pdir_idx); 904 } else { 905 /* 906 * Check if there is valid mapping for requested 907 * va, if there is, remove it. 908 */ 909 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx]; 910 if (PTE_ISVALID(pte)) { 911 pte_remove(mmu, pmap, va, PTBL_HOLD); 912 } else { 913 /* 914 * pte is not used, increment hold count 915 * for ptbl pages. 916 */ 917 if (pmap != kernel_pmap) 918 ptbl_hold(mmu, pmap, pdir_idx); 919 } 920 } 921 922 /* 923 * Insert pv_entry into pv_list for mapped page if part of managed 924 * memory. 925 */ 926 if ((m->oflags & VPO_UNMANAGED) == 0) { 927 flags |= PTE_MANAGED; 928 929 /* Create and insert pv entry. */ 930 pv_insert(pmap, va, m); 931 } 932 933 pmap->pm_stats.resident_count++; 934 935 mtx_lock_spin(&tlbivax_mutex); 936 tlb_miss_lock(); 937 938 tlb0_flush_entry(va); 939 if (pmap->pm_pdir[pdir_idx] == NULL) { 940 /* 941 * If we just allocated a new page table, hook it in 942 * the pdir. 943 */ 944 pmap->pm_pdir[pdir_idx] = ptbl; 945 } 946 pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]); 947 pte->rpn = VM_PAGE_TO_PHYS(m) & ~PTE_PA_MASK; 948 pte->flags |= (PTE_VALID | flags); 949 950 tlb_miss_unlock(); 951 mtx_unlock_spin(&tlbivax_mutex); 952} 953 954/* Return the pa for the given pmap/va. */ 955static vm_paddr_t 956pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va) 957{ 958 vm_paddr_t pa = 0; 959 pte_t *pte; 960 961 pte = pte_find(mmu, pmap, va); 962 if ((pte != NULL) && PTE_ISVALID(pte)) 963 pa = (PTE_PA(pte) | (va & PTE_PA_MASK)); 964 return (pa); 965} 966 967/* Get a pointer to a PTE in a page table. */ 968static pte_t * 969pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va) 970{ 971 unsigned int pdir_idx = PDIR_IDX(va); 972 unsigned int ptbl_idx = PTBL_IDX(va); 973 974 KASSERT((pmap != NULL), ("pte_find: invalid pmap")); 975 976 if (pmap->pm_pdir[pdir_idx]) 977 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx])); 978 979 return (NULL); 980} 981 982/**************************************************************************/ 983/* PMAP related */ 984/**************************************************************************/ 985 986/* 987 * This is called during booke_init, before the system is really initialized. 988 */ 989static void 990mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend) 991{ 992 vm_offset_t phys_kernelend; 993 struct mem_region *mp, *mp1; 994 int cnt, i, j; 995 u_int s, e, sz; 996 u_int phys_avail_count; 997 vm_size_t physsz, hwphyssz, kstack0_sz; 998 vm_offset_t kernel_pdir, kstack0, va; 999 vm_paddr_t kstack0_phys; 1000 void *dpcpu; 1001 pte_t *pte; 1002 1003 debugf("mmu_booke_bootstrap: entered\n"); 1004 1005 /* Initialize invalidation mutex */ 1006 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN); 1007 1008 /* Read TLB0 size and associativity. */ 1009 tlb0_get_tlbconf(); 1010 1011 /* 1012 * Align kernel start and end address (kernel image). 1013 * Note that kernel end does not necessarily relate to kernsize. 1014 * kernsize is the size of the kernel that is actually mapped. 1015 * Also note that "start - 1" is deliberate. With SMP, the 1016 * entry point is exactly a page from the actual load address. 1017 * As such, trunc_page() has no effect and we're off by a page. 1018 * Since we always have the ELF header between the load address 1019 * and the entry point, we can safely subtract 1 to compensate. 1020 */ 1021 kernstart = trunc_page(start - 1); 1022 data_start = round_page(kernelend); 1023 data_end = data_start; 1024 1025 /* 1026 * Addresses of preloaded modules (like file systems) use 1027 * physical addresses. Make sure we relocate those into 1028 * virtual addresses. 1029 */ 1030 preload_addr_relocate = kernstart - kernload; 1031 1032 /* Allocate the dynamic per-cpu area. */ 1033 dpcpu = (void *)data_end; 1034 data_end += DPCPU_SIZE; 1035 1036 /* Allocate space for the message buffer. */ 1037 msgbufp = (struct msgbuf *)data_end; 1038 data_end += msgbufsize; 1039 debugf(" msgbufp at 0x%08x end = 0x%08x\n", (uint32_t)msgbufp, 1040 data_end); 1041 1042 data_end = round_page(data_end); 1043 1044 /* Allocate space for ptbl_bufs. */ 1045 ptbl_bufs = (struct ptbl_buf *)data_end; 1046 data_end += sizeof(struct ptbl_buf) * PTBL_BUFS; 1047 debugf(" ptbl_bufs at 0x%08x end = 0x%08x\n", (uint32_t)ptbl_bufs, 1048 data_end); 1049 1050 data_end = round_page(data_end); 1051 1052 /* Allocate PTE tables for kernel KVA. */ 1053 kernel_pdir = data_end; 1054 kernel_ptbls = (VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS + 1055 PDIR_SIZE - 1) / PDIR_SIZE; 1056 data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE; 1057 debugf(" kernel ptbls: %d\n", kernel_ptbls); 1058 debugf(" kernel pdir at 0x%08x end = 0x%08x\n", kernel_pdir, data_end); 1059 1060 debugf(" data_end: 0x%08x\n", data_end); 1061 if (data_end - kernstart > kernsize) { 1062 kernsize += tlb1_mapin_region(kernstart + kernsize, 1063 kernload + kernsize, (data_end - kernstart) - kernsize); 1064 } 1065 data_end = kernstart + kernsize; 1066 debugf(" updated data_end: 0x%08x\n", data_end); 1067 1068 /* 1069 * Clear the structures - note we can only do it safely after the 1070 * possible additional TLB1 translations are in place (above) so that 1071 * all range up to the currently calculated 'data_end' is covered. 1072 */ 1073 dpcpu_init(dpcpu, 0); 1074 memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE); 1075 memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE); 1076 1077 /*******************************************************/ 1078 /* Set the start and end of kva. */ 1079 /*******************************************************/ 1080 virtual_avail = round_page(data_end); 1081 virtual_end = VM_MAX_KERNEL_ADDRESS; 1082 1083 /* Allocate KVA space for page zero/copy operations. */ 1084 zero_page_va = virtual_avail; 1085 virtual_avail += PAGE_SIZE; 1086 zero_page_idle_va = virtual_avail; 1087 virtual_avail += PAGE_SIZE; 1088 copy_page_src_va = virtual_avail; 1089 virtual_avail += PAGE_SIZE; 1090 copy_page_dst_va = virtual_avail; 1091 virtual_avail += PAGE_SIZE; 1092 debugf("zero_page_va = 0x%08x\n", zero_page_va); 1093 debugf("zero_page_idle_va = 0x%08x\n", zero_page_idle_va); 1094 debugf("copy_page_src_va = 0x%08x\n", copy_page_src_va); 1095 debugf("copy_page_dst_va = 0x%08x\n", copy_page_dst_va); 1096 1097 /* Initialize page zero/copy mutexes. */ 1098 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF); 1099 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF); 1100 1101 /* Allocate KVA space for ptbl bufs. */ 1102 ptbl_buf_pool_vabase = virtual_avail; 1103 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE; 1104 debugf("ptbl_buf_pool_vabase = 0x%08x end = 0x%08x\n", 1105 ptbl_buf_pool_vabase, virtual_avail); 1106 1107 /* Calculate corresponding physical addresses for the kernel region. */ 1108 phys_kernelend = kernload + kernsize; 1109 debugf("kernel image and allocated data:\n"); 1110 debugf(" kernload = 0x%08x\n", kernload); 1111 debugf(" kernstart = 0x%08x\n", kernstart); 1112 debugf(" kernsize = 0x%08x\n", kernsize); 1113 1114 if (sizeof(phys_avail) / sizeof(phys_avail[0]) < availmem_regions_sz) 1115 panic("mmu_booke_bootstrap: phys_avail too small"); 1116 1117 /* 1118 * Remove kernel physical address range from avail regions list. Page 1119 * align all regions. Non-page aligned memory isn't very interesting 1120 * to us. Also, sort the entries for ascending addresses. 1121 */ 1122 1123 /* Retrieve phys/avail mem regions */ 1124 mem_regions(&physmem_regions, &physmem_regions_sz, 1125 &availmem_regions, &availmem_regions_sz); 1126 sz = 0; 1127 cnt = availmem_regions_sz; 1128 debugf("processing avail regions:\n"); 1129 for (mp = availmem_regions; mp->mr_size; mp++) { 1130 s = mp->mr_start; 1131 e = mp->mr_start + mp->mr_size; 1132 debugf(" %08x-%08x -> ", s, e); 1133 /* Check whether this region holds all of the kernel. */ 1134 if (s < kernload && e > phys_kernelend) { 1135 availmem_regions[cnt].mr_start = phys_kernelend; 1136 availmem_regions[cnt++].mr_size = e - phys_kernelend; 1137 e = kernload; 1138 } 1139 /* Look whether this regions starts within the kernel. */ 1140 if (s >= kernload && s < phys_kernelend) { 1141 if (e <= phys_kernelend) 1142 goto empty; 1143 s = phys_kernelend; 1144 } 1145 /* Now look whether this region ends within the kernel. */ 1146 if (e > kernload && e <= phys_kernelend) { 1147 if (s >= kernload) 1148 goto empty; 1149 e = kernload; 1150 } 1151 /* Now page align the start and size of the region. */ 1152 s = round_page(s); 1153 e = trunc_page(e); 1154 if (e < s) 1155 e = s; 1156 sz = e - s; 1157 debugf("%08x-%08x = %x\n", s, e, sz); 1158 1159 /* Check whether some memory is left here. */ 1160 if (sz == 0) { 1161 empty: 1162 memmove(mp, mp + 1, 1163 (cnt - (mp - availmem_regions)) * sizeof(*mp)); 1164 cnt--; 1165 mp--; 1166 continue; 1167 } 1168 1169 /* Do an insertion sort. */ 1170 for (mp1 = availmem_regions; mp1 < mp; mp1++) 1171 if (s < mp1->mr_start) 1172 break; 1173 if (mp1 < mp) { 1174 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1); 1175 mp1->mr_start = s; 1176 mp1->mr_size = sz; 1177 } else { 1178 mp->mr_start = s; 1179 mp->mr_size = sz; 1180 } 1181 } 1182 availmem_regions_sz = cnt; 1183 1184 /*******************************************************/ 1185 /* Steal physical memory for kernel stack from the end */ 1186 /* of the first avail region */ 1187 /*******************************************************/ 1188 kstack0_sz = KSTACK_PAGES * PAGE_SIZE; 1189 kstack0_phys = availmem_regions[0].mr_start + 1190 availmem_regions[0].mr_size; 1191 kstack0_phys -= kstack0_sz; 1192 availmem_regions[0].mr_size -= kstack0_sz; 1193 1194 /*******************************************************/ 1195 /* Fill in phys_avail table, based on availmem_regions */ 1196 /*******************************************************/ 1197 phys_avail_count = 0; 1198 physsz = 0; 1199 hwphyssz = 0; 1200 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 1201 1202 debugf("fill in phys_avail:\n"); 1203 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) { 1204 1205 debugf(" region: 0x%08x - 0x%08x (0x%08x)\n", 1206 availmem_regions[i].mr_start, 1207 availmem_regions[i].mr_start + 1208 availmem_regions[i].mr_size, 1209 availmem_regions[i].mr_size); 1210 1211 if (hwphyssz != 0 && 1212 (physsz + availmem_regions[i].mr_size) >= hwphyssz) { 1213 debugf(" hw.physmem adjust\n"); 1214 if (physsz < hwphyssz) { 1215 phys_avail[j] = availmem_regions[i].mr_start; 1216 phys_avail[j + 1] = 1217 availmem_regions[i].mr_start + 1218 hwphyssz - physsz; 1219 physsz = hwphyssz; 1220 phys_avail_count++; 1221 } 1222 break; 1223 } 1224 1225 phys_avail[j] = availmem_regions[i].mr_start; 1226 phys_avail[j + 1] = availmem_regions[i].mr_start + 1227 availmem_regions[i].mr_size; 1228 phys_avail_count++; 1229 physsz += availmem_regions[i].mr_size; 1230 } 1231 physmem = btoc(physsz); 1232 1233 /* Calculate the last available physical address. */ 1234 for (i = 0; phys_avail[i + 2] != 0; i += 2) 1235 ; 1236 Maxmem = powerpc_btop(phys_avail[i + 1]); 1237 1238 debugf("Maxmem = 0x%08lx\n", Maxmem); 1239 debugf("phys_avail_count = %d\n", phys_avail_count); 1240 debugf("physsz = 0x%08x physmem = %ld (0x%08lx)\n", physsz, physmem, 1241 physmem); 1242 1243 /*******************************************************/ 1244 /* Initialize (statically allocated) kernel pmap. */ 1245 /*******************************************************/ 1246 PMAP_LOCK_INIT(kernel_pmap); 1247 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE; 1248 1249 debugf("kernel_pmap = 0x%08x\n", (uint32_t)kernel_pmap); 1250 debugf("kptbl_min = %d, kernel_ptbls = %d\n", kptbl_min, kernel_ptbls); 1251 debugf("kernel pdir range: 0x%08x - 0x%08x\n", 1252 kptbl_min * PDIR_SIZE, (kptbl_min + kernel_ptbls) * PDIR_SIZE - 1); 1253 1254 /* Initialize kernel pdir */ 1255 for (i = 0; i < kernel_ptbls; i++) 1256 kernel_pmap->pm_pdir[kptbl_min + i] = 1257 (pte_t *)(kernel_pdir + (i * PAGE_SIZE * PTBL_PAGES)); 1258 1259 for (i = 0; i < MAXCPU; i++) { 1260 kernel_pmap->pm_tid[i] = TID_KERNEL; 1261 1262 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */ 1263 tidbusy[i][0] = kernel_pmap; 1264 } 1265 1266 /* 1267 * Fill in PTEs covering kernel code and data. They are not required 1268 * for address translation, as this area is covered by static TLB1 1269 * entries, but for pte_vatopa() to work correctly with kernel area 1270 * addresses. 1271 */ 1272 for (va = kernstart; va < data_end; va += PAGE_SIZE) { 1273 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]); 1274 pte->rpn = kernload + (va - kernstart); 1275 pte->flags = PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | 1276 PTE_VALID; 1277 } 1278 /* Mark kernel_pmap active on all CPUs */ 1279 CPU_FILL(&kernel_pmap->pm_active); 1280 1281 /* 1282 * Initialize the global pv list lock. 1283 */ 1284 rw_init(&pvh_global_lock, "pmap pv global"); 1285 1286 /*******************************************************/ 1287 /* Final setup */ 1288 /*******************************************************/ 1289 1290 /* Enter kstack0 into kernel map, provide guard page */ 1291 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1292 thread0.td_kstack = kstack0; 1293 thread0.td_kstack_pages = KSTACK_PAGES; 1294 1295 debugf("kstack_sz = 0x%08x\n", kstack0_sz); 1296 debugf("kstack0_phys at 0x%08x - 0x%08x\n", 1297 kstack0_phys, kstack0_phys + kstack0_sz); 1298 debugf("kstack0 at 0x%08x - 0x%08x\n", kstack0, kstack0 + kstack0_sz); 1299 1300 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz; 1301 for (i = 0; i < KSTACK_PAGES; i++) { 1302 mmu_booke_kenter(mmu, kstack0, kstack0_phys); 1303 kstack0 += PAGE_SIZE; 1304 kstack0_phys += PAGE_SIZE; 1305 } 1306 1307 debugf("virtual_avail = %08x\n", virtual_avail); 1308 debugf("virtual_end = %08x\n", virtual_end); 1309 1310 debugf("mmu_booke_bootstrap: exit\n"); 1311} 1312 1313void 1314pmap_bootstrap_ap(volatile uint32_t *trcp __unused) 1315{ 1316 int i; 1317 1318 /* 1319 * Finish TLB1 configuration: the BSP already set up its TLB1 and we 1320 * have the snapshot of its contents in the s/w tlb1[] table, so use 1321 * these values directly to (re)program AP's TLB1 hardware. 1322 */ 1323 for (i = bp_ntlb1s; i < tlb1_idx; i++) { 1324 /* Skip invalid entries */ 1325 if (!(tlb1[i].mas1 & MAS1_VALID)) 1326 continue; 1327 1328 tlb1_write_entry(i); 1329 } 1330 1331 set_mas4_defaults(); 1332} 1333 1334/* 1335 * Get the physical page address for the given pmap/virtual address. 1336 */ 1337static vm_paddr_t 1338mmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1339{ 1340 vm_paddr_t pa; 1341 1342 PMAP_LOCK(pmap); 1343 pa = pte_vatopa(mmu, pmap, va); 1344 PMAP_UNLOCK(pmap); 1345 1346 return (pa); 1347} 1348 1349/* 1350 * Extract the physical page address associated with the given 1351 * kernel virtual address. 1352 */ 1353static vm_paddr_t 1354mmu_booke_kextract(mmu_t mmu, vm_offset_t va) 1355{ 1356 int i; 1357 1358 /* Check TLB1 mappings */ 1359 for (i = 0; i < tlb1_idx; i++) { 1360 if (!(tlb1[i].mas1 & MAS1_VALID)) 1361 continue; 1362 if (va >= tlb1[i].virt && va < tlb1[i].virt + tlb1[i].size) 1363 return (tlb1[i].phys + (va - tlb1[i].virt)); 1364 } 1365 1366 return (pte_vatopa(mmu, kernel_pmap, va)); 1367} 1368 1369/* 1370 * Initialize the pmap module. 1371 * Called by vm_init, to initialize any structures that the pmap 1372 * system needs to map virtual memory. 1373 */ 1374static void 1375mmu_booke_init(mmu_t mmu) 1376{ 1377 int shpgperproc = PMAP_SHPGPERPROC; 1378 1379 /* 1380 * Initialize the address space (zone) for the pv entries. Set a 1381 * high water mark so that the system can recover from excessive 1382 * numbers of pv entries. 1383 */ 1384 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 1385 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1386 1387 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1388 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 1389 1390 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 1391 pv_entry_high_water = 9 * (pv_entry_max / 10); 1392 1393 uma_zone_reserve_kva(pvzone, pv_entry_max); 1394 1395 /* Pre-fill pvzone with initial number of pv entries. */ 1396 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN); 1397 1398 /* Initialize ptbl allocation. */ 1399 ptbl_init(); 1400} 1401 1402/* 1403 * Map a list of wired pages into kernel virtual address space. This is 1404 * intended for temporary mappings which do not need page modification or 1405 * references recorded. Existing mappings in the region are overwritten. 1406 */ 1407static void 1408mmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1409{ 1410 vm_offset_t va; 1411 1412 va = sva; 1413 while (count-- > 0) { 1414 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1415 va += PAGE_SIZE; 1416 m++; 1417 } 1418} 1419 1420/* 1421 * Remove page mappings from kernel virtual address space. Intended for 1422 * temporary mappings entered by mmu_booke_qenter. 1423 */ 1424static void 1425mmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count) 1426{ 1427 vm_offset_t va; 1428 1429 va = sva; 1430 while (count-- > 0) { 1431 mmu_booke_kremove(mmu, va); 1432 va += PAGE_SIZE; 1433 } 1434} 1435 1436/* 1437 * Map a wired page into kernel virtual address space. 1438 */ 1439static void 1440mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1441{ 1442 1443 mmu_booke_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1444} 1445 1446static void 1447mmu_booke_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1448{ 1449 unsigned int pdir_idx = PDIR_IDX(va); 1450 unsigned int ptbl_idx = PTBL_IDX(va); 1451 uint32_t flags; 1452 pte_t *pte; 1453 1454 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1455 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va")); 1456 1457 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID; 1458 flags |= tlb_calc_wimg(pa, ma); 1459 1460 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1461 1462 mtx_lock_spin(&tlbivax_mutex); 1463 tlb_miss_lock(); 1464 1465 if (PTE_ISVALID(pte)) { 1466 1467 CTR1(KTR_PMAP, "%s: replacing entry!", __func__); 1468 1469 /* Flush entry from TLB0 */ 1470 tlb0_flush_entry(va); 1471 } 1472 1473 pte->rpn = pa & ~PTE_PA_MASK; 1474 pte->flags = flags; 1475 1476 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x " 1477 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n", 1478 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags); 1479 1480 /* Flush the real memory from the instruction cache. */ 1481 if ((flags & (PTE_I | PTE_G)) == 0) { 1482 __syncicache((void *)va, PAGE_SIZE); 1483 } 1484 1485 tlb_miss_unlock(); 1486 mtx_unlock_spin(&tlbivax_mutex); 1487} 1488 1489/* 1490 * Remove a page from kernel page table. 1491 */ 1492static void 1493mmu_booke_kremove(mmu_t mmu, vm_offset_t va) 1494{ 1495 unsigned int pdir_idx = PDIR_IDX(va); 1496 unsigned int ptbl_idx = PTBL_IDX(va); 1497 pte_t *pte; 1498 1499// CTR2(KTR_PMAP,("%s: s (va = 0x%08x)\n", __func__, va)); 1500 1501 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1502 (va <= VM_MAX_KERNEL_ADDRESS)), 1503 ("mmu_booke_kremove: invalid va")); 1504 1505 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1506 1507 if (!PTE_ISVALID(pte)) { 1508 1509 CTR1(KTR_PMAP, "%s: invalid pte", __func__); 1510 1511 return; 1512 } 1513 1514 mtx_lock_spin(&tlbivax_mutex); 1515 tlb_miss_lock(); 1516 1517 /* Invalidate entry in TLB0, update PTE. */ 1518 tlb0_flush_entry(va); 1519 pte->flags = 0; 1520 pte->rpn = 0; 1521 1522 tlb_miss_unlock(); 1523 mtx_unlock_spin(&tlbivax_mutex); 1524} 1525 1526/* 1527 * Initialize pmap associated with process 0. 1528 */ 1529static void 1530mmu_booke_pinit0(mmu_t mmu, pmap_t pmap) 1531{ 1532 1533 PMAP_LOCK_INIT(pmap); 1534 mmu_booke_pinit(mmu, pmap); 1535 PCPU_SET(curpmap, pmap); 1536} 1537 1538/* 1539 * Initialize a preallocated and zeroed pmap structure, 1540 * such as one in a vmspace structure. 1541 */ 1542static void 1543mmu_booke_pinit(mmu_t mmu, pmap_t pmap) 1544{ 1545 int i; 1546 1547 CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap, 1548 curthread->td_proc->p_pid, curthread->td_proc->p_comm); 1549 1550 KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap")); 1551 1552 for (i = 0; i < MAXCPU; i++) 1553 pmap->pm_tid[i] = TID_NONE; 1554 CPU_ZERO(&kernel_pmap->pm_active); 1555 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats)); 1556 bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES); 1557 TAILQ_INIT(&pmap->pm_ptbl_list); 1558} 1559 1560/* 1561 * Release any resources held by the given physical map. 1562 * Called when a pmap initialized by mmu_booke_pinit is being released. 1563 * Should only be called if the map contains no valid mappings. 1564 */ 1565static void 1566mmu_booke_release(mmu_t mmu, pmap_t pmap) 1567{ 1568 1569 KASSERT(pmap->pm_stats.resident_count == 0, 1570 ("pmap_release: pmap resident count %ld != 0", 1571 pmap->pm_stats.resident_count)); 1572} 1573 1574/* 1575 * Insert the given physical page at the specified virtual address in the 1576 * target physical map with the protection requested. If specified the page 1577 * will be wired down. 1578 */ 1579static void 1580mmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1581 vm_prot_t prot, boolean_t wired) 1582{ 1583 1584 rw_wlock(&pvh_global_lock); 1585 PMAP_LOCK(pmap); 1586 mmu_booke_enter_locked(mmu, pmap, va, m, prot, wired); 1587 rw_wunlock(&pvh_global_lock); 1588 PMAP_UNLOCK(pmap); 1589} 1590 1591static void 1592mmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1593 vm_prot_t prot, boolean_t wired) 1594{ 1595 pte_t *pte; 1596 vm_paddr_t pa; 1597 uint32_t flags; 1598 int su, sync; 1599 1600 pa = VM_PAGE_TO_PHYS(m); 1601 su = (pmap == kernel_pmap); 1602 sync = 0; 1603 1604 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x " 1605 // "pa=0x%08x prot=0x%08x wired=%d)\n", 1606 // (u_int32_t)pmap, su, pmap->pm_tid, 1607 // (u_int32_t)m, va, pa, prot, wired); 1608 1609 if (su) { 1610 KASSERT(((va >= virtual_avail) && 1611 (va <= VM_MAX_KERNEL_ADDRESS)), 1612 ("mmu_booke_enter_locked: kernel pmap, non kernel va")); 1613 } else { 1614 KASSERT((va <= VM_MAXUSER_ADDRESS), 1615 ("mmu_booke_enter_locked: user pmap, non user va")); 1616 } 1617 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1618 VM_OBJECT_ASSERT_LOCKED(m->object); 1619 1620 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1621 1622 /* 1623 * If there is an existing mapping, and the physical address has not 1624 * changed, must be protection or wiring change. 1625 */ 1626 if (((pte = pte_find(mmu, pmap, va)) != NULL) && 1627 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) { 1628 1629 /* 1630 * Before actually updating pte->flags we calculate and 1631 * prepare its new value in a helper var. 1632 */ 1633 flags = pte->flags; 1634 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED); 1635 1636 /* Wiring change, just update stats. */ 1637 if (wired) { 1638 if (!PTE_ISWIRED(pte)) { 1639 flags |= PTE_WIRED; 1640 pmap->pm_stats.wired_count++; 1641 } 1642 } else { 1643 if (PTE_ISWIRED(pte)) { 1644 flags &= ~PTE_WIRED; 1645 pmap->pm_stats.wired_count--; 1646 } 1647 } 1648 1649 if (prot & VM_PROT_WRITE) { 1650 /* Add write permissions. */ 1651 flags |= PTE_SW; 1652 if (!su) 1653 flags |= PTE_UW; 1654 1655 if ((flags & PTE_MANAGED) != 0) 1656 vm_page_aflag_set(m, PGA_WRITEABLE); 1657 } else { 1658 /* Handle modified pages, sense modify status. */ 1659 1660 /* 1661 * The PTE_MODIFIED flag could be set by underlying 1662 * TLB misses since we last read it (above), possibly 1663 * other CPUs could update it so we check in the PTE 1664 * directly rather than rely on that saved local flags 1665 * copy. 1666 */ 1667 if (PTE_ISMODIFIED(pte)) 1668 vm_page_dirty(m); 1669 } 1670 1671 if (prot & VM_PROT_EXECUTE) { 1672 flags |= PTE_SX; 1673 if (!su) 1674 flags |= PTE_UX; 1675 1676 /* 1677 * Check existing flags for execute permissions: if we 1678 * are turning execute permissions on, icache should 1679 * be flushed. 1680 */ 1681 if ((pte->flags & (PTE_UX | PTE_SX)) == 0) 1682 sync++; 1683 } 1684 1685 flags &= ~PTE_REFERENCED; 1686 1687 /* 1688 * The new flags value is all calculated -- only now actually 1689 * update the PTE. 1690 */ 1691 mtx_lock_spin(&tlbivax_mutex); 1692 tlb_miss_lock(); 1693 1694 tlb0_flush_entry(va); 1695 pte->flags = flags; 1696 1697 tlb_miss_unlock(); 1698 mtx_unlock_spin(&tlbivax_mutex); 1699 1700 } else { 1701 /* 1702 * If there is an existing mapping, but it's for a different 1703 * physical address, pte_enter() will delete the old mapping. 1704 */ 1705 //if ((pte != NULL) && PTE_ISVALID(pte)) 1706 // debugf("mmu_booke_enter_locked: replace\n"); 1707 //else 1708 // debugf("mmu_booke_enter_locked: new\n"); 1709 1710 /* Now set up the flags and install the new mapping. */ 1711 flags = (PTE_SR | PTE_VALID); 1712 flags |= PTE_M; 1713 1714 if (!su) 1715 flags |= PTE_UR; 1716 1717 if (prot & VM_PROT_WRITE) { 1718 flags |= PTE_SW; 1719 if (!su) 1720 flags |= PTE_UW; 1721 1722 if ((m->oflags & VPO_UNMANAGED) == 0) 1723 vm_page_aflag_set(m, PGA_WRITEABLE); 1724 } 1725 1726 if (prot & VM_PROT_EXECUTE) { 1727 flags |= PTE_SX; 1728 if (!su) 1729 flags |= PTE_UX; 1730 } 1731 1732 /* If its wired update stats. */ 1733 if (wired) { 1734 pmap->pm_stats.wired_count++; 1735 flags |= PTE_WIRED; 1736 } 1737 1738 pte_enter(mmu, pmap, m, va, flags); 1739 1740 /* Flush the real memory from the instruction cache. */ 1741 if (prot & VM_PROT_EXECUTE) 1742 sync++; 1743 } 1744 1745 if (sync && (su || pmap == PCPU_GET(curpmap))) { 1746 __syncicache((void *)va, PAGE_SIZE); 1747 sync = 0; 1748 } 1749} 1750 1751/* 1752 * Maps a sequence of resident pages belonging to the same object. 1753 * The sequence begins with the given page m_start. This page is 1754 * mapped at the given virtual address start. Each subsequent page is 1755 * mapped at a virtual address that is offset from start by the same 1756 * amount as the page is offset from m_start within the object. The 1757 * last page in the sequence is the page with the largest offset from 1758 * m_start that can be mapped at a virtual address less than the given 1759 * virtual address end. Not every virtual page between start and end 1760 * is mapped; only those for which a resident page exists with the 1761 * corresponding offset from m_start are mapped. 1762 */ 1763static void 1764mmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start, 1765 vm_offset_t end, vm_page_t m_start, vm_prot_t prot) 1766{ 1767 vm_page_t m; 1768 vm_pindex_t diff, psize; 1769 1770 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1771 1772 psize = atop(end - start); 1773 m = m_start; 1774 rw_wlock(&pvh_global_lock); 1775 PMAP_LOCK(pmap); 1776 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1777 mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m, 1778 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1779 m = TAILQ_NEXT(m, listq); 1780 } 1781 rw_wunlock(&pvh_global_lock); 1782 PMAP_UNLOCK(pmap); 1783} 1784 1785static void 1786mmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1787 vm_prot_t prot) 1788{ 1789 1790 rw_wlock(&pvh_global_lock); 1791 PMAP_LOCK(pmap); 1792 mmu_booke_enter_locked(mmu, pmap, va, m, 1793 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1794 rw_wunlock(&pvh_global_lock); 1795 PMAP_UNLOCK(pmap); 1796} 1797 1798/* 1799 * Remove the given range of addresses from the specified map. 1800 * 1801 * It is assumed that the start and end are properly rounded to the page size. 1802 */ 1803static void 1804mmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva) 1805{ 1806 pte_t *pte; 1807 uint8_t hold_flag; 1808 1809 int su = (pmap == kernel_pmap); 1810 1811 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n", 1812 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva); 1813 1814 if (su) { 1815 KASSERT(((va >= virtual_avail) && 1816 (va <= VM_MAX_KERNEL_ADDRESS)), 1817 ("mmu_booke_remove: kernel pmap, non kernel va")); 1818 } else { 1819 KASSERT((va <= VM_MAXUSER_ADDRESS), 1820 ("mmu_booke_remove: user pmap, non user va")); 1821 } 1822 1823 if (PMAP_REMOVE_DONE(pmap)) { 1824 //debugf("mmu_booke_remove: e (empty)\n"); 1825 return; 1826 } 1827 1828 hold_flag = PTBL_HOLD_FLAG(pmap); 1829 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag); 1830 1831 rw_wlock(&pvh_global_lock); 1832 PMAP_LOCK(pmap); 1833 for (; va < endva; va += PAGE_SIZE) { 1834 pte = pte_find(mmu, pmap, va); 1835 if ((pte != NULL) && PTE_ISVALID(pte)) 1836 pte_remove(mmu, pmap, va, hold_flag); 1837 } 1838 PMAP_UNLOCK(pmap); 1839 rw_wunlock(&pvh_global_lock); 1840 1841 //debugf("mmu_booke_remove: e\n"); 1842} 1843 1844/* 1845 * Remove physical page from all pmaps in which it resides. 1846 */ 1847static void 1848mmu_booke_remove_all(mmu_t mmu, vm_page_t m) 1849{ 1850 pv_entry_t pv, pvn; 1851 uint8_t hold_flag; 1852 1853 rw_wlock(&pvh_global_lock); 1854 for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) { 1855 pvn = TAILQ_NEXT(pv, pv_link); 1856 1857 PMAP_LOCK(pv->pv_pmap); 1858 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap); 1859 pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag); 1860 PMAP_UNLOCK(pv->pv_pmap); 1861 } 1862 vm_page_aflag_clear(m, PGA_WRITEABLE); 1863 rw_wunlock(&pvh_global_lock); 1864} 1865 1866/* 1867 * Map a range of physical addresses into kernel virtual address space. 1868 */ 1869static vm_offset_t 1870mmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1871 vm_paddr_t pa_end, int prot) 1872{ 1873 vm_offset_t sva = *virt; 1874 vm_offset_t va = sva; 1875 1876 //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n", 1877 // sva, pa_start, pa_end); 1878 1879 while (pa_start < pa_end) { 1880 mmu_booke_kenter(mmu, va, pa_start); 1881 va += PAGE_SIZE; 1882 pa_start += PAGE_SIZE; 1883 } 1884 *virt = va; 1885 1886 //debugf("mmu_booke_map: e (va = 0x%08x)\n", va); 1887 return (sva); 1888} 1889 1890/* 1891 * The pmap must be activated before it's address space can be accessed in any 1892 * way. 1893 */ 1894static void 1895mmu_booke_activate(mmu_t mmu, struct thread *td) 1896{ 1897 pmap_t pmap; 1898 u_int cpuid; 1899 1900 pmap = &td->td_proc->p_vmspace->vm_pmap; 1901 1902 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%08x)", 1903 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1904 1905 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!")); 1906 1907 sched_pin(); 1908 1909 cpuid = PCPU_GET(cpuid); 1910 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 1911 PCPU_SET(curpmap, pmap); 1912 1913 if (pmap->pm_tid[cpuid] == TID_NONE) 1914 tid_alloc(pmap); 1915 1916 /* Load PID0 register with pmap tid value. */ 1917 mtspr(SPR_PID0, pmap->pm_tid[cpuid]); 1918 __asm __volatile("isync"); 1919 1920 sched_unpin(); 1921 1922 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__, 1923 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm); 1924} 1925 1926/* 1927 * Deactivate the specified process's address space. 1928 */ 1929static void 1930mmu_booke_deactivate(mmu_t mmu, struct thread *td) 1931{ 1932 pmap_t pmap; 1933 1934 pmap = &td->td_proc->p_vmspace->vm_pmap; 1935 1936 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%08x", 1937 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1938 1939 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active); 1940 PCPU_SET(curpmap, NULL); 1941} 1942 1943/* 1944 * Copy the range specified by src_addr/len 1945 * from the source map to the range dst_addr/len 1946 * in the destination map. 1947 * 1948 * This routine is only advisory and need not do anything. 1949 */ 1950static void 1951mmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap, 1952 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr) 1953{ 1954 1955} 1956 1957/* 1958 * Set the physical protection on the specified range of this map as requested. 1959 */ 1960static void 1961mmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 1962 vm_prot_t prot) 1963{ 1964 vm_offset_t va; 1965 vm_page_t m; 1966 pte_t *pte; 1967 1968 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1969 mmu_booke_remove(mmu, pmap, sva, eva); 1970 return; 1971 } 1972 1973 if (prot & VM_PROT_WRITE) 1974 return; 1975 1976 PMAP_LOCK(pmap); 1977 for (va = sva; va < eva; va += PAGE_SIZE) { 1978 if ((pte = pte_find(mmu, pmap, va)) != NULL) { 1979 if (PTE_ISVALID(pte)) { 1980 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1981 1982 mtx_lock_spin(&tlbivax_mutex); 1983 tlb_miss_lock(); 1984 1985 /* Handle modified pages. */ 1986 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte)) 1987 vm_page_dirty(m); 1988 1989 tlb0_flush_entry(va); 1990 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 1991 1992 tlb_miss_unlock(); 1993 mtx_unlock_spin(&tlbivax_mutex); 1994 } 1995 } 1996 } 1997 PMAP_UNLOCK(pmap); 1998} 1999 2000/* 2001 * Clear the write and modified bits in each of the given page's mappings. 2002 */ 2003static void 2004mmu_booke_remove_write(mmu_t mmu, vm_page_t m) 2005{ 2006 pv_entry_t pv; 2007 pte_t *pte; 2008 2009 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2010 ("mmu_booke_remove_write: page %p is not managed", m)); 2011 2012 /* 2013 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 2014 * set by another thread while the object is locked. Thus, 2015 * if PGA_WRITEABLE is clear, no page table entries need updating. 2016 */ 2017 VM_OBJECT_ASSERT_WLOCKED(m->object); 2018 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 2019 return; 2020 rw_wlock(&pvh_global_lock); 2021 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2022 PMAP_LOCK(pv->pv_pmap); 2023 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2024 if (PTE_ISVALID(pte)) { 2025 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2026 2027 mtx_lock_spin(&tlbivax_mutex); 2028 tlb_miss_lock(); 2029 2030 /* Handle modified pages. */ 2031 if (PTE_ISMODIFIED(pte)) 2032 vm_page_dirty(m); 2033 2034 /* Flush mapping from TLB0. */ 2035 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 2036 2037 tlb_miss_unlock(); 2038 mtx_unlock_spin(&tlbivax_mutex); 2039 } 2040 } 2041 PMAP_UNLOCK(pv->pv_pmap); 2042 } 2043 vm_page_aflag_clear(m, PGA_WRITEABLE); 2044 rw_wunlock(&pvh_global_lock); 2045} 2046 2047static void 2048mmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2049{ 2050 pte_t *pte; 2051 pmap_t pmap; 2052 vm_page_t m; 2053 vm_offset_t addr; 2054 vm_paddr_t pa; 2055 int active, valid; 2056 2057 va = trunc_page(va); 2058 sz = round_page(sz); 2059 2060 rw_wlock(&pvh_global_lock); 2061 pmap = PCPU_GET(curpmap); 2062 active = (pm == kernel_pmap || pm == pmap) ? 1 : 0; 2063 while (sz > 0) { 2064 PMAP_LOCK(pm); 2065 pte = pte_find(mmu, pm, va); 2066 valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0; 2067 if (valid) 2068 pa = PTE_PA(pte); 2069 PMAP_UNLOCK(pm); 2070 if (valid) { 2071 if (!active) { 2072 /* Create a mapping in the active pmap. */ 2073 addr = 0; 2074 m = PHYS_TO_VM_PAGE(pa); 2075 PMAP_LOCK(pmap); 2076 pte_enter(mmu, pmap, m, addr, 2077 PTE_SR | PTE_VALID | PTE_UR); 2078 __syncicache((void *)addr, PAGE_SIZE); 2079 pte_remove(mmu, pmap, addr, PTBL_UNHOLD); 2080 PMAP_UNLOCK(pmap); 2081 } else 2082 __syncicache((void *)va, PAGE_SIZE); 2083 } 2084 va += PAGE_SIZE; 2085 sz -= PAGE_SIZE; 2086 } 2087 rw_wunlock(&pvh_global_lock); 2088} 2089 2090/* 2091 * Atomically extract and hold the physical page with the given 2092 * pmap and virtual address pair if that mapping permits the given 2093 * protection. 2094 */ 2095static vm_page_t 2096mmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, 2097 vm_prot_t prot) 2098{ 2099 pte_t *pte; 2100 vm_page_t m; 2101 uint32_t pte_wbit; 2102 vm_paddr_t pa; 2103 2104 m = NULL; 2105 pa = 0; 2106 PMAP_LOCK(pmap); 2107retry: 2108 pte = pte_find(mmu, pmap, va); 2109 if ((pte != NULL) && PTE_ISVALID(pte)) { 2110 if (pmap == kernel_pmap) 2111 pte_wbit = PTE_SW; 2112 else 2113 pte_wbit = PTE_UW; 2114 2115 if ((pte->flags & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) { 2116 if (vm_page_pa_tryrelock(pmap, PTE_PA(pte), &pa)) 2117 goto retry; 2118 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2119 vm_page_hold(m); 2120 } 2121 } 2122 2123 PA_UNLOCK_COND(pa); 2124 PMAP_UNLOCK(pmap); 2125 return (m); 2126} 2127 2128/* 2129 * Initialize a vm_page's machine-dependent fields. 2130 */ 2131static void 2132mmu_booke_page_init(mmu_t mmu, vm_page_t m) 2133{ 2134 2135 TAILQ_INIT(&m->md.pv_list); 2136} 2137 2138/* 2139 * mmu_booke_zero_page_area zeros the specified hardware page by 2140 * mapping it into virtual memory and using bzero to clear 2141 * its contents. 2142 * 2143 * off and size must reside within a single page. 2144 */ 2145static void 2146mmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 2147{ 2148 vm_offset_t va; 2149 2150 /* XXX KASSERT off and size are within a single page? */ 2151 2152 mtx_lock(&zero_page_mutex); 2153 va = zero_page_va; 2154 2155 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2156 bzero((caddr_t)va + off, size); 2157 mmu_booke_kremove(mmu, va); 2158 2159 mtx_unlock(&zero_page_mutex); 2160} 2161 2162/* 2163 * mmu_booke_zero_page zeros the specified hardware page. 2164 */ 2165static void 2166mmu_booke_zero_page(mmu_t mmu, vm_page_t m) 2167{ 2168 2169 mmu_booke_zero_page_area(mmu, m, 0, PAGE_SIZE); 2170} 2171 2172/* 2173 * mmu_booke_copy_page copies the specified (machine independent) page by 2174 * mapping the page into virtual memory and using memcopy to copy the page, 2175 * one machine dependent page at a time. 2176 */ 2177static void 2178mmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm) 2179{ 2180 vm_offset_t sva, dva; 2181 2182 sva = copy_page_src_va; 2183 dva = copy_page_dst_va; 2184 2185 mtx_lock(©_page_mutex); 2186 mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm)); 2187 mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm)); 2188 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE); 2189 mmu_booke_kremove(mmu, dva); 2190 mmu_booke_kremove(mmu, sva); 2191 mtx_unlock(©_page_mutex); 2192} 2193 2194static inline void 2195mmu_booke_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 2196 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 2197{ 2198 void *a_cp, *b_cp; 2199 vm_offset_t a_pg_offset, b_pg_offset; 2200 int cnt; 2201 2202 mtx_lock(©_page_mutex); 2203 while (xfersize > 0) { 2204 a_pg_offset = a_offset & PAGE_MASK; 2205 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 2206 mmu_booke_kenter(mmu, copy_page_src_va, 2207 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 2208 a_cp = (char *)copy_page_src_va + a_pg_offset; 2209 b_pg_offset = b_offset & PAGE_MASK; 2210 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 2211 mmu_booke_kenter(mmu, copy_page_dst_va, 2212 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 2213 b_cp = (char *)copy_page_dst_va + b_pg_offset; 2214 bcopy(a_cp, b_cp, cnt); 2215 mmu_booke_kremove(mmu, copy_page_dst_va); 2216 mmu_booke_kremove(mmu, copy_page_src_va); 2217 a_offset += cnt; 2218 b_offset += cnt; 2219 xfersize -= cnt; 2220 } 2221 mtx_unlock(©_page_mutex); 2222} 2223 2224/* 2225 * mmu_booke_zero_page_idle zeros the specified hardware page by mapping it 2226 * into virtual memory and using bzero to clear its contents. This is intended 2227 * to be called from the vm_pagezero process only and outside of Giant. No 2228 * lock is required. 2229 */ 2230static void 2231mmu_booke_zero_page_idle(mmu_t mmu, vm_page_t m) 2232{ 2233 vm_offset_t va; 2234 2235 va = zero_page_idle_va; 2236 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2237 bzero((caddr_t)va, PAGE_SIZE); 2238 mmu_booke_kremove(mmu, va); 2239} 2240 2241/* 2242 * Return whether or not the specified physical page was modified 2243 * in any of physical maps. 2244 */ 2245static boolean_t 2246mmu_booke_is_modified(mmu_t mmu, vm_page_t m) 2247{ 2248 pte_t *pte; 2249 pv_entry_t pv; 2250 boolean_t rv; 2251 2252 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2253 ("mmu_booke_is_modified: page %p is not managed", m)); 2254 rv = FALSE; 2255 2256 /* 2257 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 2258 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 2259 * is clear, no PTEs can be modified. 2260 */ 2261 VM_OBJECT_ASSERT_WLOCKED(m->object); 2262 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 2263 return (rv); 2264 rw_wlock(&pvh_global_lock); 2265 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2266 PMAP_LOCK(pv->pv_pmap); 2267 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2268 PTE_ISVALID(pte)) { 2269 if (PTE_ISMODIFIED(pte)) 2270 rv = TRUE; 2271 } 2272 PMAP_UNLOCK(pv->pv_pmap); 2273 if (rv) 2274 break; 2275 } 2276 rw_wunlock(&pvh_global_lock); 2277 return (rv); 2278} 2279 2280/* 2281 * Return whether or not the specified virtual address is eligible 2282 * for prefault. 2283 */ 2284static boolean_t 2285mmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr) 2286{ 2287 2288 return (FALSE); 2289} 2290 2291/* 2292 * Return whether or not the specified physical page was referenced 2293 * in any physical maps. 2294 */ 2295static boolean_t 2296mmu_booke_is_referenced(mmu_t mmu, vm_page_t m) 2297{ 2298 pte_t *pte; 2299 pv_entry_t pv; 2300 boolean_t rv; 2301 2302 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2303 ("mmu_booke_is_referenced: page %p is not managed", m)); 2304 rv = FALSE; 2305 rw_wlock(&pvh_global_lock); 2306 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2307 PMAP_LOCK(pv->pv_pmap); 2308 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2309 PTE_ISVALID(pte)) { 2310 if (PTE_ISREFERENCED(pte)) 2311 rv = TRUE; 2312 } 2313 PMAP_UNLOCK(pv->pv_pmap); 2314 if (rv) 2315 break; 2316 } 2317 rw_wunlock(&pvh_global_lock); 2318 return (rv); 2319} 2320 2321/* 2322 * Clear the modify bits on the specified physical page. 2323 */ 2324static void 2325mmu_booke_clear_modify(mmu_t mmu, vm_page_t m) 2326{ 2327 pte_t *pte; 2328 pv_entry_t pv; 2329 2330 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2331 ("mmu_booke_clear_modify: page %p is not managed", m)); 2332 VM_OBJECT_ASSERT_WLOCKED(m->object); 2333 KASSERT(!vm_page_xbusied(m), 2334 ("mmu_booke_clear_modify: page %p is exclusive busied", m)); 2335 2336 /* 2337 * If the page is not PG_AWRITEABLE, then no PTEs can be modified. 2338 * If the object containing the page is locked and the page is not 2339 * exclusive busied, then PG_AWRITEABLE cannot be concurrently set. 2340 */ 2341 if ((m->aflags & PGA_WRITEABLE) == 0) 2342 return; 2343 rw_wlock(&pvh_global_lock); 2344 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2345 PMAP_LOCK(pv->pv_pmap); 2346 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2347 PTE_ISVALID(pte)) { 2348 mtx_lock_spin(&tlbivax_mutex); 2349 tlb_miss_lock(); 2350 2351 if (pte->flags & (PTE_SW | PTE_UW | PTE_MODIFIED)) { 2352 tlb0_flush_entry(pv->pv_va); 2353 pte->flags &= ~(PTE_SW | PTE_UW | PTE_MODIFIED | 2354 PTE_REFERENCED); 2355 } 2356 2357 tlb_miss_unlock(); 2358 mtx_unlock_spin(&tlbivax_mutex); 2359 } 2360 PMAP_UNLOCK(pv->pv_pmap); 2361 } 2362 rw_wunlock(&pvh_global_lock); 2363} 2364 2365/* 2366 * Return a count of reference bits for a page, clearing those bits. 2367 * It is not necessary for every reference bit to be cleared, but it 2368 * is necessary that 0 only be returned when there are truly no 2369 * reference bits set. 2370 * 2371 * XXX: The exact number of bits to check and clear is a matter that 2372 * should be tested and standardized at some point in the future for 2373 * optimal aging of shared pages. 2374 */ 2375static int 2376mmu_booke_ts_referenced(mmu_t mmu, vm_page_t m) 2377{ 2378 pte_t *pte; 2379 pv_entry_t pv; 2380 int count; 2381 2382 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2383 ("mmu_booke_ts_referenced: page %p is not managed", m)); 2384 count = 0; 2385 rw_wlock(&pvh_global_lock); 2386 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2387 PMAP_LOCK(pv->pv_pmap); 2388 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2389 PTE_ISVALID(pte)) { 2390 if (PTE_ISREFERENCED(pte)) { 2391 mtx_lock_spin(&tlbivax_mutex); 2392 tlb_miss_lock(); 2393 2394 tlb0_flush_entry(pv->pv_va); 2395 pte->flags &= ~PTE_REFERENCED; 2396 2397 tlb_miss_unlock(); 2398 mtx_unlock_spin(&tlbivax_mutex); 2399 2400 if (++count > 4) { 2401 PMAP_UNLOCK(pv->pv_pmap); 2402 break; 2403 } 2404 } 2405 } 2406 PMAP_UNLOCK(pv->pv_pmap); 2407 } 2408 rw_wunlock(&pvh_global_lock); 2409 return (count); 2410} 2411 2412/* 2413 * Change wiring attribute for a map/virtual-address pair. 2414 */ 2415static void 2416mmu_booke_change_wiring(mmu_t mmu, pmap_t pmap, vm_offset_t va, boolean_t wired) 2417{ 2418 pte_t *pte; 2419 2420 PMAP_LOCK(pmap); 2421 if ((pte = pte_find(mmu, pmap, va)) != NULL) { 2422 if (wired) { 2423 if (!PTE_ISWIRED(pte)) { 2424 pte->flags |= PTE_WIRED; 2425 pmap->pm_stats.wired_count++; 2426 } 2427 } else { 2428 if (PTE_ISWIRED(pte)) { 2429 pte->flags &= ~PTE_WIRED; 2430 pmap->pm_stats.wired_count--; 2431 } 2432 } 2433 } 2434 PMAP_UNLOCK(pmap); 2435} 2436 2437/* 2438 * Return true if the pmap's pv is one of the first 16 pvs linked to from this 2439 * page. This count may be changed upwards or downwards in the future; it is 2440 * only necessary that true be returned for a small subset of pmaps for proper 2441 * page aging. 2442 */ 2443static boolean_t 2444mmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2445{ 2446 pv_entry_t pv; 2447 int loops; 2448 boolean_t rv; 2449 2450 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2451 ("mmu_booke_page_exists_quick: page %p is not managed", m)); 2452 loops = 0; 2453 rv = FALSE; 2454 rw_wlock(&pvh_global_lock); 2455 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2456 if (pv->pv_pmap == pmap) { 2457 rv = TRUE; 2458 break; 2459 } 2460 if (++loops >= 16) 2461 break; 2462 } 2463 rw_wunlock(&pvh_global_lock); 2464 return (rv); 2465} 2466 2467/* 2468 * Return the number of managed mappings to the given physical page that are 2469 * wired. 2470 */ 2471static int 2472mmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m) 2473{ 2474 pv_entry_t pv; 2475 pte_t *pte; 2476 int count = 0; 2477 2478 if ((m->oflags & VPO_UNMANAGED) != 0) 2479 return (count); 2480 rw_wlock(&pvh_global_lock); 2481 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2482 PMAP_LOCK(pv->pv_pmap); 2483 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) 2484 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte)) 2485 count++; 2486 PMAP_UNLOCK(pv->pv_pmap); 2487 } 2488 rw_wunlock(&pvh_global_lock); 2489 return (count); 2490} 2491 2492static int 2493mmu_booke_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2494{ 2495 int i; 2496 vm_offset_t va; 2497 2498 /* 2499 * This currently does not work for entries that 2500 * overlap TLB1 entries. 2501 */ 2502 for (i = 0; i < tlb1_idx; i ++) { 2503 if (tlb1_iomapped(i, pa, size, &va) == 0) 2504 return (0); 2505 } 2506 2507 return (EFAULT); 2508} 2509 2510vm_offset_t 2511mmu_booke_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 2512 vm_size_t *sz) 2513{ 2514 vm_paddr_t pa, ppa; 2515 vm_offset_t va; 2516 vm_size_t gran; 2517 2518 /* Raw physical memory dumps don't have a virtual address. */ 2519 if (md->md_vaddr == ~0UL) { 2520 /* We always map a 256MB page at 256M. */ 2521 gran = 256 * 1024 * 1024; 2522 pa = md->md_paddr + ofs; 2523 ppa = pa & ~(gran - 1); 2524 ofs = pa - ppa; 2525 va = gran; 2526 tlb1_set_entry(va, ppa, gran, _TLB_ENTRY_IO); 2527 if (*sz > (gran - ofs)) 2528 *sz = gran - ofs; 2529 return (va + ofs); 2530 } 2531 2532 /* Minidumps are based on virtual memory addresses. */ 2533 va = md->md_vaddr + ofs; 2534 if (va >= kernstart + kernsize) { 2535 gran = PAGE_SIZE - (va & PAGE_MASK); 2536 if (*sz > gran) 2537 *sz = gran; 2538 } 2539 return (va); 2540} 2541 2542void 2543mmu_booke_dumpsys_unmap(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 2544 vm_offset_t va) 2545{ 2546 2547 /* Raw physical memory dumps don't have a virtual address. */ 2548 if (md->md_vaddr == ~0UL) { 2549 tlb1_idx--; 2550 tlb1[tlb1_idx].mas1 = 0; 2551 tlb1[tlb1_idx].mas2 = 0; 2552 tlb1[tlb1_idx].mas3 = 0; 2553 tlb1_write_entry(tlb1_idx); 2554 return; 2555 } 2556 2557 /* Minidumps are based on virtual memory addresses. */ 2558 /* Nothing to do... */ 2559} 2560 2561struct pmap_md * 2562mmu_booke_scan_md(mmu_t mmu, struct pmap_md *prev) 2563{ 2564 static struct pmap_md md; 2565 pte_t *pte; 2566 vm_offset_t va; 2567 2568 if (dumpsys_minidump) { 2569 md.md_paddr = ~0UL; /* Minidumps use virtual addresses. */ 2570 if (prev == NULL) { 2571 /* 1st: kernel .data and .bss. */ 2572 md.md_index = 1; 2573 md.md_vaddr = trunc_page((uintptr_t)_etext); 2574 md.md_size = round_page((uintptr_t)_end) - md.md_vaddr; 2575 return (&md); 2576 } 2577 switch (prev->md_index) { 2578 case 1: 2579 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2580 md.md_index = 2; 2581 md.md_vaddr = data_start; 2582 md.md_size = data_end - data_start; 2583 break; 2584 case 2: 2585 /* 3rd: kernel VM. */ 2586 va = prev->md_vaddr + prev->md_size; 2587 /* Find start of next chunk (from va). */ 2588 while (va < virtual_end) { 2589 /* Don't dump the buffer cache. */ 2590 if (va >= kmi.buffer_sva && 2591 va < kmi.buffer_eva) { 2592 va = kmi.buffer_eva; 2593 continue; 2594 } 2595 pte = pte_find(mmu, kernel_pmap, va); 2596 if (pte != NULL && PTE_ISVALID(pte)) 2597 break; 2598 va += PAGE_SIZE; 2599 } 2600 if (va < virtual_end) { 2601 md.md_vaddr = va; 2602 va += PAGE_SIZE; 2603 /* Find last page in chunk. */ 2604 while (va < virtual_end) { 2605 /* Don't run into the buffer cache. */ 2606 if (va == kmi.buffer_sva) 2607 break; 2608 pte = pte_find(mmu, kernel_pmap, va); 2609 if (pte == NULL || !PTE_ISVALID(pte)) 2610 break; 2611 va += PAGE_SIZE; 2612 } 2613 md.md_size = va - md.md_vaddr; 2614 break; 2615 } 2616 md.md_index = 3; 2617 /* FALLTHROUGH */ 2618 default: 2619 return (NULL); 2620 } 2621 } else { /* minidumps */ 2622 mem_regions(&physmem_regions, &physmem_regions_sz, 2623 &availmem_regions, &availmem_regions_sz); 2624 2625 if (prev == NULL) { 2626 /* first physical chunk. */ 2627 md.md_paddr = physmem_regions[0].mr_start; 2628 md.md_size = physmem_regions[0].mr_size; 2629 md.md_vaddr = ~0UL; 2630 md.md_index = 1; 2631 } else if (md.md_index < physmem_regions_sz) { 2632 md.md_paddr = physmem_regions[md.md_index].mr_start; 2633 md.md_size = physmem_regions[md.md_index].mr_size; 2634 md.md_vaddr = ~0UL; 2635 md.md_index++; 2636 } else { 2637 /* There's no next physical chunk. */ 2638 return (NULL); 2639 } 2640 } 2641 2642 return (&md); 2643} 2644 2645/* 2646 * Map a set of physical memory pages into the kernel virtual address space. 2647 * Return a pointer to where it is mapped. This routine is intended to be used 2648 * for mapping device memory, NOT real memory. 2649 */ 2650static void * 2651mmu_booke_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2652{ 2653 2654 return (mmu_booke_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 2655} 2656 2657static void * 2658mmu_booke_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2659{ 2660 void *res; 2661 uintptr_t va; 2662 vm_size_t sz; 2663 int i; 2664 2665 /* 2666 * Check if this is premapped in TLB1. Note: this should probably also 2667 * check whether a sequence of TLB1 entries exist that match the 2668 * requirement, but now only checks the easy case. 2669 */ 2670 if (ma == VM_MEMATTR_DEFAULT) { 2671 for (i = 0; i < tlb1_idx; i++) { 2672 if (!(tlb1[i].mas1 & MAS1_VALID)) 2673 continue; 2674 if (pa >= tlb1[i].phys && 2675 (pa + size) <= (tlb1[i].phys + tlb1[i].size)) 2676 return (void *)(tlb1[i].virt + 2677 (pa - tlb1[i].phys)); 2678 } 2679 } 2680 2681 size = roundup(size, PAGE_SIZE); 2682 2683 /* 2684 * We leave a hole for device direct mapping between the maximum user 2685 * address (0x8000000) and the minimum KVA address (0xc0000000). If 2686 * devices are in there, just map them 1:1. If not, map them to the 2687 * device mapping area about VM_MAX_KERNEL_ADDRESS. These mapped 2688 * addresses should be pulled from an allocator, but since we do not 2689 * ever free TLB1 entries, it is safe just to increment a counter. 2690 * Note that there isn't a lot of address space here (128 MB) and it 2691 * is not at all difficult to imagine running out, since that is a 4:1 2692 * compression from the 0xc0000000 - 0xf0000000 address space that gets 2693 * mapped there. 2694 */ 2695 if (pa >= (VM_MAXUSER_ADDRESS + PAGE_SIZE) && 2696 (pa + size - 1) < VM_MIN_KERNEL_ADDRESS) 2697 va = pa; 2698 else 2699 va = atomic_fetchadd_int(&tlb1_map_base, size); 2700 res = (void *)va; 2701 2702 do { 2703 sz = 1 << (ilog2(size) & ~1); 2704 if (bootverbose) 2705 printf("Wiring VA=%x to PA=%x (size=%x), " 2706 "using TLB1[%d]\n", va, pa, sz, tlb1_idx); 2707 tlb1_set_entry(va, pa, sz, tlb_calc_wimg(pa, ma)); 2708 size -= sz; 2709 pa += sz; 2710 va += sz; 2711 } while (size > 0); 2712 2713 return (res); 2714} 2715 2716/* 2717 * 'Unmap' a range mapped by mmu_booke_mapdev(). 2718 */ 2719static void 2720mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2721{ 2722#ifdef SUPPORTS_SHRINKING_TLB1 2723 vm_offset_t base, offset; 2724 2725 /* 2726 * Unmap only if this is inside kernel virtual space. 2727 */ 2728 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2729 base = trunc_page(va); 2730 offset = va & PAGE_MASK; 2731 size = roundup(offset + size, PAGE_SIZE); 2732 kva_free(base, size); 2733 } 2734#endif 2735} 2736 2737/* 2738 * mmu_booke_object_init_pt preloads the ptes for a given object into the 2739 * specified pmap. This eliminates the blast of soft faults on process startup 2740 * and immediately after an mmap. 2741 */ 2742static void 2743mmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2744 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2745{ 2746 2747 VM_OBJECT_ASSERT_WLOCKED(object); 2748 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2749 ("mmu_booke_object_init_pt: non-device object")); 2750} 2751 2752/* 2753 * Perform the pmap work for mincore. 2754 */ 2755static int 2756mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2757 vm_paddr_t *locked_pa) 2758{ 2759 2760 /* XXX: this should be implemented at some point */ 2761 return (0); 2762} 2763 2764/**************************************************************************/ 2765/* TID handling */ 2766/**************************************************************************/ 2767 2768/* 2769 * Allocate a TID. If necessary, steal one from someone else. 2770 * The new TID is flushed from the TLB before returning. 2771 */ 2772static tlbtid_t 2773tid_alloc(pmap_t pmap) 2774{ 2775 tlbtid_t tid; 2776 int thiscpu; 2777 2778 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap")); 2779 2780 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap); 2781 2782 thiscpu = PCPU_GET(cpuid); 2783 2784 tid = PCPU_GET(tid_next); 2785 if (tid > TID_MAX) 2786 tid = TID_MIN; 2787 PCPU_SET(tid_next, tid + 1); 2788 2789 /* If we are stealing TID then clear the relevant pmap's field */ 2790 if (tidbusy[thiscpu][tid] != NULL) { 2791 2792 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid); 2793 2794 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE; 2795 2796 /* Flush all entries from TLB0 matching this TID. */ 2797 tid_flush(tid); 2798 } 2799 2800 tidbusy[thiscpu][tid] = pmap; 2801 pmap->pm_tid[thiscpu] = tid; 2802 __asm __volatile("msync; isync"); 2803 2804 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid, 2805 PCPU_GET(tid_next)); 2806 2807 return (tid); 2808} 2809 2810/**************************************************************************/ 2811/* TLB0 handling */ 2812/**************************************************************************/ 2813 2814static void 2815tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3, 2816 uint32_t mas7) 2817{ 2818 int as; 2819 char desc[3]; 2820 tlbtid_t tid; 2821 vm_size_t size; 2822 unsigned int tsize; 2823 2824 desc[2] = '\0'; 2825 if (mas1 & MAS1_VALID) 2826 desc[0] = 'V'; 2827 else 2828 desc[0] = ' '; 2829 2830 if (mas1 & MAS1_IPROT) 2831 desc[1] = 'P'; 2832 else 2833 desc[1] = ' '; 2834 2835 as = (mas1 & MAS1_TS_MASK) ? 1 : 0; 2836 tid = MAS1_GETTID(mas1); 2837 2838 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 2839 size = 0; 2840 if (tsize) 2841 size = tsize2size(tsize); 2842 2843 debugf("%3d: (%s) [AS=%d] " 2844 "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x " 2845 "mas2(va) = 0x%08x mas3(pa) = 0x%08x mas7 = 0x%08x\n", 2846 i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7); 2847} 2848 2849/* Convert TLB0 va and way number to tlb0[] table index. */ 2850static inline unsigned int 2851tlb0_tableidx(vm_offset_t va, unsigned int way) 2852{ 2853 unsigned int idx; 2854 2855 idx = (way * TLB0_ENTRIES_PER_WAY); 2856 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT; 2857 return (idx); 2858} 2859 2860/* 2861 * Invalidate TLB0 entry. 2862 */ 2863static inline void 2864tlb0_flush_entry(vm_offset_t va) 2865{ 2866 2867 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va); 2868 2869 mtx_assert(&tlbivax_mutex, MA_OWNED); 2870 2871 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK)); 2872 __asm __volatile("isync; msync"); 2873 __asm __volatile("tlbsync; msync"); 2874 2875 CTR1(KTR_PMAP, "%s: e", __func__); 2876} 2877 2878/* Print out contents of the MAS registers for each TLB0 entry */ 2879void 2880tlb0_print_tlbentries(void) 2881{ 2882 uint32_t mas0, mas1, mas2, mas3, mas7; 2883 int entryidx, way, idx; 2884 2885 debugf("TLB0 entries:\n"); 2886 for (way = 0; way < TLB0_WAYS; way ++) 2887 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) { 2888 2889 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 2890 mtspr(SPR_MAS0, mas0); 2891 __asm __volatile("isync"); 2892 2893 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT; 2894 mtspr(SPR_MAS2, mas2); 2895 2896 __asm __volatile("isync; tlbre"); 2897 2898 mas1 = mfspr(SPR_MAS1); 2899 mas2 = mfspr(SPR_MAS2); 2900 mas3 = mfspr(SPR_MAS3); 2901 mas7 = mfspr(SPR_MAS7); 2902 2903 idx = tlb0_tableidx(mas2, way); 2904 tlb_print_entry(idx, mas1, mas2, mas3, mas7); 2905 } 2906} 2907 2908/**************************************************************************/ 2909/* TLB1 handling */ 2910/**************************************************************************/ 2911 2912/* 2913 * TLB1 mapping notes: 2914 * 2915 * TLB1[0] Kernel text and data. 2916 * TLB1[1-15] Additional kernel text and data mappings (if required), PCI 2917 * windows, other devices mappings. 2918 */ 2919 2920/* 2921 * Write given entry to TLB1 hardware. 2922 * Use 32 bit pa, clear 4 high-order bits of RPN (mas7). 2923 */ 2924static void 2925tlb1_write_entry(unsigned int idx) 2926{ 2927 uint32_t mas0, mas7; 2928 2929 //debugf("tlb1_write_entry: s\n"); 2930 2931 /* Clear high order RPN bits */ 2932 mas7 = 0; 2933 2934 /* Select entry */ 2935 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx); 2936 //debugf("tlb1_write_entry: mas0 = 0x%08x\n", mas0); 2937 2938 mtspr(SPR_MAS0, mas0); 2939 __asm __volatile("isync"); 2940 mtspr(SPR_MAS1, tlb1[idx].mas1); 2941 __asm __volatile("isync"); 2942 mtspr(SPR_MAS2, tlb1[idx].mas2); 2943 __asm __volatile("isync"); 2944 mtspr(SPR_MAS3, tlb1[idx].mas3); 2945 __asm __volatile("isync"); 2946 mtspr(SPR_MAS7, mas7); 2947 __asm __volatile("isync; tlbwe; isync; msync"); 2948 2949 //debugf("tlb1_write_entry: e\n"); 2950} 2951 2952/* 2953 * Return the largest uint value log such that 2^log <= num. 2954 */ 2955static unsigned int 2956ilog2(unsigned int num) 2957{ 2958 int lz; 2959 2960 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num)); 2961 return (31 - lz); 2962} 2963 2964/* 2965 * Convert TLB TSIZE value to mapped region size. 2966 */ 2967static vm_size_t 2968tsize2size(unsigned int tsize) 2969{ 2970 2971 /* 2972 * size = 4^tsize KB 2973 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10) 2974 */ 2975 2976 return ((1 << (2 * tsize)) * 1024); 2977} 2978 2979/* 2980 * Convert region size (must be power of 4) to TLB TSIZE value. 2981 */ 2982static unsigned int 2983size2tsize(vm_size_t size) 2984{ 2985 2986 return (ilog2(size) / 2 - 5); 2987} 2988 2989/* 2990 * Register permanent kernel mapping in TLB1. 2991 * 2992 * Entries are created starting from index 0 (current free entry is 2993 * kept in tlb1_idx) and are not supposed to be invalidated. 2994 */ 2995static int 2996tlb1_set_entry(vm_offset_t va, vm_offset_t pa, vm_size_t size, 2997 uint32_t flags) 2998{ 2999 uint32_t ts, tid; 3000 int tsize, index; 3001 3002 index = atomic_fetchadd_int(&tlb1_idx, 1); 3003 if (index >= TLB1_ENTRIES) { 3004 printf("tlb1_set_entry: TLB1 full!\n"); 3005 return (-1); 3006 } 3007 3008 /* Convert size to TSIZE */ 3009 tsize = size2tsize(size); 3010 3011 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK; 3012 /* XXX TS is hard coded to 0 for now as we only use single address space */ 3013 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK; 3014 3015 /* 3016 * Atomicity is preserved by the atomic increment above since nothing 3017 * is ever removed from tlb1. 3018 */ 3019 3020 tlb1[index].phys = pa; 3021 tlb1[index].virt = va; 3022 tlb1[index].size = size; 3023 tlb1[index].mas1 = MAS1_VALID | MAS1_IPROT | ts | tid; 3024 tlb1[index].mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK); 3025 tlb1[index].mas2 = (va & MAS2_EPN_MASK) | flags; 3026 3027 /* Set supervisor RWX permission bits */ 3028 tlb1[index].mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX; 3029 3030 tlb1_write_entry(index); 3031 3032 /* 3033 * XXX in general TLB1 updates should be propagated between CPUs, 3034 * since current design assumes to have the same TLB1 set-up on all 3035 * cores. 3036 */ 3037 return (0); 3038} 3039 3040/* 3041 * Map in contiguous RAM region into the TLB1 using maximum of 3042 * KERNEL_REGION_MAX_TLB_ENTRIES entries. 3043 * 3044 * If necessary round up last entry size and return total size 3045 * used by all allocated entries. 3046 */ 3047vm_size_t 3048tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size) 3049{ 3050 vm_size_t pgs[KERNEL_REGION_MAX_TLB_ENTRIES]; 3051 vm_size_t mapped, pgsz, base, mask; 3052 int idx, nents; 3053 3054 /* Round up to the next 1M */ 3055 size = (size + (1 << 20) - 1) & ~((1 << 20) - 1); 3056 3057 mapped = 0; 3058 idx = 0; 3059 base = va; 3060 pgsz = 64*1024*1024; 3061 while (mapped < size) { 3062 while (mapped < size && idx < KERNEL_REGION_MAX_TLB_ENTRIES) { 3063 while (pgsz > (size - mapped)) 3064 pgsz >>= 2; 3065 pgs[idx++] = pgsz; 3066 mapped += pgsz; 3067 } 3068 3069 /* We under-map. Correct for this. */ 3070 if (mapped < size) { 3071 while (pgs[idx - 1] == pgsz) { 3072 idx--; 3073 mapped -= pgsz; 3074 } 3075 /* XXX We may increase beyond out starting point. */ 3076 pgsz <<= 2; 3077 pgs[idx++] = pgsz; 3078 mapped += pgsz; 3079 } 3080 } 3081 3082 nents = idx; 3083 mask = pgs[0] - 1; 3084 /* Align address to the boundary */ 3085 if (va & mask) { 3086 va = (va + mask) & ~mask; 3087 pa = (pa + mask) & ~mask; 3088 } 3089 3090 for (idx = 0; idx < nents; idx++) { 3091 pgsz = pgs[idx]; 3092 debugf("%u: %x -> %x, size=%x\n", idx, pa, va, pgsz); 3093 tlb1_set_entry(va, pa, pgsz, _TLB_ENTRY_MEM); 3094 pa += pgsz; 3095 va += pgsz; 3096 } 3097 3098 mapped = (va - base); 3099 printf("mapped size 0x%08x (wasted space 0x%08x)\n", 3100 mapped, mapped - size); 3101 return (mapped); 3102} 3103 3104/* 3105 * TLB1 initialization routine, to be called after the very first 3106 * assembler level setup done in locore.S. 3107 */ 3108void 3109tlb1_init() 3110{ 3111 uint32_t mas0, mas1, mas2, mas3; 3112 uint32_t tsz; 3113 u_int i; 3114 3115 if (bootinfo != NULL && bootinfo[0] != 1) { 3116 tlb1_idx = *((uint16_t *)(bootinfo + 8)); 3117 } else 3118 tlb1_idx = 1; 3119 3120 /* The first entry/entries are used to map the kernel. */ 3121 for (i = 0; i < tlb1_idx; i++) { 3122 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3123 mtspr(SPR_MAS0, mas0); 3124 __asm __volatile("isync; tlbre"); 3125 3126 mas1 = mfspr(SPR_MAS1); 3127 if ((mas1 & MAS1_VALID) == 0) 3128 continue; 3129 3130 mas2 = mfspr(SPR_MAS2); 3131 mas3 = mfspr(SPR_MAS3); 3132 3133 tlb1[i].mas1 = mas1; 3134 tlb1[i].mas2 = mfspr(SPR_MAS2); 3135 tlb1[i].mas3 = mas3; 3136 tlb1[i].virt = mas2 & MAS2_EPN_MASK; 3137 tlb1[i].phys = mas3 & MAS3_RPN; 3138 3139 if (i == 0) 3140 kernload = mas3 & MAS3_RPN; 3141 3142 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3143 tlb1[i].size = (tsz > 0) ? tsize2size(tsz) : 0; 3144 kernsize += tlb1[i].size; 3145 } 3146 3147#ifdef SMP 3148 bp_ntlb1s = tlb1_idx; 3149#endif 3150 3151 /* Purge the remaining entries */ 3152 for (i = tlb1_idx; i < TLB1_ENTRIES; i++) 3153 tlb1_write_entry(i); 3154 3155 /* Setup TLB miss defaults */ 3156 set_mas4_defaults(); 3157} 3158 3159vm_offset_t 3160pmap_early_io_map(vm_paddr_t pa, vm_size_t size) 3161{ 3162 vm_paddr_t pa_base; 3163 vm_offset_t va, sz; 3164 int i; 3165 3166 KASSERT(!pmap_bootstrapped, ("Do not use after PMAP is up!")); 3167 3168 for (i = 0; i < tlb1_idx; i++) { 3169 if (!(tlb1[i].mas1 & MAS1_VALID)) 3170 continue; 3171 if (pa >= tlb1[i].phys && (pa + size) <= 3172 (tlb1[i].phys + tlb1[i].size)) 3173 return (tlb1[i].virt + (pa - tlb1[i].phys)); 3174 } 3175 3176 pa_base = trunc_page(pa); 3177 size = roundup(size + (pa - pa_base), PAGE_SIZE); 3178 tlb1_map_base = roundup2(tlb1_map_base, 1 << (ilog2(size) & ~1)); 3179 va = tlb1_map_base + (pa - pa_base); 3180 3181 do { 3182 sz = 1 << (ilog2(size) & ~1); 3183 tlb1_set_entry(tlb1_map_base, pa_base, sz, _TLB_ENTRY_IO); 3184 size -= sz; 3185 pa_base += sz; 3186 tlb1_map_base += sz; 3187 } while (size > 0); 3188 3189#ifdef SMP 3190 bp_ntlb1s = tlb1_idx; 3191#endif 3192 3193 return (va); 3194} 3195 3196/* 3197 * Setup MAS4 defaults. 3198 * These values are loaded to MAS0-2 on a TLB miss. 3199 */ 3200static void 3201set_mas4_defaults(void) 3202{ 3203 uint32_t mas4; 3204 3205 /* Defaults: TLB0, PID0, TSIZED=4K */ 3206 mas4 = MAS4_TLBSELD0; 3207 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK; 3208#ifdef SMP 3209 mas4 |= MAS4_MD; 3210#endif 3211 mtspr(SPR_MAS4, mas4); 3212 __asm __volatile("isync"); 3213} 3214 3215/* 3216 * Print out contents of the MAS registers for each TLB1 entry 3217 */ 3218void 3219tlb1_print_tlbentries(void) 3220{ 3221 uint32_t mas0, mas1, mas2, mas3, mas7; 3222 int i; 3223 3224 debugf("TLB1 entries:\n"); 3225 for (i = 0; i < TLB1_ENTRIES; i++) { 3226 3227 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3228 mtspr(SPR_MAS0, mas0); 3229 3230 __asm __volatile("isync; tlbre"); 3231 3232 mas1 = mfspr(SPR_MAS1); 3233 mas2 = mfspr(SPR_MAS2); 3234 mas3 = mfspr(SPR_MAS3); 3235 mas7 = mfspr(SPR_MAS7); 3236 3237 tlb_print_entry(i, mas1, mas2, mas3, mas7); 3238 } 3239} 3240 3241/* 3242 * Print out contents of the in-ram tlb1 table. 3243 */ 3244void 3245tlb1_print_entries(void) 3246{ 3247 int i; 3248 3249 debugf("tlb1[] table entries:\n"); 3250 for (i = 0; i < TLB1_ENTRIES; i++) 3251 tlb_print_entry(i, tlb1[i].mas1, tlb1[i].mas2, tlb1[i].mas3, 0); 3252} 3253 3254/* 3255 * Return 0 if the physical IO range is encompassed by one of the 3256 * the TLB1 entries, otherwise return related error code. 3257 */ 3258static int 3259tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va) 3260{ 3261 uint32_t prot; 3262 vm_paddr_t pa_start; 3263 vm_paddr_t pa_end; 3264 unsigned int entry_tsize; 3265 vm_size_t entry_size; 3266 3267 *va = (vm_offset_t)NULL; 3268 3269 /* Skip invalid entries */ 3270 if (!(tlb1[i].mas1 & MAS1_VALID)) 3271 return (EINVAL); 3272 3273 /* 3274 * The entry must be cache-inhibited, guarded, and r/w 3275 * so it can function as an i/o page 3276 */ 3277 prot = tlb1[i].mas2 & (MAS2_I | MAS2_G); 3278 if (prot != (MAS2_I | MAS2_G)) 3279 return (EPERM); 3280 3281 prot = tlb1[i].mas3 & (MAS3_SR | MAS3_SW); 3282 if (prot != (MAS3_SR | MAS3_SW)) 3283 return (EPERM); 3284 3285 /* The address should be within the entry range. */ 3286 entry_tsize = (tlb1[i].mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3287 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize")); 3288 3289 entry_size = tsize2size(entry_tsize); 3290 pa_start = tlb1[i].mas3 & MAS3_RPN; 3291 pa_end = pa_start + entry_size - 1; 3292 3293 if ((pa < pa_start) || ((pa + size) > pa_end)) 3294 return (ERANGE); 3295 3296 /* Return virtual address of this mapping. */ 3297 *va = (tlb1[i].mas2 & MAS2_EPN_MASK) + (pa - pa_start); 3298 return (0); 3299} 3300