pmap.c revision 265998
1/*- 2 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * Some hw specific parts of this pmap were derived or influenced 27 * by NetBSD's ibm4xx pmap module. More generic code is shared with 28 * a few other pmap modules from the FreeBSD tree. 29 */ 30 31 /* 32 * VM layout notes: 33 * 34 * Kernel and user threads run within one common virtual address space 35 * defined by AS=0. 36 * 37 * Virtual address space layout: 38 * ----------------------------- 39 * 0x0000_0000 - 0xafff_ffff : user process 40 * 0xb000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.) 41 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved 42 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc. 43 * 0xc100_0000 - 0xfeef_ffff : KVA 44 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy 45 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs 46 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0 47 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space 48 * 0xfef0_0000 - 0xffff_ffff : I/O devices region 49 */ 50 51#include <sys/cdefs.h> 52__FBSDID("$FreeBSD: stable/10/sys/powerpc/booke/pmap.c 265998 2014-05-14 01:16:05Z ian $"); 53 54#include <sys/param.h> 55#include <sys/malloc.h> 56#include <sys/ktr.h> 57#include <sys/proc.h> 58#include <sys/user.h> 59#include <sys/queue.h> 60#include <sys/systm.h> 61#include <sys/kernel.h> 62#include <sys/linker.h> 63#include <sys/msgbuf.h> 64#include <sys/lock.h> 65#include <sys/mutex.h> 66#include <sys/rwlock.h> 67#include <sys/sched.h> 68#include <sys/smp.h> 69#include <sys/vmmeter.h> 70 71#include <vm/vm.h> 72#include <vm/vm_page.h> 73#include <vm/vm_kern.h> 74#include <vm/vm_pageout.h> 75#include <vm/vm_extern.h> 76#include <vm/vm_object.h> 77#include <vm/vm_param.h> 78#include <vm/vm_map.h> 79#include <vm/vm_pager.h> 80#include <vm/uma.h> 81 82#include <machine/cpu.h> 83#include <machine/pcb.h> 84#include <machine/platform.h> 85 86#include <machine/tlb.h> 87#include <machine/spr.h> 88#include <machine/md_var.h> 89#include <machine/mmuvar.h> 90#include <machine/pmap.h> 91#include <machine/pte.h> 92 93#include "mmu_if.h" 94 95#ifdef DEBUG 96#define debugf(fmt, args...) printf(fmt, ##args) 97#else 98#define debugf(fmt, args...) 99#endif 100 101#define TODO panic("%s: not implemented", __func__); 102 103extern struct mtx sched_lock; 104 105extern int dumpsys_minidump; 106 107extern unsigned char _etext[]; 108extern unsigned char _end[]; 109 110extern uint32_t *bootinfo; 111 112#ifdef SMP 113extern uint32_t bp_ntlb1s; 114#endif 115 116vm_paddr_t kernload; 117vm_offset_t kernstart; 118vm_size_t kernsize; 119 120/* Message buffer and tables. */ 121static vm_offset_t data_start; 122static vm_size_t data_end; 123 124/* Phys/avail memory regions. */ 125static struct mem_region *availmem_regions; 126static int availmem_regions_sz; 127static struct mem_region *physmem_regions; 128static int physmem_regions_sz; 129 130/* Reserved KVA space and mutex for mmu_booke_zero_page. */ 131static vm_offset_t zero_page_va; 132static struct mtx zero_page_mutex; 133 134static struct mtx tlbivax_mutex; 135 136/* 137 * Reserved KVA space for mmu_booke_zero_page_idle. This is used 138 * by idle thred only, no lock required. 139 */ 140static vm_offset_t zero_page_idle_va; 141 142/* Reserved KVA space and mutex for mmu_booke_copy_page. */ 143static vm_offset_t copy_page_src_va; 144static vm_offset_t copy_page_dst_va; 145static struct mtx copy_page_mutex; 146 147/**************************************************************************/ 148/* PMAP */ 149/**************************************************************************/ 150 151static void mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t, 152 vm_prot_t, boolean_t); 153 154unsigned int kptbl_min; /* Index of the first kernel ptbl. */ 155unsigned int kernel_ptbls; /* Number of KVA ptbls. */ 156 157/* 158 * If user pmap is processed with mmu_booke_remove and the resident count 159 * drops to 0, there are no more pages to remove, so we need not continue. 160 */ 161#define PMAP_REMOVE_DONE(pmap) \ 162 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0) 163 164extern void tid_flush(tlbtid_t); 165 166/**************************************************************************/ 167/* TLB and TID handling */ 168/**************************************************************************/ 169 170/* Translation ID busy table */ 171static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1]; 172 173/* 174 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500 175 * core revisions and should be read from h/w registers during early config. 176 */ 177uint32_t tlb0_entries; 178uint32_t tlb0_ways; 179uint32_t tlb0_entries_per_way; 180 181#define TLB0_ENTRIES (tlb0_entries) 182#define TLB0_WAYS (tlb0_ways) 183#define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way) 184 185#define TLB1_ENTRIES 16 186 187/* In-ram copy of the TLB1 */ 188static tlb_entry_t tlb1[TLB1_ENTRIES]; 189 190/* Next free entry in the TLB1 */ 191static unsigned int tlb1_idx; 192static vm_offset_t tlb1_map_base = VM_MAX_KERNEL_ADDRESS; 193 194static tlbtid_t tid_alloc(struct pmap *); 195 196static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t); 197 198static int tlb1_set_entry(vm_offset_t, vm_offset_t, vm_size_t, uint32_t); 199static void tlb1_write_entry(unsigned int); 200static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *); 201static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t); 202 203static vm_size_t tsize2size(unsigned int); 204static unsigned int size2tsize(vm_size_t); 205static unsigned int ilog2(unsigned int); 206 207static void set_mas4_defaults(void); 208 209static inline void tlb0_flush_entry(vm_offset_t); 210static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int); 211 212/**************************************************************************/ 213/* Page table management */ 214/**************************************************************************/ 215 216static struct rwlock_padalign pvh_global_lock; 217 218/* Data for the pv entry allocation mechanism */ 219static uma_zone_t pvzone; 220static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 221 222#define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */ 223 224#ifndef PMAP_SHPGPERPROC 225#define PMAP_SHPGPERPROC 200 226#endif 227 228static void ptbl_init(void); 229static struct ptbl_buf *ptbl_buf_alloc(void); 230static void ptbl_buf_free(struct ptbl_buf *); 231static void ptbl_free_pmap_ptbl(pmap_t, pte_t *); 232 233static pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int); 234static void ptbl_free(mmu_t, pmap_t, unsigned int); 235static void ptbl_hold(mmu_t, pmap_t, unsigned int); 236static int ptbl_unhold(mmu_t, pmap_t, unsigned int); 237 238static vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t); 239static pte_t *pte_find(mmu_t, pmap_t, vm_offset_t); 240static void pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t); 241static int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t); 242 243static pv_entry_t pv_alloc(void); 244static void pv_free(pv_entry_t); 245static void pv_insert(pmap_t, vm_offset_t, vm_page_t); 246static void pv_remove(pmap_t, vm_offset_t, vm_page_t); 247 248/* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */ 249#define PTBL_BUFS (128 * 16) 250 251struct ptbl_buf { 252 TAILQ_ENTRY(ptbl_buf) link; /* list link */ 253 vm_offset_t kva; /* va of mapping */ 254}; 255 256/* ptbl free list and a lock used for access synchronization. */ 257static TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist; 258static struct mtx ptbl_buf_freelist_lock; 259 260/* Base address of kva space allocated fot ptbl bufs. */ 261static vm_offset_t ptbl_buf_pool_vabase; 262 263/* Pointer to ptbl_buf structures. */ 264static struct ptbl_buf *ptbl_bufs; 265 266void pmap_bootstrap_ap(volatile uint32_t *); 267 268/* 269 * Kernel MMU interface 270 */ 271static void mmu_booke_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 272static void mmu_booke_clear_modify(mmu_t, vm_page_t); 273static void mmu_booke_copy(mmu_t, pmap_t, pmap_t, vm_offset_t, 274 vm_size_t, vm_offset_t); 275static void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t); 276static void mmu_booke_copy_pages(mmu_t, vm_page_t *, 277 vm_offset_t, vm_page_t *, vm_offset_t, int); 278static void mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, 279 vm_prot_t, boolean_t); 280static void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 281 vm_page_t, vm_prot_t); 282static void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, 283 vm_prot_t); 284static vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t); 285static vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t, 286 vm_prot_t); 287static void mmu_booke_init(mmu_t); 288static boolean_t mmu_booke_is_modified(mmu_t, vm_page_t); 289static boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 290static boolean_t mmu_booke_is_referenced(mmu_t, vm_page_t); 291static int mmu_booke_ts_referenced(mmu_t, vm_page_t); 292static vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, 293 int); 294static int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t, 295 vm_paddr_t *); 296static void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t, 297 vm_object_t, vm_pindex_t, vm_size_t); 298static boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t); 299static void mmu_booke_page_init(mmu_t, vm_page_t); 300static int mmu_booke_page_wired_mappings(mmu_t, vm_page_t); 301static void mmu_booke_pinit(mmu_t, pmap_t); 302static void mmu_booke_pinit0(mmu_t, pmap_t); 303static void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 304 vm_prot_t); 305static void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 306static void mmu_booke_qremove(mmu_t, vm_offset_t, int); 307static void mmu_booke_release(mmu_t, pmap_t); 308static void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 309static void mmu_booke_remove_all(mmu_t, vm_page_t); 310static void mmu_booke_remove_write(mmu_t, vm_page_t); 311static void mmu_booke_zero_page(mmu_t, vm_page_t); 312static void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int); 313static void mmu_booke_zero_page_idle(mmu_t, vm_page_t); 314static void mmu_booke_activate(mmu_t, struct thread *); 315static void mmu_booke_deactivate(mmu_t, struct thread *); 316static void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 317static void *mmu_booke_mapdev(mmu_t, vm_paddr_t, vm_size_t); 318static void *mmu_booke_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t); 319static void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t); 320static vm_paddr_t mmu_booke_kextract(mmu_t, vm_offset_t); 321static void mmu_booke_kenter(mmu_t, vm_offset_t, vm_paddr_t); 322static void mmu_booke_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t); 323static void mmu_booke_kremove(mmu_t, vm_offset_t); 324static boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 325static void mmu_booke_sync_icache(mmu_t, pmap_t, vm_offset_t, 326 vm_size_t); 327static vm_offset_t mmu_booke_dumpsys_map(mmu_t, struct pmap_md *, 328 vm_size_t, vm_size_t *); 329static void mmu_booke_dumpsys_unmap(mmu_t, struct pmap_md *, 330 vm_size_t, vm_offset_t); 331static struct pmap_md *mmu_booke_scan_md(mmu_t, struct pmap_md *); 332 333static mmu_method_t mmu_booke_methods[] = { 334 /* pmap dispatcher interface */ 335 MMUMETHOD(mmu_change_wiring, mmu_booke_change_wiring), 336 MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify), 337 MMUMETHOD(mmu_copy, mmu_booke_copy), 338 MMUMETHOD(mmu_copy_page, mmu_booke_copy_page), 339 MMUMETHOD(mmu_copy_pages, mmu_booke_copy_pages), 340 MMUMETHOD(mmu_enter, mmu_booke_enter), 341 MMUMETHOD(mmu_enter_object, mmu_booke_enter_object), 342 MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick), 343 MMUMETHOD(mmu_extract, mmu_booke_extract), 344 MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold), 345 MMUMETHOD(mmu_init, mmu_booke_init), 346 MMUMETHOD(mmu_is_modified, mmu_booke_is_modified), 347 MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable), 348 MMUMETHOD(mmu_is_referenced, mmu_booke_is_referenced), 349 MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced), 350 MMUMETHOD(mmu_map, mmu_booke_map), 351 MMUMETHOD(mmu_mincore, mmu_booke_mincore), 352 MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt), 353 MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick), 354 MMUMETHOD(mmu_page_init, mmu_booke_page_init), 355 MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings), 356 MMUMETHOD(mmu_pinit, mmu_booke_pinit), 357 MMUMETHOD(mmu_pinit0, mmu_booke_pinit0), 358 MMUMETHOD(mmu_protect, mmu_booke_protect), 359 MMUMETHOD(mmu_qenter, mmu_booke_qenter), 360 MMUMETHOD(mmu_qremove, mmu_booke_qremove), 361 MMUMETHOD(mmu_release, mmu_booke_release), 362 MMUMETHOD(mmu_remove, mmu_booke_remove), 363 MMUMETHOD(mmu_remove_all, mmu_booke_remove_all), 364 MMUMETHOD(mmu_remove_write, mmu_booke_remove_write), 365 MMUMETHOD(mmu_sync_icache, mmu_booke_sync_icache), 366 MMUMETHOD(mmu_zero_page, mmu_booke_zero_page), 367 MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area), 368 MMUMETHOD(mmu_zero_page_idle, mmu_booke_zero_page_idle), 369 MMUMETHOD(mmu_activate, mmu_booke_activate), 370 MMUMETHOD(mmu_deactivate, mmu_booke_deactivate), 371 372 /* Internal interfaces */ 373 MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap), 374 MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped), 375 MMUMETHOD(mmu_mapdev, mmu_booke_mapdev), 376 MMUMETHOD(mmu_mapdev_attr, mmu_booke_mapdev_attr), 377 MMUMETHOD(mmu_kenter, mmu_booke_kenter), 378 MMUMETHOD(mmu_kenter_attr, mmu_booke_kenter_attr), 379 MMUMETHOD(mmu_kextract, mmu_booke_kextract), 380/* MMUMETHOD(mmu_kremove, mmu_booke_kremove), */ 381 MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev), 382 383 /* dumpsys() support */ 384 MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map), 385 MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap), 386 MMUMETHOD(mmu_scan_md, mmu_booke_scan_md), 387 388 { 0, 0 } 389}; 390 391MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods, 0); 392 393static __inline uint32_t 394tlb_calc_wimg(vm_offset_t pa, vm_memattr_t ma) 395{ 396 uint32_t attrib; 397 int i; 398 399 if (ma != VM_MEMATTR_DEFAULT) { 400 switch (ma) { 401 case VM_MEMATTR_UNCACHEABLE: 402 return (PTE_I | PTE_G); 403 case VM_MEMATTR_WRITE_COMBINING: 404 case VM_MEMATTR_WRITE_BACK: 405 case VM_MEMATTR_PREFETCHABLE: 406 return (PTE_I); 407 case VM_MEMATTR_WRITE_THROUGH: 408 return (PTE_W | PTE_M); 409 } 410 } 411 412 /* 413 * Assume the page is cache inhibited and access is guarded unless 414 * it's in our available memory array. 415 */ 416 attrib = _TLB_ENTRY_IO; 417 for (i = 0; i < physmem_regions_sz; i++) { 418 if ((pa >= physmem_regions[i].mr_start) && 419 (pa < (physmem_regions[i].mr_start + 420 physmem_regions[i].mr_size))) { 421 attrib = _TLB_ENTRY_MEM; 422 break; 423 } 424 } 425 426 return (attrib); 427} 428 429static inline void 430tlb_miss_lock(void) 431{ 432#ifdef SMP 433 struct pcpu *pc; 434 435 if (!smp_started) 436 return; 437 438 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 439 if (pc != pcpup) { 440 441 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, " 442 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke_tlb_lock); 443 444 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)), 445 ("tlb_miss_lock: tried to lock self")); 446 447 tlb_lock(pc->pc_booke_tlb_lock); 448 449 CTR1(KTR_PMAP, "%s: locked", __func__); 450 } 451 } 452#endif 453} 454 455static inline void 456tlb_miss_unlock(void) 457{ 458#ifdef SMP 459 struct pcpu *pc; 460 461 if (!smp_started) 462 return; 463 464 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 465 if (pc != pcpup) { 466 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d", 467 __func__, pc->pc_cpuid); 468 469 tlb_unlock(pc->pc_booke_tlb_lock); 470 471 CTR1(KTR_PMAP, "%s: unlocked", __func__); 472 } 473 } 474#endif 475} 476 477/* Return number of entries in TLB0. */ 478static __inline void 479tlb0_get_tlbconf(void) 480{ 481 uint32_t tlb0_cfg; 482 483 tlb0_cfg = mfspr(SPR_TLB0CFG); 484 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK; 485 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT; 486 tlb0_entries_per_way = tlb0_entries / tlb0_ways; 487} 488 489/* Initialize pool of kva ptbl buffers. */ 490static void 491ptbl_init(void) 492{ 493 int i; 494 495 CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__, 496 (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS); 497 CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)", 498 __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE); 499 500 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF); 501 TAILQ_INIT(&ptbl_buf_freelist); 502 503 for (i = 0; i < PTBL_BUFS; i++) { 504 ptbl_bufs[i].kva = ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE; 505 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link); 506 } 507} 508 509/* Get a ptbl_buf from the freelist. */ 510static struct ptbl_buf * 511ptbl_buf_alloc(void) 512{ 513 struct ptbl_buf *buf; 514 515 mtx_lock(&ptbl_buf_freelist_lock); 516 buf = TAILQ_FIRST(&ptbl_buf_freelist); 517 if (buf != NULL) 518 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link); 519 mtx_unlock(&ptbl_buf_freelist_lock); 520 521 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 522 523 return (buf); 524} 525 526/* Return ptbl buff to free pool. */ 527static void 528ptbl_buf_free(struct ptbl_buf *buf) 529{ 530 531 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 532 533 mtx_lock(&ptbl_buf_freelist_lock); 534 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link); 535 mtx_unlock(&ptbl_buf_freelist_lock); 536} 537 538/* 539 * Search the list of allocated ptbl bufs and find on list of allocated ptbls 540 */ 541static void 542ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl) 543{ 544 struct ptbl_buf *pbuf; 545 546 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 547 548 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 549 550 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link) 551 if (pbuf->kva == (vm_offset_t)ptbl) { 552 /* Remove from pmap ptbl buf list. */ 553 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link); 554 555 /* Free corresponding ptbl buf. */ 556 ptbl_buf_free(pbuf); 557 break; 558 } 559} 560 561/* Allocate page table. */ 562static pte_t * 563ptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 564{ 565 vm_page_t mtbl[PTBL_PAGES]; 566 vm_page_t m; 567 struct ptbl_buf *pbuf; 568 unsigned int pidx; 569 pte_t *ptbl; 570 int i; 571 572 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 573 (pmap == kernel_pmap), pdir_idx); 574 575 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 576 ("ptbl_alloc: invalid pdir_idx")); 577 KASSERT((pmap->pm_pdir[pdir_idx] == NULL), 578 ("pte_alloc: valid ptbl entry exists!")); 579 580 pbuf = ptbl_buf_alloc(); 581 if (pbuf == NULL) 582 panic("pte_alloc: couldn't alloc kernel virtual memory"); 583 584 ptbl = (pte_t *)pbuf->kva; 585 586 CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl); 587 588 /* Allocate ptbl pages, this will sleep! */ 589 for (i = 0; i < PTBL_PAGES; i++) { 590 pidx = (PTBL_PAGES * pdir_idx) + i; 591 while ((m = vm_page_alloc(NULL, pidx, 592 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 593 594 PMAP_UNLOCK(pmap); 595 rw_wunlock(&pvh_global_lock); 596 VM_WAIT; 597 rw_wlock(&pvh_global_lock); 598 PMAP_LOCK(pmap); 599 } 600 mtbl[i] = m; 601 } 602 603 /* Map allocated pages into kernel_pmap. */ 604 mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES); 605 606 /* Zero whole ptbl. */ 607 bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE); 608 609 /* Add pbuf to the pmap ptbl bufs list. */ 610 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link); 611 612 return (ptbl); 613} 614 615/* Free ptbl pages and invalidate pdir entry. */ 616static void 617ptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 618{ 619 pte_t *ptbl; 620 vm_paddr_t pa; 621 vm_offset_t va; 622 vm_page_t m; 623 int i; 624 625 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 626 (pmap == kernel_pmap), pdir_idx); 627 628 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 629 ("ptbl_free: invalid pdir_idx")); 630 631 ptbl = pmap->pm_pdir[pdir_idx]; 632 633 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 634 635 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl")); 636 637 /* 638 * Invalidate the pdir entry as soon as possible, so that other CPUs 639 * don't attempt to look up the page tables we are releasing. 640 */ 641 mtx_lock_spin(&tlbivax_mutex); 642 tlb_miss_lock(); 643 644 pmap->pm_pdir[pdir_idx] = NULL; 645 646 tlb_miss_unlock(); 647 mtx_unlock_spin(&tlbivax_mutex); 648 649 for (i = 0; i < PTBL_PAGES; i++) { 650 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE)); 651 pa = pte_vatopa(mmu, kernel_pmap, va); 652 m = PHYS_TO_VM_PAGE(pa); 653 vm_page_free_zero(m); 654 atomic_subtract_int(&cnt.v_wire_count, 1); 655 mmu_booke_kremove(mmu, va); 656 } 657 658 ptbl_free_pmap_ptbl(pmap, ptbl); 659} 660 661/* 662 * Decrement ptbl pages hold count and attempt to free ptbl pages. 663 * Called when removing pte entry from ptbl. 664 * 665 * Return 1 if ptbl pages were freed. 666 */ 667static int 668ptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 669{ 670 pte_t *ptbl; 671 vm_paddr_t pa; 672 vm_page_t m; 673 int i; 674 675 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 676 (pmap == kernel_pmap), pdir_idx); 677 678 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 679 ("ptbl_unhold: invalid pdir_idx")); 680 KASSERT((pmap != kernel_pmap), 681 ("ptbl_unhold: unholding kernel ptbl!")); 682 683 ptbl = pmap->pm_pdir[pdir_idx]; 684 685 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl); 686 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS), 687 ("ptbl_unhold: non kva ptbl")); 688 689 /* decrement hold count */ 690 for (i = 0; i < PTBL_PAGES; i++) { 691 pa = pte_vatopa(mmu, kernel_pmap, 692 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 693 m = PHYS_TO_VM_PAGE(pa); 694 m->wire_count--; 695 } 696 697 /* 698 * Free ptbl pages if there are no pte etries in this ptbl. 699 * wire_count has the same value for all ptbl pages, so check the last 700 * page. 701 */ 702 if (m->wire_count == 0) { 703 ptbl_free(mmu, pmap, pdir_idx); 704 705 //debugf("ptbl_unhold: e (freed ptbl)\n"); 706 return (1); 707 } 708 709 return (0); 710} 711 712/* 713 * Increment hold count for ptbl pages. This routine is used when a new pte 714 * entry is being inserted into the ptbl. 715 */ 716static void 717ptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 718{ 719 vm_paddr_t pa; 720 pte_t *ptbl; 721 vm_page_t m; 722 int i; 723 724 CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap, 725 pdir_idx); 726 727 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 728 ("ptbl_hold: invalid pdir_idx")); 729 KASSERT((pmap != kernel_pmap), 730 ("ptbl_hold: holding kernel ptbl!")); 731 732 ptbl = pmap->pm_pdir[pdir_idx]; 733 734 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl")); 735 736 for (i = 0; i < PTBL_PAGES; i++) { 737 pa = pte_vatopa(mmu, kernel_pmap, 738 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 739 m = PHYS_TO_VM_PAGE(pa); 740 m->wire_count++; 741 } 742} 743 744/* Allocate pv_entry structure. */ 745pv_entry_t 746pv_alloc(void) 747{ 748 pv_entry_t pv; 749 750 pv_entry_count++; 751 if (pv_entry_count > pv_entry_high_water) 752 pagedaemon_wakeup(); 753 pv = uma_zalloc(pvzone, M_NOWAIT); 754 755 return (pv); 756} 757 758/* Free pv_entry structure. */ 759static __inline void 760pv_free(pv_entry_t pve) 761{ 762 763 pv_entry_count--; 764 uma_zfree(pvzone, pve); 765} 766 767 768/* Allocate and initialize pv_entry structure. */ 769static void 770pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m) 771{ 772 pv_entry_t pve; 773 774 //int su = (pmap == kernel_pmap); 775 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su, 776 // (u_int32_t)pmap, va, (u_int32_t)m); 777 778 pve = pv_alloc(); 779 if (pve == NULL) 780 panic("pv_insert: no pv entries!"); 781 782 pve->pv_pmap = pmap; 783 pve->pv_va = va; 784 785 /* add to pv_list */ 786 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 787 rw_assert(&pvh_global_lock, RA_WLOCKED); 788 789 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link); 790 791 //debugf("pv_insert: e\n"); 792} 793 794/* Destroy pv entry. */ 795static void 796pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m) 797{ 798 pv_entry_t pve; 799 800 //int su = (pmap == kernel_pmap); 801 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va); 802 803 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 804 rw_assert(&pvh_global_lock, RA_WLOCKED); 805 806 /* find pv entry */ 807 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) { 808 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 809 /* remove from pv_list */ 810 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link); 811 if (TAILQ_EMPTY(&m->md.pv_list)) 812 vm_page_aflag_clear(m, PGA_WRITEABLE); 813 814 /* free pv entry struct */ 815 pv_free(pve); 816 break; 817 } 818 } 819 820 //debugf("pv_remove: e\n"); 821} 822 823/* 824 * Clean pte entry, try to free page table page if requested. 825 * 826 * Return 1 if ptbl pages were freed, otherwise return 0. 827 */ 828static int 829pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags) 830{ 831 unsigned int pdir_idx = PDIR_IDX(va); 832 unsigned int ptbl_idx = PTBL_IDX(va); 833 vm_page_t m; 834 pte_t *ptbl; 835 pte_t *pte; 836 837 //int su = (pmap == kernel_pmap); 838 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n", 839 // su, (u_int32_t)pmap, va, flags); 840 841 ptbl = pmap->pm_pdir[pdir_idx]; 842 KASSERT(ptbl, ("pte_remove: null ptbl")); 843 844 pte = &ptbl[ptbl_idx]; 845 846 if (pte == NULL || !PTE_ISVALID(pte)) 847 return (0); 848 849 if (PTE_ISWIRED(pte)) 850 pmap->pm_stats.wired_count--; 851 852 /* Handle managed entry. */ 853 if (PTE_ISMANAGED(pte)) { 854 /* Get vm_page_t for mapped pte. */ 855 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 856 857 if (PTE_ISMODIFIED(pte)) 858 vm_page_dirty(m); 859 860 if (PTE_ISREFERENCED(pte)) 861 vm_page_aflag_set(m, PGA_REFERENCED); 862 863 pv_remove(pmap, va, m); 864 } 865 866 mtx_lock_spin(&tlbivax_mutex); 867 tlb_miss_lock(); 868 869 tlb0_flush_entry(va); 870 pte->flags = 0; 871 pte->rpn = 0; 872 873 tlb_miss_unlock(); 874 mtx_unlock_spin(&tlbivax_mutex); 875 876 pmap->pm_stats.resident_count--; 877 878 if (flags & PTBL_UNHOLD) { 879 //debugf("pte_remove: e (unhold)\n"); 880 return (ptbl_unhold(mmu, pmap, pdir_idx)); 881 } 882 883 //debugf("pte_remove: e\n"); 884 return (0); 885} 886 887/* 888 * Insert PTE for a given page and virtual address. 889 */ 890static void 891pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags) 892{ 893 unsigned int pdir_idx = PDIR_IDX(va); 894 unsigned int ptbl_idx = PTBL_IDX(va); 895 pte_t *ptbl, *pte; 896 897 CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__, 898 pmap == kernel_pmap, pmap, va); 899 900 /* Get the page table pointer. */ 901 ptbl = pmap->pm_pdir[pdir_idx]; 902 903 if (ptbl == NULL) { 904 /* Allocate page table pages. */ 905 ptbl = ptbl_alloc(mmu, pmap, pdir_idx); 906 } else { 907 /* 908 * Check if there is valid mapping for requested 909 * va, if there is, remove it. 910 */ 911 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx]; 912 if (PTE_ISVALID(pte)) { 913 pte_remove(mmu, pmap, va, PTBL_HOLD); 914 } else { 915 /* 916 * pte is not used, increment hold count 917 * for ptbl pages. 918 */ 919 if (pmap != kernel_pmap) 920 ptbl_hold(mmu, pmap, pdir_idx); 921 } 922 } 923 924 /* 925 * Insert pv_entry into pv_list for mapped page if part of managed 926 * memory. 927 */ 928 if ((m->oflags & VPO_UNMANAGED) == 0) { 929 flags |= PTE_MANAGED; 930 931 /* Create and insert pv entry. */ 932 pv_insert(pmap, va, m); 933 } 934 935 pmap->pm_stats.resident_count++; 936 937 mtx_lock_spin(&tlbivax_mutex); 938 tlb_miss_lock(); 939 940 tlb0_flush_entry(va); 941 if (pmap->pm_pdir[pdir_idx] == NULL) { 942 /* 943 * If we just allocated a new page table, hook it in 944 * the pdir. 945 */ 946 pmap->pm_pdir[pdir_idx] = ptbl; 947 } 948 pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]); 949 pte->rpn = VM_PAGE_TO_PHYS(m) & ~PTE_PA_MASK; 950 pte->flags |= (PTE_VALID | flags); 951 952 tlb_miss_unlock(); 953 mtx_unlock_spin(&tlbivax_mutex); 954} 955 956/* Return the pa for the given pmap/va. */ 957static vm_paddr_t 958pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va) 959{ 960 vm_paddr_t pa = 0; 961 pte_t *pte; 962 963 pte = pte_find(mmu, pmap, va); 964 if ((pte != NULL) && PTE_ISVALID(pte)) 965 pa = (PTE_PA(pte) | (va & PTE_PA_MASK)); 966 return (pa); 967} 968 969/* Get a pointer to a PTE in a page table. */ 970static pte_t * 971pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va) 972{ 973 unsigned int pdir_idx = PDIR_IDX(va); 974 unsigned int ptbl_idx = PTBL_IDX(va); 975 976 KASSERT((pmap != NULL), ("pte_find: invalid pmap")); 977 978 if (pmap->pm_pdir[pdir_idx]) 979 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx])); 980 981 return (NULL); 982} 983 984/**************************************************************************/ 985/* PMAP related */ 986/**************************************************************************/ 987 988/* 989 * This is called during booke_init, before the system is really initialized. 990 */ 991static void 992mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend) 993{ 994 vm_offset_t phys_kernelend; 995 struct mem_region *mp, *mp1; 996 int cnt, i, j; 997 u_int s, e, sz; 998 u_int phys_avail_count; 999 vm_size_t physsz, hwphyssz, kstack0_sz; 1000 vm_offset_t kernel_pdir, kstack0, va; 1001 vm_paddr_t kstack0_phys; 1002 void *dpcpu; 1003 pte_t *pte; 1004 1005 debugf("mmu_booke_bootstrap: entered\n"); 1006 1007 /* Initialize invalidation mutex */ 1008 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN); 1009 1010 /* Read TLB0 size and associativity. */ 1011 tlb0_get_tlbconf(); 1012 1013 /* 1014 * Align kernel start and end address (kernel image). 1015 * Note that kernel end does not necessarily relate to kernsize. 1016 * kernsize is the size of the kernel that is actually mapped. 1017 * Also note that "start - 1" is deliberate. With SMP, the 1018 * entry point is exactly a page from the actual load address. 1019 * As such, trunc_page() has no effect and we're off by a page. 1020 * Since we always have the ELF header between the load address 1021 * and the entry point, we can safely subtract 1 to compensate. 1022 */ 1023 kernstart = trunc_page(start - 1); 1024 data_start = round_page(kernelend); 1025 data_end = data_start; 1026 1027 /* 1028 * Addresses of preloaded modules (like file systems) use 1029 * physical addresses. Make sure we relocate those into 1030 * virtual addresses. 1031 */ 1032 preload_addr_relocate = kernstart - kernload; 1033 1034 /* Allocate the dynamic per-cpu area. */ 1035 dpcpu = (void *)data_end; 1036 data_end += DPCPU_SIZE; 1037 1038 /* Allocate space for the message buffer. */ 1039 msgbufp = (struct msgbuf *)data_end; 1040 data_end += msgbufsize; 1041 debugf(" msgbufp at 0x%08x end = 0x%08x\n", (uint32_t)msgbufp, 1042 data_end); 1043 1044 data_end = round_page(data_end); 1045 1046 /* Allocate space for ptbl_bufs. */ 1047 ptbl_bufs = (struct ptbl_buf *)data_end; 1048 data_end += sizeof(struct ptbl_buf) * PTBL_BUFS; 1049 debugf(" ptbl_bufs at 0x%08x end = 0x%08x\n", (uint32_t)ptbl_bufs, 1050 data_end); 1051 1052 data_end = round_page(data_end); 1053 1054 /* Allocate PTE tables for kernel KVA. */ 1055 kernel_pdir = data_end; 1056 kernel_ptbls = (VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS + 1057 PDIR_SIZE - 1) / PDIR_SIZE; 1058 data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE; 1059 debugf(" kernel ptbls: %d\n", kernel_ptbls); 1060 debugf(" kernel pdir at 0x%08x end = 0x%08x\n", kernel_pdir, data_end); 1061 1062 debugf(" data_end: 0x%08x\n", data_end); 1063 if (data_end - kernstart > kernsize) { 1064 kernsize += tlb1_mapin_region(kernstart + kernsize, 1065 kernload + kernsize, (data_end - kernstart) - kernsize); 1066 } 1067 data_end = kernstart + kernsize; 1068 debugf(" updated data_end: 0x%08x\n", data_end); 1069 1070 /* 1071 * Clear the structures - note we can only do it safely after the 1072 * possible additional TLB1 translations are in place (above) so that 1073 * all range up to the currently calculated 'data_end' is covered. 1074 */ 1075 dpcpu_init(dpcpu, 0); 1076 memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE); 1077 memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE); 1078 1079 /*******************************************************/ 1080 /* Set the start and end of kva. */ 1081 /*******************************************************/ 1082 virtual_avail = round_page(data_end); 1083 virtual_end = VM_MAX_KERNEL_ADDRESS; 1084 1085 /* Allocate KVA space for page zero/copy operations. */ 1086 zero_page_va = virtual_avail; 1087 virtual_avail += PAGE_SIZE; 1088 zero_page_idle_va = virtual_avail; 1089 virtual_avail += PAGE_SIZE; 1090 copy_page_src_va = virtual_avail; 1091 virtual_avail += PAGE_SIZE; 1092 copy_page_dst_va = virtual_avail; 1093 virtual_avail += PAGE_SIZE; 1094 debugf("zero_page_va = 0x%08x\n", zero_page_va); 1095 debugf("zero_page_idle_va = 0x%08x\n", zero_page_idle_va); 1096 debugf("copy_page_src_va = 0x%08x\n", copy_page_src_va); 1097 debugf("copy_page_dst_va = 0x%08x\n", copy_page_dst_va); 1098 1099 /* Initialize page zero/copy mutexes. */ 1100 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF); 1101 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF); 1102 1103 /* Allocate KVA space for ptbl bufs. */ 1104 ptbl_buf_pool_vabase = virtual_avail; 1105 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE; 1106 debugf("ptbl_buf_pool_vabase = 0x%08x end = 0x%08x\n", 1107 ptbl_buf_pool_vabase, virtual_avail); 1108 1109 /* Calculate corresponding physical addresses for the kernel region. */ 1110 phys_kernelend = kernload + kernsize; 1111 debugf("kernel image and allocated data:\n"); 1112 debugf(" kernload = 0x%08x\n", kernload); 1113 debugf(" kernstart = 0x%08x\n", kernstart); 1114 debugf(" kernsize = 0x%08x\n", kernsize); 1115 1116 if (sizeof(phys_avail) / sizeof(phys_avail[0]) < availmem_regions_sz) 1117 panic("mmu_booke_bootstrap: phys_avail too small"); 1118 1119 /* 1120 * Remove kernel physical address range from avail regions list. Page 1121 * align all regions. Non-page aligned memory isn't very interesting 1122 * to us. Also, sort the entries for ascending addresses. 1123 */ 1124 1125 /* Retrieve phys/avail mem regions */ 1126 mem_regions(&physmem_regions, &physmem_regions_sz, 1127 &availmem_regions, &availmem_regions_sz); 1128 sz = 0; 1129 cnt = availmem_regions_sz; 1130 debugf("processing avail regions:\n"); 1131 for (mp = availmem_regions; mp->mr_size; mp++) { 1132 s = mp->mr_start; 1133 e = mp->mr_start + mp->mr_size; 1134 debugf(" %08x-%08x -> ", s, e); 1135 /* Check whether this region holds all of the kernel. */ 1136 if (s < kernload && e > phys_kernelend) { 1137 availmem_regions[cnt].mr_start = phys_kernelend; 1138 availmem_regions[cnt++].mr_size = e - phys_kernelend; 1139 e = kernload; 1140 } 1141 /* Look whether this regions starts within the kernel. */ 1142 if (s >= kernload && s < phys_kernelend) { 1143 if (e <= phys_kernelend) 1144 goto empty; 1145 s = phys_kernelend; 1146 } 1147 /* Now look whether this region ends within the kernel. */ 1148 if (e > kernload && e <= phys_kernelend) { 1149 if (s >= kernload) 1150 goto empty; 1151 e = kernload; 1152 } 1153 /* Now page align the start and size of the region. */ 1154 s = round_page(s); 1155 e = trunc_page(e); 1156 if (e < s) 1157 e = s; 1158 sz = e - s; 1159 debugf("%08x-%08x = %x\n", s, e, sz); 1160 1161 /* Check whether some memory is left here. */ 1162 if (sz == 0) { 1163 empty: 1164 memmove(mp, mp + 1, 1165 (cnt - (mp - availmem_regions)) * sizeof(*mp)); 1166 cnt--; 1167 mp--; 1168 continue; 1169 } 1170 1171 /* Do an insertion sort. */ 1172 for (mp1 = availmem_regions; mp1 < mp; mp1++) 1173 if (s < mp1->mr_start) 1174 break; 1175 if (mp1 < mp) { 1176 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1); 1177 mp1->mr_start = s; 1178 mp1->mr_size = sz; 1179 } else { 1180 mp->mr_start = s; 1181 mp->mr_size = sz; 1182 } 1183 } 1184 availmem_regions_sz = cnt; 1185 1186 /*******************************************************/ 1187 /* Steal physical memory for kernel stack from the end */ 1188 /* of the first avail region */ 1189 /*******************************************************/ 1190 kstack0_sz = KSTACK_PAGES * PAGE_SIZE; 1191 kstack0_phys = availmem_regions[0].mr_start + 1192 availmem_regions[0].mr_size; 1193 kstack0_phys -= kstack0_sz; 1194 availmem_regions[0].mr_size -= kstack0_sz; 1195 1196 /*******************************************************/ 1197 /* Fill in phys_avail table, based on availmem_regions */ 1198 /*******************************************************/ 1199 phys_avail_count = 0; 1200 physsz = 0; 1201 hwphyssz = 0; 1202 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 1203 1204 debugf("fill in phys_avail:\n"); 1205 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) { 1206 1207 debugf(" region: 0x%08x - 0x%08x (0x%08x)\n", 1208 availmem_regions[i].mr_start, 1209 availmem_regions[i].mr_start + 1210 availmem_regions[i].mr_size, 1211 availmem_regions[i].mr_size); 1212 1213 if (hwphyssz != 0 && 1214 (physsz + availmem_regions[i].mr_size) >= hwphyssz) { 1215 debugf(" hw.physmem adjust\n"); 1216 if (physsz < hwphyssz) { 1217 phys_avail[j] = availmem_regions[i].mr_start; 1218 phys_avail[j + 1] = 1219 availmem_regions[i].mr_start + 1220 hwphyssz - physsz; 1221 physsz = hwphyssz; 1222 phys_avail_count++; 1223 } 1224 break; 1225 } 1226 1227 phys_avail[j] = availmem_regions[i].mr_start; 1228 phys_avail[j + 1] = availmem_regions[i].mr_start + 1229 availmem_regions[i].mr_size; 1230 phys_avail_count++; 1231 physsz += availmem_regions[i].mr_size; 1232 } 1233 physmem = btoc(physsz); 1234 1235 /* Calculate the last available physical address. */ 1236 for (i = 0; phys_avail[i + 2] != 0; i += 2) 1237 ; 1238 Maxmem = powerpc_btop(phys_avail[i + 1]); 1239 1240 debugf("Maxmem = 0x%08lx\n", Maxmem); 1241 debugf("phys_avail_count = %d\n", phys_avail_count); 1242 debugf("physsz = 0x%08x physmem = %ld (0x%08lx)\n", physsz, physmem, 1243 physmem); 1244 1245 /*******************************************************/ 1246 /* Initialize (statically allocated) kernel pmap. */ 1247 /*******************************************************/ 1248 PMAP_LOCK_INIT(kernel_pmap); 1249 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE; 1250 1251 debugf("kernel_pmap = 0x%08x\n", (uint32_t)kernel_pmap); 1252 debugf("kptbl_min = %d, kernel_ptbls = %d\n", kptbl_min, kernel_ptbls); 1253 debugf("kernel pdir range: 0x%08x - 0x%08x\n", 1254 kptbl_min * PDIR_SIZE, (kptbl_min + kernel_ptbls) * PDIR_SIZE - 1); 1255 1256 /* Initialize kernel pdir */ 1257 for (i = 0; i < kernel_ptbls; i++) 1258 kernel_pmap->pm_pdir[kptbl_min + i] = 1259 (pte_t *)(kernel_pdir + (i * PAGE_SIZE * PTBL_PAGES)); 1260 1261 for (i = 0; i < MAXCPU; i++) { 1262 kernel_pmap->pm_tid[i] = TID_KERNEL; 1263 1264 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */ 1265 tidbusy[i][0] = kernel_pmap; 1266 } 1267 1268 /* 1269 * Fill in PTEs covering kernel code and data. They are not required 1270 * for address translation, as this area is covered by static TLB1 1271 * entries, but for pte_vatopa() to work correctly with kernel area 1272 * addresses. 1273 */ 1274 for (va = kernstart; va < data_end; va += PAGE_SIZE) { 1275 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]); 1276 pte->rpn = kernload + (va - kernstart); 1277 pte->flags = PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | 1278 PTE_VALID; 1279 } 1280 /* Mark kernel_pmap active on all CPUs */ 1281 CPU_FILL(&kernel_pmap->pm_active); 1282 1283 /* 1284 * Initialize the global pv list lock. 1285 */ 1286 rw_init(&pvh_global_lock, "pmap pv global"); 1287 1288 /*******************************************************/ 1289 /* Final setup */ 1290 /*******************************************************/ 1291 1292 /* Enter kstack0 into kernel map, provide guard page */ 1293 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1294 thread0.td_kstack = kstack0; 1295 thread0.td_kstack_pages = KSTACK_PAGES; 1296 1297 debugf("kstack_sz = 0x%08x\n", kstack0_sz); 1298 debugf("kstack0_phys at 0x%08x - 0x%08x\n", 1299 kstack0_phys, kstack0_phys + kstack0_sz); 1300 debugf("kstack0 at 0x%08x - 0x%08x\n", kstack0, kstack0 + kstack0_sz); 1301 1302 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz; 1303 for (i = 0; i < KSTACK_PAGES; i++) { 1304 mmu_booke_kenter(mmu, kstack0, kstack0_phys); 1305 kstack0 += PAGE_SIZE; 1306 kstack0_phys += PAGE_SIZE; 1307 } 1308 1309 debugf("virtual_avail = %08x\n", virtual_avail); 1310 debugf("virtual_end = %08x\n", virtual_end); 1311 1312 debugf("mmu_booke_bootstrap: exit\n"); 1313} 1314 1315void 1316pmap_bootstrap_ap(volatile uint32_t *trcp __unused) 1317{ 1318 int i; 1319 1320 /* 1321 * Finish TLB1 configuration: the BSP already set up its TLB1 and we 1322 * have the snapshot of its contents in the s/w tlb1[] table, so use 1323 * these values directly to (re)program AP's TLB1 hardware. 1324 */ 1325 for (i = bp_ntlb1s; i < tlb1_idx; i++) { 1326 /* Skip invalid entries */ 1327 if (!(tlb1[i].mas1 & MAS1_VALID)) 1328 continue; 1329 1330 tlb1_write_entry(i); 1331 } 1332 1333 set_mas4_defaults(); 1334} 1335 1336/* 1337 * Get the physical page address for the given pmap/virtual address. 1338 */ 1339static vm_paddr_t 1340mmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1341{ 1342 vm_paddr_t pa; 1343 1344 PMAP_LOCK(pmap); 1345 pa = pte_vatopa(mmu, pmap, va); 1346 PMAP_UNLOCK(pmap); 1347 1348 return (pa); 1349} 1350 1351/* 1352 * Extract the physical page address associated with the given 1353 * kernel virtual address. 1354 */ 1355static vm_paddr_t 1356mmu_booke_kextract(mmu_t mmu, vm_offset_t va) 1357{ 1358 int i; 1359 1360 /* Check TLB1 mappings */ 1361 for (i = 0; i < tlb1_idx; i++) { 1362 if (!(tlb1[i].mas1 & MAS1_VALID)) 1363 continue; 1364 if (va >= tlb1[i].virt && va < tlb1[i].virt + tlb1[i].size) 1365 return (tlb1[i].phys + (va - tlb1[i].virt)); 1366 } 1367 1368 return (pte_vatopa(mmu, kernel_pmap, va)); 1369} 1370 1371/* 1372 * Initialize the pmap module. 1373 * Called by vm_init, to initialize any structures that the pmap 1374 * system needs to map virtual memory. 1375 */ 1376static void 1377mmu_booke_init(mmu_t mmu) 1378{ 1379 int shpgperproc = PMAP_SHPGPERPROC; 1380 1381 /* 1382 * Initialize the address space (zone) for the pv entries. Set a 1383 * high water mark so that the system can recover from excessive 1384 * numbers of pv entries. 1385 */ 1386 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 1387 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1388 1389 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1390 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 1391 1392 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 1393 pv_entry_high_water = 9 * (pv_entry_max / 10); 1394 1395 uma_zone_reserve_kva(pvzone, pv_entry_max); 1396 1397 /* Pre-fill pvzone with initial number of pv entries. */ 1398 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN); 1399 1400 /* Initialize ptbl allocation. */ 1401 ptbl_init(); 1402} 1403 1404/* 1405 * Map a list of wired pages into kernel virtual address space. This is 1406 * intended for temporary mappings which do not need page modification or 1407 * references recorded. Existing mappings in the region are overwritten. 1408 */ 1409static void 1410mmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1411{ 1412 vm_offset_t va; 1413 1414 va = sva; 1415 while (count-- > 0) { 1416 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1417 va += PAGE_SIZE; 1418 m++; 1419 } 1420} 1421 1422/* 1423 * Remove page mappings from kernel virtual address space. Intended for 1424 * temporary mappings entered by mmu_booke_qenter. 1425 */ 1426static void 1427mmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count) 1428{ 1429 vm_offset_t va; 1430 1431 va = sva; 1432 while (count-- > 0) { 1433 mmu_booke_kremove(mmu, va); 1434 va += PAGE_SIZE; 1435 } 1436} 1437 1438/* 1439 * Map a wired page into kernel virtual address space. 1440 */ 1441static void 1442mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1443{ 1444 1445 mmu_booke_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1446} 1447 1448static void 1449mmu_booke_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1450{ 1451 unsigned int pdir_idx = PDIR_IDX(va); 1452 unsigned int ptbl_idx = PTBL_IDX(va); 1453 uint32_t flags; 1454 pte_t *pte; 1455 1456 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1457 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va")); 1458 1459 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID; 1460 flags |= tlb_calc_wimg(pa, ma); 1461 1462 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1463 1464 mtx_lock_spin(&tlbivax_mutex); 1465 tlb_miss_lock(); 1466 1467 if (PTE_ISVALID(pte)) { 1468 1469 CTR1(KTR_PMAP, "%s: replacing entry!", __func__); 1470 1471 /* Flush entry from TLB0 */ 1472 tlb0_flush_entry(va); 1473 } 1474 1475 pte->rpn = pa & ~PTE_PA_MASK; 1476 pte->flags = flags; 1477 1478 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x " 1479 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n", 1480 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags); 1481 1482 /* Flush the real memory from the instruction cache. */ 1483 if ((flags & (PTE_I | PTE_G)) == 0) { 1484 __syncicache((void *)va, PAGE_SIZE); 1485 } 1486 1487 tlb_miss_unlock(); 1488 mtx_unlock_spin(&tlbivax_mutex); 1489} 1490 1491/* 1492 * Remove a page from kernel page table. 1493 */ 1494static void 1495mmu_booke_kremove(mmu_t mmu, vm_offset_t va) 1496{ 1497 unsigned int pdir_idx = PDIR_IDX(va); 1498 unsigned int ptbl_idx = PTBL_IDX(va); 1499 pte_t *pte; 1500 1501// CTR2(KTR_PMAP,("%s: s (va = 0x%08x)\n", __func__, va)); 1502 1503 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1504 (va <= VM_MAX_KERNEL_ADDRESS)), 1505 ("mmu_booke_kremove: invalid va")); 1506 1507 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1508 1509 if (!PTE_ISVALID(pte)) { 1510 1511 CTR1(KTR_PMAP, "%s: invalid pte", __func__); 1512 1513 return; 1514 } 1515 1516 mtx_lock_spin(&tlbivax_mutex); 1517 tlb_miss_lock(); 1518 1519 /* Invalidate entry in TLB0, update PTE. */ 1520 tlb0_flush_entry(va); 1521 pte->flags = 0; 1522 pte->rpn = 0; 1523 1524 tlb_miss_unlock(); 1525 mtx_unlock_spin(&tlbivax_mutex); 1526} 1527 1528/* 1529 * Initialize pmap associated with process 0. 1530 */ 1531static void 1532mmu_booke_pinit0(mmu_t mmu, pmap_t pmap) 1533{ 1534 1535 PMAP_LOCK_INIT(pmap); 1536 mmu_booke_pinit(mmu, pmap); 1537 PCPU_SET(curpmap, pmap); 1538} 1539 1540/* 1541 * Initialize a preallocated and zeroed pmap structure, 1542 * such as one in a vmspace structure. 1543 */ 1544static void 1545mmu_booke_pinit(mmu_t mmu, pmap_t pmap) 1546{ 1547 int i; 1548 1549 CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap, 1550 curthread->td_proc->p_pid, curthread->td_proc->p_comm); 1551 1552 KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap")); 1553 1554 for (i = 0; i < MAXCPU; i++) 1555 pmap->pm_tid[i] = TID_NONE; 1556 CPU_ZERO(&kernel_pmap->pm_active); 1557 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats)); 1558 bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES); 1559 TAILQ_INIT(&pmap->pm_ptbl_list); 1560} 1561 1562/* 1563 * Release any resources held by the given physical map. 1564 * Called when a pmap initialized by mmu_booke_pinit is being released. 1565 * Should only be called if the map contains no valid mappings. 1566 */ 1567static void 1568mmu_booke_release(mmu_t mmu, pmap_t pmap) 1569{ 1570 1571 KASSERT(pmap->pm_stats.resident_count == 0, 1572 ("pmap_release: pmap resident count %ld != 0", 1573 pmap->pm_stats.resident_count)); 1574} 1575 1576/* 1577 * Insert the given physical page at the specified virtual address in the 1578 * target physical map with the protection requested. If specified the page 1579 * will be wired down. 1580 */ 1581static void 1582mmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1583 vm_prot_t prot, boolean_t wired) 1584{ 1585 1586 rw_wlock(&pvh_global_lock); 1587 PMAP_LOCK(pmap); 1588 mmu_booke_enter_locked(mmu, pmap, va, m, prot, wired); 1589 rw_wunlock(&pvh_global_lock); 1590 PMAP_UNLOCK(pmap); 1591} 1592 1593static void 1594mmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1595 vm_prot_t prot, boolean_t wired) 1596{ 1597 pte_t *pte; 1598 vm_paddr_t pa; 1599 uint32_t flags; 1600 int su, sync; 1601 1602 pa = VM_PAGE_TO_PHYS(m); 1603 su = (pmap == kernel_pmap); 1604 sync = 0; 1605 1606 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x " 1607 // "pa=0x%08x prot=0x%08x wired=%d)\n", 1608 // (u_int32_t)pmap, su, pmap->pm_tid, 1609 // (u_int32_t)m, va, pa, prot, wired); 1610 1611 if (su) { 1612 KASSERT(((va >= virtual_avail) && 1613 (va <= VM_MAX_KERNEL_ADDRESS)), 1614 ("mmu_booke_enter_locked: kernel pmap, non kernel va")); 1615 } else { 1616 KASSERT((va <= VM_MAXUSER_ADDRESS), 1617 ("mmu_booke_enter_locked: user pmap, non user va")); 1618 } 1619 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1620 VM_OBJECT_ASSERT_LOCKED(m->object); 1621 1622 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1623 1624 /* 1625 * If there is an existing mapping, and the physical address has not 1626 * changed, must be protection or wiring change. 1627 */ 1628 if (((pte = pte_find(mmu, pmap, va)) != NULL) && 1629 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) { 1630 1631 /* 1632 * Before actually updating pte->flags we calculate and 1633 * prepare its new value in a helper var. 1634 */ 1635 flags = pte->flags; 1636 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED); 1637 1638 /* Wiring change, just update stats. */ 1639 if (wired) { 1640 if (!PTE_ISWIRED(pte)) { 1641 flags |= PTE_WIRED; 1642 pmap->pm_stats.wired_count++; 1643 } 1644 } else { 1645 if (PTE_ISWIRED(pte)) { 1646 flags &= ~PTE_WIRED; 1647 pmap->pm_stats.wired_count--; 1648 } 1649 } 1650 1651 if (prot & VM_PROT_WRITE) { 1652 /* Add write permissions. */ 1653 flags |= PTE_SW; 1654 if (!su) 1655 flags |= PTE_UW; 1656 1657 if ((flags & PTE_MANAGED) != 0) 1658 vm_page_aflag_set(m, PGA_WRITEABLE); 1659 } else { 1660 /* Handle modified pages, sense modify status. */ 1661 1662 /* 1663 * The PTE_MODIFIED flag could be set by underlying 1664 * TLB misses since we last read it (above), possibly 1665 * other CPUs could update it so we check in the PTE 1666 * directly rather than rely on that saved local flags 1667 * copy. 1668 */ 1669 if (PTE_ISMODIFIED(pte)) 1670 vm_page_dirty(m); 1671 } 1672 1673 if (prot & VM_PROT_EXECUTE) { 1674 flags |= PTE_SX; 1675 if (!su) 1676 flags |= PTE_UX; 1677 1678 /* 1679 * Check existing flags for execute permissions: if we 1680 * are turning execute permissions on, icache should 1681 * be flushed. 1682 */ 1683 if ((pte->flags & (PTE_UX | PTE_SX)) == 0) 1684 sync++; 1685 } 1686 1687 flags &= ~PTE_REFERENCED; 1688 1689 /* 1690 * The new flags value is all calculated -- only now actually 1691 * update the PTE. 1692 */ 1693 mtx_lock_spin(&tlbivax_mutex); 1694 tlb_miss_lock(); 1695 1696 tlb0_flush_entry(va); 1697 pte->flags = flags; 1698 1699 tlb_miss_unlock(); 1700 mtx_unlock_spin(&tlbivax_mutex); 1701 1702 } else { 1703 /* 1704 * If there is an existing mapping, but it's for a different 1705 * physical address, pte_enter() will delete the old mapping. 1706 */ 1707 //if ((pte != NULL) && PTE_ISVALID(pte)) 1708 // debugf("mmu_booke_enter_locked: replace\n"); 1709 //else 1710 // debugf("mmu_booke_enter_locked: new\n"); 1711 1712 /* Now set up the flags and install the new mapping. */ 1713 flags = (PTE_SR | PTE_VALID); 1714 flags |= PTE_M; 1715 1716 if (!su) 1717 flags |= PTE_UR; 1718 1719 if (prot & VM_PROT_WRITE) { 1720 flags |= PTE_SW; 1721 if (!su) 1722 flags |= PTE_UW; 1723 1724 if ((m->oflags & VPO_UNMANAGED) == 0) 1725 vm_page_aflag_set(m, PGA_WRITEABLE); 1726 } 1727 1728 if (prot & VM_PROT_EXECUTE) { 1729 flags |= PTE_SX; 1730 if (!su) 1731 flags |= PTE_UX; 1732 } 1733 1734 /* If its wired update stats. */ 1735 if (wired) { 1736 pmap->pm_stats.wired_count++; 1737 flags |= PTE_WIRED; 1738 } 1739 1740 pte_enter(mmu, pmap, m, va, flags); 1741 1742 /* Flush the real memory from the instruction cache. */ 1743 if (prot & VM_PROT_EXECUTE) 1744 sync++; 1745 } 1746 1747 if (sync && (su || pmap == PCPU_GET(curpmap))) { 1748 __syncicache((void *)va, PAGE_SIZE); 1749 sync = 0; 1750 } 1751} 1752 1753/* 1754 * Maps a sequence of resident pages belonging to the same object. 1755 * The sequence begins with the given page m_start. This page is 1756 * mapped at the given virtual address start. Each subsequent page is 1757 * mapped at a virtual address that is offset from start by the same 1758 * amount as the page is offset from m_start within the object. The 1759 * last page in the sequence is the page with the largest offset from 1760 * m_start that can be mapped at a virtual address less than the given 1761 * virtual address end. Not every virtual page between start and end 1762 * is mapped; only those for which a resident page exists with the 1763 * corresponding offset from m_start are mapped. 1764 */ 1765static void 1766mmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start, 1767 vm_offset_t end, vm_page_t m_start, vm_prot_t prot) 1768{ 1769 vm_page_t m; 1770 vm_pindex_t diff, psize; 1771 1772 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1773 1774 psize = atop(end - start); 1775 m = m_start; 1776 rw_wlock(&pvh_global_lock); 1777 PMAP_LOCK(pmap); 1778 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1779 mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m, 1780 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1781 m = TAILQ_NEXT(m, listq); 1782 } 1783 rw_wunlock(&pvh_global_lock); 1784 PMAP_UNLOCK(pmap); 1785} 1786 1787static void 1788mmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1789 vm_prot_t prot) 1790{ 1791 1792 rw_wlock(&pvh_global_lock); 1793 PMAP_LOCK(pmap); 1794 mmu_booke_enter_locked(mmu, pmap, va, m, 1795 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1796 rw_wunlock(&pvh_global_lock); 1797 PMAP_UNLOCK(pmap); 1798} 1799 1800/* 1801 * Remove the given range of addresses from the specified map. 1802 * 1803 * It is assumed that the start and end are properly rounded to the page size. 1804 */ 1805static void 1806mmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva) 1807{ 1808 pte_t *pte; 1809 uint8_t hold_flag; 1810 1811 int su = (pmap == kernel_pmap); 1812 1813 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n", 1814 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva); 1815 1816 if (su) { 1817 KASSERT(((va >= virtual_avail) && 1818 (va <= VM_MAX_KERNEL_ADDRESS)), 1819 ("mmu_booke_remove: kernel pmap, non kernel va")); 1820 } else { 1821 KASSERT((va <= VM_MAXUSER_ADDRESS), 1822 ("mmu_booke_remove: user pmap, non user va")); 1823 } 1824 1825 if (PMAP_REMOVE_DONE(pmap)) { 1826 //debugf("mmu_booke_remove: e (empty)\n"); 1827 return; 1828 } 1829 1830 hold_flag = PTBL_HOLD_FLAG(pmap); 1831 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag); 1832 1833 rw_wlock(&pvh_global_lock); 1834 PMAP_LOCK(pmap); 1835 for (; va < endva; va += PAGE_SIZE) { 1836 pte = pte_find(mmu, pmap, va); 1837 if ((pte != NULL) && PTE_ISVALID(pte)) 1838 pte_remove(mmu, pmap, va, hold_flag); 1839 } 1840 PMAP_UNLOCK(pmap); 1841 rw_wunlock(&pvh_global_lock); 1842 1843 //debugf("mmu_booke_remove: e\n"); 1844} 1845 1846/* 1847 * Remove physical page from all pmaps in which it resides. 1848 */ 1849static void 1850mmu_booke_remove_all(mmu_t mmu, vm_page_t m) 1851{ 1852 pv_entry_t pv, pvn; 1853 uint8_t hold_flag; 1854 1855 rw_wlock(&pvh_global_lock); 1856 for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) { 1857 pvn = TAILQ_NEXT(pv, pv_link); 1858 1859 PMAP_LOCK(pv->pv_pmap); 1860 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap); 1861 pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag); 1862 PMAP_UNLOCK(pv->pv_pmap); 1863 } 1864 vm_page_aflag_clear(m, PGA_WRITEABLE); 1865 rw_wunlock(&pvh_global_lock); 1866} 1867 1868/* 1869 * Map a range of physical addresses into kernel virtual address space. 1870 */ 1871static vm_offset_t 1872mmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1873 vm_paddr_t pa_end, int prot) 1874{ 1875 vm_offset_t sva = *virt; 1876 vm_offset_t va = sva; 1877 1878 //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n", 1879 // sva, pa_start, pa_end); 1880 1881 while (pa_start < pa_end) { 1882 mmu_booke_kenter(mmu, va, pa_start); 1883 va += PAGE_SIZE; 1884 pa_start += PAGE_SIZE; 1885 } 1886 *virt = va; 1887 1888 //debugf("mmu_booke_map: e (va = 0x%08x)\n", va); 1889 return (sva); 1890} 1891 1892/* 1893 * The pmap must be activated before it's address space can be accessed in any 1894 * way. 1895 */ 1896static void 1897mmu_booke_activate(mmu_t mmu, struct thread *td) 1898{ 1899 pmap_t pmap; 1900 u_int cpuid; 1901 1902 pmap = &td->td_proc->p_vmspace->vm_pmap; 1903 1904 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%08x)", 1905 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1906 1907 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!")); 1908 1909 mtx_lock_spin(&sched_lock); 1910 1911 cpuid = PCPU_GET(cpuid); 1912 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 1913 PCPU_SET(curpmap, pmap); 1914 1915 if (pmap->pm_tid[cpuid] == TID_NONE) 1916 tid_alloc(pmap); 1917 1918 /* Load PID0 register with pmap tid value. */ 1919 mtspr(SPR_PID0, pmap->pm_tid[cpuid]); 1920 __asm __volatile("isync"); 1921 1922 mtx_unlock_spin(&sched_lock); 1923 1924 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__, 1925 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm); 1926} 1927 1928/* 1929 * Deactivate the specified process's address space. 1930 */ 1931static void 1932mmu_booke_deactivate(mmu_t mmu, struct thread *td) 1933{ 1934 pmap_t pmap; 1935 1936 pmap = &td->td_proc->p_vmspace->vm_pmap; 1937 1938 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%08x", 1939 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1940 1941 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active); 1942 PCPU_SET(curpmap, NULL); 1943} 1944 1945/* 1946 * Copy the range specified by src_addr/len 1947 * from the source map to the range dst_addr/len 1948 * in the destination map. 1949 * 1950 * This routine is only advisory and need not do anything. 1951 */ 1952static void 1953mmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap, 1954 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr) 1955{ 1956 1957} 1958 1959/* 1960 * Set the physical protection on the specified range of this map as requested. 1961 */ 1962static void 1963mmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 1964 vm_prot_t prot) 1965{ 1966 vm_offset_t va; 1967 vm_page_t m; 1968 pte_t *pte; 1969 1970 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1971 mmu_booke_remove(mmu, pmap, sva, eva); 1972 return; 1973 } 1974 1975 if (prot & VM_PROT_WRITE) 1976 return; 1977 1978 PMAP_LOCK(pmap); 1979 for (va = sva; va < eva; va += PAGE_SIZE) { 1980 if ((pte = pte_find(mmu, pmap, va)) != NULL) { 1981 if (PTE_ISVALID(pte)) { 1982 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1983 1984 mtx_lock_spin(&tlbivax_mutex); 1985 tlb_miss_lock(); 1986 1987 /* Handle modified pages. */ 1988 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte)) 1989 vm_page_dirty(m); 1990 1991 tlb0_flush_entry(va); 1992 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 1993 1994 tlb_miss_unlock(); 1995 mtx_unlock_spin(&tlbivax_mutex); 1996 } 1997 } 1998 } 1999 PMAP_UNLOCK(pmap); 2000} 2001 2002/* 2003 * Clear the write and modified bits in each of the given page's mappings. 2004 */ 2005static void 2006mmu_booke_remove_write(mmu_t mmu, vm_page_t m) 2007{ 2008 pv_entry_t pv; 2009 pte_t *pte; 2010 2011 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2012 ("mmu_booke_remove_write: page %p is not managed", m)); 2013 2014 /* 2015 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 2016 * set by another thread while the object is locked. Thus, 2017 * if PGA_WRITEABLE is clear, no page table entries need updating. 2018 */ 2019 VM_OBJECT_ASSERT_WLOCKED(m->object); 2020 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 2021 return; 2022 rw_wlock(&pvh_global_lock); 2023 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2024 PMAP_LOCK(pv->pv_pmap); 2025 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2026 if (PTE_ISVALID(pte)) { 2027 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2028 2029 mtx_lock_spin(&tlbivax_mutex); 2030 tlb_miss_lock(); 2031 2032 /* Handle modified pages. */ 2033 if (PTE_ISMODIFIED(pte)) 2034 vm_page_dirty(m); 2035 2036 /* Flush mapping from TLB0. */ 2037 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 2038 2039 tlb_miss_unlock(); 2040 mtx_unlock_spin(&tlbivax_mutex); 2041 } 2042 } 2043 PMAP_UNLOCK(pv->pv_pmap); 2044 } 2045 vm_page_aflag_clear(m, PGA_WRITEABLE); 2046 rw_wunlock(&pvh_global_lock); 2047} 2048 2049static void 2050mmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2051{ 2052 pte_t *pte; 2053 pmap_t pmap; 2054 vm_page_t m; 2055 vm_offset_t addr; 2056 vm_paddr_t pa; 2057 int active, valid; 2058 2059 va = trunc_page(va); 2060 sz = round_page(sz); 2061 2062 rw_wlock(&pvh_global_lock); 2063 pmap = PCPU_GET(curpmap); 2064 active = (pm == kernel_pmap || pm == pmap) ? 1 : 0; 2065 while (sz > 0) { 2066 PMAP_LOCK(pm); 2067 pte = pte_find(mmu, pm, va); 2068 valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0; 2069 if (valid) 2070 pa = PTE_PA(pte); 2071 PMAP_UNLOCK(pm); 2072 if (valid) { 2073 if (!active) { 2074 /* Create a mapping in the active pmap. */ 2075 addr = 0; 2076 m = PHYS_TO_VM_PAGE(pa); 2077 PMAP_LOCK(pmap); 2078 pte_enter(mmu, pmap, m, addr, 2079 PTE_SR | PTE_VALID | PTE_UR); 2080 __syncicache((void *)addr, PAGE_SIZE); 2081 pte_remove(mmu, pmap, addr, PTBL_UNHOLD); 2082 PMAP_UNLOCK(pmap); 2083 } else 2084 __syncicache((void *)va, PAGE_SIZE); 2085 } 2086 va += PAGE_SIZE; 2087 sz -= PAGE_SIZE; 2088 } 2089 rw_wunlock(&pvh_global_lock); 2090} 2091 2092/* 2093 * Atomically extract and hold the physical page with the given 2094 * pmap and virtual address pair if that mapping permits the given 2095 * protection. 2096 */ 2097static vm_page_t 2098mmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, 2099 vm_prot_t prot) 2100{ 2101 pte_t *pte; 2102 vm_page_t m; 2103 uint32_t pte_wbit; 2104 vm_paddr_t pa; 2105 2106 m = NULL; 2107 pa = 0; 2108 PMAP_LOCK(pmap); 2109retry: 2110 pte = pte_find(mmu, pmap, va); 2111 if ((pte != NULL) && PTE_ISVALID(pte)) { 2112 if (pmap == kernel_pmap) 2113 pte_wbit = PTE_SW; 2114 else 2115 pte_wbit = PTE_UW; 2116 2117 if ((pte->flags & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) { 2118 if (vm_page_pa_tryrelock(pmap, PTE_PA(pte), &pa)) 2119 goto retry; 2120 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2121 vm_page_hold(m); 2122 } 2123 } 2124 2125 PA_UNLOCK_COND(pa); 2126 PMAP_UNLOCK(pmap); 2127 return (m); 2128} 2129 2130/* 2131 * Initialize a vm_page's machine-dependent fields. 2132 */ 2133static void 2134mmu_booke_page_init(mmu_t mmu, vm_page_t m) 2135{ 2136 2137 TAILQ_INIT(&m->md.pv_list); 2138} 2139 2140/* 2141 * mmu_booke_zero_page_area zeros the specified hardware page by 2142 * mapping it into virtual memory and using bzero to clear 2143 * its contents. 2144 * 2145 * off and size must reside within a single page. 2146 */ 2147static void 2148mmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 2149{ 2150 vm_offset_t va; 2151 2152 /* XXX KASSERT off and size are within a single page? */ 2153 2154 mtx_lock(&zero_page_mutex); 2155 va = zero_page_va; 2156 2157 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2158 bzero((caddr_t)va + off, size); 2159 mmu_booke_kremove(mmu, va); 2160 2161 mtx_unlock(&zero_page_mutex); 2162} 2163 2164/* 2165 * mmu_booke_zero_page zeros the specified hardware page. 2166 */ 2167static void 2168mmu_booke_zero_page(mmu_t mmu, vm_page_t m) 2169{ 2170 2171 mmu_booke_zero_page_area(mmu, m, 0, PAGE_SIZE); 2172} 2173 2174/* 2175 * mmu_booke_copy_page copies the specified (machine independent) page by 2176 * mapping the page into virtual memory and using memcopy to copy the page, 2177 * one machine dependent page at a time. 2178 */ 2179static void 2180mmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm) 2181{ 2182 vm_offset_t sva, dva; 2183 2184 sva = copy_page_src_va; 2185 dva = copy_page_dst_va; 2186 2187 mtx_lock(©_page_mutex); 2188 mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm)); 2189 mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm)); 2190 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE); 2191 mmu_booke_kremove(mmu, dva); 2192 mmu_booke_kremove(mmu, sva); 2193 mtx_unlock(©_page_mutex); 2194} 2195 2196static inline void 2197mmu_booke_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 2198 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 2199{ 2200 void *a_cp, *b_cp; 2201 vm_offset_t a_pg_offset, b_pg_offset; 2202 int cnt; 2203 2204 mtx_lock(©_page_mutex); 2205 while (xfersize > 0) { 2206 a_pg_offset = a_offset & PAGE_MASK; 2207 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 2208 mmu_booke_kenter(mmu, copy_page_src_va, 2209 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 2210 a_cp = (char *)copy_page_src_va + a_pg_offset; 2211 b_pg_offset = b_offset & PAGE_MASK; 2212 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 2213 mmu_booke_kenter(mmu, copy_page_dst_va, 2214 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 2215 b_cp = (char *)copy_page_dst_va + b_pg_offset; 2216 bcopy(a_cp, b_cp, cnt); 2217 mmu_booke_kremove(mmu, copy_page_dst_va); 2218 mmu_booke_kremove(mmu, copy_page_src_va); 2219 a_offset += cnt; 2220 b_offset += cnt; 2221 xfersize -= cnt; 2222 } 2223 mtx_unlock(©_page_mutex); 2224} 2225 2226/* 2227 * mmu_booke_zero_page_idle zeros the specified hardware page by mapping it 2228 * into virtual memory and using bzero to clear its contents. This is intended 2229 * to be called from the vm_pagezero process only and outside of Giant. No 2230 * lock is required. 2231 */ 2232static void 2233mmu_booke_zero_page_idle(mmu_t mmu, vm_page_t m) 2234{ 2235 vm_offset_t va; 2236 2237 va = zero_page_idle_va; 2238 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2239 bzero((caddr_t)va, PAGE_SIZE); 2240 mmu_booke_kremove(mmu, va); 2241} 2242 2243/* 2244 * Return whether or not the specified physical page was modified 2245 * in any of physical maps. 2246 */ 2247static boolean_t 2248mmu_booke_is_modified(mmu_t mmu, vm_page_t m) 2249{ 2250 pte_t *pte; 2251 pv_entry_t pv; 2252 boolean_t rv; 2253 2254 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2255 ("mmu_booke_is_modified: page %p is not managed", m)); 2256 rv = FALSE; 2257 2258 /* 2259 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 2260 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 2261 * is clear, no PTEs can be modified. 2262 */ 2263 VM_OBJECT_ASSERT_WLOCKED(m->object); 2264 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 2265 return (rv); 2266 rw_wlock(&pvh_global_lock); 2267 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2268 PMAP_LOCK(pv->pv_pmap); 2269 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2270 PTE_ISVALID(pte)) { 2271 if (PTE_ISMODIFIED(pte)) 2272 rv = TRUE; 2273 } 2274 PMAP_UNLOCK(pv->pv_pmap); 2275 if (rv) 2276 break; 2277 } 2278 rw_wunlock(&pvh_global_lock); 2279 return (rv); 2280} 2281 2282/* 2283 * Return whether or not the specified virtual address is eligible 2284 * for prefault. 2285 */ 2286static boolean_t 2287mmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr) 2288{ 2289 2290 return (FALSE); 2291} 2292 2293/* 2294 * Return whether or not the specified physical page was referenced 2295 * in any physical maps. 2296 */ 2297static boolean_t 2298mmu_booke_is_referenced(mmu_t mmu, vm_page_t m) 2299{ 2300 pte_t *pte; 2301 pv_entry_t pv; 2302 boolean_t rv; 2303 2304 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2305 ("mmu_booke_is_referenced: page %p is not managed", m)); 2306 rv = FALSE; 2307 rw_wlock(&pvh_global_lock); 2308 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2309 PMAP_LOCK(pv->pv_pmap); 2310 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2311 PTE_ISVALID(pte)) { 2312 if (PTE_ISREFERENCED(pte)) 2313 rv = TRUE; 2314 } 2315 PMAP_UNLOCK(pv->pv_pmap); 2316 if (rv) 2317 break; 2318 } 2319 rw_wunlock(&pvh_global_lock); 2320 return (rv); 2321} 2322 2323/* 2324 * Clear the modify bits on the specified physical page. 2325 */ 2326static void 2327mmu_booke_clear_modify(mmu_t mmu, vm_page_t m) 2328{ 2329 pte_t *pte; 2330 pv_entry_t pv; 2331 2332 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2333 ("mmu_booke_clear_modify: page %p is not managed", m)); 2334 VM_OBJECT_ASSERT_WLOCKED(m->object); 2335 KASSERT(!vm_page_xbusied(m), 2336 ("mmu_booke_clear_modify: page %p is exclusive busied", m)); 2337 2338 /* 2339 * If the page is not PG_AWRITEABLE, then no PTEs can be modified. 2340 * If the object containing the page is locked and the page is not 2341 * exclusive busied, then PG_AWRITEABLE cannot be concurrently set. 2342 */ 2343 if ((m->aflags & PGA_WRITEABLE) == 0) 2344 return; 2345 rw_wlock(&pvh_global_lock); 2346 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2347 PMAP_LOCK(pv->pv_pmap); 2348 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2349 PTE_ISVALID(pte)) { 2350 mtx_lock_spin(&tlbivax_mutex); 2351 tlb_miss_lock(); 2352 2353 if (pte->flags & (PTE_SW | PTE_UW | PTE_MODIFIED)) { 2354 tlb0_flush_entry(pv->pv_va); 2355 pte->flags &= ~(PTE_SW | PTE_UW | PTE_MODIFIED | 2356 PTE_REFERENCED); 2357 } 2358 2359 tlb_miss_unlock(); 2360 mtx_unlock_spin(&tlbivax_mutex); 2361 } 2362 PMAP_UNLOCK(pv->pv_pmap); 2363 } 2364 rw_wunlock(&pvh_global_lock); 2365} 2366 2367/* 2368 * Return a count of reference bits for a page, clearing those bits. 2369 * It is not necessary for every reference bit to be cleared, but it 2370 * is necessary that 0 only be returned when there are truly no 2371 * reference bits set. 2372 * 2373 * XXX: The exact number of bits to check and clear is a matter that 2374 * should be tested and standardized at some point in the future for 2375 * optimal aging of shared pages. 2376 */ 2377static int 2378mmu_booke_ts_referenced(mmu_t mmu, vm_page_t m) 2379{ 2380 pte_t *pte; 2381 pv_entry_t pv; 2382 int count; 2383 2384 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2385 ("mmu_booke_ts_referenced: page %p is not managed", m)); 2386 count = 0; 2387 rw_wlock(&pvh_global_lock); 2388 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2389 PMAP_LOCK(pv->pv_pmap); 2390 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2391 PTE_ISVALID(pte)) { 2392 if (PTE_ISREFERENCED(pte)) { 2393 mtx_lock_spin(&tlbivax_mutex); 2394 tlb_miss_lock(); 2395 2396 tlb0_flush_entry(pv->pv_va); 2397 pte->flags &= ~PTE_REFERENCED; 2398 2399 tlb_miss_unlock(); 2400 mtx_unlock_spin(&tlbivax_mutex); 2401 2402 if (++count > 4) { 2403 PMAP_UNLOCK(pv->pv_pmap); 2404 break; 2405 } 2406 } 2407 } 2408 PMAP_UNLOCK(pv->pv_pmap); 2409 } 2410 rw_wunlock(&pvh_global_lock); 2411 return (count); 2412} 2413 2414/* 2415 * Change wiring attribute for a map/virtual-address pair. 2416 */ 2417static void 2418mmu_booke_change_wiring(mmu_t mmu, pmap_t pmap, vm_offset_t va, boolean_t wired) 2419{ 2420 pte_t *pte; 2421 2422 PMAP_LOCK(pmap); 2423 if ((pte = pte_find(mmu, pmap, va)) != NULL) { 2424 if (wired) { 2425 if (!PTE_ISWIRED(pte)) { 2426 pte->flags |= PTE_WIRED; 2427 pmap->pm_stats.wired_count++; 2428 } 2429 } else { 2430 if (PTE_ISWIRED(pte)) { 2431 pte->flags &= ~PTE_WIRED; 2432 pmap->pm_stats.wired_count--; 2433 } 2434 } 2435 } 2436 PMAP_UNLOCK(pmap); 2437} 2438 2439/* 2440 * Return true if the pmap's pv is one of the first 16 pvs linked to from this 2441 * page. This count may be changed upwards or downwards in the future; it is 2442 * only necessary that true be returned for a small subset of pmaps for proper 2443 * page aging. 2444 */ 2445static boolean_t 2446mmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2447{ 2448 pv_entry_t pv; 2449 int loops; 2450 boolean_t rv; 2451 2452 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2453 ("mmu_booke_page_exists_quick: page %p is not managed", m)); 2454 loops = 0; 2455 rv = FALSE; 2456 rw_wlock(&pvh_global_lock); 2457 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2458 if (pv->pv_pmap == pmap) { 2459 rv = TRUE; 2460 break; 2461 } 2462 if (++loops >= 16) 2463 break; 2464 } 2465 rw_wunlock(&pvh_global_lock); 2466 return (rv); 2467} 2468 2469/* 2470 * Return the number of managed mappings to the given physical page that are 2471 * wired. 2472 */ 2473static int 2474mmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m) 2475{ 2476 pv_entry_t pv; 2477 pte_t *pte; 2478 int count = 0; 2479 2480 if ((m->oflags & VPO_UNMANAGED) != 0) 2481 return (count); 2482 rw_wlock(&pvh_global_lock); 2483 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2484 PMAP_LOCK(pv->pv_pmap); 2485 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) 2486 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte)) 2487 count++; 2488 PMAP_UNLOCK(pv->pv_pmap); 2489 } 2490 rw_wunlock(&pvh_global_lock); 2491 return (count); 2492} 2493 2494static int 2495mmu_booke_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2496{ 2497 int i; 2498 vm_offset_t va; 2499 2500 /* 2501 * This currently does not work for entries that 2502 * overlap TLB1 entries. 2503 */ 2504 for (i = 0; i < tlb1_idx; i ++) { 2505 if (tlb1_iomapped(i, pa, size, &va) == 0) 2506 return (0); 2507 } 2508 2509 return (EFAULT); 2510} 2511 2512vm_offset_t 2513mmu_booke_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 2514 vm_size_t *sz) 2515{ 2516 vm_paddr_t pa, ppa; 2517 vm_offset_t va; 2518 vm_size_t gran; 2519 2520 /* Raw physical memory dumps don't have a virtual address. */ 2521 if (md->md_vaddr == ~0UL) { 2522 /* We always map a 256MB page at 256M. */ 2523 gran = 256 * 1024 * 1024; 2524 pa = md->md_paddr + ofs; 2525 ppa = pa & ~(gran - 1); 2526 ofs = pa - ppa; 2527 va = gran; 2528 tlb1_set_entry(va, ppa, gran, _TLB_ENTRY_IO); 2529 if (*sz > (gran - ofs)) 2530 *sz = gran - ofs; 2531 return (va + ofs); 2532 } 2533 2534 /* Minidumps are based on virtual memory addresses. */ 2535 va = md->md_vaddr + ofs; 2536 if (va >= kernstart + kernsize) { 2537 gran = PAGE_SIZE - (va & PAGE_MASK); 2538 if (*sz > gran) 2539 *sz = gran; 2540 } 2541 return (va); 2542} 2543 2544void 2545mmu_booke_dumpsys_unmap(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 2546 vm_offset_t va) 2547{ 2548 2549 /* Raw physical memory dumps don't have a virtual address. */ 2550 if (md->md_vaddr == ~0UL) { 2551 tlb1_idx--; 2552 tlb1[tlb1_idx].mas1 = 0; 2553 tlb1[tlb1_idx].mas2 = 0; 2554 tlb1[tlb1_idx].mas3 = 0; 2555 tlb1_write_entry(tlb1_idx); 2556 return; 2557 } 2558 2559 /* Minidumps are based on virtual memory addresses. */ 2560 /* Nothing to do... */ 2561} 2562 2563struct pmap_md * 2564mmu_booke_scan_md(mmu_t mmu, struct pmap_md *prev) 2565{ 2566 static struct pmap_md md; 2567 pte_t *pte; 2568 vm_offset_t va; 2569 2570 if (dumpsys_minidump) { 2571 md.md_paddr = ~0UL; /* Minidumps use virtual addresses. */ 2572 if (prev == NULL) { 2573 /* 1st: kernel .data and .bss. */ 2574 md.md_index = 1; 2575 md.md_vaddr = trunc_page((uintptr_t)_etext); 2576 md.md_size = round_page((uintptr_t)_end) - md.md_vaddr; 2577 return (&md); 2578 } 2579 switch (prev->md_index) { 2580 case 1: 2581 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2582 md.md_index = 2; 2583 md.md_vaddr = data_start; 2584 md.md_size = data_end - data_start; 2585 break; 2586 case 2: 2587 /* 3rd: kernel VM. */ 2588 va = prev->md_vaddr + prev->md_size; 2589 /* Find start of next chunk (from va). */ 2590 while (va < virtual_end) { 2591 /* Don't dump the buffer cache. */ 2592 if (va >= kmi.buffer_sva && 2593 va < kmi.buffer_eva) { 2594 va = kmi.buffer_eva; 2595 continue; 2596 } 2597 pte = pte_find(mmu, kernel_pmap, va); 2598 if (pte != NULL && PTE_ISVALID(pte)) 2599 break; 2600 va += PAGE_SIZE; 2601 } 2602 if (va < virtual_end) { 2603 md.md_vaddr = va; 2604 va += PAGE_SIZE; 2605 /* Find last page in chunk. */ 2606 while (va < virtual_end) { 2607 /* Don't run into the buffer cache. */ 2608 if (va == kmi.buffer_sva) 2609 break; 2610 pte = pte_find(mmu, kernel_pmap, va); 2611 if (pte == NULL || !PTE_ISVALID(pte)) 2612 break; 2613 va += PAGE_SIZE; 2614 } 2615 md.md_size = va - md.md_vaddr; 2616 break; 2617 } 2618 md.md_index = 3; 2619 /* FALLTHROUGH */ 2620 default: 2621 return (NULL); 2622 } 2623 } else { /* minidumps */ 2624 mem_regions(&physmem_regions, &physmem_regions_sz, 2625 &availmem_regions, &availmem_regions_sz); 2626 2627 if (prev == NULL) { 2628 /* first physical chunk. */ 2629 md.md_paddr = physmem_regions[0].mr_start; 2630 md.md_size = physmem_regions[0].mr_size; 2631 md.md_vaddr = ~0UL; 2632 md.md_index = 1; 2633 } else if (md.md_index < physmem_regions_sz) { 2634 md.md_paddr = physmem_regions[md.md_index].mr_start; 2635 md.md_size = physmem_regions[md.md_index].mr_size; 2636 md.md_vaddr = ~0UL; 2637 md.md_index++; 2638 } else { 2639 /* There's no next physical chunk. */ 2640 return (NULL); 2641 } 2642 } 2643 2644 return (&md); 2645} 2646 2647/* 2648 * Map a set of physical memory pages into the kernel virtual address space. 2649 * Return a pointer to where it is mapped. This routine is intended to be used 2650 * for mapping device memory, NOT real memory. 2651 */ 2652static void * 2653mmu_booke_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2654{ 2655 2656 return (mmu_booke_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 2657} 2658 2659static void * 2660mmu_booke_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2661{ 2662 void *res; 2663 uintptr_t va; 2664 vm_size_t sz; 2665 int i; 2666 2667 /* 2668 * Check if this is premapped in TLB1. Note: this should probably also 2669 * check whether a sequence of TLB1 entries exist that match the 2670 * requirement, but now only checks the easy case. 2671 */ 2672 if (ma == VM_MEMATTR_DEFAULT) { 2673 for (i = 0; i < tlb1_idx; i++) { 2674 if (!(tlb1[i].mas1 & MAS1_VALID)) 2675 continue; 2676 if (pa >= tlb1[i].phys && 2677 (pa + size) <= (tlb1[i].phys + tlb1[i].size)) 2678 return (void *)(tlb1[i].virt + 2679 (pa - tlb1[i].phys)); 2680 } 2681 } 2682 2683 size = roundup(size, PAGE_SIZE); 2684 2685 /* 2686 * We leave a hole for device direct mapping between the maximum user 2687 * address (0x8000000) and the minimum KVA address (0xc0000000). If 2688 * devices are in there, just map them 1:1. If not, map them to the 2689 * device mapping area about VM_MAX_KERNEL_ADDRESS. These mapped 2690 * addresses should be pulled from an allocator, but since we do not 2691 * ever free TLB1 entries, it is safe just to increment a counter. 2692 * Note that there isn't a lot of address space here (128 MB) and it 2693 * is not at all difficult to imagine running out, since that is a 4:1 2694 * compression from the 0xc0000000 - 0xf0000000 address space that gets 2695 * mapped there. 2696 */ 2697 if (pa >= (VM_MAXUSER_ADDRESS + PAGE_SIZE) && 2698 (pa + size - 1) < VM_MIN_KERNEL_ADDRESS) 2699 va = pa; 2700 else 2701 va = atomic_fetchadd_int(&tlb1_map_base, size); 2702 res = (void *)va; 2703 2704 do { 2705 sz = 1 << (ilog2(size) & ~1); 2706 if (bootverbose) 2707 printf("Wiring VA=%x to PA=%x (size=%x), " 2708 "using TLB1[%d]\n", va, pa, sz, tlb1_idx); 2709 tlb1_set_entry(va, pa, sz, tlb_calc_wimg(pa, ma)); 2710 size -= sz; 2711 pa += sz; 2712 va += sz; 2713 } while (size > 0); 2714 2715 return (res); 2716} 2717 2718/* 2719 * 'Unmap' a range mapped by mmu_booke_mapdev(). 2720 */ 2721static void 2722mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2723{ 2724#ifdef SUPPORTS_SHRINKING_TLB1 2725 vm_offset_t base, offset; 2726 2727 /* 2728 * Unmap only if this is inside kernel virtual space. 2729 */ 2730 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2731 base = trunc_page(va); 2732 offset = va & PAGE_MASK; 2733 size = roundup(offset + size, PAGE_SIZE); 2734 kva_free(base, size); 2735 } 2736#endif 2737} 2738 2739/* 2740 * mmu_booke_object_init_pt preloads the ptes for a given object into the 2741 * specified pmap. This eliminates the blast of soft faults on process startup 2742 * and immediately after an mmap. 2743 */ 2744static void 2745mmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2746 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2747{ 2748 2749 VM_OBJECT_ASSERT_WLOCKED(object); 2750 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2751 ("mmu_booke_object_init_pt: non-device object")); 2752} 2753 2754/* 2755 * Perform the pmap work for mincore. 2756 */ 2757static int 2758mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2759 vm_paddr_t *locked_pa) 2760{ 2761 2762 TODO; 2763 return (0); 2764} 2765 2766/**************************************************************************/ 2767/* TID handling */ 2768/**************************************************************************/ 2769 2770/* 2771 * Allocate a TID. If necessary, steal one from someone else. 2772 * The new TID is flushed from the TLB before returning. 2773 */ 2774static tlbtid_t 2775tid_alloc(pmap_t pmap) 2776{ 2777 tlbtid_t tid; 2778 int thiscpu; 2779 2780 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap")); 2781 2782 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap); 2783 2784 thiscpu = PCPU_GET(cpuid); 2785 2786 tid = PCPU_GET(tid_next); 2787 if (tid > TID_MAX) 2788 tid = TID_MIN; 2789 PCPU_SET(tid_next, tid + 1); 2790 2791 /* If we are stealing TID then clear the relevant pmap's field */ 2792 if (tidbusy[thiscpu][tid] != NULL) { 2793 2794 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid); 2795 2796 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE; 2797 2798 /* Flush all entries from TLB0 matching this TID. */ 2799 tid_flush(tid); 2800 } 2801 2802 tidbusy[thiscpu][tid] = pmap; 2803 pmap->pm_tid[thiscpu] = tid; 2804 __asm __volatile("msync; isync"); 2805 2806 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid, 2807 PCPU_GET(tid_next)); 2808 2809 return (tid); 2810} 2811 2812/**************************************************************************/ 2813/* TLB0 handling */ 2814/**************************************************************************/ 2815 2816static void 2817tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3, 2818 uint32_t mas7) 2819{ 2820 int as; 2821 char desc[3]; 2822 tlbtid_t tid; 2823 vm_size_t size; 2824 unsigned int tsize; 2825 2826 desc[2] = '\0'; 2827 if (mas1 & MAS1_VALID) 2828 desc[0] = 'V'; 2829 else 2830 desc[0] = ' '; 2831 2832 if (mas1 & MAS1_IPROT) 2833 desc[1] = 'P'; 2834 else 2835 desc[1] = ' '; 2836 2837 as = (mas1 & MAS1_TS_MASK) ? 1 : 0; 2838 tid = MAS1_GETTID(mas1); 2839 2840 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 2841 size = 0; 2842 if (tsize) 2843 size = tsize2size(tsize); 2844 2845 debugf("%3d: (%s) [AS=%d] " 2846 "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x " 2847 "mas2(va) = 0x%08x mas3(pa) = 0x%08x mas7 = 0x%08x\n", 2848 i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7); 2849} 2850 2851/* Convert TLB0 va and way number to tlb0[] table index. */ 2852static inline unsigned int 2853tlb0_tableidx(vm_offset_t va, unsigned int way) 2854{ 2855 unsigned int idx; 2856 2857 idx = (way * TLB0_ENTRIES_PER_WAY); 2858 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT; 2859 return (idx); 2860} 2861 2862/* 2863 * Invalidate TLB0 entry. 2864 */ 2865static inline void 2866tlb0_flush_entry(vm_offset_t va) 2867{ 2868 2869 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va); 2870 2871 mtx_assert(&tlbivax_mutex, MA_OWNED); 2872 2873 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK)); 2874 __asm __volatile("isync; msync"); 2875 __asm __volatile("tlbsync; msync"); 2876 2877 CTR1(KTR_PMAP, "%s: e", __func__); 2878} 2879 2880/* Print out contents of the MAS registers for each TLB0 entry */ 2881void 2882tlb0_print_tlbentries(void) 2883{ 2884 uint32_t mas0, mas1, mas2, mas3, mas7; 2885 int entryidx, way, idx; 2886 2887 debugf("TLB0 entries:\n"); 2888 for (way = 0; way < TLB0_WAYS; way ++) 2889 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) { 2890 2891 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 2892 mtspr(SPR_MAS0, mas0); 2893 __asm __volatile("isync"); 2894 2895 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT; 2896 mtspr(SPR_MAS2, mas2); 2897 2898 __asm __volatile("isync; tlbre"); 2899 2900 mas1 = mfspr(SPR_MAS1); 2901 mas2 = mfspr(SPR_MAS2); 2902 mas3 = mfspr(SPR_MAS3); 2903 mas7 = mfspr(SPR_MAS7); 2904 2905 idx = tlb0_tableidx(mas2, way); 2906 tlb_print_entry(idx, mas1, mas2, mas3, mas7); 2907 } 2908} 2909 2910/**************************************************************************/ 2911/* TLB1 handling */ 2912/**************************************************************************/ 2913 2914/* 2915 * TLB1 mapping notes: 2916 * 2917 * TLB1[0] Kernel text and data. 2918 * TLB1[1-15] Additional kernel text and data mappings (if required), PCI 2919 * windows, other devices mappings. 2920 */ 2921 2922/* 2923 * Write given entry to TLB1 hardware. 2924 * Use 32 bit pa, clear 4 high-order bits of RPN (mas7). 2925 */ 2926static void 2927tlb1_write_entry(unsigned int idx) 2928{ 2929 uint32_t mas0, mas7; 2930 2931 //debugf("tlb1_write_entry: s\n"); 2932 2933 /* Clear high order RPN bits */ 2934 mas7 = 0; 2935 2936 /* Select entry */ 2937 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx); 2938 //debugf("tlb1_write_entry: mas0 = 0x%08x\n", mas0); 2939 2940 mtspr(SPR_MAS0, mas0); 2941 __asm __volatile("isync"); 2942 mtspr(SPR_MAS1, tlb1[idx].mas1); 2943 __asm __volatile("isync"); 2944 mtspr(SPR_MAS2, tlb1[idx].mas2); 2945 __asm __volatile("isync"); 2946 mtspr(SPR_MAS3, tlb1[idx].mas3); 2947 __asm __volatile("isync"); 2948 mtspr(SPR_MAS7, mas7); 2949 __asm __volatile("isync; tlbwe; isync; msync"); 2950 2951 //debugf("tlb1_write_entry: e\n"); 2952} 2953 2954/* 2955 * Return the largest uint value log such that 2^log <= num. 2956 */ 2957static unsigned int 2958ilog2(unsigned int num) 2959{ 2960 int lz; 2961 2962 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num)); 2963 return (31 - lz); 2964} 2965 2966/* 2967 * Convert TLB TSIZE value to mapped region size. 2968 */ 2969static vm_size_t 2970tsize2size(unsigned int tsize) 2971{ 2972 2973 /* 2974 * size = 4^tsize KB 2975 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10) 2976 */ 2977 2978 return ((1 << (2 * tsize)) * 1024); 2979} 2980 2981/* 2982 * Convert region size (must be power of 4) to TLB TSIZE value. 2983 */ 2984static unsigned int 2985size2tsize(vm_size_t size) 2986{ 2987 2988 return (ilog2(size) / 2 - 5); 2989} 2990 2991/* 2992 * Register permanent kernel mapping in TLB1. 2993 * 2994 * Entries are created starting from index 0 (current free entry is 2995 * kept in tlb1_idx) and are not supposed to be invalidated. 2996 */ 2997static int 2998tlb1_set_entry(vm_offset_t va, vm_offset_t pa, vm_size_t size, 2999 uint32_t flags) 3000{ 3001 uint32_t ts, tid; 3002 int tsize, index; 3003 3004 index = atomic_fetchadd_int(&tlb1_idx, 1); 3005 if (index >= TLB1_ENTRIES) { 3006 printf("tlb1_set_entry: TLB1 full!\n"); 3007 return (-1); 3008 } 3009 3010 /* Convert size to TSIZE */ 3011 tsize = size2tsize(size); 3012 3013 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK; 3014 /* XXX TS is hard coded to 0 for now as we only use single address space */ 3015 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK; 3016 3017 /* 3018 * Atomicity is preserved by the atomic increment above since nothing 3019 * is ever removed from tlb1. 3020 */ 3021 3022 tlb1[index].phys = pa; 3023 tlb1[index].virt = va; 3024 tlb1[index].size = size; 3025 tlb1[index].mas1 = MAS1_VALID | MAS1_IPROT | ts | tid; 3026 tlb1[index].mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK); 3027 tlb1[index].mas2 = (va & MAS2_EPN_MASK) | flags; 3028 3029 /* Set supervisor RWX permission bits */ 3030 tlb1[index].mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX; 3031 3032 tlb1_write_entry(index); 3033 3034 /* 3035 * XXX in general TLB1 updates should be propagated between CPUs, 3036 * since current design assumes to have the same TLB1 set-up on all 3037 * cores. 3038 */ 3039 return (0); 3040} 3041 3042/* 3043 * Map in contiguous RAM region into the TLB1 using maximum of 3044 * KERNEL_REGION_MAX_TLB_ENTRIES entries. 3045 * 3046 * If necessary round up last entry size and return total size 3047 * used by all allocated entries. 3048 */ 3049vm_size_t 3050tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size) 3051{ 3052 vm_size_t pgs[KERNEL_REGION_MAX_TLB_ENTRIES]; 3053 vm_size_t mapped, pgsz, base, mask; 3054 int idx, nents; 3055 3056 /* Round up to the next 1M */ 3057 size = (size + (1 << 20) - 1) & ~((1 << 20) - 1); 3058 3059 mapped = 0; 3060 idx = 0; 3061 base = va; 3062 pgsz = 64*1024*1024; 3063 while (mapped < size) { 3064 while (mapped < size && idx < KERNEL_REGION_MAX_TLB_ENTRIES) { 3065 while (pgsz > (size - mapped)) 3066 pgsz >>= 2; 3067 pgs[idx++] = pgsz; 3068 mapped += pgsz; 3069 } 3070 3071 /* We under-map. Correct for this. */ 3072 if (mapped < size) { 3073 while (pgs[idx - 1] == pgsz) { 3074 idx--; 3075 mapped -= pgsz; 3076 } 3077 /* XXX We may increase beyond out starting point. */ 3078 pgsz <<= 2; 3079 pgs[idx++] = pgsz; 3080 mapped += pgsz; 3081 } 3082 } 3083 3084 nents = idx; 3085 mask = pgs[0] - 1; 3086 /* Align address to the boundary */ 3087 if (va & mask) { 3088 va = (va + mask) & ~mask; 3089 pa = (pa + mask) & ~mask; 3090 } 3091 3092 for (idx = 0; idx < nents; idx++) { 3093 pgsz = pgs[idx]; 3094 debugf("%u: %x -> %x, size=%x\n", idx, pa, va, pgsz); 3095 tlb1_set_entry(va, pa, pgsz, _TLB_ENTRY_MEM); 3096 pa += pgsz; 3097 va += pgsz; 3098 } 3099 3100 mapped = (va - base); 3101 printf("mapped size 0x%08x (wasted space 0x%08x)\n", 3102 mapped, mapped - size); 3103 return (mapped); 3104} 3105 3106/* 3107 * TLB1 initialization routine, to be called after the very first 3108 * assembler level setup done in locore.S. 3109 */ 3110void 3111tlb1_init() 3112{ 3113 uint32_t mas0, mas1, mas2, mas3; 3114 uint32_t tsz; 3115 u_int i; 3116 3117 if (bootinfo != NULL && bootinfo[0] != 1) { 3118 tlb1_idx = *((uint16_t *)(bootinfo + 8)); 3119 } else 3120 tlb1_idx = 1; 3121 3122 /* The first entry/entries are used to map the kernel. */ 3123 for (i = 0; i < tlb1_idx; i++) { 3124 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3125 mtspr(SPR_MAS0, mas0); 3126 __asm __volatile("isync; tlbre"); 3127 3128 mas1 = mfspr(SPR_MAS1); 3129 if ((mas1 & MAS1_VALID) == 0) 3130 continue; 3131 3132 mas2 = mfspr(SPR_MAS2); 3133 mas3 = mfspr(SPR_MAS3); 3134 3135 tlb1[i].mas1 = mas1; 3136 tlb1[i].mas2 = mfspr(SPR_MAS2); 3137 tlb1[i].mas3 = mas3; 3138 tlb1[i].virt = mas2 & MAS2_EPN_MASK; 3139 tlb1[i].phys = mas3 & MAS3_RPN; 3140 3141 if (i == 0) 3142 kernload = mas3 & MAS3_RPN; 3143 3144 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3145 tlb1[i].size = (tsz > 0) ? tsize2size(tsz) : 0; 3146 kernsize += tlb1[i].size; 3147 } 3148 3149#ifdef SMP 3150 bp_ntlb1s = tlb1_idx; 3151#endif 3152 3153 /* Purge the remaining entries */ 3154 for (i = tlb1_idx; i < TLB1_ENTRIES; i++) 3155 tlb1_write_entry(i); 3156 3157 /* Setup TLB miss defaults */ 3158 set_mas4_defaults(); 3159} 3160 3161vm_offset_t 3162pmap_early_io_map(vm_paddr_t pa, vm_size_t size) 3163{ 3164 vm_paddr_t pa_base; 3165 vm_offset_t va, sz; 3166 int i; 3167 3168 KASSERT(!pmap_bootstrapped, ("Do not use after PMAP is up!")); 3169 3170 for (i = 0; i < tlb1_idx; i++) { 3171 if (!(tlb1[i].mas1 & MAS1_VALID)) 3172 continue; 3173 if (pa >= tlb1[i].phys && (pa + size) <= 3174 (tlb1[i].phys + tlb1[i].size)) 3175 return (tlb1[i].virt + (pa - tlb1[i].phys)); 3176 } 3177 3178 pa_base = trunc_page(pa); 3179 size = roundup(size + (pa - pa_base), PAGE_SIZE); 3180 va = tlb1_map_base + (pa - pa_base); 3181 3182 do { 3183 sz = 1 << (ilog2(size) & ~1); 3184 tlb1_set_entry(tlb1_map_base, pa_base, sz, _TLB_ENTRY_IO); 3185 size -= sz; 3186 pa_base += sz; 3187 tlb1_map_base += sz; 3188 } while (size > 0); 3189 3190#ifdef SMP 3191 bp_ntlb1s = tlb1_idx; 3192#endif 3193 3194 return (va); 3195} 3196 3197/* 3198 * Setup MAS4 defaults. 3199 * These values are loaded to MAS0-2 on a TLB miss. 3200 */ 3201static void 3202set_mas4_defaults(void) 3203{ 3204 uint32_t mas4; 3205 3206 /* Defaults: TLB0, PID0, TSIZED=4K */ 3207 mas4 = MAS4_TLBSELD0; 3208 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK; 3209#ifdef SMP 3210 mas4 |= MAS4_MD; 3211#endif 3212 mtspr(SPR_MAS4, mas4); 3213 __asm __volatile("isync"); 3214} 3215 3216/* 3217 * Print out contents of the MAS registers for each TLB1 entry 3218 */ 3219void 3220tlb1_print_tlbentries(void) 3221{ 3222 uint32_t mas0, mas1, mas2, mas3, mas7; 3223 int i; 3224 3225 debugf("TLB1 entries:\n"); 3226 for (i = 0; i < TLB1_ENTRIES; i++) { 3227 3228 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3229 mtspr(SPR_MAS0, mas0); 3230 3231 __asm __volatile("isync; tlbre"); 3232 3233 mas1 = mfspr(SPR_MAS1); 3234 mas2 = mfspr(SPR_MAS2); 3235 mas3 = mfspr(SPR_MAS3); 3236 mas7 = mfspr(SPR_MAS7); 3237 3238 tlb_print_entry(i, mas1, mas2, mas3, mas7); 3239 } 3240} 3241 3242/* 3243 * Print out contents of the in-ram tlb1 table. 3244 */ 3245void 3246tlb1_print_entries(void) 3247{ 3248 int i; 3249 3250 debugf("tlb1[] table entries:\n"); 3251 for (i = 0; i < TLB1_ENTRIES; i++) 3252 tlb_print_entry(i, tlb1[i].mas1, tlb1[i].mas2, tlb1[i].mas3, 0); 3253} 3254 3255/* 3256 * Return 0 if the physical IO range is encompassed by one of the 3257 * the TLB1 entries, otherwise return related error code. 3258 */ 3259static int 3260tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va) 3261{ 3262 uint32_t prot; 3263 vm_paddr_t pa_start; 3264 vm_paddr_t pa_end; 3265 unsigned int entry_tsize; 3266 vm_size_t entry_size; 3267 3268 *va = (vm_offset_t)NULL; 3269 3270 /* Skip invalid entries */ 3271 if (!(tlb1[i].mas1 & MAS1_VALID)) 3272 return (EINVAL); 3273 3274 /* 3275 * The entry must be cache-inhibited, guarded, and r/w 3276 * so it can function as an i/o page 3277 */ 3278 prot = tlb1[i].mas2 & (MAS2_I | MAS2_G); 3279 if (prot != (MAS2_I | MAS2_G)) 3280 return (EPERM); 3281 3282 prot = tlb1[i].mas3 & (MAS3_SR | MAS3_SW); 3283 if (prot != (MAS3_SR | MAS3_SW)) 3284 return (EPERM); 3285 3286 /* The address should be within the entry range. */ 3287 entry_tsize = (tlb1[i].mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3288 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize")); 3289 3290 entry_size = tsize2size(entry_tsize); 3291 pa_start = tlb1[i].mas3 & MAS3_RPN; 3292 pa_end = pa_start + entry_size - 1; 3293 3294 if ((pa < pa_start) || ((pa + size) > pa_end)) 3295 return (ERANGE); 3296 3297 /* Return virtual address of this mapping. */ 3298 *va = (tlb1[i].mas2 & MAS2_EPN_MASK) + (pa - pa_start); 3299 return (0); 3300} 3301