platform_bare.c revision 265968 
1/*-
2 * Copyright (c) 2008-2012 Semihalf.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: stable/10/sys/powerpc/booke/platform_bare.c 265968 2014-05-13 18:00:41Z ian $");
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/kernel.h>
33#include <sys/bus.h>
34#include <sys/pcpu.h>
35#include <sys/proc.h>
36#include <sys/smp.h>
37
38#include <machine/bus.h>
39#include <machine/cpu.h>
40#include <machine/hid.h>
41#include <machine/platform.h>
42#include <machine/platformvar.h>
43#include <machine/smp.h>
44#include <machine/spr.h>
45#include <machine/vmparam.h>
46
47#include <dev/fdt/fdt_common.h>
48#include <dev/ofw/ofw_bus.h>
49#include <dev/ofw/ofw_bus_subr.h>
50#include <dev/ofw/openfirm.h>
51
52#include <powerpc/mpc85xx/mpc85xx.h>
53
54#include "platform_if.h"
55
56#ifdef SMP
57extern void *ap_pcpu;
58extern vm_paddr_t kernload;		/* Kernel physical load address */
59extern uint8_t __boot_page[];		/* Boot page body */
60extern uint32_t bp_ntlb1s;
61extern uint32_t bp_tlb1[];
62extern uint32_t bp_tlb1_end[];
63#endif
64
65extern uint32_t *bootinfo;
66
67static int cpu, maxcpu;
68
69static int bare_probe(platform_t);
70static void bare_mem_regions(platform_t, struct mem_region **phys, int *physsz,
71    struct mem_region **avail, int *availsz);
72static u_long bare_timebase_freq(platform_t, struct cpuref *cpuref);
73static int bare_smp_first_cpu(platform_t, struct cpuref *cpuref);
74static int bare_smp_next_cpu(platform_t, struct cpuref *cpuref);
75static int bare_smp_get_bsp(platform_t, struct cpuref *cpuref);
76static int bare_smp_start_cpu(platform_t, struct pcpu *cpu);
77
78static void booke_reset(platform_t);
79
80static platform_method_t bare_methods[] = {
81	PLATFORMMETHOD(platform_probe,		bare_probe),
82	PLATFORMMETHOD(platform_mem_regions,	bare_mem_regions),
83	PLATFORMMETHOD(platform_timebase_freq,	bare_timebase_freq),
84
85	PLATFORMMETHOD(platform_smp_first_cpu,	bare_smp_first_cpu),
86	PLATFORMMETHOD(platform_smp_next_cpu,	bare_smp_next_cpu),
87	PLATFORMMETHOD(platform_smp_get_bsp,	bare_smp_get_bsp),
88	PLATFORMMETHOD(platform_smp_start_cpu,	bare_smp_start_cpu),
89
90	PLATFORMMETHOD(platform_reset,		booke_reset),
91
92	PLATFORMMETHOD_END
93};
94
95static platform_def_t bare_platform = {
96	"bare metal",
97	bare_methods,
98	0
99};
100
101PLATFORM_DEF(bare_platform);
102
103static int
104bare_probe(platform_t plat)
105{
106	phandle_t cpus, child;
107	uint32_t sr;
108	int i, law_max, tgt;
109
110	if ((cpus = OF_finddevice("/cpus")) != 0) {
111		for (maxcpu = 0, child = OF_child(cpus); child != 0;
112		    child = OF_peer(child), maxcpu++)
113			;
114	} else
115		maxcpu = 1;
116
117	/*
118	 * Clear local access windows. Skip DRAM entries, so we don't shoot
119	 * ourselves in the foot.
120	 */
121	law_max = law_getmax();
122	for (i = 0; i < law_max; i++) {
123		sr = ccsr_read4(OCP85XX_LAWSR(i));
124		if ((sr & 0x80000000) == 0)
125			continue;
126		tgt = (sr & 0x01f00000) >> 20;
127		if (tgt == OCP85XX_TGTIF_RAM1 || tgt == OCP85XX_TGTIF_RAM2 ||
128		    tgt == OCP85XX_TGTIF_RAM_INTL)
129			continue;
130
131		ccsr_write4(OCP85XX_LAWSR(i), sr & 0x7fffffff);
132	}
133
134	return (BUS_PROBE_GENERIC);
135}
136
137#define MEM_REGIONS	8
138static struct mem_region avail_regions[MEM_REGIONS];
139
140void
141bare_mem_regions(platform_t plat, struct mem_region **phys, int *physsz,
142    struct mem_region **avail, int *availsz)
143{
144	uint32_t memsize;
145	int i, rv;
146
147	rv = fdt_get_mem_regions(avail_regions, availsz, &memsize);
148	if (rv != 0)
149		panic("%s: could not retrieve mem regions from the 'memory' "
150		    "node, error: %d", __func__, rv);
151
152	for (i = 0; i < *availsz; i++) {
153		if (avail_regions[i].mr_start < 1048576) {
154			avail_regions[i].mr_size =
155			    avail_regions[i].mr_size -
156			    (1048576 - avail_regions[i].mr_start);
157			avail_regions[i].mr_start = 1048576;
158		}
159	}
160	*avail = avail_regions;
161
162	/* On the bare metal platform phys == avail memory */
163	*physsz = *availsz;
164	*phys = *avail;
165}
166
167static u_long
168bare_timebase_freq(platform_t plat, struct cpuref *cpuref)
169{
170	u_long ticks;
171	phandle_t cpus, child;
172	pcell_t freq;
173
174	if (bootinfo != NULL) {
175		if (bootinfo[0] == 1) {
176			/* Backward compatibility. See 8-STABLE. */
177			ticks = bootinfo[3] >> 3;
178		} else {
179			/* Compatibility with Juniper's loader. */
180			ticks = bootinfo[5] >> 3;
181		}
182	} else
183		ticks = 0;
184
185	if ((cpus = OF_finddevice("/cpus")) == -1)
186		goto out;
187
188	if ((child = OF_child(cpus)) == 0)
189		goto out;
190
191	switch (OF_getproplen(child, "timebase-frequency")) {
192	case 4:
193	{
194		uint32_t tbase;
195		OF_getprop(child, "timebase-frequency", &tbase, sizeof(tbase));
196		ticks = tbase;
197		return (ticks);
198	}
199	case 8:
200	{
201		uint64_t tbase;
202		OF_getprop(child, "timebase-frequency", &tbase, sizeof(tbase));
203		ticks = tbase;
204		return (ticks);
205	}
206	default:
207		break;
208	}
209
210	freq = 0;
211	if (OF_getprop(child, "bus-frequency", (void *)&freq,
212	    sizeof(freq)) <= 0)
213		goto out;
214
215	/*
216	 * Time Base and Decrementer are updated every 8 CCB bus clocks.
217	 * HID0[SEL_TBCLK] = 0
218	 */
219	if (freq != 0)
220		ticks = freq / 8;
221
222out:
223	if (ticks <= 0)
224		panic("Unable to determine timebase frequency!");
225
226	return (ticks);
227}
228
229static int
230bare_smp_first_cpu(platform_t plat, struct cpuref *cpuref)
231{
232
233	cpu = 0;
234	cpuref->cr_cpuid = cpu;
235	cpuref->cr_hwref = cpuref->cr_cpuid;
236	if (bootverbose)
237		printf("powerpc_smp_first_cpu: cpuid %d\n", cpuref->cr_cpuid);
238	cpu++;
239
240	return (0);
241}
242
243static int
244bare_smp_next_cpu(platform_t plat, struct cpuref *cpuref)
245{
246
247	if (cpu >= maxcpu)
248		return (ENOENT);
249
250	cpuref->cr_cpuid = cpu++;
251	cpuref->cr_hwref = cpuref->cr_cpuid;
252	if (bootverbose)
253		printf("powerpc_smp_next_cpu: cpuid %d\n", cpuref->cr_cpuid);
254
255	return (0);
256}
257
258static int
259bare_smp_get_bsp(platform_t plat, struct cpuref *cpuref)
260{
261
262	cpuref->cr_cpuid = mfspr(SPR_PIR);
263	cpuref->cr_hwref = cpuref->cr_cpuid;
264
265	return (0);
266}
267
268static int
269bare_smp_start_cpu(platform_t plat, struct pcpu *pc)
270{
271#ifdef SMP
272	uint32_t *tlb1;
273	uint32_t bptr, eebpcr;
274	int i, timeout;
275
276	eebpcr = ccsr_read4(OCP85XX_EEBPCR);
277	if ((eebpcr & (1 << (pc->pc_cpuid + 24))) != 0) {
278		printf("SMP: CPU %d already out of hold-off state!\n",
279		    pc->pc_cpuid);
280		return (ENXIO);
281	}
282
283	ap_pcpu = pc;
284
285	i = 0;
286	tlb1 = bp_tlb1;
287	while (i < bp_ntlb1s && tlb1 < bp_tlb1_end) {
288		mtspr(SPR_MAS0, MAS0_TLBSEL(1) | MAS0_ESEL(i));
289		__asm __volatile("isync; tlbre");
290		tlb1[0] = mfspr(SPR_MAS1);
291		tlb1[1] = mfspr(SPR_MAS2);
292		tlb1[2] = mfspr(SPR_MAS3);
293		i++;
294		tlb1 += 3;
295	}
296	if (i < bp_ntlb1s)
297		bp_ntlb1s = i;
298
299	/*
300	 * Set BPTR to the physical address of the boot page
301	 */
302	bptr = ((uint32_t)__boot_page - KERNBASE) + kernload;
303	KASSERT((bptr & 0xfff) == 0,
304	    ("%s: boot page is not aligned (%#x)", __func__, bptr));
305	bptr = (bptr >> 12) | 0x80000000u;
306	ccsr_write4(OCP85XX_BPTR, bptr);
307	__asm __volatile("isync; msync");
308
309	/* Flush caches to have our changes hit DRAM. */
310	cpu_flush_dcache(__boot_page, 4096);
311
312	/*
313	 * Release AP from hold-off state
314	 */
315	eebpcr |= (1 << (pc->pc_cpuid + 24));
316	ccsr_write4(OCP85XX_EEBPCR, eebpcr);
317	__asm __volatile("isync; msync");
318
319	timeout = 500;
320	while (!pc->pc_awake && timeout--)
321		DELAY(1000);	/* wait 1ms */
322
323	/*
324	 * Disable boot page translation so that the 4K page at the default
325	 * address (= 0xfffff000) isn't permanently remapped and thus not
326	 * usable otherwise.
327	 */
328	ccsr_write4(OCP85XX_BPTR, 0);
329	__asm __volatile("isync; msync");
330
331	if (!pc->pc_awake)
332		printf("SMP: CPU %d didn't wake up.\n", pc->pc_cpuid);
333	return ((pc->pc_awake) ? 0 : EBUSY);
334#else
335	/* No SMP support */
336	return (ENXIO);
337#endif
338}
339
340static void
341booke_reset(platform_t plat)
342{
343
344	/*
345	 * Try the dedicated reset register first.
346	 * If the SoC doesn't have one, we'll fall
347	 * back to using the debug control register.
348	 */
349	ccsr_write4(OCP85XX_RSTCR, 2);
350
351	/* Clear DBCR0, disables debug interrupts and events. */
352	mtspr(SPR_DBCR0, 0);
353	__asm __volatile("isync");
354
355	/* Enable Debug Interrupts in MSR. */
356	mtmsr(mfmsr() | PSL_DE);
357
358	/* Enable debug interrupts and issue reset. */
359	mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM | DBCR0_RST_SYSTEM);
360
361	printf("Reset failed...\n");
362	while (1)
363		;
364}
365
366