machdep_e500.c revision 265996 
1/*-
2 * Copyright (c) 2011-2012 Semihalf.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: stable/10/sys/powerpc/booke/machdep_e500.c 265996 2014-05-14 00:51:26Z ian $");
29
30#include <sys/types.h>
31#include <sys/reboot.h>
32
33#include <machine/machdep.h>
34
35#include <dev/fdt/fdt_common.h>
36
37#include <powerpc/mpc85xx/mpc85xx.h>
38
39extern void dcache_enable(void);
40extern void dcache_inval(void);
41extern void icache_enable(void);
42extern void icache_inval(void);
43extern void l2cache_enable(void);
44extern void l2cache_inval(void);
45
46void
47booke_init_tlb(vm_paddr_t fdt_immr_pa)
48{
49
50}
51
52void
53booke_enable_l1_cache(void)
54{
55	uint32_t csr;
56
57	/* Enable D-cache if applicable */
58	csr = mfspr(SPR_L1CSR0);
59	if ((csr & L1CSR0_DCE) == 0) {
60		dcache_inval();
61		dcache_enable();
62	}
63
64	csr = mfspr(SPR_L1CSR0);
65	if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR0_DCE) == 0)
66		printf("L1 D-cache %sabled\n",
67		    (csr & L1CSR0_DCE) ? "en" : "dis");
68
69	/* Enable L1 I-cache if applicable. */
70	csr = mfspr(SPR_L1CSR1);
71	if ((csr & L1CSR1_ICE) == 0) {
72		icache_inval();
73		icache_enable();
74	}
75
76	csr = mfspr(SPR_L1CSR1);
77	if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR1_ICE) == 0)
78		printf("L1 I-cache %sabled\n",
79		    (csr & L1CSR1_ICE) ? "en" : "dis");
80}
81
82#if 0
83void
84booke_enable_l2_cache(void)
85{
86	uint32_t csr;
87
88	/* Enable L2 cache on E500mc */
89	if ((((mfpvr() >> 16) & 0xFFFF) == FSL_E500mc) ||
90	    (((mfpvr() >> 16) & 0xFFFF) == FSL_E5500)) {
91		csr = mfspr(SPR_L2CSR0);
92		if ((csr & L2CSR0_L2E) == 0) {
93			l2cache_inval();
94			l2cache_enable();
95		}
96
97		csr = mfspr(SPR_L2CSR0);
98		if ((boothowto & RB_VERBOSE) != 0 || (csr & L2CSR0_L2E) == 0)
99			printf("L2 cache %sabled\n",
100			    (csr & L2CSR0_L2E) ? "en" : "dis");
101	}
102}
103
104void
105booke_enable_l3_cache(void)
106{
107	uint32_t csr, size, ver;
108
109	/* Enable L3 CoreNet Platform Cache (CPC) */
110	ver = SVR_VER(mfspr(SPR_SVR));
111	if (ver == SVR_P2041 || ver == SVR_P2041E || ver == SVR_P3041 ||
112	    ver == SVR_P3041E || ver == SVR_P5020 || ver == SVR_P5020E) {
113		csr = ccsr_read4(OCP85XX_CPC_CSR0);
114		if ((csr & OCP85XX_CPC_CSR0_CE) == 0) {
115			l3cache_inval();
116			l3cache_enable();
117		}
118
119		csr = ccsr_read4(OCP85XX_CPC_CSR0);
120		if ((boothowto & RB_VERBOSE) != 0 ||
121		    (csr & OCP85XX_CPC_CSR0_CE) == 0) {
122			size = OCP85XX_CPC_CFG0_SZ_K(ccsr_read4(OCP85XX_CPC_CFG0));
123			printf("L3 Corenet Platform Cache: %d KB %sabled\n",
124			    size, (csr & OCP85XX_CPC_CSR0_CE) == 0 ?
125			    "dis" : "en");
126		}
127	}
128}
129
130void
131booke_disable_l2_cache(void)
132{
133}
134
135static void
136l3cache_inval(void)
137{
138
139	/* Flash invalidate the CPC and clear all the locks */
140	ccsr_write4(OCP85XX_CPC_CSR0, OCP85XX_CPC_CSR0_FI |
141	    OCP85XX_CPC_CSR0_LFC);
142	while (ccsr_read4(OCP85XX_CPC_CSR0) & (OCP85XX_CPC_CSR0_FI |
143	    OCP85XX_CPC_CSR0_LFC))
144		;
145}
146
147static void
148l3cache_enable(void)
149{
150
151	ccsr_write4(OCP85XX_CPC_CSR0, OCP85XX_CPC_CSR0_CE |
152	    OCP85XX_CPC_CSR0_PE);
153	/* Read back to sync write */
154	ccsr_read4(OCP85XX_CPC_CSR0);
155}
156#endif
157