trap_subr32.S revision 260670
1/* $FreeBSD: stable/10/sys/powerpc/aim/trap_subr32.S 260670 2014-01-15 05:19:37Z jhibbits $ */ 2/* $NetBSD: trap_subr.S,v 1.20 2002/04/22 23:20:08 kleink Exp $ */ 3 4/*- 5 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 6 * Copyright (C) 1995, 1996 TooLs GmbH. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by TooLs GmbH. 20 * 4. The name of TooLs GmbH may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/* 36 * NOTICE: This is not a standalone file. to use it, #include it in 37 * your port's locore.S, like so: 38 * 39 * #include <powerpc/aim/trap_subr.S> 40 */ 41 42/* 43 * Save/restore segment registers 44 */ 45#define RESTORE_SRS(pmap,sr) mtsr 0,sr; \ 46 lwz sr,1*4(pmap); mtsr 1,sr; \ 47 lwz sr,2*4(pmap); mtsr 2,sr; \ 48 lwz sr,3*4(pmap); mtsr 3,sr; \ 49 lwz sr,4*4(pmap); mtsr 4,sr; \ 50 lwz sr,5*4(pmap); mtsr 5,sr; \ 51 lwz sr,6*4(pmap); mtsr 6,sr; \ 52 lwz sr,7*4(pmap); mtsr 7,sr; \ 53 lwz sr,8*4(pmap); mtsr 8,sr; \ 54 lwz sr,9*4(pmap); mtsr 9,sr; \ 55 lwz sr,10*4(pmap); mtsr 10,sr; \ 56 lwz sr,11*4(pmap); mtsr 11,sr; \ 57 /* Skip segment 12 (USER_SR), which is restored differently */ \ 58 lwz sr,13*4(pmap); mtsr 13,sr; \ 59 lwz sr,14*4(pmap); mtsr 14,sr; \ 60 lwz sr,15*4(pmap); mtsr 15,sr; isync; 61 62/* 63 * User SRs are loaded through a pointer to the current pmap. 64 */ 65#define RESTORE_USER_SRS(pmap,sr) \ 66 GET_CPUINFO(pmap); \ 67 lwz pmap,PC_CURPMAP(pmap); \ 68 lwzu sr,PM_SR(pmap); \ 69 RESTORE_SRS(pmap,sr) \ 70 /* Restore SR 12 */ \ 71 lwz sr,12*4(pmap); mtsr 12,sr 72 73/* 74 * Kernel SRs are loaded directly from kernel_pmap_ 75 */ 76#define RESTORE_KERN_SRS(pmap,sr) \ 77 lis pmap,CNAME(kernel_pmap_store)@ha; \ 78 lwzu sr,CNAME(kernel_pmap_store)+PM_SR@l(pmap); \ 79 RESTORE_SRS(pmap,sr) 80 81/* 82 * FRAME_SETUP assumes: 83 * SPRG1 SP (1) 84 * SPRG3 trap type 85 * savearea r28-r31,DAR,DSISR (DAR & DSISR only for DSI traps) 86 * r28 LR 87 * r29 CR 88 * r30 scratch 89 * r31 scratch 90 * r1 kernel stack 91 * SRR0/1 as at start of trap 92 */ 93#define FRAME_SETUP(savearea) \ 94/* Have to enable translation to allow access of kernel stack: */ \ 95 GET_CPUINFO(%r31); \ 96 mfsrr0 %r30; \ 97 stw %r30,(savearea+CPUSAVE_SRR0)(%r31); /* save SRR0 */ \ 98 mfsrr1 %r30; \ 99 stw %r30,(savearea+CPUSAVE_SRR1)(%r31); /* save SRR1 */ \ 100 mfmsr %r30; \ 101 ori %r30,%r30,(PSL_DR|PSL_IR|PSL_RI)@l; /* relocation on */ \ 102 mtmsr %r30; /* stack can now be accessed */ \ 103 isync; \ 104 mfsprg1 %r31; /* get saved SP */ \ 105 stwu %r31,-FRAMELEN(%r1); /* save it in the callframe */ \ 106 stw %r0, FRAME_0+8(%r1); /* save r0 in the trapframe */ \ 107 stw %r31,FRAME_1+8(%r1); /* save SP " " */ \ 108 stw %r2, FRAME_2+8(%r1); /* save r2 " " */ \ 109 stw %r28,FRAME_LR+8(%r1); /* save LR " " */ \ 110 stw %r29,FRAME_CR+8(%r1); /* save CR " " */ \ 111 GET_CPUINFO(%r2); \ 112 lwz %r28,(savearea+CPUSAVE_R28)(%r2); /* get saved r28 */ \ 113 lwz %r29,(savearea+CPUSAVE_R29)(%r2); /* get saved r29 */ \ 114 lwz %r30,(savearea+CPUSAVE_R30)(%r2); /* get saved r30 */ \ 115 lwz %r31,(savearea+CPUSAVE_R31)(%r2); /* get saved r31 */ \ 116 stw %r3, FRAME_3+8(%r1); /* save r3-r31 */ \ 117 stw %r4, FRAME_4+8(%r1); \ 118 stw %r5, FRAME_5+8(%r1); \ 119 stw %r6, FRAME_6+8(%r1); \ 120 stw %r7, FRAME_7+8(%r1); \ 121 stw %r8, FRAME_8+8(%r1); \ 122 stw %r9, FRAME_9+8(%r1); \ 123 stw %r10, FRAME_10+8(%r1); \ 124 stw %r11, FRAME_11+8(%r1); \ 125 stw %r12, FRAME_12+8(%r1); \ 126 stw %r13, FRAME_13+8(%r1); \ 127 stw %r14, FRAME_14+8(%r1); \ 128 stw %r15, FRAME_15+8(%r1); \ 129 stw %r16, FRAME_16+8(%r1); \ 130 stw %r17, FRAME_17+8(%r1); \ 131 stw %r18, FRAME_18+8(%r1); \ 132 stw %r19, FRAME_19+8(%r1); \ 133 stw %r20, FRAME_20+8(%r1); \ 134 stw %r21, FRAME_21+8(%r1); \ 135 stw %r22, FRAME_22+8(%r1); \ 136 stw %r23, FRAME_23+8(%r1); \ 137 stw %r24, FRAME_24+8(%r1); \ 138 stw %r25, FRAME_25+8(%r1); \ 139 stw %r26, FRAME_26+8(%r1); \ 140 stw %r27, FRAME_27+8(%r1); \ 141 stw %r28, FRAME_28+8(%r1); \ 142 stw %r29, FRAME_29+8(%r1); \ 143 stw %r30, FRAME_30+8(%r1); \ 144 stw %r31, FRAME_31+8(%r1); \ 145 lwz %r28,(savearea+CPUSAVE_AIM_DAR)(%r2); /* saved DAR */ \ 146 lwz %r29,(savearea+CPUSAVE_AIM_DSISR)(%r2);/* saved DSISR */\ 147 lwz %r30,(savearea+CPUSAVE_SRR0)(%r2); /* saved SRR0 */ \ 148 lwz %r31,(savearea+CPUSAVE_SRR1)(%r2); /* saved SRR1 */ \ 149 mfxer %r3; \ 150 mfctr %r4; \ 151 mfsprg3 %r5; \ 152 stw %r3, FRAME_XER+8(1); /* save xer/ctr/exc */ \ 153 stw %r4, FRAME_CTR+8(1); \ 154 stw %r5, FRAME_EXC+8(1); \ 155 stw %r28,FRAME_AIM_DAR+8(1); \ 156 stw %r29,FRAME_AIM_DSISR+8(1); /* save dsisr/srr0/srr1 */ \ 157 stw %r30,FRAME_SRR0+8(1); \ 158 stw %r31,FRAME_SRR1+8(1); \ 159 lwz %r2,PC_CURTHREAD(%r2) /* set curthread pointer */ 160 161#define FRAME_LEAVE(savearea) \ 162/* Disable exceptions: */ \ 163 mfmsr %r2; \ 164 andi. %r2,%r2,~PSL_EE@l; \ 165 mtmsr %r2; \ 166 isync; \ 167/* Now restore regs: */ \ 168 lwz %r2,FRAME_SRR0+8(%r1); \ 169 lwz %r3,FRAME_SRR1+8(%r1); \ 170 lwz %r4,FRAME_CTR+8(%r1); \ 171 lwz %r5,FRAME_XER+8(%r1); \ 172 lwz %r6,FRAME_LR+8(%r1); \ 173 GET_CPUINFO(%r7); \ 174 stw %r2,(savearea+CPUSAVE_SRR0)(%r7); /* save SRR0 */ \ 175 stw %r3,(savearea+CPUSAVE_SRR1)(%r7); /* save SRR1 */ \ 176 lwz %r7,FRAME_CR+8(%r1); \ 177 mtctr %r4; \ 178 mtxer %r5; \ 179 mtlr %r6; \ 180 mtsprg1 %r7; /* save cr */ \ 181 lwz %r31,FRAME_31+8(%r1); /* restore r0-31 */ \ 182 lwz %r30,FRAME_30+8(%r1); \ 183 lwz %r29,FRAME_29+8(%r1); \ 184 lwz %r28,FRAME_28+8(%r1); \ 185 lwz %r27,FRAME_27+8(%r1); \ 186 lwz %r26,FRAME_26+8(%r1); \ 187 lwz %r25,FRAME_25+8(%r1); \ 188 lwz %r24,FRAME_24+8(%r1); \ 189 lwz %r23,FRAME_23+8(%r1); \ 190 lwz %r22,FRAME_22+8(%r1); \ 191 lwz %r21,FRAME_21+8(%r1); \ 192 lwz %r20,FRAME_20+8(%r1); \ 193 lwz %r19,FRAME_19+8(%r1); \ 194 lwz %r18,FRAME_18+8(%r1); \ 195 lwz %r17,FRAME_17+8(%r1); \ 196 lwz %r16,FRAME_16+8(%r1); \ 197 lwz %r15,FRAME_15+8(%r1); \ 198 lwz %r14,FRAME_14+8(%r1); \ 199 lwz %r13,FRAME_13+8(%r1); \ 200 lwz %r12,FRAME_12+8(%r1); \ 201 lwz %r11,FRAME_11+8(%r1); \ 202 lwz %r10,FRAME_10+8(%r1); \ 203 lwz %r9, FRAME_9+8(%r1); \ 204 lwz %r8, FRAME_8+8(%r1); \ 205 lwz %r7, FRAME_7+8(%r1); \ 206 lwz %r6, FRAME_6+8(%r1); \ 207 lwz %r5, FRAME_5+8(%r1); \ 208 lwz %r4, FRAME_4+8(%r1); \ 209 lwz %r3, FRAME_3+8(%r1); \ 210 lwz %r2, FRAME_2+8(%r1); \ 211 lwz %r0, FRAME_0+8(%r1); \ 212 lwz %r1, FRAME_1+8(%r1); \ 213/* Can't touch %r1 from here on */ \ 214 mtsprg2 %r2; /* save r2 & r3 */ \ 215 mtsprg3 %r3; \ 216/* Disable translation, machine check and recoverability: */ \ 217 mfmsr %r2; \ 218 andi. %r2,%r2,~(PSL_DR|PSL_IR|PSL_ME|PSL_RI)@l; \ 219 mtmsr %r2; \ 220 isync; \ 221/* Decide whether we return to user mode: */ \ 222 GET_CPUINFO(%r2); \ 223 lwz %r3,(savearea+CPUSAVE_SRR1)(%r2); \ 224 mtcr %r3; \ 225 bf 17,1f; /* branch if PSL_PR is false */ \ 226/* Restore user SRs */ \ 227 RESTORE_USER_SRS(%r2,%r3); \ 2281: mfsprg1 %r2; /* restore cr */ \ 229 mtcr %r2; \ 230 GET_CPUINFO(%r2); \ 231 lwz %r3,(savearea+CPUSAVE_SRR0)(%r2); /* restore srr0 */ \ 232 mtsrr0 %r3; \ 233 lwz %r3,(savearea+CPUSAVE_SRR1)(%r2); /* restore srr1 */ \ 234 \ 235 /* Make sure HV bit of MSR propagated to SRR1 */ \ 236 mfmsr %r2; \ 237 or %r3,%r2,%r3; \ 238 \ 239 mtsrr1 %r3; \ 240 mfsprg2 %r2; /* restore r2 & r3 */ \ 241 mfsprg3 %r3 242 243#ifdef KDTRACE_HOOKS 244 .data 245 .globl dtrace_invop_calltrap_addr 246 .align 4 247 .type dtrace_invop_calltrap_addr, @object 248 .size dtrace_invop_calltrap_addr, 4 249dtrace_invop_calltrap_addr: 250 .word 0 251 .word 0 252 253 .text 254#endif 255 256/* 257 * The next two routines are 64-bit glue code. The first is used to test if 258 * we are on a 64-bit system. By copying it to the illegal instruction 259 * handler, we can test for 64-bit mode by trying to execute a 64-bit 260 * instruction and seeing what happens. The second gets copied in front 261 * of all the other handlers to restore 32-bit bridge mode when traps 262 * are taken. 263 */ 264 265/* 64-bit test code. Sets SPRG2 to 0 if an illegal instruction is executed */ 266 267 .globl CNAME(testppc64),CNAME(testppc64size) 268CNAME(testppc64): 269 mtsprg1 %r31 270 mfsrr0 %r31 271 addi %r31, %r31, 4 272 mtsrr0 %r31 273 274 li %r31, 0 275 mtsprg2 %r31 276 mfsprg1 %r31 277 278 rfi 279CNAME(testppc64size) = .-CNAME(testppc64) 280 281 282/* 64-bit bridge mode restore snippet. Gets copied in front of everything else 283 * on 64-bit systems. */ 284 285 .globl CNAME(restorebridge),CNAME(restorebridgesize) 286CNAME(restorebridge): 287 mtsprg1 %r31 288 mfmsr %r31 289 clrldi %r31,%r31,1 290 mtmsrd %r31 291 mfsprg1 %r31 292 isync 293CNAME(restorebridgesize) = .-CNAME(restorebridge) 294 295#ifdef SMP 296/* 297 * Processor reset exception handler. These are typically 298 * the first instructions the processor executes after a 299 * software reset. We do this in two bits so that we are 300 * not still hanging around in the trap handling region 301 * once the MMU is turned on. 302 */ 303 .globl CNAME(rstcode), CNAME(rstsize) 304CNAME(rstcode): 305 ba cpu_reset 306CNAME(rstsize) = . - CNAME(rstcode) 307 308cpu_reset: 309 bl 1f 310 311 .space 124 312 3131: 314 mflr %r1 315 addi %r1,%r1,(124-16)@l 316 317 lis %r3,1@l 318 bla CNAME(cpudep_ap_early_bootstrap) 319 lis %r3,1@l 320 bla CNAME(pmap_cpu_bootstrap) 321 bla CNAME(cpudep_ap_bootstrap) 322 mr %r1,%r3 323 bla CNAME(machdep_ap_bootstrap) 324 325 /* Should not be reached */ 3269: 327 b 9b 328#endif 329 330/* 331 * This code gets copied to all the trap vectors 332 * (except ISI/DSI, ALI, and the interrupts) 333 */ 334 335 .globl CNAME(trapcode),CNAME(trapsize) 336CNAME(trapcode): 337 mtsprg1 %r1 /* save SP */ 338 mflr %r1 /* Save the old LR in r1 */ 339 mtsprg2 %r1 /* And then in SPRG2 */ 340 li %r1, 0x20 /* How to get the vector from LR */ 341 bla generictrap /* LR & SPRG3 is exception # */ 342CNAME(trapsize) = .-CNAME(trapcode) 343 344/* 345 * 64-bit version of trapcode. Identical, except it calls generictrap64. 346 */ 347 .globl CNAME(trapcode64) 348CNAME(trapcode64): 349 mtsprg1 %r1 /* save SP */ 350 mflr %r1 /* Save the old LR in r1 */ 351 mtsprg2 %r1 /* And then in SPRG2 */ 352 li %r1, 0x20 /* How to get the vector from LR */ 353 bla generictrap64 /* LR & SPRG3 is exception # */ 354 355/* 356 * For ALI: has to save DSISR and DAR 357 */ 358 .globl CNAME(alitrap),CNAME(alisize) 359CNAME(alitrap): 360 mtsprg1 %r1 /* save SP */ 361 GET_CPUINFO(%r1) 362 stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */ 363 stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 364 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 365 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 366 mfdar %r30 367 mfdsisr %r31 368 stw %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) 369 stw %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) 370 mfsprg1 %r1 /* restore SP, in case of branch */ 371 mflr %r28 /* save LR */ 372 mfcr %r29 /* save CR */ 373 374 /* Put our exception vector in SPRG3 */ 375 li %r31, EXC_ALI 376 mtsprg3 %r31 377 378 /* Test whether we already had PR set */ 379 mfsrr1 %r31 380 mtcr %r31 381 bla s_trap 382CNAME(alisize) = .-CNAME(alitrap) 383 384/* 385 * G2 specific: instuction TLB miss. 386 */ 387 .globl CNAME(imisstrap),CNAME(imisssize) 388CNAME(imisstrap): 389 mfspr %r2, SPR_HASH1 /* get first pointer */ 390 addi %r1, 0, 8 /* load 8 for counter */ 391 mfctr %r0 /* save counter */ 392 mfspr %r3, SPR_ICMP /* get first compare value */ 393 addi %r2, %r2, -8 /* pre dec the pointer */ 394im0: 395 mtctr %r1 /* load counter */ 396im1: 397 lwzu %r1, 8(%r2) /* get next pte */ 398 cmp 0, %r1, %r3 /* see if found pte */ 399 bdnzf 2, im1 /* dec count br if cmp ne and if 400 * count not zero */ 401 bne instr_sec_hash /* if not found set up second hash 402 * or exit */ 403 lwz %r1, +4(%r2) /* load tlb entry lower-word */ 404 andi. %r3, %r1, 8 /* check G bit */ 405 bne do_isi_prot /* if guarded, take an ISI */ 406 mtctr %r0 /* restore counter */ 407 mfspr %r0, SPR_IMISS /* get the miss address for the tlbli */ 408 mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */ 409 mtcrf 0x80, %r3 /* restore CR0 */ 410 mtspr SPR_RPA, %r1 /* set the pte */ 411 ori %r1, %r1, 0x100 /* set reference bit */ 412 srwi %r1, %r1, 8 /* get byte 7 of pte */ 413 tlbli %r0 /* load the itlb */ 414 stb %r1, +6(%r2) /* update page table */ 415 rfi /* return to executing program */ 416 417instr_sec_hash: 418 andi. %r1, %r3, 0x0040 /* see if we have done second hash */ 419 bne do_isi /* if so, go to ISI interrupt */ 420 mfspr %r2, SPR_HASH2 /* get the second pointer */ 421 ori %r3, %r3, 0x0040 /* change the compare value */ 422 addi %r1, %r0, 8 /* load 8 for counter */ 423 addi %r2, %r2, -8 /* pre dec for update on load */ 424 b im0 /* try second hash */ 425 426/* Create a faked ISI interrupt as the address was not found */ 427do_isi_prot: 428 mfspr %r3, SPR_SRR1 /* get srr1 */ 429 andi. %r2, %r3, 0xffff /* clean upper srr1 */ 430 addis %r2, %r2, 0x0800 /* or in srr<4> = 1 to flag prot 431 * violation */ 432 b isi1 433do_isi: 434 mfspr %r3, SPR_SRR1 /* get srr1 */ 435 andi. %r2, %r3, 0xffff /* clean srr1 */ 436 addis %r2, %r2, 0x4000 /* or in srr1<1> = 1 to flag pte 437 * not found */ 438isi1: 439 mtctr %r0 /* restore counter */ 440 mtspr SPR_SRR1, %r2 /* set srr1 */ 441 mfmsr %r0 /* get msr */ 442 xoris %r0, %r0, 0x2 /* flip the msr<tgpr> bit */ 443 mtcrf 0x80, %r3 /* restore CR0 */ 444 mtmsr %r0 /* flip back to the native gprs */ 445 ba EXC_ISI /* go to instr. access interrupt */ 446 447CNAME(imisssize) = .-CNAME(imisstrap) 448 449/* 450 * G2 specific: data load TLB miss. 451 */ 452 .globl CNAME(dlmisstrap),CNAME(dlmisssize) 453CNAME(dlmisstrap): 454 mfspr %r2, SPR_HASH1 /* get first pointer */ 455 addi %r1, 0, 8 /* load 8 for counter */ 456 mfctr %r0 /* save counter */ 457 mfspr %r3, SPR_DCMP /* get first compare value */ 458 addi %r2, %r2, -8 /* pre dec the pointer */ 459dm0: 460 mtctr %r1 /* load counter */ 461dm1: 462 lwzu %r1, 8(%r2) /* get next pte */ 463 cmp 0, 0, %r1, %r3 /* see if found pte */ 464 bdnzf 2, dm1 /* dec count br if cmp ne and if 465 * count not zero */ 466 bne data_sec_hash /* if not found set up second hash 467 * or exit */ 468 lwz %r1, +4(%r2) /* load tlb entry lower-word */ 469 mtctr %r0 /* restore counter */ 470 mfspr %r0, SPR_DMISS /* get the miss address for the tlbld */ 471 mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */ 472 mtcrf 0x80, %r3 /* restore CR0 */ 473 mtspr SPR_RPA, %r1 /* set the pte */ 474 ori %r1, %r1, 0x100 /* set reference bit */ 475 srwi %r1, %r1, 8 /* get byte 7 of pte */ 476 tlbld %r0 /* load the dtlb */ 477 stb %r1, +6(%r2) /* update page table */ 478 rfi /* return to executing program */ 479 480data_sec_hash: 481 andi. %r1, %r3, 0x0040 /* see if we have done second hash */ 482 bne do_dsi /* if so, go to DSI interrupt */ 483 mfspr %r2, SPR_HASH2 /* get the second pointer */ 484 ori %r3, %r3, 0x0040 /* change the compare value */ 485 addi %r1, 0, 8 /* load 8 for counter */ 486 addi %r2, %r2, -8 /* pre dec for update on load */ 487 b dm0 /* try second hash */ 488 489CNAME(dlmisssize) = .-CNAME(dlmisstrap) 490 491/* 492 * G2 specific: data store TLB miss. 493 */ 494 .globl CNAME(dsmisstrap),CNAME(dsmisssize) 495CNAME(dsmisstrap): 496 mfspr %r2, SPR_HASH1 /* get first pointer */ 497 addi %r1, 0, 8 /* load 8 for counter */ 498 mfctr %r0 /* save counter */ 499 mfspr %r3, SPR_DCMP /* get first compare value */ 500 addi %r2, %r2, -8 /* pre dec the pointer */ 501ds0: 502 mtctr %r1 /* load counter */ 503ds1: 504 lwzu %r1, 8(%r2) /* get next pte */ 505 cmp 0, 0, %r1, %r3 /* see if found pte */ 506 bdnzf 2, ds1 /* dec count br if cmp ne and if 507 * count not zero */ 508 bne data_store_sec_hash /* if not found set up second hash 509 * or exit */ 510 lwz %r1, +4(%r2) /* load tlb entry lower-word */ 511 andi. %r3, %r1, 0x80 /* check the C-bit */ 512 beq data_store_chk_prot /* if (C==0) 513 * go check protection modes */ 514ds2: 515 mtctr %r0 /* restore counter */ 516 mfspr %r0, SPR_DMISS /* get the miss address for the tlbld */ 517 mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */ 518 mtcrf 0x80, %r3 /* restore CR0 */ 519 mtspr SPR_RPA, %r1 /* set the pte */ 520 tlbld %r0 /* load the dtlb */ 521 rfi /* return to executing program */ 522 523data_store_sec_hash: 524 andi. %r1, %r3, 0x0040 /* see if we have done second hash */ 525 bne do_dsi /* if so, go to DSI interrupt */ 526 mfspr %r2, SPR_HASH2 /* get the second pointer */ 527 ori %r3, %r3, 0x0040 /* change the compare value */ 528 addi %r1, 0, 8 /* load 8 for counter */ 529 addi %r2, %r2, -8 /* pre dec for update on load */ 530 b ds0 /* try second hash */ 531 532/* Check the protection before setting PTE(c-bit) */ 533data_store_chk_prot: 534 rlwinm. %r3,%r1,30,0,1 /* test PP */ 535 bge- chk0 /* if (PP == 00 or PP == 01) 536 * goto chk0: */ 537 andi. %r3, %r1, 1 /* test PP[0] */ 538 beq+ chk2 /* return if PP[0] == 0 */ 539 b do_dsi_prot /* else DSIp */ 540chk0: 541 mfspr %r3,SPR_SRR1 /* get old msr */ 542 andis. %r3,%r3,0x0008 /* test the KEY bit (SRR1-bit 12) */ 543 beq chk2 /* if (KEY==0) goto chk2: */ 544 b do_dsi_prot /* else do_dsi_prot */ 545chk2: 546 ori %r1, %r1, 0x180 /* set reference and change bit */ 547 sth %r1, 6(%r2) /* update page table */ 548 b ds2 /* and back we go */ 549 550/* Create a faked DSI interrupt as the address was not found */ 551do_dsi: 552 mfspr %r3, SPR_SRR1 /* get srr1 */ 553 rlwinm %r1,%r3,9,6,6 /* get srr1<flag> to bit 6 for 554 * load/store, zero rest */ 555 addis %r1, %r1, 0x4000 /* or in dsisr<1> = 1 to flag pte 556 * not found */ 557 b dsi1 558 559do_dsi_prot: 560 mfspr %r3, SPR_SRR1 /* get srr1 */ 561 rlwinm %r1,%r3,9,6,6 /* get srr1<flag> to bit 6 for 562 *load/store, zero rest */ 563 addis %r1, %r1, 0x0800 /* or in dsisr<4> = 1 to flag prot 564 * violation */ 565 566dsi1: 567 mtctr %r0 /* restore counter */ 568 andi. %r2, %r3, 0xffff /* clear upper bits of srr1 */ 569 mtspr SPR_SRR1, %r2 /* set srr1 */ 570 mtspr SPR_DSISR, %r1 /* load the dsisr */ 571 mfspr %r1, SPR_DMISS /* get miss address */ 572 rlwinm. %r2,%r2,0,31,31 /* test LE bit */ 573 beq dsi2 /* if little endian then: */ 574 xor %r1, %r1, 0x07 /* de-mung the data address */ 575dsi2: 576 mtspr SPR_DAR, %r1 /* put in dar */ 577 mfmsr %r0 /* get msr */ 578 xoris %r0, %r0, 0x2 /* flip the msr<tgpr> bit */ 579 mtcrf 0x80, %r3 /* restore CR0 */ 580 mtmsr %r0 /* flip back to the native gprs */ 581 ba EXC_DSI /* branch to DSI interrupt */ 582 583CNAME(dsmisssize) = .-CNAME(dsmisstrap) 584 585/* 586 * Similar to the above for DSI 587 * Has to handle BAT spills 588 * and standard pagetable spills 589 */ 590 .globl CNAME(dsitrap),CNAME(dsisize) 591CNAME(dsitrap): 592 mtsprg1 %r1 /* save SP */ 593 GET_CPUINFO(%r1) 594 stw %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */ 595 stw %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1) 596 stw %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 597 stw %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 598 mfsprg1 %r1 /* restore SP */ 599 mfcr %r29 /* save CR */ 600 mfxer %r30 /* save XER */ 601 mtsprg2 %r30 /* in SPRG2 */ 602 mfsrr1 %r31 /* test kernel mode */ 603 mtcr %r31 604 bt 17,1f /* branch if PSL_PR is set */ 605 mfdar %r31 /* get fault address */ 606 rlwinm %r31,%r31,7,25,28 /* get segment * 8 */ 607 608 /* get batu */ 609 addis %r31,%r31,CNAME(battable)@ha 610 lwz %r30,CNAME(battable)@l(31) 611 mtcr %r30 612 bf 30,1f /* branch if supervisor valid is 613 false */ 614 /* get batl */ 615 lwz %r31,CNAME(battable)+4@l(31) 616/* We randomly use the highest two bat registers here */ 617 mftb %r28 618 andi. %r28,%r28,1 619 bne 2f 620 mtdbatu 2,%r30 621 mtdbatl 2,%r31 622 b 3f 6232: 624 mtdbatu 3,%r30 625 mtdbatl 3,%r31 6263: 627 mfsprg2 %r30 /* restore XER */ 628 mtxer %r30 629 mtcr %r29 /* restore CR */ 630 mtsprg1 %r1 631 GET_CPUINFO(%r1) 632 lwz %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* restore r28-r31 */ 633 lwz %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1) 634 lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 635 lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 636 mfsprg1 %r1 637 rfi /* return to trapped code */ 6381: 639 mflr %r28 /* save LR (SP already saved) */ 640 bla disitrap 641CNAME(dsisize) = .-CNAME(dsitrap) 642 643/* 644 * Preamble code for DSI/ISI traps 645 */ 646disitrap: 647 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */ 648 mflr %r1 649 andi. %r1,%r1,0xff00 650 mtsprg3 %r1 651 652 GET_CPUINFO(%r1) 653 lwz %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) 654 stw %r30,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 655 lwz %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) 656 stw %r31,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 657 lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 658 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 659 lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 660 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 661 mfdar %r30 662 mfdsisr %r31 663 stw %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) 664 stw %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) 665 666#ifdef KDB 667 /* Try and detect a kernel stack overflow */ 668 mfsrr1 %r31 669 mtcr %r31 670 bt 17,realtrap /* branch is user mode */ 671 mfsprg1 %r31 /* get old SP */ 672 sub. %r30,%r31,%r30 /* SP - DAR */ 673 bge 1f 674 neg %r30,%r30 /* modulo value */ 6751: cmplwi %cr0,%r30,4096 /* is DAR within a page of SP? */ 676 bge %cr0,realtrap /* no, too far away. */ 677 678 /* Now convert this DSI into a DDB trap. */ 679 GET_CPUINFO(%r1) 680 lwz %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) /* get DAR */ 681 stw %r30,(PC_DBSAVE +CPUSAVE_AIM_DAR)(%r1) /* save DAR */ 682 lwz %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) /* get DSISR */ 683 stw %r31,(PC_DBSAVE +CPUSAVE_AIM_DSISR)(%r1) /* save DSISR */ 684 lwz %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* get r28 */ 685 stw %r30,(PC_DBSAVE +CPUSAVE_R28)(%r1) /* save r28 */ 686 lwz %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) /* get r29 */ 687 stw %r31,(PC_DBSAVE +CPUSAVE_R29)(%r1) /* save r29 */ 688 lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) /* get r30 */ 689 stw %r30,(PC_DBSAVE +CPUSAVE_R30)(%r1) /* save r30 */ 690 lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) /* get r31 */ 691 stw %r31,(PC_DBSAVE +CPUSAVE_R31)(%r1) /* save r31 */ 692 b dbtrap 693#endif 694 695 /* XXX need stack probe here */ 696realtrap: 697/* Test whether we already had PR set */ 698 mfsrr1 %r1 699 mtcr %r1 700 mfsprg1 %r1 /* restore SP (might have been 701 overwritten) */ 702 bf 17,k_trap /* branch if PSL_PR is false */ 703 GET_CPUINFO(%r1) 704 lwz %r1,PC_CURPCB(%r1) 705 RESTORE_KERN_SRS(%r30,%r31) /* enable kernel mapping */ 706 ba s_trap 707 708/* 709 * generictrap does some standard setup for trap handling to minimize 710 * the code that need be installed in the actual vectors. It expects 711 * the following conditions. 712 * 713 * R1 - Trap vector = LR & (0xff00 | R1) 714 * SPRG1 - Original R1 contents 715 * SPRG2 - Original LR 716 */ 717 718generictrap64: 719 mtsprg3 %r31 720 mfmsr %r31 721 clrldi %r31,%r31,1 722 mtmsrd %r31 723 mfsprg3 %r31 724 isync 725 726generictrap: 727 /* Save R1 for computing the exception vector */ 728 mtsprg3 %r1 729 730 /* Save interesting registers */ 731 GET_CPUINFO(%r1) 732 stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */ 733 stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 734 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 735 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 736 mfsprg1 %r1 /* restore SP, in case of branch */ 737 mfsprg2 %r28 /* save LR */ 738 mfcr %r29 /* save CR */ 739 740 /* Compute the exception vector from the link register */ 741 mfsprg3 %r31 742 ori %r31,%r31,0xff00 743 mflr %r30 744 and %r30,%r30,%r31 745 mtsprg3 %r30 746 747 /* Test whether we already had PR set */ 748 mfsrr1 %r31 749 mtcr %r31 750 751s_trap: 752 bf 17,k_trap /* branch if PSL_PR is false */ 753 GET_CPUINFO(%r1) 754u_trap: 755 lwz %r1,PC_CURPCB(%r1) 756 RESTORE_KERN_SRS(%r30,%r31) /* enable kernel mapping */ 757 758/* 759 * Now the common trap catching code. 760 */ 761k_trap: 762 FRAME_SETUP(PC_TEMPSAVE) 763 /* Restore USER_SR */ 764 GET_CPUINFO(%r30) 765 lwz %r30,PC_CURPCB(%r30) 766 lwz %r30,PCB_AIM_USR_VSID(%r30) 767 mtsr USER_SR,%r30; sync; isync 768/* Call C interrupt dispatcher: */ 769trapagain: 770 addi %r3,%r1,8 771 bl CNAME(powerpc_interrupt) 772 .globl CNAME(trapexit) /* backtrace code sentinel */ 773CNAME(trapexit): 774 775/* Disable interrupts: */ 776 mfmsr %r3 777 andi. %r3,%r3,~PSL_EE@l 778 mtmsr %r3 779/* Test AST pending: */ 780 lwz %r5,FRAME_SRR1+8(%r1) 781 mtcr %r5 782 bf 17,1f /* branch if PSL_PR is false */ 783 784 GET_CPUINFO(%r3) /* get per-CPU pointer */ 785 lwz %r4, TD_FLAGS(%r2) /* get thread flags value 786 * (r2 is curthread) */ 787 lis %r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@h 788 ori %r5,%r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@l 789 and. %r4,%r4,%r5 790 beq 1f 791 mfmsr %r3 /* re-enable interrupts */ 792 ori %r3,%r3,PSL_EE@l 793 mtmsr %r3 794 isync 795 addi %r3,%r1,8 796 bl CNAME(ast) 797 .globl CNAME(asttrapexit) /* backtrace code sentinel #2 */ 798CNAME(asttrapexit): 799 b trapexit /* test ast ret value ? */ 8001: 801 FRAME_LEAVE(PC_TEMPSAVE) 802 803 .globl CNAME(rfi_patch1) /* replace rfi with rfid on ppc64 */ 804CNAME(rfi_patch1): 805 rfi 806 807 .globl CNAME(rfid_patch) 808CNAME(rfid_patch): 809 rfid 810 811#if defined(KDB) 812/* 813 * Deliberate entry to dbtrap 814 */ 815 .globl CNAME(breakpoint) 816CNAME(breakpoint): 817 mtsprg1 %r1 818 mfmsr %r3 819 mtsrr1 %r3 820 andi. %r3,%r3,~(PSL_EE|PSL_ME)@l 821 mtmsr %r3 /* disable interrupts */ 822 isync 823 GET_CPUINFO(%r3) 824 stw %r28,(PC_DBSAVE+CPUSAVE_R28)(%r3) 825 stw %r29,(PC_DBSAVE+CPUSAVE_R29)(%r3) 826 stw %r30,(PC_DBSAVE+CPUSAVE_R30)(%r3) 827 stw %r31,(PC_DBSAVE+CPUSAVE_R31)(%r3) 828 mflr %r28 829 li %r29,EXC_BPT 830 mtlr %r29 831 mfcr %r29 832 mtsrr0 %r28 833 834/* 835 * Now the kdb trap catching code. 836 */ 837dbtrap: 838 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */ 839 mflr %r1 840 andi. %r1,%r1,0xff00 841 mtsprg3 %r1 842 843 lis %r1,(tmpstk+TMPSTKSZ-16)@ha /* get new SP */ 844 addi %r1,%r1,(tmpstk+TMPSTKSZ-16)@l 845 846 FRAME_SETUP(PC_DBSAVE) 847/* Call C trap code: */ 848 addi %r3,%r1,8 849 bl CNAME(db_trap_glue) 850 or. %r3,%r3,%r3 851 bne dbleave 852/* This wasn't for KDB, so switch to real trap: */ 853 lwz %r3,FRAME_EXC+8(%r1) /* save exception */ 854 GET_CPUINFO(%r4) 855 stw %r3,(PC_DBSAVE+CPUSAVE_R31)(%r4) 856 FRAME_LEAVE(PC_DBSAVE) 857 mtsprg1 %r1 /* prepare for entrance to realtrap */ 858 GET_CPUINFO(%r1) 859 stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 860 stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 861 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 862 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 863 mflr %r28 864 mfcr %r29 865 lwz %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) 866 mtsprg3 %r31 /* SPRG3 was clobbered by FRAME_LEAVE */ 867 mfsprg1 %r1 868 b realtrap 869dbleave: 870 FRAME_LEAVE(PC_DBSAVE) 871 .globl CNAME(rfi_patch2) /* replace rfi with rfid on ppc64 */ 872CNAME(rfi_patch2): 873 rfi 874 875/* 876 * In case of KDB we want a separate trap catcher for it 877 */ 878 .globl CNAME(dblow),CNAME(dbsize) 879CNAME(dblow): 880 mtsprg1 %r1 /* save SP */ 881 mtsprg2 %r29 /* save r29 */ 882 mfcr %r29 /* save CR in r29 */ 883 mfsrr1 %r1 884 mtcr %r1 885 bf 17,2f /* branch if privileged */ 8861: 887 /* Unprivileged case */ 888 mtcr %r29 /* put the condition register back */ 889 mfsprg2 %r29 /* ... and r29 */ 890 mflr %r1 /* save LR */ 891 mtsprg2 %r1 /* And then in SPRG2 */ 892 li %r1, 0 /* How to get the vector from LR */ 893 894 bla generictrap /* and we look like a generic trap */ 8952: 896#ifdef KDTRACE_HOOKS 897 /* Privileged, so drop to KDB */ 898 mfsrr0 %r1 899 mtsprg3 %r3 900 lwz %r1,0(%r1) 901 /* Check if it's a DTrace trap. */ 902 li %r3,0x0808 903 addis %r3,%r3,0x7c81 904 cmplw %cr0,%r3,%r1 905 mfsprg3 %r3 906 beq %cr0,1b 907#endif 908 /* Privileged, so drop to KDB */ 909 GET_CPUINFO(%r1) 910 stw %r28,(PC_DBSAVE+CPUSAVE_R28)(%r1) /* free r28 */ 911 mfsprg2 %r28 /* r29 holds cr... */ 912 stw %r28,(PC_DBSAVE+CPUSAVE_R29)(%r1) /* free r29 */ 913 stw %r30,(PC_DBSAVE+CPUSAVE_R30)(%r1) /* free r30 */ 914 stw %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) /* free r31 */ 915 mflr %r28 /* save LR */ 916 bla dbtrap 917CNAME(dbsize) = .-CNAME(dblow) 918#endif /* KDB */ 919