mmu_oea64.c revision 287945
1/*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29/*- 30 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 31 * Copyright (C) 1995, 1996 TooLs GmbH. 32 * All rights reserved. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. All advertising materials mentioning features or use of this software 43 * must display the following acknowledgement: 44 * This product includes software developed by TooLs GmbH. 45 * 4. The name of TooLs GmbH may not be used to endorse or promote products 46 * derived from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 51 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 52 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 53 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 54 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 55 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 56 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 57 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 58 * 59 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 60 */ 61/*- 62 * Copyright (C) 2001 Benno Rice. 63 * All rights reserved. 64 * 65 * Redistribution and use in source and binary forms, with or without 66 * modification, are permitted provided that the following conditions 67 * are met: 68 * 1. Redistributions of source code must retain the above copyright 69 * notice, this list of conditions and the following disclaimer. 70 * 2. Redistributions in binary form must reproduce the above copyright 71 * notice, this list of conditions and the following disclaimer in the 72 * documentation and/or other materials provided with the distribution. 73 * 74 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 75 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 76 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 77 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 78 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 79 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 80 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 81 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 82 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 83 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 84 */ 85 86#include <sys/cdefs.h> 87__FBSDID("$FreeBSD: stable/10/sys/powerpc/aim/mmu_oea64.c 287945 2015-09-17 23:31:44Z rstone $"); 88 89/* 90 * Manages physical address maps. 91 * 92 * Since the information managed by this module is also stored by the 93 * logical address mapping module, this module may throw away valid virtual 94 * to physical mappings at almost any time. However, invalidations of 95 * mappings must be done as requested. 96 * 97 * In order to cope with hardware architectures which make virtual to 98 * physical map invalidates expensive, this module may delay invalidate 99 * reduced protection operations until such time as they are actually 100 * necessary. This module is given full information as to which processors 101 * are currently using which maps, and to when physical maps must be made 102 * correct. 103 */ 104 105#include "opt_compat.h" 106#include "opt_kstack_pages.h" 107 108#include <sys/param.h> 109#include <sys/kernel.h> 110#include <sys/queue.h> 111#include <sys/cpuset.h> 112#include <sys/ktr.h> 113#include <sys/lock.h> 114#include <sys/msgbuf.h> 115#include <sys/malloc.h> 116#include <sys/mutex.h> 117#include <sys/proc.h> 118#include <sys/rwlock.h> 119#include <sys/sched.h> 120#include <sys/sysctl.h> 121#include <sys/systm.h> 122#include <sys/vmmeter.h> 123 124#include <sys/kdb.h> 125 126#include <dev/ofw/openfirm.h> 127 128#include <vm/vm.h> 129#include <vm/vm_param.h> 130#include <vm/vm_kern.h> 131#include <vm/vm_page.h> 132#include <vm/vm_map.h> 133#include <vm/vm_object.h> 134#include <vm/vm_extern.h> 135#include <vm/vm_pageout.h> 136#include <vm/uma.h> 137 138#include <machine/_inttypes.h> 139#include <machine/cpu.h> 140#include <machine/platform.h> 141#include <machine/frame.h> 142#include <machine/md_var.h> 143#include <machine/psl.h> 144#include <machine/bat.h> 145#include <machine/hid.h> 146#include <machine/pte.h> 147#include <machine/sr.h> 148#include <machine/trap.h> 149#include <machine/mmuvar.h> 150 151#include "mmu_oea64.h" 152#include "mmu_if.h" 153#include "moea64_if.h" 154 155void moea64_release_vsid(uint64_t vsid); 156uintptr_t moea64_get_unique_vsid(void); 157 158#define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 159#define ENABLE_TRANS(msr) mtmsr(msr) 160 161#define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 162#define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 163#define VSID_HASH_MASK 0x0000007fffffffffULL 164 165/* 166 * Locking semantics: 167 * -- Read lock: if no modifications are being made to either the PVO lists 168 * or page table or if any modifications being made result in internal 169 * changes (e.g. wiring, protection) such that the existence of the PVOs 170 * is unchanged and they remain associated with the same pmap (in which 171 * case the changes should be protected by the pmap lock) 172 * -- Write lock: required if PTEs/PVOs are being inserted or removed. 173 */ 174 175#define LOCK_TABLE_RD() rw_rlock(&moea64_table_lock) 176#define UNLOCK_TABLE_RD() rw_runlock(&moea64_table_lock) 177#define LOCK_TABLE_WR() rw_wlock(&moea64_table_lock) 178#define UNLOCK_TABLE_WR() rw_wunlock(&moea64_table_lock) 179 180struct ofw_map { 181 cell_t om_va; 182 cell_t om_len; 183 uint64_t om_pa; 184 cell_t om_mode; 185}; 186 187extern unsigned char _etext[]; 188extern unsigned char _end[]; 189 190extern int dumpsys_minidump; 191 192/* 193 * Map of physical memory regions. 194 */ 195static struct mem_region *regions; 196static struct mem_region *pregions; 197static u_int phys_avail_count; 198static int regions_sz, pregions_sz; 199 200extern void bs_remap_earlyboot(void); 201 202/* 203 * Lock for the pteg and pvo tables. 204 */ 205struct rwlock moea64_table_lock; 206struct mtx moea64_slb_mutex; 207 208/* 209 * PTEG data. 210 */ 211u_int moea64_pteg_count; 212u_int moea64_pteg_mask; 213 214/* 215 * PVO data. 216 */ 217struct pvo_head *moea64_pvo_table; /* pvo entries by pteg index */ 218 219uma_zone_t moea64_upvo_zone; /* zone for pvo entries for unmanaged pages */ 220uma_zone_t moea64_mpvo_zone; /* zone for pvo entries for managed pages */ 221 222#define BPVO_POOL_SIZE 327680 223static struct pvo_entry *moea64_bpvo_pool; 224static int moea64_bpvo_pool_index = 0; 225 226#define VSID_NBPW (sizeof(u_int32_t) * 8) 227#ifdef __powerpc64__ 228#define NVSIDS (NPMAPS * 16) 229#define VSID_HASHMASK 0xffffffffUL 230#else 231#define NVSIDS NPMAPS 232#define VSID_HASHMASK 0xfffffUL 233#endif 234static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW]; 235 236static boolean_t moea64_initialized = FALSE; 237 238/* 239 * Statistics. 240 */ 241u_int moea64_pte_valid = 0; 242u_int moea64_pte_overflow = 0; 243u_int moea64_pvo_entries = 0; 244u_int moea64_pvo_enter_calls = 0; 245u_int moea64_pvo_remove_calls = 0; 246SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 247 &moea64_pte_valid, 0, ""); 248SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 249 &moea64_pte_overflow, 0, ""); 250SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 251 &moea64_pvo_entries, 0, ""); 252SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 253 &moea64_pvo_enter_calls, 0, ""); 254SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 255 &moea64_pvo_remove_calls, 0, ""); 256 257vm_offset_t moea64_scratchpage_va[2]; 258struct pvo_entry *moea64_scratchpage_pvo[2]; 259uintptr_t moea64_scratchpage_pte[2]; 260struct mtx moea64_scratchpage_mtx; 261 262uint64_t moea64_large_page_mask = 0; 263uint64_t moea64_large_page_size = 0; 264int moea64_large_page_shift = 0; 265 266/* 267 * PVO calls. 268 */ 269static int moea64_pvo_enter(mmu_t, pmap_t, uma_zone_t, struct pvo_head *, 270 vm_offset_t, vm_offset_t, uint64_t, int, int8_t); 271static void moea64_pvo_remove(mmu_t, struct pvo_entry *); 272static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t); 273 274/* 275 * Utility routines. 276 */ 277static boolean_t moea64_query_bit(mmu_t, vm_page_t, u_int64_t); 278static u_int moea64_clear_bit(mmu_t, vm_page_t, u_int64_t); 279static void moea64_kremove(mmu_t, vm_offset_t); 280static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va, 281 vm_offset_t pa, vm_size_t sz); 282 283/* 284 * Kernel MMU interface 285 */ 286void moea64_clear_modify(mmu_t, vm_page_t); 287void moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 288void moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 289 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 290int moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, 291 u_int flags, int8_t psind); 292void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 293 vm_prot_t); 294void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 295vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 296vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 297void moea64_init(mmu_t); 298boolean_t moea64_is_modified(mmu_t, vm_page_t); 299boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 300boolean_t moea64_is_referenced(mmu_t, vm_page_t); 301int moea64_ts_referenced(mmu_t, vm_page_t); 302vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 303boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 304int moea64_page_wired_mappings(mmu_t, vm_page_t); 305void moea64_pinit(mmu_t, pmap_t); 306void moea64_pinit0(mmu_t, pmap_t); 307void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 308void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 309void moea64_qremove(mmu_t, vm_offset_t, int); 310void moea64_release(mmu_t, pmap_t); 311void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 312void moea64_remove_pages(mmu_t, pmap_t); 313void moea64_remove_all(mmu_t, vm_page_t); 314void moea64_remove_write(mmu_t, vm_page_t); 315void moea64_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 316void moea64_zero_page(mmu_t, vm_page_t); 317void moea64_zero_page_area(mmu_t, vm_page_t, int, int); 318void moea64_zero_page_idle(mmu_t, vm_page_t); 319void moea64_activate(mmu_t, struct thread *); 320void moea64_deactivate(mmu_t, struct thread *); 321void *moea64_mapdev(mmu_t, vm_paddr_t, vm_size_t); 322void *moea64_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t); 323void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 324vm_paddr_t moea64_kextract(mmu_t, vm_offset_t); 325void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma); 326void moea64_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t ma); 327void moea64_kenter(mmu_t, vm_offset_t, vm_paddr_t); 328boolean_t moea64_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 329static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 330vm_offset_t moea64_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 331 vm_size_t *sz); 332struct pmap_md * moea64_scan_md(mmu_t mmu, struct pmap_md *prev); 333 334static mmu_method_t moea64_methods[] = { 335 MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 336 MMUMETHOD(mmu_copy_page, moea64_copy_page), 337 MMUMETHOD(mmu_copy_pages, moea64_copy_pages), 338 MMUMETHOD(mmu_enter, moea64_enter), 339 MMUMETHOD(mmu_enter_object, moea64_enter_object), 340 MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 341 MMUMETHOD(mmu_extract, moea64_extract), 342 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 343 MMUMETHOD(mmu_init, moea64_init), 344 MMUMETHOD(mmu_is_modified, moea64_is_modified), 345 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable), 346 MMUMETHOD(mmu_is_referenced, moea64_is_referenced), 347 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 348 MMUMETHOD(mmu_map, moea64_map), 349 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 350 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 351 MMUMETHOD(mmu_pinit, moea64_pinit), 352 MMUMETHOD(mmu_pinit0, moea64_pinit0), 353 MMUMETHOD(mmu_protect, moea64_protect), 354 MMUMETHOD(mmu_qenter, moea64_qenter), 355 MMUMETHOD(mmu_qremove, moea64_qremove), 356 MMUMETHOD(mmu_release, moea64_release), 357 MMUMETHOD(mmu_remove, moea64_remove), 358 MMUMETHOD(mmu_remove_pages, moea64_remove_pages), 359 MMUMETHOD(mmu_remove_all, moea64_remove_all), 360 MMUMETHOD(mmu_remove_write, moea64_remove_write), 361 MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 362 MMUMETHOD(mmu_unwire, moea64_unwire), 363 MMUMETHOD(mmu_zero_page, moea64_zero_page), 364 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 365 MMUMETHOD(mmu_zero_page_idle, moea64_zero_page_idle), 366 MMUMETHOD(mmu_activate, moea64_activate), 367 MMUMETHOD(mmu_deactivate, moea64_deactivate), 368 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr), 369 370 /* Internal interfaces */ 371 MMUMETHOD(mmu_mapdev, moea64_mapdev), 372 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr), 373 MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 374 MMUMETHOD(mmu_kextract, moea64_kextract), 375 MMUMETHOD(mmu_kenter, moea64_kenter), 376 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr), 377 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 378 MMUMETHOD(mmu_scan_md, moea64_scan_md), 379 MMUMETHOD(mmu_dumpsys_map, moea64_dumpsys_map), 380 381 { 0, 0 } 382}; 383 384MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0); 385 386static __inline u_int 387va_to_pteg(uint64_t vsid, vm_offset_t addr, int large) 388{ 389 uint64_t hash; 390 int shift; 391 392 shift = large ? moea64_large_page_shift : ADDR_PIDX_SHFT; 393 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)addr & ADDR_PIDX) >> 394 shift); 395 return (hash & moea64_pteg_mask); 396} 397 398static __inline struct pvo_head * 399vm_page_to_pvoh(vm_page_t m) 400{ 401 402 return (&m->md.mdpg_pvoh); 403} 404 405static __inline void 406moea64_pte_create(struct lpte *pt, uint64_t vsid, vm_offset_t va, 407 uint64_t pte_lo, int flags) 408{ 409 410 /* 411 * Construct a PTE. Default to IMB initially. Valid bit only gets 412 * set when the real pte is set in memory. 413 * 414 * Note: Don't set the valid bit for correct operation of tlb update. 415 */ 416 pt->pte_hi = (vsid << LPTE_VSID_SHIFT) | 417 (((uint64_t)(va & ADDR_PIDX) >> ADDR_API_SHFT64) & LPTE_API); 418 419 if (flags & PVO_LARGE) 420 pt->pte_hi |= LPTE_BIG; 421 422 pt->pte_lo = pte_lo; 423} 424 425static __inline uint64_t 426moea64_calc_wimg(vm_offset_t pa, vm_memattr_t ma) 427{ 428 uint64_t pte_lo; 429 int i; 430 431 if (ma != VM_MEMATTR_DEFAULT) { 432 switch (ma) { 433 case VM_MEMATTR_UNCACHEABLE: 434 return (LPTE_I | LPTE_G); 435 case VM_MEMATTR_WRITE_COMBINING: 436 case VM_MEMATTR_WRITE_BACK: 437 case VM_MEMATTR_PREFETCHABLE: 438 return (LPTE_I); 439 case VM_MEMATTR_WRITE_THROUGH: 440 return (LPTE_W | LPTE_M); 441 } 442 } 443 444 /* 445 * Assume the page is cache inhibited and access is guarded unless 446 * it's in our available memory array. 447 */ 448 pte_lo = LPTE_I | LPTE_G; 449 for (i = 0; i < pregions_sz; i++) { 450 if ((pa >= pregions[i].mr_start) && 451 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 452 pte_lo &= ~(LPTE_I | LPTE_G); 453 pte_lo |= LPTE_M; 454 break; 455 } 456 } 457 458 return pte_lo; 459} 460 461/* 462 * Quick sort callout for comparing memory regions. 463 */ 464static int om_cmp(const void *a, const void *b); 465 466static int 467om_cmp(const void *a, const void *b) 468{ 469 const struct ofw_map *mapa; 470 const struct ofw_map *mapb; 471 472 mapa = a; 473 mapb = b; 474 if (mapa->om_pa < mapb->om_pa) 475 return (-1); 476 else if (mapa->om_pa > mapb->om_pa) 477 return (1); 478 else 479 return (0); 480} 481 482static void 483moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz) 484{ 485 struct ofw_map translations[sz/(4*sizeof(cell_t))]; /*>= 4 cells per */ 486 pcell_t acells, trans_cells[sz/sizeof(cell_t)]; 487 register_t msr; 488 vm_offset_t off; 489 vm_paddr_t pa_base; 490 int i, j; 491 492 bzero(translations, sz); 493 OF_getprop(OF_finddevice("/"), "#address-cells", &acells, 494 sizeof(acells)); 495 if (OF_getprop(mmu, "translations", trans_cells, sz) == -1) 496 panic("moea64_bootstrap: can't get ofw translations"); 497 498 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 499 sz /= sizeof(cell_t); 500 for (i = 0, j = 0; i < sz; j++) { 501 translations[j].om_va = trans_cells[i++]; 502 translations[j].om_len = trans_cells[i++]; 503 translations[j].om_pa = trans_cells[i++]; 504 if (acells == 2) { 505 translations[j].om_pa <<= 32; 506 translations[j].om_pa |= trans_cells[i++]; 507 } 508 translations[j].om_mode = trans_cells[i++]; 509 } 510 KASSERT(i == sz, ("Translations map has incorrect cell count (%d/%zd)", 511 i, sz)); 512 513 sz = j; 514 qsort(translations, sz, sizeof (*translations), om_cmp); 515 516 for (i = 0; i < sz; i++) { 517 pa_base = translations[i].om_pa; 518 #ifndef __powerpc64__ 519 if ((translations[i].om_pa >> 32) != 0) 520 panic("OFW translations above 32-bit boundary!"); 521 #endif 522 523 if (pa_base % PAGE_SIZE) 524 panic("OFW translation not page-aligned (phys)!"); 525 if (translations[i].om_va % PAGE_SIZE) 526 panic("OFW translation not page-aligned (virt)!"); 527 528 CTR3(KTR_PMAP, "translation: pa=%#zx va=%#x len=%#x", 529 pa_base, translations[i].om_va, translations[i].om_len); 530 531 /* Now enter the pages for this mapping */ 532 533 DISABLE_TRANS(msr); 534 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 535 if (moea64_pvo_find_va(kernel_pmap, 536 translations[i].om_va + off) != NULL) 537 continue; 538 539 moea64_kenter(mmup, translations[i].om_va + off, 540 pa_base + off); 541 } 542 ENABLE_TRANS(msr); 543 } 544} 545 546#ifdef __powerpc64__ 547static void 548moea64_probe_large_page(void) 549{ 550 uint16_t pvr = mfpvr() >> 16; 551 552 switch (pvr) { 553 case IBM970: 554 case IBM970FX: 555 case IBM970MP: 556 powerpc_sync(); isync(); 557 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); 558 powerpc_sync(); isync(); 559 560 /* FALLTHROUGH */ 561 default: 562 moea64_large_page_size = 0x1000000; /* 16 MB */ 563 moea64_large_page_shift = 24; 564 } 565 566 moea64_large_page_mask = moea64_large_page_size - 1; 567} 568 569static void 570moea64_bootstrap_slb_prefault(vm_offset_t va, int large) 571{ 572 struct slb *cache; 573 struct slb entry; 574 uint64_t esid, slbe; 575 uint64_t i; 576 577 cache = PCPU_GET(slb); 578 esid = va >> ADDR_SR_SHFT; 579 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID; 580 581 for (i = 0; i < 64; i++) { 582 if (cache[i].slbe == (slbe | i)) 583 return; 584 } 585 586 entry.slbe = slbe; 587 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT; 588 if (large) 589 entry.slbv |= SLBV_L; 590 591 slb_insert_kernel(entry.slbe, entry.slbv); 592} 593#endif 594 595static void 596moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart, 597 vm_offset_t kernelend) 598{ 599 register_t msr; 600 vm_paddr_t pa; 601 vm_offset_t size, off; 602 uint64_t pte_lo; 603 int i; 604 605 if (moea64_large_page_size == 0) 606 hw_direct_map = 0; 607 608 DISABLE_TRANS(msr); 609 if (hw_direct_map) { 610 LOCK_TABLE_WR(); 611 PMAP_LOCK(kernel_pmap); 612 for (i = 0; i < pregions_sz; i++) { 613 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start + 614 pregions[i].mr_size; pa += moea64_large_page_size) { 615 pte_lo = LPTE_M; 616 617 /* 618 * Set memory access as guarded if prefetch within 619 * the page could exit the available physmem area. 620 */ 621 if (pa & moea64_large_page_mask) { 622 pa &= moea64_large_page_mask; 623 pte_lo |= LPTE_G; 624 } 625 if (pa + moea64_large_page_size > 626 pregions[i].mr_start + pregions[i].mr_size) 627 pte_lo |= LPTE_G; 628 629 moea64_pvo_enter(mmup, kernel_pmap, moea64_upvo_zone, 630 NULL, pa, pa, pte_lo, 631 PVO_WIRED | PVO_LARGE, 0); 632 } 633 } 634 PMAP_UNLOCK(kernel_pmap); 635 UNLOCK_TABLE_WR(); 636 } else { 637 size = sizeof(struct pvo_head) * moea64_pteg_count; 638 off = (vm_offset_t)(moea64_pvo_table); 639 for (pa = off; pa < off + size; pa += PAGE_SIZE) 640 moea64_kenter(mmup, pa, pa); 641 size = BPVO_POOL_SIZE*sizeof(struct pvo_entry); 642 off = (vm_offset_t)(moea64_bpvo_pool); 643 for (pa = off; pa < off + size; pa += PAGE_SIZE) 644 moea64_kenter(mmup, pa, pa); 645 646 /* 647 * Map certain important things, like ourselves. 648 * 649 * NOTE: We do not map the exception vector space. That code is 650 * used only in real mode, and leaving it unmapped allows us to 651 * catch NULL pointer deferences, instead of making NULL a valid 652 * address. 653 */ 654 655 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; 656 pa += PAGE_SIZE) 657 moea64_kenter(mmup, pa, pa); 658 } 659 ENABLE_TRANS(msr); 660 661 /* 662 * Allow user to override unmapped_buf_allowed for testing. 663 * XXXKIB Only direct map implementation was tested. 664 */ 665 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed", 666 &unmapped_buf_allowed)) 667 unmapped_buf_allowed = hw_direct_map; 668} 669 670void 671moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 672{ 673 int i, j; 674 vm_size_t physsz, hwphyssz; 675 676#ifndef __powerpc64__ 677 /* We don't have a direct map since there is no BAT */ 678 hw_direct_map = 0; 679 680 /* Make sure battable is zero, since we have no BAT */ 681 for (i = 0; i < 16; i++) { 682 battable[i].batu = 0; 683 battable[i].batl = 0; 684 } 685#else 686 moea64_probe_large_page(); 687 688 /* Use a direct map if we have large page support */ 689 if (moea64_large_page_size > 0) 690 hw_direct_map = 1; 691 else 692 hw_direct_map = 0; 693#endif 694 695 /* Get physical memory regions from firmware */ 696 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 697 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 698 699 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 700 panic("moea64_bootstrap: phys_avail too small"); 701 702 phys_avail_count = 0; 703 physsz = 0; 704 hwphyssz = 0; 705 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 706 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 707 CTR3(KTR_PMAP, "region: %#zx - %#zx (%#zx)", 708 regions[i].mr_start, regions[i].mr_start + 709 regions[i].mr_size, regions[i].mr_size); 710 if (hwphyssz != 0 && 711 (physsz + regions[i].mr_size) >= hwphyssz) { 712 if (physsz < hwphyssz) { 713 phys_avail[j] = regions[i].mr_start; 714 phys_avail[j + 1] = regions[i].mr_start + 715 hwphyssz - physsz; 716 physsz = hwphyssz; 717 phys_avail_count++; 718 } 719 break; 720 } 721 phys_avail[j] = regions[i].mr_start; 722 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 723 phys_avail_count++; 724 physsz += regions[i].mr_size; 725 } 726 727 /* Check for overlap with the kernel and exception vectors */ 728 for (j = 0; j < 2*phys_avail_count; j+=2) { 729 if (phys_avail[j] < EXC_LAST) 730 phys_avail[j] += EXC_LAST; 731 732 if (kernelstart >= phys_avail[j] && 733 kernelstart < phys_avail[j+1]) { 734 if (kernelend < phys_avail[j+1]) { 735 phys_avail[2*phys_avail_count] = 736 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 737 phys_avail[2*phys_avail_count + 1] = 738 phys_avail[j+1]; 739 phys_avail_count++; 740 } 741 742 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 743 } 744 745 if (kernelend >= phys_avail[j] && 746 kernelend < phys_avail[j+1]) { 747 if (kernelstart > phys_avail[j]) { 748 phys_avail[2*phys_avail_count] = phys_avail[j]; 749 phys_avail[2*phys_avail_count + 1] = 750 kernelstart & ~PAGE_MASK; 751 phys_avail_count++; 752 } 753 754 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 755 } 756 } 757 758 physmem = btoc(physsz); 759 760#ifdef PTEGCOUNT 761 moea64_pteg_count = PTEGCOUNT; 762#else 763 moea64_pteg_count = 0x1000; 764 765 while (moea64_pteg_count < physmem) 766 moea64_pteg_count <<= 1; 767 768 moea64_pteg_count >>= 1; 769#endif /* PTEGCOUNT */ 770} 771 772void 773moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 774{ 775 vm_size_t size; 776 register_t msr; 777 int i; 778 779 /* 780 * Set PTEG mask 781 */ 782 moea64_pteg_mask = moea64_pteg_count - 1; 783 784 /* 785 * Allocate pv/overflow lists. 786 */ 787 size = sizeof(struct pvo_head) * moea64_pteg_count; 788 789 moea64_pvo_table = (struct pvo_head *)moea64_bootstrap_alloc(size, 790 PAGE_SIZE); 791 CTR1(KTR_PMAP, "moea64_bootstrap: PVO table at %p", moea64_pvo_table); 792 793 DISABLE_TRANS(msr); 794 for (i = 0; i < moea64_pteg_count; i++) 795 LIST_INIT(&moea64_pvo_table[i]); 796 ENABLE_TRANS(msr); 797 798 /* 799 * Initialize the lock that synchronizes access to the pteg and pvo 800 * tables. 801 */ 802 rw_init_flags(&moea64_table_lock, "pmap tables", RW_RECURSE); 803 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF); 804 805 /* 806 * Initialise the unmanaged pvo pool. 807 */ 808 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 809 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 810 moea64_bpvo_pool_index = 0; 811 812 /* 813 * Make sure kernel vsid is allocated as well as VSID 0. 814 */ 815 #ifndef __powerpc64__ 816 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW] 817 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 818 moea64_vsid_bitmap[0] |= 1; 819 #endif 820 821 /* 822 * Initialize the kernel pmap (which is statically allocated). 823 */ 824 #ifdef __powerpc64__ 825 for (i = 0; i < 64; i++) { 826 pcpup->pc_slb[i].slbv = 0; 827 pcpup->pc_slb[i].slbe = 0; 828 } 829 #else 830 for (i = 0; i < 16; i++) 831 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 832 #endif 833 834 kernel_pmap->pmap_phys = kernel_pmap; 835 CPU_FILL(&kernel_pmap->pm_active); 836 RB_INIT(&kernel_pmap->pmap_pvo); 837 838 PMAP_LOCK_INIT(kernel_pmap); 839 840 /* 841 * Now map in all the other buffers we allocated earlier 842 */ 843 844 moea64_setup_direct_map(mmup, kernelstart, kernelend); 845} 846 847void 848moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 849{ 850 ihandle_t mmui; 851 phandle_t chosen; 852 phandle_t mmu; 853 size_t sz; 854 int i; 855 vm_offset_t pa, va; 856 void *dpcpu; 857 858 /* 859 * Set up the Open Firmware pmap and add its mappings if not in real 860 * mode. 861 */ 862 863 chosen = OF_finddevice("/chosen"); 864 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1) { 865 mmu = OF_instance_to_package(mmui); 866 if (mmu == -1 || (sz = OF_getproplen(mmu, "translations")) == -1) 867 sz = 0; 868 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 869 panic("moea64_bootstrap: too many ofw translations"); 870 871 if (sz > 0) 872 moea64_add_ofw_mappings(mmup, mmu, sz); 873 } 874 875 /* 876 * Calculate the last available physical address. 877 */ 878 for (i = 0; phys_avail[i + 2] != 0; i += 2) 879 ; 880 Maxmem = powerpc_btop(phys_avail[i + 1]); 881 882 /* 883 * Initialize MMU and remap early physical mappings 884 */ 885 MMU_CPU_BOOTSTRAP(mmup,0); 886 mtmsr(mfmsr() | PSL_DR | PSL_IR); 887 pmap_bootstrapped++; 888 bs_remap_earlyboot(); 889 890 /* 891 * Set the start and end of kva. 892 */ 893 virtual_avail = VM_MIN_KERNEL_ADDRESS; 894 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 895 896 /* 897 * Map the entire KVA range into the SLB. We must not fault there. 898 */ 899 #ifdef __powerpc64__ 900 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH) 901 moea64_bootstrap_slb_prefault(va, 0); 902 #endif 903 904 /* 905 * Figure out how far we can extend virtual_end into segment 16 906 * without running into existing mappings. Segment 16 is guaranteed 907 * to contain neither RAM nor devices (at least on Apple hardware), 908 * but will generally contain some OFW mappings we should not 909 * step on. 910 */ 911 912 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */ 913 PMAP_LOCK(kernel_pmap); 914 while (virtual_end < VM_MAX_KERNEL_ADDRESS && 915 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL) 916 virtual_end += PAGE_SIZE; 917 PMAP_UNLOCK(kernel_pmap); 918 #endif 919 920 /* 921 * Allocate a kernel stack with a guard page for thread0 and map it 922 * into the kernel page map. 923 */ 924 pa = moea64_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 925 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 926 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 927 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va); 928 thread0.td_kstack = va; 929 thread0.td_kstack_pages = KSTACK_PAGES; 930 for (i = 0; i < KSTACK_PAGES; i++) { 931 moea64_kenter(mmup, va, pa); 932 pa += PAGE_SIZE; 933 va += PAGE_SIZE; 934 } 935 936 /* 937 * Allocate virtual address space for the message buffer. 938 */ 939 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE); 940 msgbufp = (struct msgbuf *)virtual_avail; 941 va = virtual_avail; 942 virtual_avail += round_page(msgbufsize); 943 while (va < virtual_avail) { 944 moea64_kenter(mmup, va, pa); 945 pa += PAGE_SIZE; 946 va += PAGE_SIZE; 947 } 948 949 /* 950 * Allocate virtual address space for the dynamic percpu area. 951 */ 952 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 953 dpcpu = (void *)virtual_avail; 954 va = virtual_avail; 955 virtual_avail += DPCPU_SIZE; 956 while (va < virtual_avail) { 957 moea64_kenter(mmup, va, pa); 958 pa += PAGE_SIZE; 959 va += PAGE_SIZE; 960 } 961 dpcpu_init(dpcpu, 0); 962 963 /* 964 * Allocate some things for page zeroing. We put this directly 965 * in the page table, marked with LPTE_LOCKED, to avoid any 966 * of the PVO book-keeping or other parts of the VM system 967 * from even knowing that this hack exists. 968 */ 969 970 if (!hw_direct_map) { 971 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, 972 MTX_DEF); 973 for (i = 0; i < 2; i++) { 974 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 975 virtual_end -= PAGE_SIZE; 976 977 moea64_kenter(mmup, moea64_scratchpage_va[i], 0); 978 979 moea64_scratchpage_pvo[i] = moea64_pvo_find_va( 980 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]); 981 LOCK_TABLE_RD(); 982 moea64_scratchpage_pte[i] = MOEA64_PVO_TO_PTE( 983 mmup, moea64_scratchpage_pvo[i]); 984 moea64_scratchpage_pvo[i]->pvo_pte.lpte.pte_hi 985 |= LPTE_LOCKED; 986 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[i], 987 &moea64_scratchpage_pvo[i]->pvo_pte.lpte, 988 moea64_scratchpage_pvo[i]->pvo_vpn); 989 UNLOCK_TABLE_RD(); 990 } 991 } 992} 993 994/* 995 * Activate a user pmap. The pmap must be activated before its address 996 * space can be accessed in any way. 997 */ 998void 999moea64_activate(mmu_t mmu, struct thread *td) 1000{ 1001 pmap_t pm; 1002 1003 pm = &td->td_proc->p_vmspace->vm_pmap; 1004 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1005 1006 #ifdef __powerpc64__ 1007 PCPU_SET(userslb, pm->pm_slb); 1008 #else 1009 PCPU_SET(curpmap, pm->pmap_phys); 1010 #endif 1011} 1012 1013void 1014moea64_deactivate(mmu_t mmu, struct thread *td) 1015{ 1016 pmap_t pm; 1017 1018 pm = &td->td_proc->p_vmspace->vm_pmap; 1019 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1020 #ifdef __powerpc64__ 1021 PCPU_SET(userslb, NULL); 1022 #else 1023 PCPU_SET(curpmap, NULL); 1024 #endif 1025} 1026 1027void 1028moea64_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1029{ 1030 struct pvo_entry key, *pvo; 1031 uintptr_t pt; 1032 1033 LOCK_TABLE_RD(); 1034 PMAP_LOCK(pm); 1035 key.pvo_vaddr = sva; 1036 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1037 pvo != NULL && PVO_VADDR(pvo) < eva; 1038 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1039 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1040 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1041 panic("moea64_unwire: pvo %p is missing PVO_WIRED", 1042 pvo); 1043 pvo->pvo_vaddr &= ~PVO_WIRED; 1044 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_WIRED) == 0) 1045 panic("moea64_unwire: pte %p is missing LPTE_WIRED", 1046 &pvo->pvo_pte.lpte); 1047 pvo->pvo_pte.lpte.pte_hi &= ~LPTE_WIRED; 1048 if (pt != -1) { 1049 /* 1050 * The PTE's wired attribute is not a hardware 1051 * feature, so there is no need to invalidate any TLB 1052 * entries. 1053 */ 1054 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1055 pvo->pvo_vpn); 1056 } 1057 pm->pm_stats.wired_count--; 1058 } 1059 UNLOCK_TABLE_RD(); 1060 PMAP_UNLOCK(pm); 1061} 1062 1063/* 1064 * This goes through and sets the physical address of our 1065 * special scratch PTE to the PA we want to zero or copy. Because 1066 * of locking issues (this can get called in pvo_enter() by 1067 * the UMA allocator), we can't use most other utility functions here 1068 */ 1069 1070static __inline 1071void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_offset_t pa) { 1072 1073 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!")); 1074 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1075 1076 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo &= 1077 ~(LPTE_WIMG | LPTE_RPGN); 1078 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo |= 1079 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa; 1080 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[which], 1081 &moea64_scratchpage_pvo[which]->pvo_pte.lpte, 1082 moea64_scratchpage_pvo[which]->pvo_vpn); 1083 isync(); 1084} 1085 1086void 1087moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1088{ 1089 vm_offset_t dst; 1090 vm_offset_t src; 1091 1092 dst = VM_PAGE_TO_PHYS(mdst); 1093 src = VM_PAGE_TO_PHYS(msrc); 1094 1095 if (hw_direct_map) { 1096 bcopy((void *)src, (void *)dst, PAGE_SIZE); 1097 } else { 1098 mtx_lock(&moea64_scratchpage_mtx); 1099 1100 moea64_set_scratchpage_pa(mmu, 0, src); 1101 moea64_set_scratchpage_pa(mmu, 1, dst); 1102 1103 bcopy((void *)moea64_scratchpage_va[0], 1104 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1105 1106 mtx_unlock(&moea64_scratchpage_mtx); 1107 } 1108} 1109 1110static inline void 1111moea64_copy_pages_dmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1112 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1113{ 1114 void *a_cp, *b_cp; 1115 vm_offset_t a_pg_offset, b_pg_offset; 1116 int cnt; 1117 1118 while (xfersize > 0) { 1119 a_pg_offset = a_offset & PAGE_MASK; 1120 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1121 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) + 1122 a_pg_offset; 1123 b_pg_offset = b_offset & PAGE_MASK; 1124 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1125 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) + 1126 b_pg_offset; 1127 bcopy(a_cp, b_cp, cnt); 1128 a_offset += cnt; 1129 b_offset += cnt; 1130 xfersize -= cnt; 1131 } 1132} 1133 1134static inline void 1135moea64_copy_pages_nodmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1136 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1137{ 1138 void *a_cp, *b_cp; 1139 vm_offset_t a_pg_offset, b_pg_offset; 1140 int cnt; 1141 1142 mtx_lock(&moea64_scratchpage_mtx); 1143 while (xfersize > 0) { 1144 a_pg_offset = a_offset & PAGE_MASK; 1145 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1146 moea64_set_scratchpage_pa(mmu, 0, 1147 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 1148 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset; 1149 b_pg_offset = b_offset & PAGE_MASK; 1150 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1151 moea64_set_scratchpage_pa(mmu, 1, 1152 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 1153 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset; 1154 bcopy(a_cp, b_cp, cnt); 1155 a_offset += cnt; 1156 b_offset += cnt; 1157 xfersize -= cnt; 1158 } 1159 mtx_unlock(&moea64_scratchpage_mtx); 1160} 1161 1162void 1163moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1164 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1165{ 1166 1167 if (hw_direct_map) { 1168 moea64_copy_pages_dmap(mmu, ma, a_offset, mb, b_offset, 1169 xfersize); 1170 } else { 1171 moea64_copy_pages_nodmap(mmu, ma, a_offset, mb, b_offset, 1172 xfersize); 1173 } 1174} 1175 1176void 1177moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1178{ 1179 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1180 1181 if (size + off > PAGE_SIZE) 1182 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1183 1184 if (hw_direct_map) { 1185 bzero((caddr_t)pa + off, size); 1186 } else { 1187 mtx_lock(&moea64_scratchpage_mtx); 1188 moea64_set_scratchpage_pa(mmu, 0, pa); 1189 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1190 mtx_unlock(&moea64_scratchpage_mtx); 1191 } 1192} 1193 1194/* 1195 * Zero a page of physical memory by temporarily mapping it 1196 */ 1197void 1198moea64_zero_page(mmu_t mmu, vm_page_t m) 1199{ 1200 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1201 vm_offset_t va, off; 1202 1203 if (!hw_direct_map) { 1204 mtx_lock(&moea64_scratchpage_mtx); 1205 1206 moea64_set_scratchpage_pa(mmu, 0, pa); 1207 va = moea64_scratchpage_va[0]; 1208 } else { 1209 va = pa; 1210 } 1211 1212 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1213 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 1214 1215 if (!hw_direct_map) 1216 mtx_unlock(&moea64_scratchpage_mtx); 1217} 1218 1219void 1220moea64_zero_page_idle(mmu_t mmu, vm_page_t m) 1221{ 1222 1223 moea64_zero_page(mmu, m); 1224} 1225 1226/* 1227 * Map the given physical page at the specified virtual address in the 1228 * target pmap with the protection requested. If specified the page 1229 * will be wired down. 1230 */ 1231 1232int 1233moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1234 vm_prot_t prot, u_int flags, int8_t psind) 1235{ 1236 struct pvo_head *pvo_head; 1237 uma_zone_t zone; 1238 vm_page_t pg; 1239 uint64_t pte_lo; 1240 u_int pvo_flags; 1241 int error; 1242 1243 if (!moea64_initialized) { 1244 pvo_head = NULL; 1245 pg = NULL; 1246 zone = moea64_upvo_zone; 1247 pvo_flags = 0; 1248 } else { 1249 pvo_head = vm_page_to_pvoh(m); 1250 pg = m; 1251 zone = moea64_mpvo_zone; 1252 pvo_flags = PVO_MANAGED; 1253 } 1254 1255 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1256 VM_OBJECT_ASSERT_LOCKED(m->object); 1257 1258 /* XXX change the pvo head for fake pages */ 1259 if ((m->oflags & VPO_UNMANAGED) != 0) { 1260 pvo_flags &= ~PVO_MANAGED; 1261 pvo_head = NULL; 1262 zone = moea64_upvo_zone; 1263 } 1264 1265 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1266 1267 if (prot & VM_PROT_WRITE) { 1268 pte_lo |= LPTE_BW; 1269 if (pmap_bootstrapped && 1270 (m->oflags & VPO_UNMANAGED) == 0) 1271 vm_page_aflag_set(m, PGA_WRITEABLE); 1272 } else 1273 pte_lo |= LPTE_BR; 1274 1275 if ((prot & VM_PROT_EXECUTE) == 0) 1276 pte_lo |= LPTE_NOEXEC; 1277 1278 if ((flags & PMAP_ENTER_WIRED) != 0) 1279 pvo_flags |= PVO_WIRED; 1280 1281 for (;;) { 1282 LOCK_TABLE_WR(); 1283 PMAP_LOCK(pmap); 1284 error = moea64_pvo_enter(mmu, pmap, zone, pvo_head, va, 1285 VM_PAGE_TO_PHYS(m), pte_lo, pvo_flags, psind); 1286 PMAP_UNLOCK(pmap); 1287 UNLOCK_TABLE_WR(); 1288 if (error != ENOMEM) 1289 break; 1290 if ((flags & PMAP_ENTER_NOSLEEP) != 0) 1291 return (KERN_RESOURCE_SHORTAGE); 1292 VM_OBJECT_ASSERT_UNLOCKED(m->object); 1293 VM_WAIT; 1294 } 1295 1296 /* 1297 * Flush the page from the instruction cache if this page is 1298 * mapped executable and cacheable. 1299 */ 1300 if (pmap != kernel_pmap && !(m->aflags & PGA_EXECUTABLE) && 1301 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1302 vm_page_aflag_set(m, PGA_EXECUTABLE); 1303 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1304 } 1305 return (KERN_SUCCESS); 1306} 1307 1308static void 1309moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t pa, 1310 vm_size_t sz) 1311{ 1312 1313 /* 1314 * This is much trickier than on older systems because 1315 * we can't sync the icache on physical addresses directly 1316 * without a direct map. Instead we check a couple of cases 1317 * where the memory is already mapped in and, failing that, 1318 * use the same trick we use for page zeroing to create 1319 * a temporary mapping for this physical address. 1320 */ 1321 1322 if (!pmap_bootstrapped) { 1323 /* 1324 * If PMAP is not bootstrapped, we are likely to be 1325 * in real mode. 1326 */ 1327 __syncicache((void *)pa, sz); 1328 } else if (pmap == kernel_pmap) { 1329 __syncicache((void *)va, sz); 1330 } else if (hw_direct_map) { 1331 __syncicache((void *)pa, sz); 1332 } else { 1333 /* Use the scratch page to set up a temp mapping */ 1334 1335 mtx_lock(&moea64_scratchpage_mtx); 1336 1337 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF); 1338 __syncicache((void *)(moea64_scratchpage_va[1] + 1339 (va & ADDR_POFF)), sz); 1340 1341 mtx_unlock(&moea64_scratchpage_mtx); 1342 } 1343} 1344 1345/* 1346 * Maps a sequence of resident pages belonging to the same object. 1347 * The sequence begins with the given page m_start. This page is 1348 * mapped at the given virtual address start. Each subsequent page is 1349 * mapped at a virtual address that is offset from start by the same 1350 * amount as the page is offset from m_start within the object. The 1351 * last page in the sequence is the page with the largest offset from 1352 * m_start that can be mapped at a virtual address less than the given 1353 * virtual address end. Not every virtual page between start and end 1354 * is mapped; only those for which a resident page exists with the 1355 * corresponding offset from m_start are mapped. 1356 */ 1357void 1358moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1359 vm_page_t m_start, vm_prot_t prot) 1360{ 1361 vm_page_t m; 1362 vm_pindex_t diff, psize; 1363 1364 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1365 1366 psize = atop(end - start); 1367 m = m_start; 1368 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1369 moea64_enter(mmu, pm, start + ptoa(diff), m, prot & 1370 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP, 0); 1371 m = TAILQ_NEXT(m, listq); 1372 } 1373} 1374 1375void 1376moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1377 vm_prot_t prot) 1378{ 1379 1380 moea64_enter(mmu, pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1381 PMAP_ENTER_NOSLEEP, 0); 1382} 1383 1384vm_paddr_t 1385moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1386{ 1387 struct pvo_entry *pvo; 1388 vm_paddr_t pa; 1389 1390 PMAP_LOCK(pm); 1391 pvo = moea64_pvo_find_va(pm, va); 1392 if (pvo == NULL) 1393 pa = 0; 1394 else 1395 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | 1396 (va - PVO_VADDR(pvo)); 1397 PMAP_UNLOCK(pm); 1398 return (pa); 1399} 1400 1401/* 1402 * Atomically extract and hold the physical page with the given 1403 * pmap and virtual address pair if that mapping permits the given 1404 * protection. 1405 */ 1406vm_page_t 1407moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1408{ 1409 struct pvo_entry *pvo; 1410 vm_page_t m; 1411 vm_paddr_t pa; 1412 1413 m = NULL; 1414 pa = 0; 1415 PMAP_LOCK(pmap); 1416retry: 1417 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1418 if (pvo != NULL && (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) && 1419 ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == LPTE_RW || 1420 (prot & VM_PROT_WRITE) == 0)) { 1421 if (vm_page_pa_tryrelock(pmap, 1422 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, &pa)) 1423 goto retry; 1424 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 1425 vm_page_hold(m); 1426 } 1427 PA_UNLOCK_COND(pa); 1428 PMAP_UNLOCK(pmap); 1429 return (m); 1430} 1431 1432static mmu_t installed_mmu; 1433 1434static void * 1435moea64_uma_page_alloc(uma_zone_t zone, vm_size_t bytes, uint8_t *flags, 1436 int wait) 1437{ 1438 /* 1439 * This entire routine is a horrible hack to avoid bothering kmem 1440 * for new KVA addresses. Because this can get called from inside 1441 * kmem allocation routines, calling kmem for a new address here 1442 * can lead to multiply locking non-recursive mutexes. 1443 */ 1444 vm_offset_t va; 1445 1446 vm_page_t m; 1447 int pflags, needed_lock; 1448 1449 *flags = UMA_SLAB_PRIV; 1450 needed_lock = !PMAP_LOCKED(kernel_pmap); 1451 pflags = malloc2vm_flags(wait) | VM_ALLOC_WIRED; 1452 1453 for (;;) { 1454 m = vm_page_alloc(NULL, 0, pflags | VM_ALLOC_NOOBJ); 1455 if (m == NULL) { 1456 if (wait & M_NOWAIT) 1457 return (NULL); 1458 VM_WAIT; 1459 } else 1460 break; 1461 } 1462 1463 va = VM_PAGE_TO_PHYS(m); 1464 1465 LOCK_TABLE_WR(); 1466 if (needed_lock) 1467 PMAP_LOCK(kernel_pmap); 1468 1469 moea64_pvo_enter(installed_mmu, kernel_pmap, moea64_upvo_zone, 1470 NULL, va, VM_PAGE_TO_PHYS(m), LPTE_M, PVO_WIRED | PVO_BOOTSTRAP, 1471 0); 1472 1473 if (needed_lock) 1474 PMAP_UNLOCK(kernel_pmap); 1475 UNLOCK_TABLE_WR(); 1476 1477 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1478 bzero((void *)va, PAGE_SIZE); 1479 1480 return (void *)va; 1481} 1482 1483extern int elf32_nxstack; 1484 1485void 1486moea64_init(mmu_t mmu) 1487{ 1488 1489 CTR0(KTR_PMAP, "moea64_init"); 1490 1491 moea64_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1492 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1493 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1494 moea64_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1495 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1496 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1497 1498 if (!hw_direct_map) { 1499 installed_mmu = mmu; 1500 uma_zone_set_allocf(moea64_upvo_zone,moea64_uma_page_alloc); 1501 uma_zone_set_allocf(moea64_mpvo_zone,moea64_uma_page_alloc); 1502 } 1503 1504#ifdef COMPAT_FREEBSD32 1505 elf32_nxstack = 1; 1506#endif 1507 1508 moea64_initialized = TRUE; 1509} 1510 1511boolean_t 1512moea64_is_referenced(mmu_t mmu, vm_page_t m) 1513{ 1514 1515 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1516 ("moea64_is_referenced: page %p is not managed", m)); 1517 return (moea64_query_bit(mmu, m, PTE_REF)); 1518} 1519 1520boolean_t 1521moea64_is_modified(mmu_t mmu, vm_page_t m) 1522{ 1523 1524 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1525 ("moea64_is_modified: page %p is not managed", m)); 1526 1527 /* 1528 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1529 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1530 * is clear, no PTEs can have LPTE_CHG set. 1531 */ 1532 VM_OBJECT_ASSERT_LOCKED(m->object); 1533 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1534 return (FALSE); 1535 return (moea64_query_bit(mmu, m, LPTE_CHG)); 1536} 1537 1538boolean_t 1539moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1540{ 1541 struct pvo_entry *pvo; 1542 boolean_t rv; 1543 1544 PMAP_LOCK(pmap); 1545 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1546 rv = pvo == NULL || (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0; 1547 PMAP_UNLOCK(pmap); 1548 return (rv); 1549} 1550 1551void 1552moea64_clear_modify(mmu_t mmu, vm_page_t m) 1553{ 1554 1555 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1556 ("moea64_clear_modify: page %p is not managed", m)); 1557 VM_OBJECT_ASSERT_WLOCKED(m->object); 1558 KASSERT(!vm_page_xbusied(m), 1559 ("moea64_clear_modify: page %p is exclusive busied", m)); 1560 1561 /* 1562 * If the page is not PGA_WRITEABLE, then no PTEs can have LPTE_CHG 1563 * set. If the object containing the page is locked and the page is 1564 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 1565 */ 1566 if ((m->aflags & PGA_WRITEABLE) == 0) 1567 return; 1568 moea64_clear_bit(mmu, m, LPTE_CHG); 1569} 1570 1571/* 1572 * Clear the write and modified bits in each of the given page's mappings. 1573 */ 1574void 1575moea64_remove_write(mmu_t mmu, vm_page_t m) 1576{ 1577 struct pvo_entry *pvo; 1578 uintptr_t pt; 1579 pmap_t pmap; 1580 uint64_t lo = 0; 1581 1582 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1583 ("moea64_remove_write: page %p is not managed", m)); 1584 1585 /* 1586 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1587 * set by another thread while the object is locked. Thus, 1588 * if PGA_WRITEABLE is clear, no page table entries need updating. 1589 */ 1590 VM_OBJECT_ASSERT_WLOCKED(m->object); 1591 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1592 return; 1593 powerpc_sync(); 1594 LOCK_TABLE_RD(); 1595 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1596 pmap = pvo->pvo_pmap; 1597 PMAP_LOCK(pmap); 1598 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) { 1599 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1600 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1601 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1602 if (pt != -1) { 1603 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 1604 lo |= pvo->pvo_pte.lpte.pte_lo; 1605 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_CHG; 1606 MOEA64_PTE_CHANGE(mmu, pt, 1607 &pvo->pvo_pte.lpte, pvo->pvo_vpn); 1608 if (pvo->pvo_pmap == kernel_pmap) 1609 isync(); 1610 } 1611 } 1612 if ((lo & LPTE_CHG) != 0) 1613 vm_page_dirty(m); 1614 PMAP_UNLOCK(pmap); 1615 } 1616 UNLOCK_TABLE_RD(); 1617 vm_page_aflag_clear(m, PGA_WRITEABLE); 1618} 1619 1620/* 1621 * moea64_ts_referenced: 1622 * 1623 * Return a count of reference bits for a page, clearing those bits. 1624 * It is not necessary for every reference bit to be cleared, but it 1625 * is necessary that 0 only be returned when there are truly no 1626 * reference bits set. 1627 * 1628 * XXX: The exact number of bits to check and clear is a matter that 1629 * should be tested and standardized at some point in the future for 1630 * optimal aging of shared pages. 1631 */ 1632int 1633moea64_ts_referenced(mmu_t mmu, vm_page_t m) 1634{ 1635 1636 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1637 ("moea64_ts_referenced: page %p is not managed", m)); 1638 return (moea64_clear_bit(mmu, m, LPTE_REF)); 1639} 1640 1641/* 1642 * Modify the WIMG settings of all mappings for a page. 1643 */ 1644void 1645moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1646{ 1647 struct pvo_entry *pvo; 1648 struct pvo_head *pvo_head; 1649 uintptr_t pt; 1650 pmap_t pmap; 1651 uint64_t lo; 1652 1653 if ((m->oflags & VPO_UNMANAGED) != 0) { 1654 m->md.mdpg_cache_attrs = ma; 1655 return; 1656 } 1657 1658 pvo_head = vm_page_to_pvoh(m); 1659 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1660 LOCK_TABLE_RD(); 1661 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1662 pmap = pvo->pvo_pmap; 1663 PMAP_LOCK(pmap); 1664 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1665 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_WIMG; 1666 pvo->pvo_pte.lpte.pte_lo |= lo; 1667 if (pt != -1) { 1668 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1669 pvo->pvo_vpn); 1670 if (pvo->pvo_pmap == kernel_pmap) 1671 isync(); 1672 } 1673 PMAP_UNLOCK(pmap); 1674 } 1675 UNLOCK_TABLE_RD(); 1676 m->md.mdpg_cache_attrs = ma; 1677} 1678 1679/* 1680 * Map a wired page into kernel virtual address space. 1681 */ 1682void 1683moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma) 1684{ 1685 uint64_t pte_lo; 1686 int error; 1687 1688 pte_lo = moea64_calc_wimg(pa, ma); 1689 1690 LOCK_TABLE_WR(); 1691 PMAP_LOCK(kernel_pmap); 1692 error = moea64_pvo_enter(mmu, kernel_pmap, moea64_upvo_zone, 1693 NULL, va, pa, pte_lo, PVO_WIRED, 0); 1694 PMAP_UNLOCK(kernel_pmap); 1695 UNLOCK_TABLE_WR(); 1696 1697 if (error != 0 && error != ENOENT) 1698 panic("moea64_kenter: failed to enter va %#zx pa %#zx: %d", va, 1699 pa, error); 1700} 1701 1702void 1703moea64_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1704{ 1705 1706 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1707} 1708 1709/* 1710 * Extract the physical page address associated with the given kernel virtual 1711 * address. 1712 */ 1713vm_paddr_t 1714moea64_kextract(mmu_t mmu, vm_offset_t va) 1715{ 1716 struct pvo_entry *pvo; 1717 vm_paddr_t pa; 1718 1719 /* 1720 * Shortcut the direct-mapped case when applicable. We never put 1721 * anything but 1:1 mappings below VM_MIN_KERNEL_ADDRESS. 1722 */ 1723 if (va < VM_MIN_KERNEL_ADDRESS) 1724 return (va); 1725 1726 PMAP_LOCK(kernel_pmap); 1727 pvo = moea64_pvo_find_va(kernel_pmap, va); 1728 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR, 1729 va)); 1730 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1731 PMAP_UNLOCK(kernel_pmap); 1732 return (pa); 1733} 1734 1735/* 1736 * Remove a wired page from kernel virtual address space. 1737 */ 1738void 1739moea64_kremove(mmu_t mmu, vm_offset_t va) 1740{ 1741 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1742} 1743 1744/* 1745 * Map a range of physical addresses into kernel virtual address space. 1746 * 1747 * The value passed in *virt is a suggested virtual address for the mapping. 1748 * Architectures which can support a direct-mapped physical to virtual region 1749 * can return the appropriate address within that region, leaving '*virt' 1750 * unchanged. We cannot and therefore do not; *virt is updated with the 1751 * first usable address after the mapped region. 1752 */ 1753vm_offset_t 1754moea64_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1755 vm_paddr_t pa_end, int prot) 1756{ 1757 vm_offset_t sva, va; 1758 1759 sva = *virt; 1760 va = sva; 1761 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1762 moea64_kenter(mmu, va, pa_start); 1763 *virt = va; 1764 1765 return (sva); 1766} 1767 1768/* 1769 * Returns true if the pmap's pv is one of the first 1770 * 16 pvs linked to from this page. This count may 1771 * be changed upwards or downwards in the future; it 1772 * is only necessary that true be returned for a small 1773 * subset of pmaps for proper page aging. 1774 */ 1775boolean_t 1776moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1777{ 1778 int loops; 1779 struct pvo_entry *pvo; 1780 boolean_t rv; 1781 1782 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1783 ("moea64_page_exists_quick: page %p is not managed", m)); 1784 loops = 0; 1785 rv = FALSE; 1786 LOCK_TABLE_RD(); 1787 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1788 if (pvo->pvo_pmap == pmap) { 1789 rv = TRUE; 1790 break; 1791 } 1792 if (++loops >= 16) 1793 break; 1794 } 1795 UNLOCK_TABLE_RD(); 1796 return (rv); 1797} 1798 1799/* 1800 * Return the number of managed mappings to the given physical page 1801 * that are wired. 1802 */ 1803int 1804moea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 1805{ 1806 struct pvo_entry *pvo; 1807 int count; 1808 1809 count = 0; 1810 if ((m->oflags & VPO_UNMANAGED) != 0) 1811 return (count); 1812 LOCK_TABLE_RD(); 1813 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1814 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1815 count++; 1816 UNLOCK_TABLE_RD(); 1817 return (count); 1818} 1819 1820static uintptr_t moea64_vsidcontext; 1821 1822uintptr_t 1823moea64_get_unique_vsid(void) { 1824 u_int entropy; 1825 register_t hash; 1826 uint32_t mask; 1827 int i; 1828 1829 entropy = 0; 1830 __asm __volatile("mftb %0" : "=r"(entropy)); 1831 1832 mtx_lock(&moea64_slb_mutex); 1833 for (i = 0; i < NVSIDS; i += VSID_NBPW) { 1834 u_int n; 1835 1836 /* 1837 * Create a new value by mutiplying by a prime and adding in 1838 * entropy from the timebase register. This is to make the 1839 * VSID more random so that the PT hash function collides 1840 * less often. (Note that the prime casues gcc to do shifts 1841 * instead of a multiply.) 1842 */ 1843 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 1844 hash = moea64_vsidcontext & (NVSIDS - 1); 1845 if (hash == 0) /* 0 is special, avoid it */ 1846 continue; 1847 n = hash >> 5; 1848 mask = 1 << (hash & (VSID_NBPW - 1)); 1849 hash = (moea64_vsidcontext & VSID_HASHMASK); 1850 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 1851 /* anything free in this bucket? */ 1852 if (moea64_vsid_bitmap[n] == 0xffffffff) { 1853 entropy = (moea64_vsidcontext >> 20); 1854 continue; 1855 } 1856 i = ffs(~moea64_vsid_bitmap[n]) - 1; 1857 mask = 1 << i; 1858 hash &= VSID_HASHMASK & ~(VSID_NBPW - 1); 1859 hash |= i; 1860 } 1861 KASSERT(!(moea64_vsid_bitmap[n] & mask), 1862 ("Allocating in-use VSID %#zx\n", hash)); 1863 moea64_vsid_bitmap[n] |= mask; 1864 mtx_unlock(&moea64_slb_mutex); 1865 return (hash); 1866 } 1867 1868 mtx_unlock(&moea64_slb_mutex); 1869 panic("%s: out of segments",__func__); 1870} 1871 1872#ifdef __powerpc64__ 1873void 1874moea64_pinit(mmu_t mmu, pmap_t pmap) 1875{ 1876 1877 RB_INIT(&pmap->pmap_pvo); 1878 1879 pmap->pm_slb_tree_root = slb_alloc_tree(); 1880 pmap->pm_slb = slb_alloc_user_cache(); 1881 pmap->pm_slb_len = 0; 1882} 1883#else 1884void 1885moea64_pinit(mmu_t mmu, pmap_t pmap) 1886{ 1887 int i; 1888 uint32_t hash; 1889 1890 RB_INIT(&pmap->pmap_pvo); 1891 1892 if (pmap_bootstrapped) 1893 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, 1894 (vm_offset_t)pmap); 1895 else 1896 pmap->pmap_phys = pmap; 1897 1898 /* 1899 * Allocate some segment registers for this pmap. 1900 */ 1901 hash = moea64_get_unique_vsid(); 1902 1903 for (i = 0; i < 16; i++) 1904 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1905 1906 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0")); 1907} 1908#endif 1909 1910/* 1911 * Initialize the pmap associated with process 0. 1912 */ 1913void 1914moea64_pinit0(mmu_t mmu, pmap_t pm) 1915{ 1916 1917 PMAP_LOCK_INIT(pm); 1918 moea64_pinit(mmu, pm); 1919 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1920} 1921 1922/* 1923 * Set the physical protection on the specified range of this map as requested. 1924 */ 1925static void 1926moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot) 1927{ 1928 uintptr_t pt; 1929 struct vm_page *pg; 1930 uint64_t oldlo; 1931 1932 PMAP_LOCK_ASSERT(pm, MA_OWNED); 1933 1934 /* 1935 * Grab the PTE pointer before we diddle with the cached PTE 1936 * copy. 1937 */ 1938 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1939 1940 /* 1941 * Change the protection of the page. 1942 */ 1943 oldlo = pvo->pvo_pte.lpte.pte_lo; 1944 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1945 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_NOEXEC; 1946 if ((prot & VM_PROT_EXECUTE) == 0) 1947 pvo->pvo_pte.lpte.pte_lo |= LPTE_NOEXEC; 1948 if (prot & VM_PROT_WRITE) 1949 pvo->pvo_pte.lpte.pte_lo |= LPTE_BW; 1950 else 1951 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1952 1953 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 1954 1955 /* 1956 * If the PVO is in the page table, update that pte as well. 1957 */ 1958 if (pt != -1) 1959 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1960 pvo->pvo_vpn); 1961 if (pm != kernel_pmap && pg != NULL && !(pg->aflags & PGA_EXECUTABLE) && 1962 (pvo->pvo_pte.lpte.pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1963 if ((pg->oflags & VPO_UNMANAGED) == 0) 1964 vm_page_aflag_set(pg, PGA_EXECUTABLE); 1965 moea64_syncicache(mmu, pm, PVO_VADDR(pvo), 1966 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, PAGE_SIZE); 1967 } 1968 1969 /* 1970 * Update vm about the REF/CHG bits if the page is managed and we have 1971 * removed write access. 1972 */ 1973 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED && 1974 (oldlo & LPTE_PP) != LPTE_BR && !(prot & VM_PROT_WRITE)) { 1975 if (pg != NULL) { 1976 if (pvo->pvo_pte.lpte.pte_lo & LPTE_CHG) 1977 vm_page_dirty(pg); 1978 if (pvo->pvo_pte.lpte.pte_lo & LPTE_REF) 1979 vm_page_aflag_set(pg, PGA_REFERENCED); 1980 } 1981 } 1982} 1983 1984void 1985moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1986 vm_prot_t prot) 1987{ 1988 struct pvo_entry *pvo, *tpvo, key; 1989 1990 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, 1991 sva, eva, prot); 1992 1993 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1994 ("moea64_protect: non current pmap")); 1995 1996 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1997 moea64_remove(mmu, pm, sva, eva); 1998 return; 1999 } 2000 2001 LOCK_TABLE_RD(); 2002 PMAP_LOCK(pm); 2003 key.pvo_vaddr = sva; 2004 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2005 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2006 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2007 moea64_pvo_protect(mmu, pm, pvo, prot); 2008 } 2009 UNLOCK_TABLE_RD(); 2010 PMAP_UNLOCK(pm); 2011} 2012 2013/* 2014 * Map a list of wired pages into kernel virtual address space. This is 2015 * intended for temporary mappings which do not need page modification or 2016 * references recorded. Existing mappings in the region are overwritten. 2017 */ 2018void 2019moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 2020{ 2021 while (count-- > 0) { 2022 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 2023 va += PAGE_SIZE; 2024 m++; 2025 } 2026} 2027 2028/* 2029 * Remove page mappings from kernel virtual address space. Intended for 2030 * temporary mappings entered by moea64_qenter. 2031 */ 2032void 2033moea64_qremove(mmu_t mmu, vm_offset_t va, int count) 2034{ 2035 while (count-- > 0) { 2036 moea64_kremove(mmu, va); 2037 va += PAGE_SIZE; 2038 } 2039} 2040 2041void 2042moea64_release_vsid(uint64_t vsid) 2043{ 2044 int idx, mask; 2045 2046 mtx_lock(&moea64_slb_mutex); 2047 idx = vsid & (NVSIDS-1); 2048 mask = 1 << (idx % VSID_NBPW); 2049 idx /= VSID_NBPW; 2050 KASSERT(moea64_vsid_bitmap[idx] & mask, 2051 ("Freeing unallocated VSID %#jx", vsid)); 2052 moea64_vsid_bitmap[idx] &= ~mask; 2053 mtx_unlock(&moea64_slb_mutex); 2054} 2055 2056 2057void 2058moea64_release(mmu_t mmu, pmap_t pmap) 2059{ 2060 2061 /* 2062 * Free segment registers' VSIDs 2063 */ 2064 #ifdef __powerpc64__ 2065 slb_free_tree(pmap); 2066 slb_free_user_cache(pmap->pm_slb); 2067 #else 2068 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0")); 2069 2070 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0])); 2071 #endif 2072} 2073 2074/* 2075 * Remove all pages mapped by the specified pmap 2076 */ 2077void 2078moea64_remove_pages(mmu_t mmu, pmap_t pm) 2079{ 2080 struct pvo_entry *pvo, *tpvo; 2081 2082 LOCK_TABLE_WR(); 2083 PMAP_LOCK(pm); 2084 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) { 2085 if (!(pvo->pvo_vaddr & PVO_WIRED)) 2086 moea64_pvo_remove(mmu, pvo); 2087 } 2088 UNLOCK_TABLE_WR(); 2089 PMAP_UNLOCK(pm); 2090} 2091 2092/* 2093 * Remove the given range of addresses from the specified map. 2094 */ 2095void 2096moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 2097{ 2098 struct pvo_entry *pvo, *tpvo, key; 2099 2100 /* 2101 * Perform an unsynchronized read. This is, however, safe. 2102 */ 2103 if (pm->pm_stats.resident_count == 0) 2104 return; 2105 2106 LOCK_TABLE_WR(); 2107 PMAP_LOCK(pm); 2108 key.pvo_vaddr = sva; 2109 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2110 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2111 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2112 moea64_pvo_remove(mmu, pvo); 2113 } 2114 UNLOCK_TABLE_WR(); 2115 PMAP_UNLOCK(pm); 2116} 2117 2118/* 2119 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 2120 * will reflect changes in pte's back to the vm_page. 2121 */ 2122void 2123moea64_remove_all(mmu_t mmu, vm_page_t m) 2124{ 2125 struct pvo_entry *pvo, *next_pvo; 2126 pmap_t pmap; 2127 2128 LOCK_TABLE_WR(); 2129 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) { 2130 pmap = pvo->pvo_pmap; 2131 PMAP_LOCK(pmap); 2132 moea64_pvo_remove(mmu, pvo); 2133 PMAP_UNLOCK(pmap); 2134 } 2135 UNLOCK_TABLE_WR(); 2136 if ((m->aflags & PGA_WRITEABLE) && moea64_is_modified(mmu, m)) 2137 vm_page_dirty(m); 2138 vm_page_aflag_clear(m, PGA_WRITEABLE); 2139 vm_page_aflag_clear(m, PGA_EXECUTABLE); 2140} 2141 2142/* 2143 * Allocate a physical page of memory directly from the phys_avail map. 2144 * Can only be called from moea64_bootstrap before avail start and end are 2145 * calculated. 2146 */ 2147vm_offset_t 2148moea64_bootstrap_alloc(vm_size_t size, u_int align) 2149{ 2150 vm_offset_t s, e; 2151 int i, j; 2152 2153 size = round_page(size); 2154 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2155 if (align != 0) 2156 s = (phys_avail[i] + align - 1) & ~(align - 1); 2157 else 2158 s = phys_avail[i]; 2159 e = s + size; 2160 2161 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2162 continue; 2163 2164 if (s + size > platform_real_maxaddr()) 2165 continue; 2166 2167 if (s == phys_avail[i]) { 2168 phys_avail[i] += size; 2169 } else if (e == phys_avail[i + 1]) { 2170 phys_avail[i + 1] -= size; 2171 } else { 2172 for (j = phys_avail_count * 2; j > i; j -= 2) { 2173 phys_avail[j] = phys_avail[j - 2]; 2174 phys_avail[j + 1] = phys_avail[j - 1]; 2175 } 2176 2177 phys_avail[i + 3] = phys_avail[i + 1]; 2178 phys_avail[i + 1] = s; 2179 phys_avail[i + 2] = e; 2180 phys_avail_count++; 2181 } 2182 2183 return (s); 2184 } 2185 panic("moea64_bootstrap_alloc: could not allocate memory"); 2186} 2187 2188static int 2189moea64_pvo_enter(mmu_t mmu, pmap_t pm, uma_zone_t zone, 2190 struct pvo_head *pvo_head, vm_offset_t va, vm_offset_t pa, 2191 uint64_t pte_lo, int flags, int8_t psind __unused) 2192{ 2193 struct pvo_entry *pvo; 2194 uintptr_t pt; 2195 uint64_t vsid; 2196 int first; 2197 u_int ptegidx; 2198 int i; 2199 int bootstrap; 2200 2201 /* 2202 * One nasty thing that can happen here is that the UMA calls to 2203 * allocate new PVOs need to map more memory, which calls pvo_enter(), 2204 * which calls UMA... 2205 * 2206 * We break the loop by detecting recursion and allocating out of 2207 * the bootstrap pool. 2208 */ 2209 2210 first = 0; 2211 bootstrap = (flags & PVO_BOOTSTRAP); 2212 2213 if (!moea64_initialized) 2214 bootstrap = 1; 2215 2216 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2217 rw_assert(&moea64_table_lock, RA_WLOCKED); 2218 2219 /* 2220 * Compute the PTE Group index. 2221 */ 2222 va &= ~ADDR_POFF; 2223 vsid = va_to_vsid(pm, va); 2224 ptegidx = va_to_pteg(vsid, va, flags & PVO_LARGE); 2225 2226 /* 2227 * Remove any existing mapping for this page. Reuse the pvo entry if 2228 * there is a mapping. 2229 */ 2230 moea64_pvo_enter_calls++; 2231 2232 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) { 2233 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2234 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) == pa && 2235 (pvo->pvo_pte.lpte.pte_lo & (LPTE_NOEXEC | LPTE_PP)) 2236 == (pte_lo & (LPTE_NOEXEC | LPTE_PP))) { 2237 /* 2238 * The physical page and protection are not 2239 * changing. Instead, this may be a request 2240 * to change the mapping's wired attribute. 2241 */ 2242 pt = -1; 2243 if ((flags & PVO_WIRED) != 0 && 2244 (pvo->pvo_vaddr & PVO_WIRED) == 0) { 2245 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2246 pvo->pvo_vaddr |= PVO_WIRED; 2247 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED; 2248 pm->pm_stats.wired_count++; 2249 } else if ((flags & PVO_WIRED) == 0 && 2250 (pvo->pvo_vaddr & PVO_WIRED) != 0) { 2251 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2252 pvo->pvo_vaddr &= ~PVO_WIRED; 2253 pvo->pvo_pte.lpte.pte_hi &= ~LPTE_WIRED; 2254 pm->pm_stats.wired_count--; 2255 } 2256 if (!(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID)) { 2257 KASSERT(pt == -1, 2258 ("moea64_pvo_enter: valid pt")); 2259 /* Re-insert if spilled */ 2260 i = MOEA64_PTE_INSERT(mmu, ptegidx, 2261 &pvo->pvo_pte.lpte); 2262 if (i >= 0) 2263 PVO_PTEGIDX_SET(pvo, i); 2264 moea64_pte_overflow--; 2265 } else if (pt != -1) { 2266 /* 2267 * The PTE's wired attribute is not a 2268 * hardware feature, so there is no 2269 * need to invalidate any TLB entries. 2270 */ 2271 MOEA64_PTE_CHANGE(mmu, pt, 2272 &pvo->pvo_pte.lpte, pvo->pvo_vpn); 2273 } 2274 return (0); 2275 } 2276 moea64_pvo_remove(mmu, pvo); 2277 break; 2278 } 2279 } 2280 2281 /* 2282 * If we aren't overwriting a mapping, try to allocate. 2283 */ 2284 if (bootstrap) { 2285 if (moea64_bpvo_pool_index >= BPVO_POOL_SIZE) { 2286 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd", 2287 moea64_bpvo_pool_index, BPVO_POOL_SIZE, 2288 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 2289 } 2290 pvo = &moea64_bpvo_pool[moea64_bpvo_pool_index]; 2291 moea64_bpvo_pool_index++; 2292 bootstrap = 1; 2293 } else { 2294 pvo = uma_zalloc(zone, M_NOWAIT); 2295 } 2296 2297 if (pvo == NULL) 2298 return (ENOMEM); 2299 2300 moea64_pvo_entries++; 2301 pvo->pvo_vaddr = va; 2302 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT) 2303 | (vsid << 16); 2304 pvo->pvo_pmap = pm; 2305 LIST_INSERT_HEAD(&moea64_pvo_table[ptegidx], pvo, pvo_olink); 2306 pvo->pvo_vaddr &= ~ADDR_POFF; 2307 2308 if (flags & PVO_WIRED) 2309 pvo->pvo_vaddr |= PVO_WIRED; 2310 if (pvo_head != NULL) 2311 pvo->pvo_vaddr |= PVO_MANAGED; 2312 if (bootstrap) 2313 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 2314 if (flags & PVO_LARGE) 2315 pvo->pvo_vaddr |= PVO_LARGE; 2316 2317 moea64_pte_create(&pvo->pvo_pte.lpte, vsid, va, 2318 (uint64_t)(pa) | pte_lo, flags); 2319 2320 /* 2321 * Add to pmap list 2322 */ 2323 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo); 2324 2325 /* 2326 * Remember if the list was empty and therefore will be the first 2327 * item. 2328 */ 2329 if (pvo_head != NULL) { 2330 if (LIST_FIRST(pvo_head) == NULL) 2331 first = 1; 2332 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2333 } 2334 2335 if (pvo->pvo_vaddr & PVO_WIRED) { 2336 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED; 2337 pm->pm_stats.wired_count++; 2338 } 2339 pm->pm_stats.resident_count++; 2340 2341 /* 2342 * We hope this succeeds but it isn't required. 2343 */ 2344 i = MOEA64_PTE_INSERT(mmu, ptegidx, &pvo->pvo_pte.lpte); 2345 if (i >= 0) { 2346 PVO_PTEGIDX_SET(pvo, i); 2347 } else { 2348 panic("moea64_pvo_enter: overflow"); 2349 moea64_pte_overflow++; 2350 } 2351 2352 if (pm == kernel_pmap) 2353 isync(); 2354 2355#ifdef __powerpc64__ 2356 /* 2357 * Make sure all our bootstrap mappings are in the SLB as soon 2358 * as virtual memory is switched on. 2359 */ 2360 if (!pmap_bootstrapped) 2361 moea64_bootstrap_slb_prefault(va, flags & PVO_LARGE); 2362#endif 2363 2364 return (first ? ENOENT : 0); 2365} 2366 2367static void 2368moea64_pvo_remove(mmu_t mmu, struct pvo_entry *pvo) 2369{ 2370 struct vm_page *pg; 2371 uintptr_t pt; 2372 2373 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2374 rw_assert(&moea64_table_lock, RA_WLOCKED); 2375 2376 /* 2377 * If there is an active pte entry, we need to deactivate it (and 2378 * save the ref & cfg bits). 2379 */ 2380 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2381 if (pt != -1) { 2382 MOEA64_PTE_UNSET(mmu, pt, &pvo->pvo_pte.lpte, pvo->pvo_vpn); 2383 PVO_PTEGIDX_CLR(pvo); 2384 } else { 2385 moea64_pte_overflow--; 2386 } 2387 2388 /* 2389 * Update our statistics. 2390 */ 2391 pvo->pvo_pmap->pm_stats.resident_count--; 2392 if (pvo->pvo_vaddr & PVO_WIRED) 2393 pvo->pvo_pmap->pm_stats.wired_count--; 2394 2395 /* 2396 * Remove this PVO from the pmap list. 2397 */ 2398 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2399 2400 /* 2401 * Remove this from the overflow list and return it to the pool 2402 * if we aren't going to reuse it. 2403 */ 2404 LIST_REMOVE(pvo, pvo_olink); 2405 2406 /* 2407 * Update vm about the REF/CHG bits if the page is managed. 2408 */ 2409 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 2410 2411 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED && pg != NULL) { 2412 LIST_REMOVE(pvo, pvo_vlink); 2413 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) { 2414 if (pvo->pvo_pte.lpte.pte_lo & LPTE_CHG) 2415 vm_page_dirty(pg); 2416 if (pvo->pvo_pte.lpte.pte_lo & LPTE_REF) 2417 vm_page_aflag_set(pg, PGA_REFERENCED); 2418 if (LIST_EMPTY(vm_page_to_pvoh(pg))) 2419 vm_page_aflag_clear(pg, PGA_WRITEABLE); 2420 } 2421 if (LIST_EMPTY(vm_page_to_pvoh(pg))) 2422 vm_page_aflag_clear(pg, PGA_EXECUTABLE); 2423 } 2424 2425 moea64_pvo_entries--; 2426 moea64_pvo_remove_calls++; 2427 2428 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2429 uma_zfree((pvo->pvo_vaddr & PVO_MANAGED) ? moea64_mpvo_zone : 2430 moea64_upvo_zone, pvo); 2431} 2432 2433static struct pvo_entry * 2434moea64_pvo_find_va(pmap_t pm, vm_offset_t va) 2435{ 2436 struct pvo_entry key; 2437 2438 key.pvo_vaddr = va & ~ADDR_POFF; 2439 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key)); 2440} 2441 2442static boolean_t 2443moea64_query_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2444{ 2445 struct pvo_entry *pvo; 2446 uintptr_t pt; 2447 2448 LOCK_TABLE_RD(); 2449 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2450 /* 2451 * See if we saved the bit off. If so, return success. 2452 */ 2453 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2454 UNLOCK_TABLE_RD(); 2455 return (TRUE); 2456 } 2457 } 2458 2459 /* 2460 * No luck, now go through the hard part of looking at the PTEs 2461 * themselves. Sync so that any pending REF/CHG bits are flushed to 2462 * the PTEs. 2463 */ 2464 powerpc_sync(); 2465 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2466 2467 /* 2468 * See if this pvo has a valid PTE. if so, fetch the 2469 * REF/CHG bits from the valid PTE. If the appropriate 2470 * ptebit is set, return success. 2471 */ 2472 PMAP_LOCK(pvo->pvo_pmap); 2473 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2474 if (pt != -1) { 2475 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 2476 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2477 PMAP_UNLOCK(pvo->pvo_pmap); 2478 UNLOCK_TABLE_RD(); 2479 return (TRUE); 2480 } 2481 } 2482 PMAP_UNLOCK(pvo->pvo_pmap); 2483 } 2484 2485 UNLOCK_TABLE_RD(); 2486 return (FALSE); 2487} 2488 2489static u_int 2490moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2491{ 2492 u_int count; 2493 struct pvo_entry *pvo; 2494 uintptr_t pt; 2495 2496 /* 2497 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2498 * we can reset the right ones). note that since the pvo entries and 2499 * list heads are accessed via BAT0 and are never placed in the page 2500 * table, we don't have to worry about further accesses setting the 2501 * REF/CHG bits. 2502 */ 2503 powerpc_sync(); 2504 2505 /* 2506 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2507 * valid pte clear the ptebit from the valid pte. 2508 */ 2509 count = 0; 2510 LOCK_TABLE_RD(); 2511 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2512 PMAP_LOCK(pvo->pvo_pmap); 2513 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2514 if (pt != -1) { 2515 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 2516 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2517 count++; 2518 MOEA64_PTE_CLEAR(mmu, pt, &pvo->pvo_pte.lpte, 2519 pvo->pvo_vpn, ptebit); 2520 } 2521 } 2522 pvo->pvo_pte.lpte.pte_lo &= ~ptebit; 2523 PMAP_UNLOCK(pvo->pvo_pmap); 2524 } 2525 2526 UNLOCK_TABLE_RD(); 2527 return (count); 2528} 2529 2530boolean_t 2531moea64_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2532{ 2533 struct pvo_entry *pvo, key; 2534 vm_offset_t ppa; 2535 int error = 0; 2536 2537 PMAP_LOCK(kernel_pmap); 2538 key.pvo_vaddr = ppa = pa & ~ADDR_POFF; 2539 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key); 2540 ppa < pa + size; ppa += PAGE_SIZE, 2541 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) { 2542 if (pvo == NULL || 2543 (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) != ppa) { 2544 error = EFAULT; 2545 break; 2546 } 2547 } 2548 PMAP_UNLOCK(kernel_pmap); 2549 2550 return (error); 2551} 2552 2553/* 2554 * Map a set of physical memory pages into the kernel virtual 2555 * address space. Return a pointer to where it is mapped. This 2556 * routine is intended to be used for mapping device memory, 2557 * NOT real memory. 2558 */ 2559void * 2560moea64_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma) 2561{ 2562 vm_offset_t va, tmpva, ppa, offset; 2563 2564 ppa = trunc_page(pa); 2565 offset = pa & PAGE_MASK; 2566 size = roundup2(offset + size, PAGE_SIZE); 2567 2568 va = kva_alloc(size); 2569 2570 if (!va) 2571 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2572 2573 for (tmpva = va; size > 0;) { 2574 moea64_kenter_attr(mmu, tmpva, ppa, ma); 2575 size -= PAGE_SIZE; 2576 tmpva += PAGE_SIZE; 2577 ppa += PAGE_SIZE; 2578 } 2579 2580 return ((void *)(va + offset)); 2581} 2582 2583void * 2584moea64_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2585{ 2586 2587 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT); 2588} 2589 2590void 2591moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2592{ 2593 vm_offset_t base, offset; 2594 2595 base = trunc_page(va); 2596 offset = va & PAGE_MASK; 2597 size = roundup2(offset + size, PAGE_SIZE); 2598 2599 kva_free(base, size); 2600} 2601 2602void 2603moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2604{ 2605 struct pvo_entry *pvo; 2606 vm_offset_t lim; 2607 vm_paddr_t pa; 2608 vm_size_t len; 2609 2610 PMAP_LOCK(pm); 2611 while (sz > 0) { 2612 lim = round_page(va); 2613 len = MIN(lim - va, sz); 2614 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 2615 if (pvo != NULL && !(pvo->pvo_pte.lpte.pte_lo & LPTE_I)) { 2616 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | 2617 (va & ADDR_POFF); 2618 moea64_syncicache(mmu, pm, va, pa, len); 2619 } 2620 va += len; 2621 sz -= len; 2622 } 2623 PMAP_UNLOCK(pm); 2624} 2625 2626vm_offset_t 2627moea64_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 2628 vm_size_t *sz) 2629{ 2630 if (md->md_vaddr == ~0UL) 2631 return (md->md_paddr + ofs); 2632 else 2633 return (md->md_vaddr + ofs); 2634} 2635 2636struct pmap_md * 2637moea64_scan_md(mmu_t mmu, struct pmap_md *prev) 2638{ 2639 static struct pmap_md md; 2640 struct pvo_entry *pvo; 2641 vm_offset_t va; 2642 2643 if (dumpsys_minidump) { 2644 md.md_paddr = ~0UL; /* Minidumps use virtual addresses. */ 2645 if (prev == NULL) { 2646 /* 1st: kernel .data and .bss. */ 2647 md.md_index = 1; 2648 md.md_vaddr = trunc_page((uintptr_t)_etext); 2649 md.md_size = round_page((uintptr_t)_end) - md.md_vaddr; 2650 return (&md); 2651 } 2652 switch (prev->md_index) { 2653 case 1: 2654 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2655 md.md_index = 2; 2656 md.md_vaddr = (vm_offset_t)msgbufp->msg_ptr; 2657 md.md_size = round_page(msgbufp->msg_size); 2658 break; 2659 case 2: 2660 /* 3rd: kernel VM. */ 2661 va = prev->md_vaddr + prev->md_size; 2662 /* Find start of next chunk (from va). */ 2663 while (va < virtual_end) { 2664 /* Don't dump the buffer cache. */ 2665 if (va >= kmi.buffer_sva && 2666 va < kmi.buffer_eva) { 2667 va = kmi.buffer_eva; 2668 continue; 2669 } 2670 pvo = moea64_pvo_find_va(kernel_pmap, 2671 va & ~ADDR_POFF); 2672 if (pvo != NULL && 2673 (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID)) 2674 break; 2675 va += PAGE_SIZE; 2676 } 2677 if (va < virtual_end) { 2678 md.md_vaddr = va; 2679 va += PAGE_SIZE; 2680 /* Find last page in chunk. */ 2681 while (va < virtual_end) { 2682 /* Don't run into the buffer cache. */ 2683 if (va == kmi.buffer_sva) 2684 break; 2685 pvo = moea64_pvo_find_va(kernel_pmap, 2686 va & ~ADDR_POFF); 2687 if (pvo == NULL || 2688 !(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID)) 2689 break; 2690 va += PAGE_SIZE; 2691 } 2692 md.md_size = va - md.md_vaddr; 2693 break; 2694 } 2695 md.md_index = 3; 2696 /* FALLTHROUGH */ 2697 default: 2698 return (NULL); 2699 } 2700 } else { /* minidumps */ 2701 if (prev == NULL) { 2702 /* first physical chunk. */ 2703 md.md_paddr = pregions[0].mr_start; 2704 md.md_size = pregions[0].mr_size; 2705 md.md_vaddr = ~0UL; 2706 md.md_index = 1; 2707 } else if (md.md_index < pregions_sz) { 2708 md.md_paddr = pregions[md.md_index].mr_start; 2709 md.md_size = pregions[md.md_index].mr_size; 2710 md.md_vaddr = ~0UL; 2711 md.md_index++; 2712 } else { 2713 /* There's no next physical chunk. */ 2714 return (NULL); 2715 } 2716 } 2717 2718 return (&md); 2719} 2720