mmu_oea64.c revision 270439
1/*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29/*- 30 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 31 * Copyright (C) 1995, 1996 TooLs GmbH. 32 * All rights reserved. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. All advertising materials mentioning features or use of this software 43 * must display the following acknowledgement: 44 * This product includes software developed by TooLs GmbH. 45 * 4. The name of TooLs GmbH may not be used to endorse or promote products 46 * derived from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 51 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 52 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 53 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 54 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 55 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 56 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 57 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 58 * 59 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 60 */ 61/*- 62 * Copyright (C) 2001 Benno Rice. 63 * All rights reserved. 64 * 65 * Redistribution and use in source and binary forms, with or without 66 * modification, are permitted provided that the following conditions 67 * are met: 68 * 1. Redistributions of source code must retain the above copyright 69 * notice, this list of conditions and the following disclaimer. 70 * 2. Redistributions in binary form must reproduce the above copyright 71 * notice, this list of conditions and the following disclaimer in the 72 * documentation and/or other materials provided with the distribution. 73 * 74 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 75 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 76 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 77 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 78 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 79 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 80 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 81 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 82 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 83 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 84 */ 85 86#include <sys/cdefs.h> 87__FBSDID("$FreeBSD: stable/10/sys/powerpc/aim/mmu_oea64.c 270439 2014-08-24 07:53:15Z kib $"); 88 89/* 90 * Manages physical address maps. 91 * 92 * Since the information managed by this module is also stored by the 93 * logical address mapping module, this module may throw away valid virtual 94 * to physical mappings at almost any time. However, invalidations of 95 * mappings must be done as requested. 96 * 97 * In order to cope with hardware architectures which make virtual to 98 * physical map invalidates expensive, this module may delay invalidate 99 * reduced protection operations until such time as they are actually 100 * necessary. This module is given full information as to which processors 101 * are currently using which maps, and to when physical maps must be made 102 * correct. 103 */ 104 105#include "opt_compat.h" 106#include "opt_kstack_pages.h" 107 108#include <sys/param.h> 109#include <sys/kernel.h> 110#include <sys/queue.h> 111#include <sys/cpuset.h> 112#include <sys/ktr.h> 113#include <sys/lock.h> 114#include <sys/msgbuf.h> 115#include <sys/malloc.h> 116#include <sys/mutex.h> 117#include <sys/proc.h> 118#include <sys/rwlock.h> 119#include <sys/sched.h> 120#include <sys/sysctl.h> 121#include <sys/systm.h> 122#include <sys/vmmeter.h> 123 124#include <sys/kdb.h> 125 126#include <dev/ofw/openfirm.h> 127 128#include <vm/vm.h> 129#include <vm/vm_param.h> 130#include <vm/vm_kern.h> 131#include <vm/vm_page.h> 132#include <vm/vm_map.h> 133#include <vm/vm_object.h> 134#include <vm/vm_extern.h> 135#include <vm/vm_pageout.h> 136#include <vm/uma.h> 137 138#include <machine/_inttypes.h> 139#include <machine/cpu.h> 140#include <machine/platform.h> 141#include <machine/frame.h> 142#include <machine/md_var.h> 143#include <machine/psl.h> 144#include <machine/bat.h> 145#include <machine/hid.h> 146#include <machine/pte.h> 147#include <machine/sr.h> 148#include <machine/trap.h> 149#include <machine/mmuvar.h> 150 151#include "mmu_oea64.h" 152#include "mmu_if.h" 153#include "moea64_if.h" 154 155void moea64_release_vsid(uint64_t vsid); 156uintptr_t moea64_get_unique_vsid(void); 157 158#define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 159#define ENABLE_TRANS(msr) mtmsr(msr) 160 161#define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 162#define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 163#define VSID_HASH_MASK 0x0000007fffffffffULL 164 165/* 166 * Locking semantics: 167 * -- Read lock: if no modifications are being made to either the PVO lists 168 * or page table or if any modifications being made result in internal 169 * changes (e.g. wiring, protection) such that the existence of the PVOs 170 * is unchanged and they remain associated with the same pmap (in which 171 * case the changes should be protected by the pmap lock) 172 * -- Write lock: required if PTEs/PVOs are being inserted or removed. 173 */ 174 175#define LOCK_TABLE_RD() rw_rlock(&moea64_table_lock) 176#define UNLOCK_TABLE_RD() rw_runlock(&moea64_table_lock) 177#define LOCK_TABLE_WR() rw_wlock(&moea64_table_lock) 178#define UNLOCK_TABLE_WR() rw_wunlock(&moea64_table_lock) 179 180struct ofw_map { 181 cell_t om_va; 182 cell_t om_len; 183 uint64_t om_pa; 184 cell_t om_mode; 185}; 186 187extern unsigned char _etext[]; 188extern unsigned char _end[]; 189 190extern int dumpsys_minidump; 191 192/* 193 * Map of physical memory regions. 194 */ 195static struct mem_region *regions; 196static struct mem_region *pregions; 197static u_int phys_avail_count; 198static int regions_sz, pregions_sz; 199 200extern void bs_remap_earlyboot(void); 201 202/* 203 * Lock for the pteg and pvo tables. 204 */ 205struct rwlock moea64_table_lock; 206struct mtx moea64_slb_mutex; 207 208/* 209 * PTEG data. 210 */ 211u_int moea64_pteg_count; 212u_int moea64_pteg_mask; 213 214/* 215 * PVO data. 216 */ 217struct pvo_head *moea64_pvo_table; /* pvo entries by pteg index */ 218 219uma_zone_t moea64_upvo_zone; /* zone for pvo entries for unmanaged pages */ 220uma_zone_t moea64_mpvo_zone; /* zone for pvo entries for managed pages */ 221 222#define BPVO_POOL_SIZE 327680 223static struct pvo_entry *moea64_bpvo_pool; 224static int moea64_bpvo_pool_index = 0; 225 226#define VSID_NBPW (sizeof(u_int32_t) * 8) 227#ifdef __powerpc64__ 228#define NVSIDS (NPMAPS * 16) 229#define VSID_HASHMASK 0xffffffffUL 230#else 231#define NVSIDS NPMAPS 232#define VSID_HASHMASK 0xfffffUL 233#endif 234static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW]; 235 236static boolean_t moea64_initialized = FALSE; 237 238/* 239 * Statistics. 240 */ 241u_int moea64_pte_valid = 0; 242u_int moea64_pte_overflow = 0; 243u_int moea64_pvo_entries = 0; 244u_int moea64_pvo_enter_calls = 0; 245u_int moea64_pvo_remove_calls = 0; 246SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 247 &moea64_pte_valid, 0, ""); 248SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 249 &moea64_pte_overflow, 0, ""); 250SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 251 &moea64_pvo_entries, 0, ""); 252SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 253 &moea64_pvo_enter_calls, 0, ""); 254SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 255 &moea64_pvo_remove_calls, 0, ""); 256 257vm_offset_t moea64_scratchpage_va[2]; 258struct pvo_entry *moea64_scratchpage_pvo[2]; 259uintptr_t moea64_scratchpage_pte[2]; 260struct mtx moea64_scratchpage_mtx; 261 262uint64_t moea64_large_page_mask = 0; 263uint64_t moea64_large_page_size = 0; 264int moea64_large_page_shift = 0; 265 266/* 267 * PVO calls. 268 */ 269static int moea64_pvo_enter(mmu_t, pmap_t, uma_zone_t, struct pvo_head *, 270 vm_offset_t, vm_offset_t, uint64_t, int, int8_t); 271static void moea64_pvo_remove(mmu_t, struct pvo_entry *); 272static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t); 273 274/* 275 * Utility routines. 276 */ 277static boolean_t moea64_query_bit(mmu_t, vm_page_t, u_int64_t); 278static u_int moea64_clear_bit(mmu_t, vm_page_t, u_int64_t); 279static void moea64_kremove(mmu_t, vm_offset_t); 280static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va, 281 vm_offset_t pa, vm_size_t sz); 282 283/* 284 * Kernel MMU interface 285 */ 286void moea64_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 287void moea64_clear_modify(mmu_t, vm_page_t); 288void moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 289void moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 290 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 291int moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, 292 u_int flags, int8_t psind); 293void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 294 vm_prot_t); 295void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 296vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 297vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 298void moea64_init(mmu_t); 299boolean_t moea64_is_modified(mmu_t, vm_page_t); 300boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 301boolean_t moea64_is_referenced(mmu_t, vm_page_t); 302int moea64_ts_referenced(mmu_t, vm_page_t); 303vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 304boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 305int moea64_page_wired_mappings(mmu_t, vm_page_t); 306void moea64_pinit(mmu_t, pmap_t); 307void moea64_pinit0(mmu_t, pmap_t); 308void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 309void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 310void moea64_qremove(mmu_t, vm_offset_t, int); 311void moea64_release(mmu_t, pmap_t); 312void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 313void moea64_remove_pages(mmu_t, pmap_t); 314void moea64_remove_all(mmu_t, vm_page_t); 315void moea64_remove_write(mmu_t, vm_page_t); 316void moea64_zero_page(mmu_t, vm_page_t); 317void moea64_zero_page_area(mmu_t, vm_page_t, int, int); 318void moea64_zero_page_idle(mmu_t, vm_page_t); 319void moea64_activate(mmu_t, struct thread *); 320void moea64_deactivate(mmu_t, struct thread *); 321void *moea64_mapdev(mmu_t, vm_paddr_t, vm_size_t); 322void *moea64_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t); 323void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 324vm_paddr_t moea64_kextract(mmu_t, vm_offset_t); 325void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma); 326void moea64_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t ma); 327void moea64_kenter(mmu_t, vm_offset_t, vm_paddr_t); 328boolean_t moea64_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 329static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 330vm_offset_t moea64_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 331 vm_size_t *sz); 332struct pmap_md * moea64_scan_md(mmu_t mmu, struct pmap_md *prev); 333 334static mmu_method_t moea64_methods[] = { 335 MMUMETHOD(mmu_change_wiring, moea64_change_wiring), 336 MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 337 MMUMETHOD(mmu_copy_page, moea64_copy_page), 338 MMUMETHOD(mmu_copy_pages, moea64_copy_pages), 339 MMUMETHOD(mmu_enter, moea64_enter), 340 MMUMETHOD(mmu_enter_object, moea64_enter_object), 341 MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 342 MMUMETHOD(mmu_extract, moea64_extract), 343 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 344 MMUMETHOD(mmu_init, moea64_init), 345 MMUMETHOD(mmu_is_modified, moea64_is_modified), 346 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable), 347 MMUMETHOD(mmu_is_referenced, moea64_is_referenced), 348 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 349 MMUMETHOD(mmu_map, moea64_map), 350 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 351 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 352 MMUMETHOD(mmu_pinit, moea64_pinit), 353 MMUMETHOD(mmu_pinit0, moea64_pinit0), 354 MMUMETHOD(mmu_protect, moea64_protect), 355 MMUMETHOD(mmu_qenter, moea64_qenter), 356 MMUMETHOD(mmu_qremove, moea64_qremove), 357 MMUMETHOD(mmu_release, moea64_release), 358 MMUMETHOD(mmu_remove, moea64_remove), 359 MMUMETHOD(mmu_remove_pages, moea64_remove_pages), 360 MMUMETHOD(mmu_remove_all, moea64_remove_all), 361 MMUMETHOD(mmu_remove_write, moea64_remove_write), 362 MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 363 MMUMETHOD(mmu_zero_page, moea64_zero_page), 364 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 365 MMUMETHOD(mmu_zero_page_idle, moea64_zero_page_idle), 366 MMUMETHOD(mmu_activate, moea64_activate), 367 MMUMETHOD(mmu_deactivate, moea64_deactivate), 368 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr), 369 370 /* Internal interfaces */ 371 MMUMETHOD(mmu_mapdev, moea64_mapdev), 372 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr), 373 MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 374 MMUMETHOD(mmu_kextract, moea64_kextract), 375 MMUMETHOD(mmu_kenter, moea64_kenter), 376 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr), 377 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 378 MMUMETHOD(mmu_scan_md, moea64_scan_md), 379 MMUMETHOD(mmu_dumpsys_map, moea64_dumpsys_map), 380 381 { 0, 0 } 382}; 383 384MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0); 385 386static __inline u_int 387va_to_pteg(uint64_t vsid, vm_offset_t addr, int large) 388{ 389 uint64_t hash; 390 int shift; 391 392 shift = large ? moea64_large_page_shift : ADDR_PIDX_SHFT; 393 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)addr & ADDR_PIDX) >> 394 shift); 395 return (hash & moea64_pteg_mask); 396} 397 398static __inline struct pvo_head * 399vm_page_to_pvoh(vm_page_t m) 400{ 401 402 return (&m->md.mdpg_pvoh); 403} 404 405static __inline void 406moea64_pte_create(struct lpte *pt, uint64_t vsid, vm_offset_t va, 407 uint64_t pte_lo, int flags) 408{ 409 410 /* 411 * Construct a PTE. Default to IMB initially. Valid bit only gets 412 * set when the real pte is set in memory. 413 * 414 * Note: Don't set the valid bit for correct operation of tlb update. 415 */ 416 pt->pte_hi = (vsid << LPTE_VSID_SHIFT) | 417 (((uint64_t)(va & ADDR_PIDX) >> ADDR_API_SHFT64) & LPTE_API); 418 419 if (flags & PVO_LARGE) 420 pt->pte_hi |= LPTE_BIG; 421 422 pt->pte_lo = pte_lo; 423} 424 425static __inline uint64_t 426moea64_calc_wimg(vm_offset_t pa, vm_memattr_t ma) 427{ 428 uint64_t pte_lo; 429 int i; 430 431 if (ma != VM_MEMATTR_DEFAULT) { 432 switch (ma) { 433 case VM_MEMATTR_UNCACHEABLE: 434 return (LPTE_I | LPTE_G); 435 case VM_MEMATTR_WRITE_COMBINING: 436 case VM_MEMATTR_WRITE_BACK: 437 case VM_MEMATTR_PREFETCHABLE: 438 return (LPTE_I); 439 case VM_MEMATTR_WRITE_THROUGH: 440 return (LPTE_W | LPTE_M); 441 } 442 } 443 444 /* 445 * Assume the page is cache inhibited and access is guarded unless 446 * it's in our available memory array. 447 */ 448 pte_lo = LPTE_I | LPTE_G; 449 for (i = 0; i < pregions_sz; i++) { 450 if ((pa >= pregions[i].mr_start) && 451 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 452 pte_lo &= ~(LPTE_I | LPTE_G); 453 pte_lo |= LPTE_M; 454 break; 455 } 456 } 457 458 return pte_lo; 459} 460 461/* 462 * Quick sort callout for comparing memory regions. 463 */ 464static int om_cmp(const void *a, const void *b); 465 466static int 467om_cmp(const void *a, const void *b) 468{ 469 const struct ofw_map *mapa; 470 const struct ofw_map *mapb; 471 472 mapa = a; 473 mapb = b; 474 if (mapa->om_pa < mapb->om_pa) 475 return (-1); 476 else if (mapa->om_pa > mapb->om_pa) 477 return (1); 478 else 479 return (0); 480} 481 482static void 483moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz) 484{ 485 struct ofw_map translations[sz/(4*sizeof(cell_t))]; /*>= 4 cells per */ 486 pcell_t acells, trans_cells[sz/sizeof(cell_t)]; 487 register_t msr; 488 vm_offset_t off; 489 vm_paddr_t pa_base; 490 int i, j; 491 492 bzero(translations, sz); 493 OF_getprop(OF_finddevice("/"), "#address-cells", &acells, 494 sizeof(acells)); 495 if (OF_getprop(mmu, "translations", trans_cells, sz) == -1) 496 panic("moea64_bootstrap: can't get ofw translations"); 497 498 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 499 sz /= sizeof(cell_t); 500 for (i = 0, j = 0; i < sz; j++) { 501 translations[j].om_va = trans_cells[i++]; 502 translations[j].om_len = trans_cells[i++]; 503 translations[j].om_pa = trans_cells[i++]; 504 if (acells == 2) { 505 translations[j].om_pa <<= 32; 506 translations[j].om_pa |= trans_cells[i++]; 507 } 508 translations[j].om_mode = trans_cells[i++]; 509 } 510 KASSERT(i == sz, ("Translations map has incorrect cell count (%d/%zd)", 511 i, sz)); 512 513 sz = j; 514 qsort(translations, sz, sizeof (*translations), om_cmp); 515 516 for (i = 0; i < sz; i++) { 517 pa_base = translations[i].om_pa; 518 #ifndef __powerpc64__ 519 if ((translations[i].om_pa >> 32) != 0) 520 panic("OFW translations above 32-bit boundary!"); 521 #endif 522 523 if (pa_base % PAGE_SIZE) 524 panic("OFW translation not page-aligned (phys)!"); 525 if (translations[i].om_va % PAGE_SIZE) 526 panic("OFW translation not page-aligned (virt)!"); 527 528 CTR3(KTR_PMAP, "translation: pa=%#zx va=%#x len=%#x", 529 pa_base, translations[i].om_va, translations[i].om_len); 530 531 /* Now enter the pages for this mapping */ 532 533 DISABLE_TRANS(msr); 534 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 535 if (moea64_pvo_find_va(kernel_pmap, 536 translations[i].om_va + off) != NULL) 537 continue; 538 539 moea64_kenter(mmup, translations[i].om_va + off, 540 pa_base + off); 541 } 542 ENABLE_TRANS(msr); 543 } 544} 545 546#ifdef __powerpc64__ 547static void 548moea64_probe_large_page(void) 549{ 550 uint16_t pvr = mfpvr() >> 16; 551 552 switch (pvr) { 553 case IBM970: 554 case IBM970FX: 555 case IBM970MP: 556 powerpc_sync(); isync(); 557 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); 558 powerpc_sync(); isync(); 559 560 /* FALLTHROUGH */ 561 default: 562 moea64_large_page_size = 0x1000000; /* 16 MB */ 563 moea64_large_page_shift = 24; 564 } 565 566 moea64_large_page_mask = moea64_large_page_size - 1; 567} 568 569static void 570moea64_bootstrap_slb_prefault(vm_offset_t va, int large) 571{ 572 struct slb *cache; 573 struct slb entry; 574 uint64_t esid, slbe; 575 uint64_t i; 576 577 cache = PCPU_GET(slb); 578 esid = va >> ADDR_SR_SHFT; 579 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID; 580 581 for (i = 0; i < 64; i++) { 582 if (cache[i].slbe == (slbe | i)) 583 return; 584 } 585 586 entry.slbe = slbe; 587 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT; 588 if (large) 589 entry.slbv |= SLBV_L; 590 591 slb_insert_kernel(entry.slbe, entry.slbv); 592} 593#endif 594 595static void 596moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart, 597 vm_offset_t kernelend) 598{ 599 register_t msr; 600 vm_paddr_t pa; 601 vm_offset_t size, off; 602 uint64_t pte_lo; 603 int i; 604 605 if (moea64_large_page_size == 0) 606 hw_direct_map = 0; 607 608 DISABLE_TRANS(msr); 609 if (hw_direct_map) { 610 LOCK_TABLE_WR(); 611 PMAP_LOCK(kernel_pmap); 612 for (i = 0; i < pregions_sz; i++) { 613 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start + 614 pregions[i].mr_size; pa += moea64_large_page_size) { 615 pte_lo = LPTE_M; 616 617 /* 618 * Set memory access as guarded if prefetch within 619 * the page could exit the available physmem area. 620 */ 621 if (pa & moea64_large_page_mask) { 622 pa &= moea64_large_page_mask; 623 pte_lo |= LPTE_G; 624 } 625 if (pa + moea64_large_page_size > 626 pregions[i].mr_start + pregions[i].mr_size) 627 pte_lo |= LPTE_G; 628 629 moea64_pvo_enter(mmup, kernel_pmap, moea64_upvo_zone, 630 NULL, pa, pa, pte_lo, 631 PVO_WIRED | PVO_LARGE, 0); 632 } 633 } 634 PMAP_UNLOCK(kernel_pmap); 635 UNLOCK_TABLE_WR(); 636 } else { 637 size = sizeof(struct pvo_head) * moea64_pteg_count; 638 off = (vm_offset_t)(moea64_pvo_table); 639 for (pa = off; pa < off + size; pa += PAGE_SIZE) 640 moea64_kenter(mmup, pa, pa); 641 size = BPVO_POOL_SIZE*sizeof(struct pvo_entry); 642 off = (vm_offset_t)(moea64_bpvo_pool); 643 for (pa = off; pa < off + size; pa += PAGE_SIZE) 644 moea64_kenter(mmup, pa, pa); 645 646 /* 647 * Map certain important things, like ourselves. 648 * 649 * NOTE: We do not map the exception vector space. That code is 650 * used only in real mode, and leaving it unmapped allows us to 651 * catch NULL pointer deferences, instead of making NULL a valid 652 * address. 653 */ 654 655 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; 656 pa += PAGE_SIZE) 657 moea64_kenter(mmup, pa, pa); 658 } 659 ENABLE_TRANS(msr); 660 661 /* 662 * Allow user to override unmapped_buf_allowed for testing. 663 * XXXKIB Only direct map implementation was tested. 664 */ 665 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed", 666 &unmapped_buf_allowed)) 667 unmapped_buf_allowed = hw_direct_map; 668} 669 670void 671moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 672{ 673 int i, j; 674 vm_size_t physsz, hwphyssz; 675 676#ifndef __powerpc64__ 677 /* We don't have a direct map since there is no BAT */ 678 hw_direct_map = 0; 679 680 /* Make sure battable is zero, since we have no BAT */ 681 for (i = 0; i < 16; i++) { 682 battable[i].batu = 0; 683 battable[i].batl = 0; 684 } 685#else 686 moea64_probe_large_page(); 687 688 /* Use a direct map if we have large page support */ 689 if (moea64_large_page_size > 0) 690 hw_direct_map = 1; 691 else 692 hw_direct_map = 0; 693#endif 694 695 /* Get physical memory regions from firmware */ 696 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 697 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 698 699 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 700 panic("moea64_bootstrap: phys_avail too small"); 701 702 phys_avail_count = 0; 703 physsz = 0; 704 hwphyssz = 0; 705 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 706 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 707 CTR3(KTR_PMAP, "region: %#zx - %#zx (%#zx)", 708 regions[i].mr_start, regions[i].mr_start + 709 regions[i].mr_size, regions[i].mr_size); 710 if (hwphyssz != 0 && 711 (physsz + regions[i].mr_size) >= hwphyssz) { 712 if (physsz < hwphyssz) { 713 phys_avail[j] = regions[i].mr_start; 714 phys_avail[j + 1] = regions[i].mr_start + 715 hwphyssz - physsz; 716 physsz = hwphyssz; 717 phys_avail_count++; 718 } 719 break; 720 } 721 phys_avail[j] = regions[i].mr_start; 722 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 723 phys_avail_count++; 724 physsz += regions[i].mr_size; 725 } 726 727 /* Check for overlap with the kernel and exception vectors */ 728 for (j = 0; j < 2*phys_avail_count; j+=2) { 729 if (phys_avail[j] < EXC_LAST) 730 phys_avail[j] += EXC_LAST; 731 732 if (kernelstart >= phys_avail[j] && 733 kernelstart < phys_avail[j+1]) { 734 if (kernelend < phys_avail[j+1]) { 735 phys_avail[2*phys_avail_count] = 736 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 737 phys_avail[2*phys_avail_count + 1] = 738 phys_avail[j+1]; 739 phys_avail_count++; 740 } 741 742 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 743 } 744 745 if (kernelend >= phys_avail[j] && 746 kernelend < phys_avail[j+1]) { 747 if (kernelstart > phys_avail[j]) { 748 phys_avail[2*phys_avail_count] = phys_avail[j]; 749 phys_avail[2*phys_avail_count + 1] = 750 kernelstart & ~PAGE_MASK; 751 phys_avail_count++; 752 } 753 754 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 755 } 756 } 757 758 physmem = btoc(physsz); 759 760#ifdef PTEGCOUNT 761 moea64_pteg_count = PTEGCOUNT; 762#else 763 moea64_pteg_count = 0x1000; 764 765 while (moea64_pteg_count < physmem) 766 moea64_pteg_count <<= 1; 767 768 moea64_pteg_count >>= 1; 769#endif /* PTEGCOUNT */ 770} 771 772void 773moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 774{ 775 vm_size_t size; 776 register_t msr; 777 int i; 778 779 /* 780 * Set PTEG mask 781 */ 782 moea64_pteg_mask = moea64_pteg_count - 1; 783 784 /* 785 * Allocate pv/overflow lists. 786 */ 787 size = sizeof(struct pvo_head) * moea64_pteg_count; 788 789 moea64_pvo_table = (struct pvo_head *)moea64_bootstrap_alloc(size, 790 PAGE_SIZE); 791 CTR1(KTR_PMAP, "moea64_bootstrap: PVO table at %p", moea64_pvo_table); 792 793 DISABLE_TRANS(msr); 794 for (i = 0; i < moea64_pteg_count; i++) 795 LIST_INIT(&moea64_pvo_table[i]); 796 ENABLE_TRANS(msr); 797 798 /* 799 * Initialize the lock that synchronizes access to the pteg and pvo 800 * tables. 801 */ 802 rw_init_flags(&moea64_table_lock, "pmap tables", RW_RECURSE); 803 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF); 804 805 /* 806 * Initialise the unmanaged pvo pool. 807 */ 808 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 809 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 810 moea64_bpvo_pool_index = 0; 811 812 /* 813 * Make sure kernel vsid is allocated as well as VSID 0. 814 */ 815 #ifndef __powerpc64__ 816 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW] 817 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 818 moea64_vsid_bitmap[0] |= 1; 819 #endif 820 821 /* 822 * Initialize the kernel pmap (which is statically allocated). 823 */ 824 #ifdef __powerpc64__ 825 for (i = 0; i < 64; i++) { 826 pcpup->pc_slb[i].slbv = 0; 827 pcpup->pc_slb[i].slbe = 0; 828 } 829 #else 830 for (i = 0; i < 16; i++) 831 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 832 #endif 833 834 kernel_pmap->pmap_phys = kernel_pmap; 835 CPU_FILL(&kernel_pmap->pm_active); 836 RB_INIT(&kernel_pmap->pmap_pvo); 837 838 PMAP_LOCK_INIT(kernel_pmap); 839 840 /* 841 * Now map in all the other buffers we allocated earlier 842 */ 843 844 moea64_setup_direct_map(mmup, kernelstart, kernelend); 845} 846 847void 848moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 849{ 850 ihandle_t mmui; 851 phandle_t chosen; 852 phandle_t mmu; 853 size_t sz; 854 int i; 855 vm_offset_t pa, va; 856 void *dpcpu; 857 858 /* 859 * Set up the Open Firmware pmap and add its mappings if not in real 860 * mode. 861 */ 862 863 chosen = OF_finddevice("/chosen"); 864 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1) { 865 mmu = OF_instance_to_package(mmui); 866 if (mmu == -1 || (sz = OF_getproplen(mmu, "translations")) == -1) 867 sz = 0; 868 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 869 panic("moea64_bootstrap: too many ofw translations"); 870 871 if (sz > 0) 872 moea64_add_ofw_mappings(mmup, mmu, sz); 873 } 874 875 /* 876 * Calculate the last available physical address. 877 */ 878 for (i = 0; phys_avail[i + 2] != 0; i += 2) 879 ; 880 Maxmem = powerpc_btop(phys_avail[i + 1]); 881 882 /* 883 * Initialize MMU and remap early physical mappings 884 */ 885 MMU_CPU_BOOTSTRAP(mmup,0); 886 mtmsr(mfmsr() | PSL_DR | PSL_IR); 887 pmap_bootstrapped++; 888 bs_remap_earlyboot(); 889 890 /* 891 * Set the start and end of kva. 892 */ 893 virtual_avail = VM_MIN_KERNEL_ADDRESS; 894 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 895 896 /* 897 * Map the entire KVA range into the SLB. We must not fault there. 898 */ 899 #ifdef __powerpc64__ 900 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH) 901 moea64_bootstrap_slb_prefault(va, 0); 902 #endif 903 904 /* 905 * Figure out how far we can extend virtual_end into segment 16 906 * without running into existing mappings. Segment 16 is guaranteed 907 * to contain neither RAM nor devices (at least on Apple hardware), 908 * but will generally contain some OFW mappings we should not 909 * step on. 910 */ 911 912 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */ 913 PMAP_LOCK(kernel_pmap); 914 while (virtual_end < VM_MAX_KERNEL_ADDRESS && 915 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL) 916 virtual_end += PAGE_SIZE; 917 PMAP_UNLOCK(kernel_pmap); 918 #endif 919 920 /* 921 * Allocate a kernel stack with a guard page for thread0 and map it 922 * into the kernel page map. 923 */ 924 pa = moea64_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 925 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 926 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 927 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va); 928 thread0.td_kstack = va; 929 thread0.td_kstack_pages = KSTACK_PAGES; 930 for (i = 0; i < KSTACK_PAGES; i++) { 931 moea64_kenter(mmup, va, pa); 932 pa += PAGE_SIZE; 933 va += PAGE_SIZE; 934 } 935 936 /* 937 * Allocate virtual address space for the message buffer. 938 */ 939 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE); 940 msgbufp = (struct msgbuf *)virtual_avail; 941 va = virtual_avail; 942 virtual_avail += round_page(msgbufsize); 943 while (va < virtual_avail) { 944 moea64_kenter(mmup, va, pa); 945 pa += PAGE_SIZE; 946 va += PAGE_SIZE; 947 } 948 949 /* 950 * Allocate virtual address space for the dynamic percpu area. 951 */ 952 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 953 dpcpu = (void *)virtual_avail; 954 va = virtual_avail; 955 virtual_avail += DPCPU_SIZE; 956 while (va < virtual_avail) { 957 moea64_kenter(mmup, va, pa); 958 pa += PAGE_SIZE; 959 va += PAGE_SIZE; 960 } 961 dpcpu_init(dpcpu, 0); 962 963 /* 964 * Allocate some things for page zeroing. We put this directly 965 * in the page table, marked with LPTE_LOCKED, to avoid any 966 * of the PVO book-keeping or other parts of the VM system 967 * from even knowing that this hack exists. 968 */ 969 970 if (!hw_direct_map) { 971 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, 972 MTX_DEF); 973 for (i = 0; i < 2; i++) { 974 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 975 virtual_end -= PAGE_SIZE; 976 977 moea64_kenter(mmup, moea64_scratchpage_va[i], 0); 978 979 moea64_scratchpage_pvo[i] = moea64_pvo_find_va( 980 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]); 981 LOCK_TABLE_RD(); 982 moea64_scratchpage_pte[i] = MOEA64_PVO_TO_PTE( 983 mmup, moea64_scratchpage_pvo[i]); 984 moea64_scratchpage_pvo[i]->pvo_pte.lpte.pte_hi 985 |= LPTE_LOCKED; 986 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[i], 987 &moea64_scratchpage_pvo[i]->pvo_pte.lpte, 988 moea64_scratchpage_pvo[i]->pvo_vpn); 989 UNLOCK_TABLE_RD(); 990 } 991 } 992} 993 994/* 995 * Activate a user pmap. The pmap must be activated before its address 996 * space can be accessed in any way. 997 */ 998void 999moea64_activate(mmu_t mmu, struct thread *td) 1000{ 1001 pmap_t pm; 1002 1003 pm = &td->td_proc->p_vmspace->vm_pmap; 1004 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1005 1006 #ifdef __powerpc64__ 1007 PCPU_SET(userslb, pm->pm_slb); 1008 #else 1009 PCPU_SET(curpmap, pm->pmap_phys); 1010 #endif 1011} 1012 1013void 1014moea64_deactivate(mmu_t mmu, struct thread *td) 1015{ 1016 pmap_t pm; 1017 1018 pm = &td->td_proc->p_vmspace->vm_pmap; 1019 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1020 #ifdef __powerpc64__ 1021 PCPU_SET(userslb, NULL); 1022 #else 1023 PCPU_SET(curpmap, NULL); 1024 #endif 1025} 1026 1027void 1028moea64_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 1029{ 1030 struct pvo_entry *pvo; 1031 uintptr_t pt; 1032 uint64_t vsid; 1033 int i, ptegidx; 1034 1035 LOCK_TABLE_WR(); 1036 PMAP_LOCK(pm); 1037 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 1038 1039 if (pvo != NULL) { 1040 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1041 1042 if (wired) { 1043 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1044 pm->pm_stats.wired_count++; 1045 pvo->pvo_vaddr |= PVO_WIRED; 1046 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED; 1047 } else { 1048 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1049 pm->pm_stats.wired_count--; 1050 pvo->pvo_vaddr &= ~PVO_WIRED; 1051 pvo->pvo_pte.lpte.pte_hi &= ~LPTE_WIRED; 1052 } 1053 1054 if (pt != -1) { 1055 /* Update wiring flag in page table. */ 1056 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1057 pvo->pvo_vpn); 1058 } else if (wired) { 1059 /* 1060 * If we are wiring the page, and it wasn't in the 1061 * page table before, add it. 1062 */ 1063 vsid = PVO_VSID(pvo); 1064 ptegidx = va_to_pteg(vsid, PVO_VADDR(pvo), 1065 pvo->pvo_vaddr & PVO_LARGE); 1066 1067 i = MOEA64_PTE_INSERT(mmu, ptegidx, &pvo->pvo_pte.lpte); 1068 1069 if (i >= 0) { 1070 PVO_PTEGIDX_CLR(pvo); 1071 PVO_PTEGIDX_SET(pvo, i); 1072 } 1073 } 1074 1075 } 1076 UNLOCK_TABLE_WR(); 1077 PMAP_UNLOCK(pm); 1078} 1079 1080/* 1081 * This goes through and sets the physical address of our 1082 * special scratch PTE to the PA we want to zero or copy. Because 1083 * of locking issues (this can get called in pvo_enter() by 1084 * the UMA allocator), we can't use most other utility functions here 1085 */ 1086 1087static __inline 1088void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_offset_t pa) { 1089 1090 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!")); 1091 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1092 1093 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo &= 1094 ~(LPTE_WIMG | LPTE_RPGN); 1095 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo |= 1096 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa; 1097 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[which], 1098 &moea64_scratchpage_pvo[which]->pvo_pte.lpte, 1099 moea64_scratchpage_pvo[which]->pvo_vpn); 1100 isync(); 1101} 1102 1103void 1104moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1105{ 1106 vm_offset_t dst; 1107 vm_offset_t src; 1108 1109 dst = VM_PAGE_TO_PHYS(mdst); 1110 src = VM_PAGE_TO_PHYS(msrc); 1111 1112 if (hw_direct_map) { 1113 bcopy((void *)src, (void *)dst, PAGE_SIZE); 1114 } else { 1115 mtx_lock(&moea64_scratchpage_mtx); 1116 1117 moea64_set_scratchpage_pa(mmu, 0, src); 1118 moea64_set_scratchpage_pa(mmu, 1, dst); 1119 1120 bcopy((void *)moea64_scratchpage_va[0], 1121 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1122 1123 mtx_unlock(&moea64_scratchpage_mtx); 1124 } 1125} 1126 1127static inline void 1128moea64_copy_pages_dmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1129 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1130{ 1131 void *a_cp, *b_cp; 1132 vm_offset_t a_pg_offset, b_pg_offset; 1133 int cnt; 1134 1135 while (xfersize > 0) { 1136 a_pg_offset = a_offset & PAGE_MASK; 1137 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1138 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) + 1139 a_pg_offset; 1140 b_pg_offset = b_offset & PAGE_MASK; 1141 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1142 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) + 1143 b_pg_offset; 1144 bcopy(a_cp, b_cp, cnt); 1145 a_offset += cnt; 1146 b_offset += cnt; 1147 xfersize -= cnt; 1148 } 1149} 1150 1151static inline void 1152moea64_copy_pages_nodmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1153 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1154{ 1155 void *a_cp, *b_cp; 1156 vm_offset_t a_pg_offset, b_pg_offset; 1157 int cnt; 1158 1159 mtx_lock(&moea64_scratchpage_mtx); 1160 while (xfersize > 0) { 1161 a_pg_offset = a_offset & PAGE_MASK; 1162 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1163 moea64_set_scratchpage_pa(mmu, 0, 1164 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 1165 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset; 1166 b_pg_offset = b_offset & PAGE_MASK; 1167 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1168 moea64_set_scratchpage_pa(mmu, 1, 1169 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 1170 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset; 1171 bcopy(a_cp, b_cp, cnt); 1172 a_offset += cnt; 1173 b_offset += cnt; 1174 xfersize -= cnt; 1175 } 1176 mtx_unlock(&moea64_scratchpage_mtx); 1177} 1178 1179void 1180moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1181 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1182{ 1183 1184 if (hw_direct_map) { 1185 moea64_copy_pages_dmap(mmu, ma, a_offset, mb, b_offset, 1186 xfersize); 1187 } else { 1188 moea64_copy_pages_nodmap(mmu, ma, a_offset, mb, b_offset, 1189 xfersize); 1190 } 1191} 1192 1193void 1194moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1195{ 1196 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1197 1198 if (size + off > PAGE_SIZE) 1199 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1200 1201 if (hw_direct_map) { 1202 bzero((caddr_t)pa + off, size); 1203 } else { 1204 mtx_lock(&moea64_scratchpage_mtx); 1205 moea64_set_scratchpage_pa(mmu, 0, pa); 1206 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1207 mtx_unlock(&moea64_scratchpage_mtx); 1208 } 1209} 1210 1211/* 1212 * Zero a page of physical memory by temporarily mapping it 1213 */ 1214void 1215moea64_zero_page(mmu_t mmu, vm_page_t m) 1216{ 1217 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1218 vm_offset_t va, off; 1219 1220 if (!hw_direct_map) { 1221 mtx_lock(&moea64_scratchpage_mtx); 1222 1223 moea64_set_scratchpage_pa(mmu, 0, pa); 1224 va = moea64_scratchpage_va[0]; 1225 } else { 1226 va = pa; 1227 } 1228 1229 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1230 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 1231 1232 if (!hw_direct_map) 1233 mtx_unlock(&moea64_scratchpage_mtx); 1234} 1235 1236void 1237moea64_zero_page_idle(mmu_t mmu, vm_page_t m) 1238{ 1239 1240 moea64_zero_page(mmu, m); 1241} 1242 1243/* 1244 * Map the given physical page at the specified virtual address in the 1245 * target pmap with the protection requested. If specified the page 1246 * will be wired down. 1247 */ 1248 1249int 1250moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1251 vm_prot_t prot, u_int flags, int8_t psind) 1252{ 1253 struct pvo_head *pvo_head; 1254 uma_zone_t zone; 1255 vm_page_t pg; 1256 uint64_t pte_lo; 1257 u_int pvo_flags; 1258 int error; 1259 1260 if (!moea64_initialized) { 1261 pvo_head = NULL; 1262 pg = NULL; 1263 zone = moea64_upvo_zone; 1264 pvo_flags = 0; 1265 } else { 1266 pvo_head = vm_page_to_pvoh(m); 1267 pg = m; 1268 zone = moea64_mpvo_zone; 1269 pvo_flags = PVO_MANAGED; 1270 } 1271 1272 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1273 VM_OBJECT_ASSERT_LOCKED(m->object); 1274 1275 /* XXX change the pvo head for fake pages */ 1276 if ((m->oflags & VPO_UNMANAGED) != 0) { 1277 pvo_flags &= ~PVO_MANAGED; 1278 pvo_head = NULL; 1279 zone = moea64_upvo_zone; 1280 } 1281 1282 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1283 1284 if (prot & VM_PROT_WRITE) { 1285 pte_lo |= LPTE_BW; 1286 if (pmap_bootstrapped && 1287 (m->oflags & VPO_UNMANAGED) == 0) 1288 vm_page_aflag_set(m, PGA_WRITEABLE); 1289 } else 1290 pte_lo |= LPTE_BR; 1291 1292 if ((prot & VM_PROT_EXECUTE) == 0) 1293 pte_lo |= LPTE_NOEXEC; 1294 1295 if ((flags & PMAP_ENTER_WIRED) != 0) 1296 pvo_flags |= PVO_WIRED; 1297 1298 for (;;) { 1299 LOCK_TABLE_WR(); 1300 PMAP_LOCK(pmap); 1301 error = moea64_pvo_enter(mmu, pmap, zone, pvo_head, va, 1302 VM_PAGE_TO_PHYS(m), pte_lo, pvo_flags, psind); 1303 PMAP_UNLOCK(pmap); 1304 UNLOCK_TABLE_WR(); 1305 if (error != ENOMEM) 1306 break; 1307 if ((flags & PMAP_ENTER_NOSLEEP) != 0) 1308 return (KERN_RESOURCE_SHORTAGE); 1309 VM_OBJECT_ASSERT_UNLOCKED(m->object); 1310 VM_WAIT; 1311 } 1312 1313 /* 1314 * Flush the page from the instruction cache if this page is 1315 * mapped executable and cacheable. 1316 */ 1317 if (pmap != kernel_pmap && !(m->aflags & PGA_EXECUTABLE) && 1318 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1319 vm_page_aflag_set(m, PGA_EXECUTABLE); 1320 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1321 } 1322 return (KERN_SUCCESS); 1323} 1324 1325static void 1326moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t pa, 1327 vm_size_t sz) 1328{ 1329 1330 /* 1331 * This is much trickier than on older systems because 1332 * we can't sync the icache on physical addresses directly 1333 * without a direct map. Instead we check a couple of cases 1334 * where the memory is already mapped in and, failing that, 1335 * use the same trick we use for page zeroing to create 1336 * a temporary mapping for this physical address. 1337 */ 1338 1339 if (!pmap_bootstrapped) { 1340 /* 1341 * If PMAP is not bootstrapped, we are likely to be 1342 * in real mode. 1343 */ 1344 __syncicache((void *)pa, sz); 1345 } else if (pmap == kernel_pmap) { 1346 __syncicache((void *)va, sz); 1347 } else if (hw_direct_map) { 1348 __syncicache((void *)pa, sz); 1349 } else { 1350 /* Use the scratch page to set up a temp mapping */ 1351 1352 mtx_lock(&moea64_scratchpage_mtx); 1353 1354 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF); 1355 __syncicache((void *)(moea64_scratchpage_va[1] + 1356 (va & ADDR_POFF)), sz); 1357 1358 mtx_unlock(&moea64_scratchpage_mtx); 1359 } 1360} 1361 1362/* 1363 * Maps a sequence of resident pages belonging to the same object. 1364 * The sequence begins with the given page m_start. This page is 1365 * mapped at the given virtual address start. Each subsequent page is 1366 * mapped at a virtual address that is offset from start by the same 1367 * amount as the page is offset from m_start within the object. The 1368 * last page in the sequence is the page with the largest offset from 1369 * m_start that can be mapped at a virtual address less than the given 1370 * virtual address end. Not every virtual page between start and end 1371 * is mapped; only those for which a resident page exists with the 1372 * corresponding offset from m_start are mapped. 1373 */ 1374void 1375moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1376 vm_page_t m_start, vm_prot_t prot) 1377{ 1378 vm_page_t m; 1379 vm_pindex_t diff, psize; 1380 1381 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1382 1383 psize = atop(end - start); 1384 m = m_start; 1385 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1386 moea64_enter(mmu, pm, start + ptoa(diff), m, prot & 1387 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP, 0); 1388 m = TAILQ_NEXT(m, listq); 1389 } 1390} 1391 1392void 1393moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1394 vm_prot_t prot) 1395{ 1396 1397 moea64_enter(mmu, pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1398 PMAP_ENTER_NOSLEEP, 0); 1399} 1400 1401vm_paddr_t 1402moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1403{ 1404 struct pvo_entry *pvo; 1405 vm_paddr_t pa; 1406 1407 PMAP_LOCK(pm); 1408 pvo = moea64_pvo_find_va(pm, va); 1409 if (pvo == NULL) 1410 pa = 0; 1411 else 1412 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | 1413 (va - PVO_VADDR(pvo)); 1414 PMAP_UNLOCK(pm); 1415 return (pa); 1416} 1417 1418/* 1419 * Atomically extract and hold the physical page with the given 1420 * pmap and virtual address pair if that mapping permits the given 1421 * protection. 1422 */ 1423vm_page_t 1424moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1425{ 1426 struct pvo_entry *pvo; 1427 vm_page_t m; 1428 vm_paddr_t pa; 1429 1430 m = NULL; 1431 pa = 0; 1432 PMAP_LOCK(pmap); 1433retry: 1434 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1435 if (pvo != NULL && (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) && 1436 ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == LPTE_RW || 1437 (prot & VM_PROT_WRITE) == 0)) { 1438 if (vm_page_pa_tryrelock(pmap, 1439 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, &pa)) 1440 goto retry; 1441 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 1442 vm_page_hold(m); 1443 } 1444 PA_UNLOCK_COND(pa); 1445 PMAP_UNLOCK(pmap); 1446 return (m); 1447} 1448 1449static mmu_t installed_mmu; 1450 1451static void * 1452moea64_uma_page_alloc(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 1453{ 1454 /* 1455 * This entire routine is a horrible hack to avoid bothering kmem 1456 * for new KVA addresses. Because this can get called from inside 1457 * kmem allocation routines, calling kmem for a new address here 1458 * can lead to multiply locking non-recursive mutexes. 1459 */ 1460 vm_offset_t va; 1461 1462 vm_page_t m; 1463 int pflags, needed_lock; 1464 1465 *flags = UMA_SLAB_PRIV; 1466 needed_lock = !PMAP_LOCKED(kernel_pmap); 1467 pflags = malloc2vm_flags(wait) | VM_ALLOC_WIRED; 1468 1469 for (;;) { 1470 m = vm_page_alloc(NULL, 0, pflags | VM_ALLOC_NOOBJ); 1471 if (m == NULL) { 1472 if (wait & M_NOWAIT) 1473 return (NULL); 1474 VM_WAIT; 1475 } else 1476 break; 1477 } 1478 1479 va = VM_PAGE_TO_PHYS(m); 1480 1481 LOCK_TABLE_WR(); 1482 if (needed_lock) 1483 PMAP_LOCK(kernel_pmap); 1484 1485 moea64_pvo_enter(installed_mmu, kernel_pmap, moea64_upvo_zone, 1486 NULL, va, VM_PAGE_TO_PHYS(m), LPTE_M, PVO_WIRED | PVO_BOOTSTRAP, 1487 0); 1488 1489 if (needed_lock) 1490 PMAP_UNLOCK(kernel_pmap); 1491 UNLOCK_TABLE_WR(); 1492 1493 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1494 bzero((void *)va, PAGE_SIZE); 1495 1496 return (void *)va; 1497} 1498 1499extern int elf32_nxstack; 1500 1501void 1502moea64_init(mmu_t mmu) 1503{ 1504 1505 CTR0(KTR_PMAP, "moea64_init"); 1506 1507 moea64_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1508 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1509 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1510 moea64_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1511 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1512 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1513 1514 if (!hw_direct_map) { 1515 installed_mmu = mmu; 1516 uma_zone_set_allocf(moea64_upvo_zone,moea64_uma_page_alloc); 1517 uma_zone_set_allocf(moea64_mpvo_zone,moea64_uma_page_alloc); 1518 } 1519 1520#ifdef COMPAT_FREEBSD32 1521 elf32_nxstack = 1; 1522#endif 1523 1524 moea64_initialized = TRUE; 1525} 1526 1527boolean_t 1528moea64_is_referenced(mmu_t mmu, vm_page_t m) 1529{ 1530 1531 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1532 ("moea64_is_referenced: page %p is not managed", m)); 1533 return (moea64_query_bit(mmu, m, PTE_REF)); 1534} 1535 1536boolean_t 1537moea64_is_modified(mmu_t mmu, vm_page_t m) 1538{ 1539 1540 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1541 ("moea64_is_modified: page %p is not managed", m)); 1542 1543 /* 1544 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1545 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1546 * is clear, no PTEs can have LPTE_CHG set. 1547 */ 1548 VM_OBJECT_ASSERT_LOCKED(m->object); 1549 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1550 return (FALSE); 1551 return (moea64_query_bit(mmu, m, LPTE_CHG)); 1552} 1553 1554boolean_t 1555moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1556{ 1557 struct pvo_entry *pvo; 1558 boolean_t rv; 1559 1560 PMAP_LOCK(pmap); 1561 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1562 rv = pvo == NULL || (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0; 1563 PMAP_UNLOCK(pmap); 1564 return (rv); 1565} 1566 1567void 1568moea64_clear_modify(mmu_t mmu, vm_page_t m) 1569{ 1570 1571 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1572 ("moea64_clear_modify: page %p is not managed", m)); 1573 VM_OBJECT_ASSERT_WLOCKED(m->object); 1574 KASSERT(!vm_page_xbusied(m), 1575 ("moea64_clear_modify: page %p is exclusive busied", m)); 1576 1577 /* 1578 * If the page is not PGA_WRITEABLE, then no PTEs can have LPTE_CHG 1579 * set. If the object containing the page is locked and the page is 1580 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 1581 */ 1582 if ((m->aflags & PGA_WRITEABLE) == 0) 1583 return; 1584 moea64_clear_bit(mmu, m, LPTE_CHG); 1585} 1586 1587/* 1588 * Clear the write and modified bits in each of the given page's mappings. 1589 */ 1590void 1591moea64_remove_write(mmu_t mmu, vm_page_t m) 1592{ 1593 struct pvo_entry *pvo; 1594 uintptr_t pt; 1595 pmap_t pmap; 1596 uint64_t lo = 0; 1597 1598 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1599 ("moea64_remove_write: page %p is not managed", m)); 1600 1601 /* 1602 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1603 * set by another thread while the object is locked. Thus, 1604 * if PGA_WRITEABLE is clear, no page table entries need updating. 1605 */ 1606 VM_OBJECT_ASSERT_WLOCKED(m->object); 1607 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1608 return; 1609 powerpc_sync(); 1610 LOCK_TABLE_RD(); 1611 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1612 pmap = pvo->pvo_pmap; 1613 PMAP_LOCK(pmap); 1614 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) { 1615 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1616 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1617 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1618 if (pt != -1) { 1619 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 1620 lo |= pvo->pvo_pte.lpte.pte_lo; 1621 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_CHG; 1622 MOEA64_PTE_CHANGE(mmu, pt, 1623 &pvo->pvo_pte.lpte, pvo->pvo_vpn); 1624 if (pvo->pvo_pmap == kernel_pmap) 1625 isync(); 1626 } 1627 } 1628 if ((lo & LPTE_CHG) != 0) 1629 vm_page_dirty(m); 1630 PMAP_UNLOCK(pmap); 1631 } 1632 UNLOCK_TABLE_RD(); 1633 vm_page_aflag_clear(m, PGA_WRITEABLE); 1634} 1635 1636/* 1637 * moea64_ts_referenced: 1638 * 1639 * Return a count of reference bits for a page, clearing those bits. 1640 * It is not necessary for every reference bit to be cleared, but it 1641 * is necessary that 0 only be returned when there are truly no 1642 * reference bits set. 1643 * 1644 * XXX: The exact number of bits to check and clear is a matter that 1645 * should be tested and standardized at some point in the future for 1646 * optimal aging of shared pages. 1647 */ 1648int 1649moea64_ts_referenced(mmu_t mmu, vm_page_t m) 1650{ 1651 1652 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1653 ("moea64_ts_referenced: page %p is not managed", m)); 1654 return (moea64_clear_bit(mmu, m, LPTE_REF)); 1655} 1656 1657/* 1658 * Modify the WIMG settings of all mappings for a page. 1659 */ 1660void 1661moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1662{ 1663 struct pvo_entry *pvo; 1664 struct pvo_head *pvo_head; 1665 uintptr_t pt; 1666 pmap_t pmap; 1667 uint64_t lo; 1668 1669 if ((m->oflags & VPO_UNMANAGED) != 0) { 1670 m->md.mdpg_cache_attrs = ma; 1671 return; 1672 } 1673 1674 pvo_head = vm_page_to_pvoh(m); 1675 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1676 LOCK_TABLE_RD(); 1677 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1678 pmap = pvo->pvo_pmap; 1679 PMAP_LOCK(pmap); 1680 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1681 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_WIMG; 1682 pvo->pvo_pte.lpte.pte_lo |= lo; 1683 if (pt != -1) { 1684 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1685 pvo->pvo_vpn); 1686 if (pvo->pvo_pmap == kernel_pmap) 1687 isync(); 1688 } 1689 PMAP_UNLOCK(pmap); 1690 } 1691 UNLOCK_TABLE_RD(); 1692 m->md.mdpg_cache_attrs = ma; 1693} 1694 1695/* 1696 * Map a wired page into kernel virtual address space. 1697 */ 1698void 1699moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma) 1700{ 1701 uint64_t pte_lo; 1702 int error; 1703 1704 pte_lo = moea64_calc_wimg(pa, ma); 1705 1706 LOCK_TABLE_WR(); 1707 PMAP_LOCK(kernel_pmap); 1708 error = moea64_pvo_enter(mmu, kernel_pmap, moea64_upvo_zone, 1709 NULL, va, pa, pte_lo, PVO_WIRED, 0); 1710 PMAP_UNLOCK(kernel_pmap); 1711 UNLOCK_TABLE_WR(); 1712 1713 if (error != 0 && error != ENOENT) 1714 panic("moea64_kenter: failed to enter va %#zx pa %#zx: %d", va, 1715 pa, error); 1716} 1717 1718void 1719moea64_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1720{ 1721 1722 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1723} 1724 1725/* 1726 * Extract the physical page address associated with the given kernel virtual 1727 * address. 1728 */ 1729vm_paddr_t 1730moea64_kextract(mmu_t mmu, vm_offset_t va) 1731{ 1732 struct pvo_entry *pvo; 1733 vm_paddr_t pa; 1734 1735 /* 1736 * Shortcut the direct-mapped case when applicable. We never put 1737 * anything but 1:1 mappings below VM_MIN_KERNEL_ADDRESS. 1738 */ 1739 if (va < VM_MIN_KERNEL_ADDRESS) 1740 return (va); 1741 1742 PMAP_LOCK(kernel_pmap); 1743 pvo = moea64_pvo_find_va(kernel_pmap, va); 1744 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR, 1745 va)); 1746 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1747 PMAP_UNLOCK(kernel_pmap); 1748 return (pa); 1749} 1750 1751/* 1752 * Remove a wired page from kernel virtual address space. 1753 */ 1754void 1755moea64_kremove(mmu_t mmu, vm_offset_t va) 1756{ 1757 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1758} 1759 1760/* 1761 * Map a range of physical addresses into kernel virtual address space. 1762 * 1763 * The value passed in *virt is a suggested virtual address for the mapping. 1764 * Architectures which can support a direct-mapped physical to virtual region 1765 * can return the appropriate address within that region, leaving '*virt' 1766 * unchanged. We cannot and therefore do not; *virt is updated with the 1767 * first usable address after the mapped region. 1768 */ 1769vm_offset_t 1770moea64_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1771 vm_paddr_t pa_end, int prot) 1772{ 1773 vm_offset_t sva, va; 1774 1775 sva = *virt; 1776 va = sva; 1777 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1778 moea64_kenter(mmu, va, pa_start); 1779 *virt = va; 1780 1781 return (sva); 1782} 1783 1784/* 1785 * Returns true if the pmap's pv is one of the first 1786 * 16 pvs linked to from this page. This count may 1787 * be changed upwards or downwards in the future; it 1788 * is only necessary that true be returned for a small 1789 * subset of pmaps for proper page aging. 1790 */ 1791boolean_t 1792moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1793{ 1794 int loops; 1795 struct pvo_entry *pvo; 1796 boolean_t rv; 1797 1798 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1799 ("moea64_page_exists_quick: page %p is not managed", m)); 1800 loops = 0; 1801 rv = FALSE; 1802 LOCK_TABLE_RD(); 1803 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1804 if (pvo->pvo_pmap == pmap) { 1805 rv = TRUE; 1806 break; 1807 } 1808 if (++loops >= 16) 1809 break; 1810 } 1811 UNLOCK_TABLE_RD(); 1812 return (rv); 1813} 1814 1815/* 1816 * Return the number of managed mappings to the given physical page 1817 * that are wired. 1818 */ 1819int 1820moea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 1821{ 1822 struct pvo_entry *pvo; 1823 int count; 1824 1825 count = 0; 1826 if ((m->oflags & VPO_UNMANAGED) != 0) 1827 return (count); 1828 LOCK_TABLE_RD(); 1829 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1830 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1831 count++; 1832 UNLOCK_TABLE_RD(); 1833 return (count); 1834} 1835 1836static uintptr_t moea64_vsidcontext; 1837 1838uintptr_t 1839moea64_get_unique_vsid(void) { 1840 u_int entropy; 1841 register_t hash; 1842 uint32_t mask; 1843 int i; 1844 1845 entropy = 0; 1846 __asm __volatile("mftb %0" : "=r"(entropy)); 1847 1848 mtx_lock(&moea64_slb_mutex); 1849 for (i = 0; i < NVSIDS; i += VSID_NBPW) { 1850 u_int n; 1851 1852 /* 1853 * Create a new value by mutiplying by a prime and adding in 1854 * entropy from the timebase register. This is to make the 1855 * VSID more random so that the PT hash function collides 1856 * less often. (Note that the prime casues gcc to do shifts 1857 * instead of a multiply.) 1858 */ 1859 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 1860 hash = moea64_vsidcontext & (NVSIDS - 1); 1861 if (hash == 0) /* 0 is special, avoid it */ 1862 continue; 1863 n = hash >> 5; 1864 mask = 1 << (hash & (VSID_NBPW - 1)); 1865 hash = (moea64_vsidcontext & VSID_HASHMASK); 1866 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 1867 /* anything free in this bucket? */ 1868 if (moea64_vsid_bitmap[n] == 0xffffffff) { 1869 entropy = (moea64_vsidcontext >> 20); 1870 continue; 1871 } 1872 i = ffs(~moea64_vsid_bitmap[n]) - 1; 1873 mask = 1 << i; 1874 hash &= VSID_HASHMASK & ~(VSID_NBPW - 1); 1875 hash |= i; 1876 } 1877 KASSERT(!(moea64_vsid_bitmap[n] & mask), 1878 ("Allocating in-use VSID %#zx\n", hash)); 1879 moea64_vsid_bitmap[n] |= mask; 1880 mtx_unlock(&moea64_slb_mutex); 1881 return (hash); 1882 } 1883 1884 mtx_unlock(&moea64_slb_mutex); 1885 panic("%s: out of segments",__func__); 1886} 1887 1888#ifdef __powerpc64__ 1889void 1890moea64_pinit(mmu_t mmu, pmap_t pmap) 1891{ 1892 1893 RB_INIT(&pmap->pmap_pvo); 1894 1895 pmap->pm_slb_tree_root = slb_alloc_tree(); 1896 pmap->pm_slb = slb_alloc_user_cache(); 1897 pmap->pm_slb_len = 0; 1898} 1899#else 1900void 1901moea64_pinit(mmu_t mmu, pmap_t pmap) 1902{ 1903 int i; 1904 uint32_t hash; 1905 1906 RB_INIT(&pmap->pmap_pvo); 1907 1908 if (pmap_bootstrapped) 1909 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, 1910 (vm_offset_t)pmap); 1911 else 1912 pmap->pmap_phys = pmap; 1913 1914 /* 1915 * Allocate some segment registers for this pmap. 1916 */ 1917 hash = moea64_get_unique_vsid(); 1918 1919 for (i = 0; i < 16; i++) 1920 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1921 1922 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0")); 1923} 1924#endif 1925 1926/* 1927 * Initialize the pmap associated with process 0. 1928 */ 1929void 1930moea64_pinit0(mmu_t mmu, pmap_t pm) 1931{ 1932 1933 PMAP_LOCK_INIT(pm); 1934 moea64_pinit(mmu, pm); 1935 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1936} 1937 1938/* 1939 * Set the physical protection on the specified range of this map as requested. 1940 */ 1941static void 1942moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot) 1943{ 1944 uintptr_t pt; 1945 struct vm_page *pg; 1946 uint64_t oldlo; 1947 1948 PMAP_LOCK_ASSERT(pm, MA_OWNED); 1949 1950 /* 1951 * Grab the PTE pointer before we diddle with the cached PTE 1952 * copy. 1953 */ 1954 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1955 1956 /* 1957 * Change the protection of the page. 1958 */ 1959 oldlo = pvo->pvo_pte.lpte.pte_lo; 1960 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1961 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_NOEXEC; 1962 if ((prot & VM_PROT_EXECUTE) == 0) 1963 pvo->pvo_pte.lpte.pte_lo |= LPTE_NOEXEC; 1964 if (prot & VM_PROT_WRITE) 1965 pvo->pvo_pte.lpte.pte_lo |= LPTE_BW; 1966 else 1967 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1968 1969 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 1970 1971 /* 1972 * If the PVO is in the page table, update that pte as well. 1973 */ 1974 if (pt != -1) 1975 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1976 pvo->pvo_vpn); 1977 if (pm != kernel_pmap && pg != NULL && !(pg->aflags & PGA_EXECUTABLE) && 1978 (pvo->pvo_pte.lpte.pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1979 if ((pg->oflags & VPO_UNMANAGED) == 0) 1980 vm_page_aflag_set(pg, PGA_EXECUTABLE); 1981 moea64_syncicache(mmu, pm, PVO_VADDR(pvo), 1982 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, PAGE_SIZE); 1983 } 1984 1985 /* 1986 * Update vm about the REF/CHG bits if the page is managed and we have 1987 * removed write access. 1988 */ 1989 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED && 1990 (oldlo & LPTE_PP) != LPTE_BR && !(prot & VM_PROT_WRITE)) { 1991 if (pg != NULL) { 1992 if (pvo->pvo_pte.lpte.pte_lo & LPTE_CHG) 1993 vm_page_dirty(pg); 1994 if (pvo->pvo_pte.lpte.pte_lo & LPTE_REF) 1995 vm_page_aflag_set(pg, PGA_REFERENCED); 1996 } 1997 } 1998} 1999 2000void 2001moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 2002 vm_prot_t prot) 2003{ 2004 struct pvo_entry *pvo, *tpvo, key; 2005 2006 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, 2007 sva, eva, prot); 2008 2009 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 2010 ("moea64_protect: non current pmap")); 2011 2012 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2013 moea64_remove(mmu, pm, sva, eva); 2014 return; 2015 } 2016 2017 LOCK_TABLE_RD(); 2018 PMAP_LOCK(pm); 2019 key.pvo_vaddr = sva; 2020 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2021 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2022 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2023 moea64_pvo_protect(mmu, pm, pvo, prot); 2024 } 2025 UNLOCK_TABLE_RD(); 2026 PMAP_UNLOCK(pm); 2027} 2028 2029/* 2030 * Map a list of wired pages into kernel virtual address space. This is 2031 * intended for temporary mappings which do not need page modification or 2032 * references recorded. Existing mappings in the region are overwritten. 2033 */ 2034void 2035moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 2036{ 2037 while (count-- > 0) { 2038 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 2039 va += PAGE_SIZE; 2040 m++; 2041 } 2042} 2043 2044/* 2045 * Remove page mappings from kernel virtual address space. Intended for 2046 * temporary mappings entered by moea64_qenter. 2047 */ 2048void 2049moea64_qremove(mmu_t mmu, vm_offset_t va, int count) 2050{ 2051 while (count-- > 0) { 2052 moea64_kremove(mmu, va); 2053 va += PAGE_SIZE; 2054 } 2055} 2056 2057void 2058moea64_release_vsid(uint64_t vsid) 2059{ 2060 int idx, mask; 2061 2062 mtx_lock(&moea64_slb_mutex); 2063 idx = vsid & (NVSIDS-1); 2064 mask = 1 << (idx % VSID_NBPW); 2065 idx /= VSID_NBPW; 2066 KASSERT(moea64_vsid_bitmap[idx] & mask, 2067 ("Freeing unallocated VSID %#jx", vsid)); 2068 moea64_vsid_bitmap[idx] &= ~mask; 2069 mtx_unlock(&moea64_slb_mutex); 2070} 2071 2072 2073void 2074moea64_release(mmu_t mmu, pmap_t pmap) 2075{ 2076 2077 /* 2078 * Free segment registers' VSIDs 2079 */ 2080 #ifdef __powerpc64__ 2081 slb_free_tree(pmap); 2082 slb_free_user_cache(pmap->pm_slb); 2083 #else 2084 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0")); 2085 2086 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0])); 2087 #endif 2088} 2089 2090/* 2091 * Remove all pages mapped by the specified pmap 2092 */ 2093void 2094moea64_remove_pages(mmu_t mmu, pmap_t pm) 2095{ 2096 struct pvo_entry *pvo, *tpvo; 2097 2098 LOCK_TABLE_WR(); 2099 PMAP_LOCK(pm); 2100 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) { 2101 if (!(pvo->pvo_vaddr & PVO_WIRED)) 2102 moea64_pvo_remove(mmu, pvo); 2103 } 2104 UNLOCK_TABLE_WR(); 2105 PMAP_UNLOCK(pm); 2106} 2107 2108/* 2109 * Remove the given range of addresses from the specified map. 2110 */ 2111void 2112moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 2113{ 2114 struct pvo_entry *pvo, *tpvo, key; 2115 2116 /* 2117 * Perform an unsynchronized read. This is, however, safe. 2118 */ 2119 if (pm->pm_stats.resident_count == 0) 2120 return; 2121 2122 LOCK_TABLE_WR(); 2123 PMAP_LOCK(pm); 2124 key.pvo_vaddr = sva; 2125 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2126 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2127 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2128 moea64_pvo_remove(mmu, pvo); 2129 } 2130 UNLOCK_TABLE_WR(); 2131 PMAP_UNLOCK(pm); 2132} 2133 2134/* 2135 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 2136 * will reflect changes in pte's back to the vm_page. 2137 */ 2138void 2139moea64_remove_all(mmu_t mmu, vm_page_t m) 2140{ 2141 struct pvo_entry *pvo, *next_pvo; 2142 pmap_t pmap; 2143 2144 LOCK_TABLE_WR(); 2145 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) { 2146 pmap = pvo->pvo_pmap; 2147 PMAP_LOCK(pmap); 2148 moea64_pvo_remove(mmu, pvo); 2149 PMAP_UNLOCK(pmap); 2150 } 2151 UNLOCK_TABLE_WR(); 2152 if ((m->aflags & PGA_WRITEABLE) && moea64_is_modified(mmu, m)) 2153 vm_page_dirty(m); 2154 vm_page_aflag_clear(m, PGA_WRITEABLE); 2155 vm_page_aflag_clear(m, PGA_EXECUTABLE); 2156} 2157 2158/* 2159 * Allocate a physical page of memory directly from the phys_avail map. 2160 * Can only be called from moea64_bootstrap before avail start and end are 2161 * calculated. 2162 */ 2163vm_offset_t 2164moea64_bootstrap_alloc(vm_size_t size, u_int align) 2165{ 2166 vm_offset_t s, e; 2167 int i, j; 2168 2169 size = round_page(size); 2170 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2171 if (align != 0) 2172 s = (phys_avail[i] + align - 1) & ~(align - 1); 2173 else 2174 s = phys_avail[i]; 2175 e = s + size; 2176 2177 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2178 continue; 2179 2180 if (s + size > platform_real_maxaddr()) 2181 continue; 2182 2183 if (s == phys_avail[i]) { 2184 phys_avail[i] += size; 2185 } else if (e == phys_avail[i + 1]) { 2186 phys_avail[i + 1] -= size; 2187 } else { 2188 for (j = phys_avail_count * 2; j > i; j -= 2) { 2189 phys_avail[j] = phys_avail[j - 2]; 2190 phys_avail[j + 1] = phys_avail[j - 1]; 2191 } 2192 2193 phys_avail[i + 3] = phys_avail[i + 1]; 2194 phys_avail[i + 1] = s; 2195 phys_avail[i + 2] = e; 2196 phys_avail_count++; 2197 } 2198 2199 return (s); 2200 } 2201 panic("moea64_bootstrap_alloc: could not allocate memory"); 2202} 2203 2204static int 2205moea64_pvo_enter(mmu_t mmu, pmap_t pm, uma_zone_t zone, 2206 struct pvo_head *pvo_head, vm_offset_t va, vm_offset_t pa, 2207 uint64_t pte_lo, int flags, int8_t psind __unused) 2208{ 2209 struct pvo_entry *pvo; 2210 uint64_t vsid; 2211 int first; 2212 u_int ptegidx; 2213 int i; 2214 int bootstrap; 2215 2216 /* 2217 * One nasty thing that can happen here is that the UMA calls to 2218 * allocate new PVOs need to map more memory, which calls pvo_enter(), 2219 * which calls UMA... 2220 * 2221 * We break the loop by detecting recursion and allocating out of 2222 * the bootstrap pool. 2223 */ 2224 2225 first = 0; 2226 bootstrap = (flags & PVO_BOOTSTRAP); 2227 2228 if (!moea64_initialized) 2229 bootstrap = 1; 2230 2231 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2232 rw_assert(&moea64_table_lock, RA_WLOCKED); 2233 2234 /* 2235 * Compute the PTE Group index. 2236 */ 2237 va &= ~ADDR_POFF; 2238 vsid = va_to_vsid(pm, va); 2239 ptegidx = va_to_pteg(vsid, va, flags & PVO_LARGE); 2240 2241 /* 2242 * Remove any existing mapping for this page. Reuse the pvo entry if 2243 * there is a mapping. 2244 */ 2245 moea64_pvo_enter_calls++; 2246 2247 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) { 2248 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2249 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) == pa && 2250 (pvo->pvo_pte.lpte.pte_lo & (LPTE_NOEXEC | LPTE_PP)) 2251 == (pte_lo & (LPTE_NOEXEC | LPTE_PP))) { 2252 if (!(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID)) { 2253 /* Re-insert if spilled */ 2254 i = MOEA64_PTE_INSERT(mmu, ptegidx, 2255 &pvo->pvo_pte.lpte); 2256 if (i >= 0) 2257 PVO_PTEGIDX_SET(pvo, i); 2258 moea64_pte_overflow--; 2259 } 2260 return (0); 2261 } 2262 moea64_pvo_remove(mmu, pvo); 2263 break; 2264 } 2265 } 2266 2267 /* 2268 * If we aren't overwriting a mapping, try to allocate. 2269 */ 2270 if (bootstrap) { 2271 if (moea64_bpvo_pool_index >= BPVO_POOL_SIZE) { 2272 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd", 2273 moea64_bpvo_pool_index, BPVO_POOL_SIZE, 2274 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 2275 } 2276 pvo = &moea64_bpvo_pool[moea64_bpvo_pool_index]; 2277 moea64_bpvo_pool_index++; 2278 bootstrap = 1; 2279 } else { 2280 pvo = uma_zalloc(zone, M_NOWAIT); 2281 } 2282 2283 if (pvo == NULL) 2284 return (ENOMEM); 2285 2286 moea64_pvo_entries++; 2287 pvo->pvo_vaddr = va; 2288 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT) 2289 | (vsid << 16); 2290 pvo->pvo_pmap = pm; 2291 LIST_INSERT_HEAD(&moea64_pvo_table[ptegidx], pvo, pvo_olink); 2292 pvo->pvo_vaddr &= ~ADDR_POFF; 2293 2294 if (flags & PVO_WIRED) 2295 pvo->pvo_vaddr |= PVO_WIRED; 2296 if (pvo_head != NULL) 2297 pvo->pvo_vaddr |= PVO_MANAGED; 2298 if (bootstrap) 2299 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 2300 if (flags & PVO_LARGE) 2301 pvo->pvo_vaddr |= PVO_LARGE; 2302 2303 moea64_pte_create(&pvo->pvo_pte.lpte, vsid, va, 2304 (uint64_t)(pa) | pte_lo, flags); 2305 2306 /* 2307 * Add to pmap list 2308 */ 2309 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo); 2310 2311 /* 2312 * Remember if the list was empty and therefore will be the first 2313 * item. 2314 */ 2315 if (pvo_head != NULL) { 2316 if (LIST_FIRST(pvo_head) == NULL) 2317 first = 1; 2318 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2319 } 2320 2321 if (pvo->pvo_vaddr & PVO_WIRED) { 2322 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED; 2323 pm->pm_stats.wired_count++; 2324 } 2325 pm->pm_stats.resident_count++; 2326 2327 /* 2328 * We hope this succeeds but it isn't required. 2329 */ 2330 i = MOEA64_PTE_INSERT(mmu, ptegidx, &pvo->pvo_pte.lpte); 2331 if (i >= 0) { 2332 PVO_PTEGIDX_SET(pvo, i); 2333 } else { 2334 panic("moea64_pvo_enter: overflow"); 2335 moea64_pte_overflow++; 2336 } 2337 2338 if (pm == kernel_pmap) 2339 isync(); 2340 2341#ifdef __powerpc64__ 2342 /* 2343 * Make sure all our bootstrap mappings are in the SLB as soon 2344 * as virtual memory is switched on. 2345 */ 2346 if (!pmap_bootstrapped) 2347 moea64_bootstrap_slb_prefault(va, flags & PVO_LARGE); 2348#endif 2349 2350 return (first ? ENOENT : 0); 2351} 2352 2353static void 2354moea64_pvo_remove(mmu_t mmu, struct pvo_entry *pvo) 2355{ 2356 struct vm_page *pg; 2357 uintptr_t pt; 2358 2359 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2360 rw_assert(&moea64_table_lock, RA_WLOCKED); 2361 2362 /* 2363 * If there is an active pte entry, we need to deactivate it (and 2364 * save the ref & cfg bits). 2365 */ 2366 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2367 if (pt != -1) { 2368 MOEA64_PTE_UNSET(mmu, pt, &pvo->pvo_pte.lpte, pvo->pvo_vpn); 2369 PVO_PTEGIDX_CLR(pvo); 2370 } else { 2371 moea64_pte_overflow--; 2372 } 2373 2374 /* 2375 * Update our statistics. 2376 */ 2377 pvo->pvo_pmap->pm_stats.resident_count--; 2378 if (pvo->pvo_vaddr & PVO_WIRED) 2379 pvo->pvo_pmap->pm_stats.wired_count--; 2380 2381 /* 2382 * Remove this PVO from the pmap list. 2383 */ 2384 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2385 2386 /* 2387 * Remove this from the overflow list and return it to the pool 2388 * if we aren't going to reuse it. 2389 */ 2390 LIST_REMOVE(pvo, pvo_olink); 2391 2392 /* 2393 * Update vm about the REF/CHG bits if the page is managed. 2394 */ 2395 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 2396 2397 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED && pg != NULL) { 2398 LIST_REMOVE(pvo, pvo_vlink); 2399 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) { 2400 if (pvo->pvo_pte.lpte.pte_lo & LPTE_CHG) 2401 vm_page_dirty(pg); 2402 if (pvo->pvo_pte.lpte.pte_lo & LPTE_REF) 2403 vm_page_aflag_set(pg, PGA_REFERENCED); 2404 if (LIST_EMPTY(vm_page_to_pvoh(pg))) 2405 vm_page_aflag_clear(pg, PGA_WRITEABLE); 2406 } 2407 if (LIST_EMPTY(vm_page_to_pvoh(pg))) 2408 vm_page_aflag_clear(pg, PGA_EXECUTABLE); 2409 } 2410 2411 moea64_pvo_entries--; 2412 moea64_pvo_remove_calls++; 2413 2414 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2415 uma_zfree((pvo->pvo_vaddr & PVO_MANAGED) ? moea64_mpvo_zone : 2416 moea64_upvo_zone, pvo); 2417} 2418 2419static struct pvo_entry * 2420moea64_pvo_find_va(pmap_t pm, vm_offset_t va) 2421{ 2422 struct pvo_entry key; 2423 2424 key.pvo_vaddr = va & ~ADDR_POFF; 2425 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key)); 2426} 2427 2428static boolean_t 2429moea64_query_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2430{ 2431 struct pvo_entry *pvo; 2432 uintptr_t pt; 2433 2434 LOCK_TABLE_RD(); 2435 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2436 /* 2437 * See if we saved the bit off. If so, return success. 2438 */ 2439 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2440 UNLOCK_TABLE_RD(); 2441 return (TRUE); 2442 } 2443 } 2444 2445 /* 2446 * No luck, now go through the hard part of looking at the PTEs 2447 * themselves. Sync so that any pending REF/CHG bits are flushed to 2448 * the PTEs. 2449 */ 2450 powerpc_sync(); 2451 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2452 2453 /* 2454 * See if this pvo has a valid PTE. if so, fetch the 2455 * REF/CHG bits from the valid PTE. If the appropriate 2456 * ptebit is set, return success. 2457 */ 2458 PMAP_LOCK(pvo->pvo_pmap); 2459 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2460 if (pt != -1) { 2461 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 2462 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2463 PMAP_UNLOCK(pvo->pvo_pmap); 2464 UNLOCK_TABLE_RD(); 2465 return (TRUE); 2466 } 2467 } 2468 PMAP_UNLOCK(pvo->pvo_pmap); 2469 } 2470 2471 UNLOCK_TABLE_RD(); 2472 return (FALSE); 2473} 2474 2475static u_int 2476moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2477{ 2478 u_int count; 2479 struct pvo_entry *pvo; 2480 uintptr_t pt; 2481 2482 /* 2483 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2484 * we can reset the right ones). note that since the pvo entries and 2485 * list heads are accessed via BAT0 and are never placed in the page 2486 * table, we don't have to worry about further accesses setting the 2487 * REF/CHG bits. 2488 */ 2489 powerpc_sync(); 2490 2491 /* 2492 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2493 * valid pte clear the ptebit from the valid pte. 2494 */ 2495 count = 0; 2496 LOCK_TABLE_RD(); 2497 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2498 PMAP_LOCK(pvo->pvo_pmap); 2499 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2500 if (pt != -1) { 2501 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 2502 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2503 count++; 2504 MOEA64_PTE_CLEAR(mmu, pt, &pvo->pvo_pte.lpte, 2505 pvo->pvo_vpn, ptebit); 2506 } 2507 } 2508 pvo->pvo_pte.lpte.pte_lo &= ~ptebit; 2509 PMAP_UNLOCK(pvo->pvo_pmap); 2510 } 2511 2512 UNLOCK_TABLE_RD(); 2513 return (count); 2514} 2515 2516boolean_t 2517moea64_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2518{ 2519 struct pvo_entry *pvo, key; 2520 vm_offset_t ppa; 2521 int error = 0; 2522 2523 PMAP_LOCK(kernel_pmap); 2524 key.pvo_vaddr = ppa = pa & ~ADDR_POFF; 2525 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key); 2526 ppa < pa + size; ppa += PAGE_SIZE, 2527 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) { 2528 if (pvo == NULL || 2529 (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) != ppa) { 2530 error = EFAULT; 2531 break; 2532 } 2533 } 2534 PMAP_UNLOCK(kernel_pmap); 2535 2536 return (error); 2537} 2538 2539/* 2540 * Map a set of physical memory pages into the kernel virtual 2541 * address space. Return a pointer to where it is mapped. This 2542 * routine is intended to be used for mapping device memory, 2543 * NOT real memory. 2544 */ 2545void * 2546moea64_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma) 2547{ 2548 vm_offset_t va, tmpva, ppa, offset; 2549 2550 ppa = trunc_page(pa); 2551 offset = pa & PAGE_MASK; 2552 size = roundup2(offset + size, PAGE_SIZE); 2553 2554 va = kva_alloc(size); 2555 2556 if (!va) 2557 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2558 2559 for (tmpva = va; size > 0;) { 2560 moea64_kenter_attr(mmu, tmpva, ppa, ma); 2561 size -= PAGE_SIZE; 2562 tmpva += PAGE_SIZE; 2563 ppa += PAGE_SIZE; 2564 } 2565 2566 return ((void *)(va + offset)); 2567} 2568 2569void * 2570moea64_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2571{ 2572 2573 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT); 2574} 2575 2576void 2577moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2578{ 2579 vm_offset_t base, offset; 2580 2581 base = trunc_page(va); 2582 offset = va & PAGE_MASK; 2583 size = roundup2(offset + size, PAGE_SIZE); 2584 2585 kva_free(base, size); 2586} 2587 2588void 2589moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2590{ 2591 struct pvo_entry *pvo; 2592 vm_offset_t lim; 2593 vm_paddr_t pa; 2594 vm_size_t len; 2595 2596 PMAP_LOCK(pm); 2597 while (sz > 0) { 2598 lim = round_page(va); 2599 len = MIN(lim - va, sz); 2600 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 2601 if (pvo != NULL && !(pvo->pvo_pte.lpte.pte_lo & LPTE_I)) { 2602 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | 2603 (va & ADDR_POFF); 2604 moea64_syncicache(mmu, pm, va, pa, len); 2605 } 2606 va += len; 2607 sz -= len; 2608 } 2609 PMAP_UNLOCK(pm); 2610} 2611 2612vm_offset_t 2613moea64_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 2614 vm_size_t *sz) 2615{ 2616 if (md->md_vaddr == ~0UL) 2617 return (md->md_paddr + ofs); 2618 else 2619 return (md->md_vaddr + ofs); 2620} 2621 2622struct pmap_md * 2623moea64_scan_md(mmu_t mmu, struct pmap_md *prev) 2624{ 2625 static struct pmap_md md; 2626 struct pvo_entry *pvo; 2627 vm_offset_t va; 2628 2629 if (dumpsys_minidump) { 2630 md.md_paddr = ~0UL; /* Minidumps use virtual addresses. */ 2631 if (prev == NULL) { 2632 /* 1st: kernel .data and .bss. */ 2633 md.md_index = 1; 2634 md.md_vaddr = trunc_page((uintptr_t)_etext); 2635 md.md_size = round_page((uintptr_t)_end) - md.md_vaddr; 2636 return (&md); 2637 } 2638 switch (prev->md_index) { 2639 case 1: 2640 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2641 md.md_index = 2; 2642 md.md_vaddr = (vm_offset_t)msgbufp->msg_ptr; 2643 md.md_size = round_page(msgbufp->msg_size); 2644 break; 2645 case 2: 2646 /* 3rd: kernel VM. */ 2647 va = prev->md_vaddr + prev->md_size; 2648 /* Find start of next chunk (from va). */ 2649 while (va < virtual_end) { 2650 /* Don't dump the buffer cache. */ 2651 if (va >= kmi.buffer_sva && 2652 va < kmi.buffer_eva) { 2653 va = kmi.buffer_eva; 2654 continue; 2655 } 2656 pvo = moea64_pvo_find_va(kernel_pmap, 2657 va & ~ADDR_POFF); 2658 if (pvo != NULL && 2659 (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID)) 2660 break; 2661 va += PAGE_SIZE; 2662 } 2663 if (va < virtual_end) { 2664 md.md_vaddr = va; 2665 va += PAGE_SIZE; 2666 /* Find last page in chunk. */ 2667 while (va < virtual_end) { 2668 /* Don't run into the buffer cache. */ 2669 if (va == kmi.buffer_sva) 2670 break; 2671 pvo = moea64_pvo_find_va(kernel_pmap, 2672 va & ~ADDR_POFF); 2673 if (pvo == NULL || 2674 !(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID)) 2675 break; 2676 va += PAGE_SIZE; 2677 } 2678 md.md_size = va - md.md_vaddr; 2679 break; 2680 } 2681 md.md_index = 3; 2682 /* FALLTHROUGH */ 2683 default: 2684 return (NULL); 2685 } 2686 } else { /* minidumps */ 2687 if (prev == NULL) { 2688 /* first physical chunk. */ 2689 md.md_paddr = pregions[0].mr_start; 2690 md.md_size = pregions[0].mr_size; 2691 md.md_vaddr = ~0UL; 2692 md.md_index = 1; 2693 } else if (md.md_index < pregions_sz) { 2694 md.md_paddr = pregions[md.md_index].mr_start; 2695 md.md_size = pregions[md.md_index].mr_size; 2696 md.md_vaddr = ~0UL; 2697 md.md_index++; 2698 } else { 2699 /* There's no next physical chunk. */ 2700 return (NULL); 2701 } 2702 } 2703 2704 return (&md); 2705} 2706