13529Sse/************************************************************************** 23529Sse** 350477Speter** $FreeBSD$ 43529Sse** 53529Sse** Device driver for the NCR 53C810 PCI-SCSI-Controller. 63529Sse** 73529Sse** 386bsd / FreeBSD / NetBSD 83529Sse** 93529Sse**------------------------------------------------------------------------- 103529Sse** 113529Sse** Written for 386bsd and FreeBSD by 127232Sse** wolf@cologne.de Wolfgang Stanglmeier 133529Sse** se@mi.Uni-Koeln.de Stefan Esser 143529Sse** 153529Sse** Ported to NetBSD by 163529Sse** mycroft@gnu.ai.mit.edu 173529Sse** 183529Sse**------------------------------------------------------------------------- 19139834Sscottl*/ 20139825Simp/*- 213529Sse** Copyright (c) 1994 Wolfgang Stanglmeier. All rights reserved. 223529Sse** 233529Sse** Redistribution and use in source and binary forms, with or without 243529Sse** modification, are permitted provided that the following conditions 253529Sse** are met: 263529Sse** 1. Redistributions of source code must retain the above copyright 273529Sse** notice, this list of conditions and the following disclaimer. 283529Sse** 2. Redistributions in binary form must reproduce the above copyright 293529Sse** notice, this list of conditions and the following disclaimer in the 303529Sse** documentation and/or other materials provided with the distribution. 313529Sse** 3. The name of the author may not be used to endorse or promote products 323529Sse** derived from this software without specific prior written permission. 333529Sse** 343529Sse** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 353529Sse** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 363529Sse** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 373529Sse** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 383529Sse** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 393529Sse** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 403529Sse** DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 413529Sse** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 423529Sse** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 433529Sse** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 443529Sse** 453529Sse*************************************************************************** 463529Sse*/ 473529Sse 483529Sse#ifndef __NCR_REG_H__ 493529Sse#define __NCR_REG_H__ 503529Sse 513529Sse/*----------------------------------------------------------------- 523529Sse** 533529Sse** The ncr 53c810 register structure. 543529Sse** 553529Sse**----------------------------------------------------------------- 563529Sse*/ 573529Sse 583529Ssestruct ncr_reg { 593529Sse/*00*/ u_char nc_scntl0; /* full arb., ena parity, par->ATN */ 603529Sse 613529Sse/*01*/ u_char nc_scntl1; /* no reset */ 623529Sse #define ISCON 0x10 /* connected to scsi */ 633529Sse #define CRST 0x08 /* force reset */ 643529Sse 653529Sse/*02*/ u_char nc_scntl2; /* no disconnect expected */ 663529Sse #define SDU 0x80 /* cmd: disconnect will raise error */ 673529Sse #define CHM 0x40 /* sta: chained mode */ 683529Sse #define WSS 0x08 /* sta: wide scsi send [W]*/ 693529Sse #define WSR 0x01 /* sta: wide scsi received [W]*/ 703529Sse 713529Sse/*03*/ u_char nc_scntl3; /* cnf system clock dependent */ 723529Sse #define EWS 0x08 /* cmd: enable wide scsi [W]*/ 733529Sse 743529Sse/*04*/ u_char nc_scid; /* cnf host adapter scsi address */ 753529Sse #define RRE 0x40 /* r/w:e enable response to resel. */ 763529Sse #define SRE 0x20 /* r/w:e enable response to select */ 773529Sse 783529Sse/*05*/ u_char nc_sxfer; /* ### Sync speed and count */ 793529Sse 803529Sse/*06*/ u_char nc_sdid; /* ### Destination-ID */ 813529Sse 823529Sse/*07*/ u_char nc_gpreg; /* ??? IO-Pins */ 833529Sse 843529Sse/*08*/ u_char nc_sfbr; /* ### First byte in phase */ 853529Sse 863529Sse/*09*/ u_char nc_socl; 873529Sse #define CREQ 0x80 /* r/w: SCSI-REQ */ 883529Sse #define CACK 0x40 /* r/w: SCSI-ACK */ 893529Sse #define CBSY 0x20 /* r/w: SCSI-BSY */ 903529Sse #define CSEL 0x10 /* r/w: SCSI-SEL */ 913529Sse #define CATN 0x08 /* r/w: SCSI-ATN */ 923529Sse #define CMSG 0x04 /* r/w: SCSI-MSG */ 933529Sse #define CC_D 0x02 /* r/w: SCSI-C_D */ 943529Sse #define CI_O 0x01 /* r/w: SCSI-I_O */ 953529Sse 963529Sse/*0a*/ u_char nc_ssid; 973529Sse 983529Sse/*0b*/ u_char nc_sbcl; 997232Sse 1003529Sse/*0c*/ u_char nc_dstat; 1013529Sse #define DFE 0x80 /* sta: dma fifo empty */ 1023529Sse #define MDPE 0x40 /* int: master data parity error */ 1033529Sse #define BF 0x20 /* int: script: bus fault */ 1043529Sse #define ABRT 0x10 /* int: script: command aborted */ 1053529Sse #define SSI 0x08 /* int: script: single step */ 1063529Sse #define SIR 0x04 /* int: script: interrupt instruct. */ 1073529Sse #define IID 0x01 /* int: script: illegal instruct. */ 1083529Sse 1093529Sse/*0d*/ u_char nc_sstat0; 1103529Sse #define ILF 0x80 /* sta: data in SIDL register lsb */ 1113529Sse #define ORF 0x40 /* sta: data in SODR register lsb */ 1123529Sse #define OLF 0x20 /* sta: data in SODL register lsb */ 1133529Sse #define AIP 0x10 /* sta: arbitration in progress */ 1143529Sse #define LOA 0x08 /* sta: arbitration lost */ 1153529Sse #define WOA 0x04 /* sta: arbitration won */ 1163529Sse #define IRST 0x02 /* sta: scsi reset signal */ 1173529Sse #define SDP 0x01 /* sta: scsi parity signal */ 1183529Sse 1193529Sse/*0e*/ u_char nc_sstat1; 1203529Sse #define FF3210 0xf0 /* sta: bytes in the scsi fifo */ 1213529Sse 1223529Sse/*0f*/ u_char nc_sstat2; 1233529Sse #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/ 1243529Sse #define ORF1 0x40 /* sta: data in SODR register msb[W]*/ 1253529Sse #define OLF1 0x20 /* sta: data in SODL register msb[W]*/ 1266132Sdg #define LDSC 0x02 /* sta: disconnect & reconnect */ 1273529Sse 12828960Sse/*10*/ u_int32_t nc_dsa; /* --> Base page */ 1293529Sse 1303529Sse/*14*/ u_char nc_istat; /* --> Main Command and status */ 1313529Sse #define CABRT 0x80 /* cmd: abort current operation */ 1323529Sse #define SRST 0x40 /* mod: reset chip */ 1333529Sse #define SIGP 0x20 /* r/w: message from host to ncr */ 1343529Sse #define SEM 0x10 /* r/w: message between host + ncr */ 1353529Sse #define CON 0x08 /* sta: connected to scsi */ 1363529Sse #define INTF 0x04 /* sta: int on the fly (reset by wr)*/ 1373529Sse #define SIP 0x02 /* sta: scsi-interrupt */ 1383529Sse #define DIP 0x01 /* sta: host/script interrupt */ 1393529Sse 1403529Sse/*15*/ u_char nc_15_; 1413529Sse/*16*/ u_char nc_16_; 1423529Sse/*17*/ u_char nc_17_; 1433529Sse 1443529Sse/*18*/ u_char nc_ctest0; 1453529Sse/*19*/ u_char nc_ctest1; 1463529Sse 1473529Sse/*1a*/ u_char nc_ctest2; 1483529Sse #define CSIGP 0x40 1493529Sse 1503529Sse/*1b*/ u_char nc_ctest3; 15120435Sse #define FLF 0x08 /* cmd: flush dma fifo */ 15220435Sse #define CLF 0x04 /* cmd: clear dma fifo */ 15320435Sse #define FM 0x02 /* mod: fetch pin mode */ 15420435Sse #define WRIE 0x01 /* mod: write and invalidate enable */ 1553529Sse 15628960Sse/*1c*/ u_int32_t nc_temp; /* ### Temporary stack */ 1577232Sse 1583529Sse/*20*/ u_char nc_dfifo; 1593529Sse/*21*/ u_char nc_ctest4; 16020435Sse #define BDIS 0x80 /* mod: burst disable */ 16120435Sse #define MPEE 0x08 /* mod: master parity error enable */ 16220435Sse 1633529Sse/*22*/ u_char nc_ctest5; 16427684Sse #define DFS 0x20 /* mod: dma fifo size */ 1653529Sse/*23*/ u_char nc_ctest6; 1663529Sse 16728960Sse/*24*/ u_int32_t nc_dbc; /* ### Byte count and command */ 16828960Sse/*28*/ u_int32_t nc_dnad; /* ### Next command register */ 16928960Sse/*2c*/ u_int32_t nc_dsp; /* --> Script Pointer */ 17028960Sse/*30*/ u_int32_t nc_dsps; /* --> Script pointer save/opcode#2 */ 17128960Sse/*34*/ u_int32_t nc_scratcha; /* ??? Temporary register a */ 1723529Sse 1733529Sse/*38*/ u_char nc_dmode; 17420435Sse #define BL_2 0x80 /* mod: burst length shift value +2 */ 17520435Sse #define BL_1 0x40 /* mod: burst length shift value +1 */ 17620435Sse #define ERL 0x08 /* mod: enable read line */ 17720435Sse #define ERMP 0x04 /* mod: enable read multiple */ 17820435Sse #define BOF 0x02 /* mod: burst op code fetch */ 17920435Sse 1803529Sse/*39*/ u_char nc_dien; 1813529Sse/*3a*/ u_char nc_dwt; 1823529Sse 1833529Sse/*3b*/ u_char nc_dcntl; /* --> Script execution control */ 18420435Sse #define CLSE 0x80 /* mod: cache line size enable */ 18520435Sse #define PFF 0x40 /* cmd: pre-fetch flush */ 18620435Sse #define PFEN 0x20 /* mod: pre-fetch enable */ 1873529Sse #define SSM 0x10 /* mod: single step mode */ 18820435Sse #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */ 1893529Sse #define STD 0x04 /* cmd: start dma mode */ 19020435Sse #define IRQD 0x02 /* mod: irq disable */ 1913529Sse #define NOCOM 0x01 /* cmd: protect sfbr while reselect */ 1923529Sse 19328960Sse/*3c*/ u_int32_t nc_adder; 1943529Sse 1953529Sse/*40*/ u_short nc_sien; /* -->: interrupt enable */ 1963529Sse/*42*/ u_short nc_sist; /* <--: interrupt status */ 1973529Sse #define STO 0x0400/* sta: timeout (select) */ 1983529Sse #define GEN 0x0200/* sta: timeout (general) */ 1993529Sse #define HTH 0x0100/* sta: timeout (handshake) */ 2003529Sse #define MA 0x80 /* sta: phase mismatch */ 2013529Sse #define CMP 0x40 /* sta: arbitration complete */ 2023529Sse #define SEL 0x20 /* sta: selected by another device */ 2033529Sse #define RSL 0x10 /* sta: reselected by another device*/ 2043529Sse #define SGE 0x08 /* sta: gross error (over/underflow)*/ 2053529Sse #define UDC 0x04 /* sta: unexpected disconnect */ 2063529Sse #define RST 0x02 /* sta: scsi bus reset detected */ 2073529Sse #define PAR 0x01 /* sta: scsi parity error */ 2083529Sse 2093529Sse/*44*/ u_char nc_slpar; 2103529Sse/*45*/ u_char nc_swide; 2113529Sse/*46*/ u_char nc_macntl; 2123529Sse/*47*/ u_char nc_gpcntl; 2133529Sse/*48*/ u_char nc_stime0; /* cmd: timeout for select&handshake*/ 2143529Sse/*49*/ u_char nc_stime1; /* cmd: timeout user defined */ 2153529Sse/*4a*/ u_short nc_respid; /* sta: Reselect-IDs */ 2163529Sse 2173529Sse/*4c*/ u_char nc_stest0; 2183529Sse 2193529Sse/*4d*/ u_char nc_stest1; 22018875Sse #define DBLEN 0x08 /* clock doubler running */ 22118875Sse #define DBLSEL 0x04 /* clock doubler selected */ 2223529Sse 2233529Sse/*4e*/ u_char nc_stest2; 2243529Sse #define ROF 0x40 /* reset scsi offset (after gross error!) */ 2253529Sse #define EXT 0x02 /* extended filtering */ 2263529Sse 2273529Sse/*4f*/ u_char nc_stest3; 2283529Sse #define TE 0x80 /* c: tolerAnt enable */ 22927684Sse #define HSC 0x20 /* c: Halt SCSI Clock */ 2303529Sse #define CSF 0x02 /* c: clear scsi fifo */ 2317232Sse 2323529Sse/*50*/ u_short nc_sidl; /* Lowlevel: latched from scsi data */ 23327684Sse/*52*/ u_char nc_stest4; 23427684Sse #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */ 23527684Sse #define SMODE_HVD 0x40 /* High Voltage Differential */ 23627684Sse #define SMODE_SE 0x80 /* Single Ended */ 23727684Sse #define SMODE_LVD 0xc0 /* Low Voltage Differential */ 23827684Sse #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */ 23927684Sse 24027684Sse/*53*/ u_char nc_53_; 2413529Sse/*54*/ u_short nc_sodl; /* Lowlevel: data out to scsi data */ 2423529Sse/*56*/ u_short nc_56_; 2433529Sse/*58*/ u_short nc_sbdl; /* Lowlevel: data from scsi data */ 2443529Sse/*5a*/ u_short nc_5a_; 2453529Sse/*5c*/ u_char nc_scr0; /* Working register B */ 2463529Sse/*5d*/ u_char nc_scr1; /* */ 2473529Sse/*5e*/ u_char nc_scr2; /* */ 2483529Sse/*5f*/ u_char nc_scr3; /* */ 2493529Sse/*60*/ 2503529Sse}; 2517232Sse 2523529Sse/*----------------------------------------------------------- 2533529Sse** 2543529Sse** Utility macros for the script. 2553529Sse** 2563529Sse**----------------------------------------------------------- 2573529Sse*/ 2583529Sse 2593529Sse#define REGJ(p,r) (offsetof(struct ncr_reg, p ## r)) 2603529Sse#define REG(r) REGJ (nc_, r) 2613529Sse 2623529Sse#ifndef TARGET_MODE 2633529Sse#define TARGET_MODE 0 2643529Sse#endif 2653529Sse 26628960Ssetypedef u_int32_t ncrcmd; 2673529Sse 2683529Sse/*----------------------------------------------------------- 2693529Sse** 2703529Sse** SCSI phases 2713529Sse** 2723529Sse**----------------------------------------------------------- 2733529Sse*/ 2743529Sse 2753529Sse#define SCR_DATA_OUT 0x00000000 2763529Sse#define SCR_DATA_IN 0x01000000 2773529Sse#define SCR_COMMAND 0x02000000 2783529Sse#define SCR_STATUS 0x03000000 2793529Sse#define SCR_ILG_OUT 0x04000000 2803529Sse#define SCR_ILG_IN 0x05000000 2813529Sse#define SCR_MSG_OUT 0x06000000 2823529Sse#define SCR_MSG_IN 0x07000000 2833529Sse 2843529Sse/*----------------------------------------------------------- 2853529Sse** 2863529Sse** Data transfer via SCSI. 2873529Sse** 2883529Sse**----------------------------------------------------------- 2893529Sse** 2903529Sse** MOVE_ABS (LEN) 2913529Sse** <<start address>> 2923529Sse** 2933529Sse** MOVE_IND (LEN) 2943529Sse** <<dnad_offset>> 2953529Sse** 2963529Sse** MOVE_TBL 2973529Sse** <<dnad_offset>> 2983529Sse** 2993529Sse**----------------------------------------------------------- 3003529Sse*/ 3013529Sse 3023529Sse#define SCR_MOVE_ABS(l) ((0x08000000 ^ (TARGET_MODE << 1ul)) | (l)) 3033529Sse#define SCR_MOVE_IND(l) ((0x28000000 ^ (TARGET_MODE << 1ul)) | (l)) 3043529Sse#define SCR_MOVE_TBL (0x18000000 ^ (TARGET_MODE << 1ul)) 3053529Sse 3063529Ssestruct scr_tblmove { 30728960Sse u_int32_t size; 30828960Sse u_int32_t addr; 3093529Sse}; 3107232Sse 3113529Sse/*----------------------------------------------------------- 3123529Sse** 3133529Sse** Selection 3143529Sse** 3153529Sse**----------------------------------------------------------- 3163529Sse** 3173529Sse** SEL_ABS | SCR_ID (0..7) [ | REL_JMP] 3183529Sse** <<alternate_address>> 3193529Sse** 3203529Sse** SEL_TBL | << dnad_offset>> [ | REL_JMP] 3213529Sse** <<alternate_address>> 3223529Sse** 3233529Sse**----------------------------------------------------------- 3243529Sse*/ 3253529Sse 3263529Sse#define SCR_SEL_ABS 0x40000000 3273529Sse#define SCR_SEL_ABS_ATN 0x41000000 3283529Sse#define SCR_SEL_TBL 0x42000000 3293529Sse#define SCR_SEL_TBL_ATN 0x43000000 3303529Sse 3313529Ssestruct scr_tblsel { 3323529Sse u_char sel_0; 3333529Sse u_char sel_sxfer; 3343529Sse u_char sel_id; 3353529Sse u_char sel_scntl3; 3363529Sse}; 3373529Sse 3383529Sse#define SCR_JMP_REL 0x04000000 33928960Sse#define SCR_ID(id) (((u_int32_t)(id)) << 16) 3403529Sse 3413529Sse/*----------------------------------------------------------- 3423529Sse** 3433529Sse** Waiting for Disconnect or Reselect 3443529Sse** 3453529Sse**----------------------------------------------------------- 3463529Sse** 3473529Sse** WAIT_DISC 3483529Sse** dummy: <<alternate_address>> 3493529Sse** 3503529Sse** WAIT_RESEL 3513529Sse** <<alternate_address>> 3523529Sse** 3533529Sse**----------------------------------------------------------- 3543529Sse*/ 3553529Sse 3563529Sse#define SCR_WAIT_DISC 0x48000000 3573529Sse#define SCR_WAIT_RESEL 0x50000000 3587232Sse 3593529Sse/*----------------------------------------------------------- 3603529Sse** 3613529Sse** Bit Set / Reset 3623529Sse** 3633529Sse**----------------------------------------------------------- 3643529Sse** 3653529Sse** SET (flags {|.. }) 3663529Sse** 3673529Sse** CLR (flags {|.. }) 3683529Sse** 3693529Sse**----------------------------------------------------------- 3703529Sse*/ 3713529Sse 3723529Sse#define SCR_SET(f) (0x58000000 | (f)) 3733529Sse#define SCR_CLR(f) (0x60000000 | (f)) 3743529Sse 3753529Sse#define SCR_CARRY 0x00000400 3763529Sse#define SCR_TRG 0x00000200 3773529Sse#define SCR_ACK 0x00000040 3783529Sse#define SCR_ATN 0x00000008 3793529Sse 3803529Sse 3813529Sse/*----------------------------------------------------------- 3823529Sse** 3833529Sse** Memory to memory move 3843529Sse** 3853529Sse**----------------------------------------------------------- 3863529Sse** 3873529Sse** COPY (bytecount) 3883529Sse** << source_address >> 3893529Sse** << destination_address >> 3903529Sse** 39127684Sse** SCR_COPY sets the NO FLUSH option by default. 39227684Sse** SCR_COPY_F does not set this option. 39327684Sse** 39427684Sse** For chips which do not support this option, 39527684Sse** ncr_copy_and_bind() will remove this bit. 3963529Sse**----------------------------------------------------------- 3973529Sse*/ 3983529Sse 39927684Sse#define SCR_NO_FLUSH 0x01000000 4007232Sse 40127684Sse#define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n)) 40227684Sse#define SCR_COPY_F(n) (0xc0000000 | (n)) 40327684Sse 40427684Sse 4053529Sse/*----------------------------------------------------------- 4063529Sse** 4073529Sse** Register move and binary operations 4083529Sse** 4093529Sse**----------------------------------------------------------- 4103529Sse** 4113529Sse** SFBR_REG (reg, op, data) reg = SFBR op data 4123529Sse** << 0 >> 4133529Sse** 4143529Sse** REG_SFBR (reg, op, data) SFBR = reg op data 4153529Sse** << 0 >> 4163529Sse** 4173529Sse** REG_REG (reg, op, data) reg = reg op data 4183529Sse** << 0 >> 4193529Sse** 4203529Sse**----------------------------------------------------------- 4213529Sse*/ 4223529Sse 4233529Sse#define SCR_REG_OFS(ofs) ((ofs) << 16ul) 4243529Sse 4253529Sse#define SCR_SFBR_REG(reg,op,data) \ 4263529Sse (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | ((data)<<8ul)) 4273529Sse 4283529Sse#define SCR_REG_SFBR(reg,op,data) \ 4293529Sse (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | ((data)<<8ul)) 4303529Sse 4313529Sse#define SCR_REG_REG(reg,op,data) \ 4323529Sse (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | ((data)<<8ul)) 4333529Sse 4343529Sse 4353529Sse#define SCR_LOAD 0x00000000 4363529Sse#define SCR_SHL 0x01000000 4373529Sse#define SCR_OR 0x02000000 4383529Sse#define SCR_XOR 0x03000000 4393529Sse#define SCR_AND 0x04000000 4403529Sse#define SCR_SHR 0x05000000 4413529Sse#define SCR_ADD 0x06000000 4423529Sse#define SCR_ADDC 0x07000000 4437232Sse 4443529Sse/*----------------------------------------------------------- 4453529Sse** 4463529Sse** FROM_REG (reg) reg = SFBR 4473529Sse** << 0 >> 4483529Sse** 4493529Sse** TO_REG (reg) SFBR = reg 4503529Sse** << 0 >> 4513529Sse** 4523529Sse** LOAD_REG (reg, data) reg = <data> 4533529Sse** << 0 >> 4543529Sse** 4553529Sse** LOAD_SFBR(data) SFBR = <data> 4563529Sse** << 0 >> 4573529Sse** 4583529Sse**----------------------------------------------------------- 4593529Sse*/ 4603529Sse 4613529Sse#define SCR_FROM_REG(reg) \ 4623529Sse SCR_REG_SFBR(reg,SCR_OR,0) 4633529Sse 4643529Sse#define SCR_TO_REG(reg) \ 4653529Sse SCR_SFBR_REG(reg,SCR_OR,0) 4663529Sse 4673529Sse#define SCR_LOAD_REG(reg,data) \ 4683529Sse SCR_REG_REG(reg,SCR_LOAD,data) 4693529Sse 4703529Sse#define SCR_LOAD_SFBR(data) \ 4713529Sse (SCR_REG_SFBR (gpreg, SCR_LOAD, data)) 4727232Sse 4733529Sse/*----------------------------------------------------------- 4743529Sse** 4753529Sse** Waiting for Disconnect or Reselect 4763529Sse** 4773529Sse**----------------------------------------------------------- 4783529Sse** 4793529Sse** JUMP [ | IFTRUE/IFFALSE ( ... ) ] 4803529Sse** <<address>> 4813529Sse** 4823529Sse** JUMPR [ | IFTRUE/IFFALSE ( ... ) ] 4833529Sse** <<distance>> 4843529Sse** 4853529Sse** CALL [ | IFTRUE/IFFALSE ( ... ) ] 4863529Sse** <<address>> 4873529Sse** 4883529Sse** CALLR [ | IFTRUE/IFFALSE ( ... ) ] 4893529Sse** <<distance>> 4903529Sse** 4913529Sse** RETURN [ | IFTRUE/IFFALSE ( ... ) ] 4923529Sse** <<dummy>> 4933529Sse** 4943529Sse** INT [ | IFTRUE/IFFALSE ( ... ) ] 4953529Sse** <<ident>> 4963529Sse** 4973529Sse** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ] 4983529Sse** <<ident>> 4993529Sse** 5003529Sse** Conditions: 5013529Sse** WHEN (phase) 5023529Sse** IF (phase) 5033529Sse** CARRY 5043529Sse** DATA (data, mask) 5053529Sse** 5063529Sse**----------------------------------------------------------- 5073529Sse*/ 5083529Sse 50927684Sse#define SCR_NO_OP 0x80000000 5103529Sse#define SCR_JUMP 0x80080000 5113529Sse#define SCR_JUMPR 0x80880000 5123529Sse#define SCR_CALL 0x88080000 5133529Sse#define SCR_CALLR 0x88880000 5143529Sse#define SCR_RETURN 0x90080000 5153529Sse#define SCR_INT 0x98080000 5163529Sse#define SCR_INT_FLY 0x98180000 5173529Sse 5183529Sse#define IFFALSE(arg) (0x00080000 | (arg)) 5193529Sse#define IFTRUE(arg) (0x00000000 | (arg)) 5203529Sse 5213529Sse#define WHEN(phase) (0x00030000 | (phase)) 5223529Sse#define IF(phase) (0x00020000 | (phase)) 5233529Sse 5243529Sse#define DATA(D) (0x00040000 | ((D) & 0xff)) 5253529Sse#define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff)) 5263529Sse 5273529Sse#define CARRYSET (0x00200000) 5287232Sse 5293529Sse/*----------------------------------------------------------- 5303529Sse** 5313529Sse** SCSI constants. 5323529Sse** 5333529Sse**----------------------------------------------------------- 5343529Sse*/ 5353529Sse 5363529Sse/* 5373529Sse** Messages 5383529Sse*/ 5393529Sse#define M_X_MODIFY_DP (0x00) 5403529Sse 5413529Sse/* 5423529Sse** Status 5433529Sse*/ 54439247Sgibbs#define SCSI_STATUS_ILLEGAL (0xff) 54539247Sgibbs#define SCSI_STATUS_SENSE (0x80) 5463529Sse 54727684Sse/* 54827684Sse** Bits defining chip features. 54927684Sse** For now only some of them are used, since we explicitely 55027684Sse** deal with PCI device id and revision id. 55127684Sse*/ 55227684Sse#define FE_LED0 (1<<0) 55327684Sse#define FE_WIDE (1<<1) 55427684Sse#define FE_ULTRA (1<<2) 55527684Sse#define FE_ULTRA2 (1<<3) 55627684Sse#define FE_DBLR (1<<4) 55727684Sse#define FE_QUAD (1<<5) 55827684Sse#define FE_ERL (1<<6) 55927684Sse#define FE_CLSE (1<<7) 56027684Sse#define FE_WRIE (1<<8) 56127684Sse#define FE_ERMP (1<<9) 56227684Sse#define FE_BOF (1<<10) 56327684Sse#define FE_DFS (1<<11) 56427684Sse#define FE_PFEN (1<<12) 56527684Sse#define FE_LDSTR (1<<13) 56627684Sse#define FE_RAM (1<<14) 56727684Sse#define FE_CLK80 (1<<15) 56827684Sse#define FE_DIFF (1<<16) 56927684Sse#define FE_BIOS (1<<17) 57028645Sse#define FE_CACHE_SET (FE_ERL|FE_CLSE|FE_WRIE|FE_ERMP) 57127684Sse#define FE_SCSI_SET (FE_WIDE|FE_ULTRA|FE_ULTRA2|FE_DBLR|FE_QUAD|F_CLK80) 57227684Sse#define FE_SPECIAL_SET (FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM) 57327684Sse 5743529Sse#endif /*__NCR_REG_H__*/ 575