pci.h revision 271127
1232809Sjmallett/*- 2232809Sjmallett * Copyright (c) 2010 Isilon Systems, Inc. 3232809Sjmallett * Copyright (c) 2010 iX Systems, Inc. 4232809Sjmallett * Copyright (c) 2010 Panasas, Inc. 5232809Sjmallett * Copyright (c) 2013, 2014 Mellanox Technologies, Ltd. 6232809Sjmallett * All rights reserved. 7232809Sjmallett * 8232809Sjmallett * Redistribution and use in source and binary forms, with or without 9232809Sjmallett * modification, are permitted provided that the following conditions 10232809Sjmallett * are met: 11232809Sjmallett * 1. Redistributions of source code must retain the above copyright 12232809Sjmallett * notice unmodified, this list of conditions, and the following 13232809Sjmallett * disclaimer. 14232809Sjmallett * 2. Redistributions in binary form must reproduce the above copyright 15232809Sjmallett * notice, this list of conditions and the following disclaimer in the 16232809Sjmallett * documentation and/or other materials provided with the distribution. 17232809Sjmallett * 18232809Sjmallett * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19232809Sjmallett * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20232809Sjmallett * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21232809Sjmallett * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22232809Sjmallett * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23232809Sjmallett * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24232809Sjmallett * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25232809Sjmallett * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26232809Sjmallett * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27232809Sjmallett * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28232809Sjmallett */ 29232809Sjmallett 30232809Sjmallett#ifndef _LINUX_PCI_H_ 31232809Sjmallett#define _LINUX_PCI_H_ 32232809Sjmallett 33232809Sjmallett#define CONFIG_PCI_MSI 34232809Sjmallett 35232809Sjmallett#include <linux/types.h> 36232809Sjmallett 37232809Sjmallett#include <sys/param.h> 38232809Sjmallett#include <sys/bus.h> 39232809Sjmallett#include <sys/pciio.h> 40232809Sjmallett#include <sys/rman.h> 41232809Sjmallett#include <dev/pci/pcivar.h> 42232809Sjmallett#include <dev/pci/pcireg.h> 43232809Sjmallett#include <dev/pci/pci_private.h> 44232809Sjmallett 45232809Sjmallett#include <machine/resource.h> 46232809Sjmallett 47232809Sjmallett#include <linux/list.h> 48232809Sjmallett#include <linux/dmapool.h> 49232809Sjmallett#include <linux/dma-mapping.h> 50232809Sjmallett#include <linux/compiler.h> 51232809Sjmallett#include <linux/errno.h> 52232809Sjmallett#include <asm/atomic.h> 53232809Sjmallett#include <linux/device.h> 54232809Sjmallett 55232809Sjmallettstruct pci_device_id { 56232809Sjmallett uint32_t vendor; 57232809Sjmallett uint32_t device; 58232809Sjmallett uint32_t subvendor; 59232809Sjmallett uint32_t subdevice; 60232809Sjmallett uint32_t class_mask; 61232809Sjmallett uintptr_t driver_data; 62232809Sjmallett}; 63232809Sjmallett 64232809Sjmallett#define MODULE_DEVICE_TABLE(bus, table) 65232809Sjmallett#define PCI_ANY_ID (-1) 66232809Sjmallett#define PCI_VENDOR_ID_MELLANOX 0x15b3 67232809Sjmallett#define PCI_VENDOR_ID_TOPSPIN 0x1867 68232809Sjmallett#define PCI_DEVICE_ID_MELLANOX_TAVOR 0x5a44 69232809Sjmallett#define PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE 0x5a46 70232809Sjmallett#define PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT 0x6278 71232809Sjmallett#define PCI_DEVICE_ID_MELLANOX_ARBEL 0x6282 72232809Sjmallett#define PCI_DEVICE_ID_MELLANOX_SINAI_OLD 0x5e8c 73232809Sjmallett#define PCI_DEVICE_ID_MELLANOX_SINAI 0x6274 74232809Sjmallett 75232809Sjmallett#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 76232809Sjmallett#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 77232809Sjmallett#define PCI_FUNC(devfn) ((devfn) & 0x07) 78232809Sjmallett 79232809Sjmallett#define PCI_VDEVICE(_vendor, _device) \ 80232809Sjmallett .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 81232809Sjmallett .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 82232809Sjmallett#define PCI_DEVICE(_vendor, _device) \ 83232809Sjmallett .vendor = (_vendor), .device = (_device), \ 84232809Sjmallett .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 85232809Sjmallett 86232809Sjmallett#define to_pci_dev(n) container_of(n, struct pci_dev, dev) 87232809Sjmallett 88232809Sjmallett#define PCI_VENDOR_ID PCIR_DEVVENDOR 89232809Sjmallett#define PCI_COMMAND PCIR_COMMAND 90232809Sjmallett#define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 91232809Sjmallett#define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 92232809Sjmallett#define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 93232809Sjmallett#define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 94232809Sjmallett#define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 95232809Sjmallett#define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 96232809Sjmallett#define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 97232809Sjmallett#define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 98232809Sjmallett#define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 99232809Sjmallett#define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 100232809Sjmallett#define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 101232809Sjmallett#define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 102232809Sjmallett#define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 103232809Sjmallett#define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 104232809Sjmallett#define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 105232809Sjmallett#define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 106232809Sjmallett#define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 107232809Sjmallett#define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 108232809Sjmallett#define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 109232809Sjmallett#define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 110232809Sjmallett#define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 111232809Sjmallett#define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 112232809Sjmallett#define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 113232809Sjmallett#define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 114232809Sjmallett#define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 115232809Sjmallett#define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 116232809Sjmallett 117232809Sjmallett 118232809Sjmallett#define IORESOURCE_MEM SYS_RES_MEMORY 119232809Sjmallett#define IORESOURCE_IO SYS_RES_IOPORT 120232809Sjmallett#define IORESOURCE_IRQ SYS_RES_IRQ 121232809Sjmallett 122232809Sjmallettstruct pci_dev; 123232809Sjmallett 124232809Sjmallett 125232809Sjmallettstruct pci_driver { 126232809Sjmallett struct list_head links; 127232809Sjmallett char *name; 128232809Sjmallett const struct pci_device_id *id_table; 129232809Sjmallett int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 130232809Sjmallett void (*remove)(struct pci_dev *dev); 131232809Sjmallett int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 132232809Sjmallett int (*resume) (struct pci_dev *dev); /* Device woken up */ 133232809Sjmallett driver_t driver; 134232809Sjmallett devclass_t bsdclass; 135232809Sjmallett const struct pci_error_handlers *err_handler; 136232809Sjmallett}; 137232809Sjmallett 138232809Sjmallettextern struct list_head pci_drivers; 139232809Sjmallettextern struct list_head pci_devices; 140232809Sjmallettextern spinlock_t pci_lock; 141232809Sjmallett 142232809Sjmallett#define __devexit_p(x) x 143232809Sjmallett 144232809Sjmallettstruct pci_dev { 145232809Sjmallett struct device dev; 146232809Sjmallett struct list_head links; 147232809Sjmallett struct pci_driver *pdrv; 148232809Sjmallett uint64_t dma_mask; 149232809Sjmallett uint16_t device; 150232809Sjmallett uint16_t vendor; 151232809Sjmallett unsigned int irq; 152232809Sjmallett unsigned int devfn; 153232809Sjmallett u8 revision; 154232809Sjmallett struct pci_devinfo *bus; /* bus this device is on, equivalent to linux struct pci_bus */ 155232809Sjmallett}; 156232809Sjmallett 157232809Sjmallettstatic inline struct resource_list_entry * 158232809Sjmallett_pci_get_rle(struct pci_dev *pdev, int type, int rid) 159232809Sjmallett{ 160232809Sjmallett struct pci_devinfo *dinfo; 161232809Sjmallett struct resource_list *rl; 162232809Sjmallett 163232809Sjmallett dinfo = device_get_ivars(pdev->dev.bsddev); 164232809Sjmallett rl = &dinfo->resources; 165232809Sjmallett return resource_list_find(rl, type, rid); 166232809Sjmallett} 167232809Sjmallett 168232809Sjmallettstatic inline struct resource_list_entry * 169232809Sjmallett_pci_get_bar(struct pci_dev *pdev, int bar) 170232809Sjmallett{ 171232809Sjmallett struct resource_list_entry *rle; 172232809Sjmallett 173232809Sjmallett bar = PCIR_BAR(bar); 174232809Sjmallett if ((rle = _pci_get_rle(pdev, SYS_RES_MEMORY, bar)) == NULL) 175232809Sjmallett rle = _pci_get_rle(pdev, SYS_RES_IOPORT, bar); 176232809Sjmallett return (rle); 177232809Sjmallett} 178232809Sjmallett 179232809Sjmallettstatic inline struct device * 180232809Sjmallett_pci_find_irq_dev(unsigned int irq) 181232809Sjmallett{ 182232809Sjmallett struct pci_dev *pdev; 183232809Sjmallett 184232809Sjmallett spin_lock(&pci_lock); 185232809Sjmallett list_for_each_entry(pdev, &pci_devices, links) { 186232809Sjmallett if (irq == pdev->dev.irq) 187232809Sjmallett break; 188232809Sjmallett if (irq >= pdev->dev.msix && irq < pdev->dev.msix_max) 189232809Sjmallett break; 190232809Sjmallett } 191232809Sjmallett spin_unlock(&pci_lock); 192232809Sjmallett if (pdev) 193232809Sjmallett return &pdev->dev; 194232809Sjmallett return (NULL); 195232809Sjmallett} 196232809Sjmallett 197232809Sjmallettstatic inline unsigned long 198232809Sjmallettpci_resource_start(struct pci_dev *pdev, int bar) 199232809Sjmallett{ 200232809Sjmallett struct resource_list_entry *rle; 201232809Sjmallett 202232809Sjmallett if ((rle = _pci_get_bar(pdev, bar)) == NULL) 203232809Sjmallett return (0); 204232809Sjmallett return rle->start; 205232809Sjmallett} 206232809Sjmallett 207232809Sjmallettstatic inline unsigned long 208232809Sjmallettpci_resource_len(struct pci_dev *pdev, int bar) 209232809Sjmallett{ 210232809Sjmallett struct resource_list_entry *rle; 211232809Sjmallett 212232809Sjmallett if ((rle = _pci_get_bar(pdev, bar)) == NULL) 213232809Sjmallett return (0); 214232809Sjmallett return rle->count; 215232809Sjmallett} 216232809Sjmallett 217232809Sjmallett/* 218232809Sjmallett * All drivers just seem to want to inspect the type not flags. 219232809Sjmallett */ 220232809Sjmallettstatic inline int 221232809Sjmallettpci_resource_flags(struct pci_dev *pdev, int bar) 222232809Sjmallett{ 223232809Sjmallett struct resource_list_entry *rle; 224232809Sjmallett 225232809Sjmallett if ((rle = _pci_get_bar(pdev, bar)) == NULL) 226232809Sjmallett return (0); 227232809Sjmallett return rle->type; 228232809Sjmallett} 229232809Sjmallett 230232809Sjmallettstatic inline const char * 231232809Sjmallettpci_name(struct pci_dev *d) 232232809Sjmallett{ 233232809Sjmallett 234232809Sjmallett return device_get_desc(d->dev.bsddev); 235232809Sjmallett} 236232809Sjmallett 237232809Sjmallettstatic inline void * 238232809Sjmallettpci_get_drvdata(struct pci_dev *pdev) 239232809Sjmallett{ 240232809Sjmallett 241232809Sjmallett return dev_get_drvdata(&pdev->dev); 242232809Sjmallett} 243232809Sjmallett 244232809Sjmallettstatic inline void 245232809Sjmallettpci_set_drvdata(struct pci_dev *pdev, void *data) 246232809Sjmallett{ 247232809Sjmallett 248232809Sjmallett dev_set_drvdata(&pdev->dev, data); 249232809Sjmallett} 250232809Sjmallett 251232809Sjmallettstatic inline int 252232809Sjmallettpci_enable_device(struct pci_dev *pdev) 253232809Sjmallett{ 254232809Sjmallett 255232809Sjmallett pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 256232809Sjmallett pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 257232809Sjmallett return (0); 258232809Sjmallett} 259232809Sjmallett 260232809Sjmallettstatic inline void 261232809Sjmallettpci_disable_device(struct pci_dev *pdev) 262232809Sjmallett{ 263232809Sjmallett} 264232809Sjmallett 265232809Sjmallettstatic inline int 266232809Sjmallettpci_set_master(struct pci_dev *pdev) 267232809Sjmallett{ 268232809Sjmallett 269232809Sjmallett pci_enable_busmaster(pdev->dev.bsddev); 270232809Sjmallett return (0); 271232809Sjmallett} 272232809Sjmallett 273232809Sjmallettstatic inline int 274232809Sjmallettpci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 275232809Sjmallett{ 276232809Sjmallett int rid; 277232809Sjmallett int type; 278232809Sjmallett 279232809Sjmallett type = pci_resource_flags(pdev, bar); 280232809Sjmallett if (type == 0) 281232809Sjmallett return (-ENODEV); 282232809Sjmallett rid = PCIR_BAR(bar); 283232809Sjmallett if (bus_alloc_resource_any(pdev->dev.bsddev, type, &rid, 284232809Sjmallett RF_ACTIVE) == NULL) 285232809Sjmallett return (-EINVAL); 286232809Sjmallett return (0); 287232809Sjmallett} 288232809Sjmallett 289232809Sjmallettstatic inline void 290232809Sjmallettpci_release_region(struct pci_dev *pdev, int bar) 291232809Sjmallett{ 292232809Sjmallett struct resource_list_entry *rle; 293232809Sjmallett 294232809Sjmallett if ((rle = _pci_get_bar(pdev, bar)) == NULL) 295232809Sjmallett return; 296232809Sjmallett bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 297232809Sjmallett} 298232809Sjmallett 299232809Sjmallettstatic inline void 300232809Sjmallettpci_release_regions(struct pci_dev *pdev) 301232809Sjmallett{ 302232809Sjmallett int i; 303232809Sjmallett 304232809Sjmallett for (i = 0; i <= PCIR_MAX_BAR_0; i++) 305232809Sjmallett pci_release_region(pdev, i); 306232809Sjmallett} 307232809Sjmallett 308static inline int 309pci_request_regions(struct pci_dev *pdev, const char *res_name) 310{ 311 int error; 312 int i; 313 314 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 315 error = pci_request_region(pdev, i, res_name); 316 if (error && error != -ENODEV) { 317 pci_release_regions(pdev); 318 return (error); 319 } 320 } 321 return (0); 322} 323 324static inline void 325pci_disable_msix(struct pci_dev *pdev) 326{ 327 328 pci_release_msi(pdev->dev.bsddev); 329} 330 331#define PCI_CAP_ID_EXP PCIY_EXPRESS 332#define PCI_CAP_ID_PCIX PCIY_PCIX 333 334 335static inline int 336pci_find_capability(struct pci_dev *pdev, int capid) 337{ 338 int reg; 339 340 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 341 return (0); 342 return (reg); 343} 344 345 346 347 348/** 349 * pci_pcie_cap - get the saved PCIe capability offset 350 * @dev: PCI device 351 * 352 * PCIe capability offset is calculated at PCI device initialization 353 * time and saved in the data structure. This function returns saved 354 * PCIe capability offset. Using this instead of pci_find_capability() 355 * reduces unnecessary search in the PCI configuration space. If you 356 * need to calculate PCIe capability offset from raw device for some 357 * reasons, please use pci_find_capability() instead. 358 */ 359static inline int pci_pcie_cap(struct pci_dev *dev) 360{ 361 return pci_find_capability(dev, PCI_CAP_ID_EXP); 362} 363 364 365static inline int 366pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val) 367{ 368 369 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 370 return (0); 371} 372 373static inline int 374pci_read_config_word(struct pci_dev *pdev, int where, u16 *val) 375{ 376 377 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 378 return (0); 379} 380 381static inline int 382pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val) 383{ 384 385 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 386 return (0); 387} 388 389static inline int 390pci_write_config_byte(struct pci_dev *pdev, int where, u8 val) 391{ 392 393 pci_write_config(pdev->dev.bsddev, where, val, 1); 394 return (0); 395} 396 397static inline int 398pci_write_config_word(struct pci_dev *pdev, int where, u16 val) 399{ 400 401 pci_write_config(pdev->dev.bsddev, where, val, 2); 402 return (0); 403} 404 405static inline int 406pci_write_config_dword(struct pci_dev *pdev, int where, u32 val) 407{ 408 409 pci_write_config(pdev->dev.bsddev, where, val, 4); 410 return (0); 411} 412 413static struct pci_driver * 414linux_pci_find(device_t dev, const struct pci_device_id **idp) 415{ 416 const struct pci_device_id *id; 417 struct pci_driver *pdrv; 418 uint16_t vendor; 419 uint16_t device; 420 421 vendor = pci_get_vendor(dev); 422 device = pci_get_device(dev); 423 424 spin_lock(&pci_lock); 425 list_for_each_entry(pdrv, &pci_drivers, links) { 426 for (id = pdrv->id_table; id->vendor != 0; id++) { 427 if (vendor == id->vendor && device == id->device) { 428 *idp = id; 429 spin_unlock(&pci_lock); 430 return (pdrv); 431 } 432 } 433 } 434 spin_unlock(&pci_lock); 435 return (NULL); 436} 437 438static inline int 439linux_pci_probe(device_t dev) 440{ 441 const struct pci_device_id *id; 442 struct pci_driver *pdrv; 443 444 if ((pdrv = linux_pci_find(dev, &id)) == NULL) 445 return (ENXIO); 446 if (device_get_driver(dev) != &pdrv->driver) 447 return (ENXIO); 448 device_set_desc(dev, pdrv->name); 449 return (0); 450} 451 452static inline int 453linux_pci_attach(device_t dev) 454{ 455 struct resource_list_entry *rle; 456 struct pci_dev *pdev; 457 struct pci_driver *pdrv; 458 const struct pci_device_id *id; 459 int error; 460 461 pdrv = linux_pci_find(dev, &id); 462 pdev = device_get_softc(dev); 463 pdev->dev.parent = &linux_rootdev; 464 pdev->dev.bsddev = dev; 465 INIT_LIST_HEAD(&pdev->dev.irqents); 466 pdev->device = id->device; 467 pdev->vendor = id->vendor; 468 pdev->dev.dma_mask = &pdev->dma_mask; 469 pdev->pdrv = pdrv; 470 kobject_init(&pdev->dev.kobj, &dev_ktype); 471 kobject_set_name(&pdev->dev.kobj, device_get_nameunit(dev)); 472 kobject_add(&pdev->dev.kobj, &linux_rootdev.kobj, 473 kobject_name(&pdev->dev.kobj)); 474 rle = _pci_get_rle(pdev, SYS_RES_IRQ, 0); 475 if (rle) 476 pdev->dev.irq = rle->start; 477 else 478 pdev->dev.irq = 0; 479 pdev->irq = pdev->dev.irq; 480 mtx_unlock(&Giant); 481 spin_lock(&pci_lock); 482 list_add(&pdev->links, &pci_devices); 483 spin_unlock(&pci_lock); 484 error = pdrv->probe(pdev, id); 485 mtx_lock(&Giant); 486 if (error) { 487 spin_lock(&pci_lock); 488 list_del(&pdev->links); 489 spin_unlock(&pci_lock); 490 put_device(&pdev->dev); 491 return (-error); 492 } 493 return (0); 494} 495 496static inline int 497linux_pci_detach(device_t dev) 498{ 499 struct pci_dev *pdev; 500 501 pdev = device_get_softc(dev); 502 mtx_unlock(&Giant); 503 pdev->pdrv->remove(pdev); 504 mtx_lock(&Giant); 505 spin_lock(&pci_lock); 506 list_del(&pdev->links); 507 spin_unlock(&pci_lock); 508 put_device(&pdev->dev); 509 510 return (0); 511} 512 513static device_method_t pci_methods[] = { 514 DEVMETHOD(device_probe, linux_pci_probe), 515 DEVMETHOD(device_attach, linux_pci_attach), 516 DEVMETHOD(device_detach, linux_pci_detach), 517 {0, 0} 518}; 519 520static inline int 521pci_register_driver(struct pci_driver *pdrv) 522{ 523 devclass_t bus; 524 int error; 525 526 spin_lock(&pci_lock); 527 list_add(&pdrv->links, &pci_drivers); 528 spin_unlock(&pci_lock); 529 bus = devclass_find("pci"); 530 pdrv->driver.name = pdrv->name; 531 pdrv->driver.methods = pci_methods; 532 pdrv->driver.size = sizeof(struct pci_dev); 533 mtx_lock(&Giant); 534 error = devclass_add_driver(bus, &pdrv->driver, BUS_PASS_DEFAULT, 535 &pdrv->bsdclass); 536 mtx_unlock(&Giant); 537 if (error) 538 return (-error); 539 return (0); 540} 541 542static inline void 543pci_unregister_driver(struct pci_driver *pdrv) 544{ 545 devclass_t bus; 546 547 list_del(&pdrv->links); 548 bus = devclass_find("pci"); 549 mtx_lock(&Giant); 550 devclass_delete_driver(bus, &pdrv->driver); 551 mtx_unlock(&Giant); 552} 553 554struct msix_entry { 555 int entry; 556 int vector; 557}; 558 559/* 560 * Enable msix, positive errors indicate actual number of available 561 * vectors. Negative errors are failures. 562 */ 563static inline int 564pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 565{ 566 struct resource_list_entry *rle; 567 int error; 568 int avail; 569 int i; 570 571 avail = pci_msix_count(pdev->dev.bsddev); 572 if (avail < nreq) { 573 if (avail == 0) 574 return -EINVAL; 575 return avail; 576 } 577 avail = nreq; 578 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 579 return error; 580 rle = _pci_get_rle(pdev, SYS_RES_IRQ, 1); 581 pdev->dev.msix = rle->start; 582 pdev->dev.msix_max = rle->start + avail; 583 for (i = 0; i < nreq; i++) 584 entries[i].vector = pdev->dev.msix + i; 585 return (0); 586} 587 588static inline int pci_channel_offline(struct pci_dev *pdev) 589{ 590 return false; 591} 592 593static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 594{ 595 return -ENODEV; 596} 597static inline void pci_disable_sriov(struct pci_dev *dev) 598{ 599} 600 601/** 602 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table 603 * @_table: device table name 604 * 605 * This macro is used to create a struct pci_device_id array (a device table) 606 * in a generic manner. 607 */ 608#define DEFINE_PCI_DEVICE_TABLE(_table) \ 609 const struct pci_device_id _table[] __devinitdata 610 611 612/* XXX This should not be necessary. */ 613#define pcix_set_mmrbc(d, v) 0 614#define pcix_get_max_mmrbc(d) 0 615#define pcie_set_readrq(d, v) 0 616 617#define PCI_DMA_BIDIRECTIONAL 0 618#define PCI_DMA_TODEVICE 1 619#define PCI_DMA_FROMDEVICE 2 620#define PCI_DMA_NONE 3 621 622#define pci_pool dma_pool 623#define pci_pool_destroy dma_pool_destroy 624#define pci_pool_alloc dma_pool_alloc 625#define pci_pool_free dma_pool_free 626#define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 627 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 628#define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 629 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 630 _size, _vaddr, _dma_handle) 631#define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 632 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 633 _sg, _nents, (enum dma_data_direction)_dir) 634#define pci_map_single(_hwdev, _ptr, _size, _dir) \ 635 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 636 (_ptr), (_size), (enum dma_data_direction)_dir) 637#define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 638 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 639 _addr, _size, (enum dma_data_direction)_dir) 640#define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 641 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 642 _sg, _nents, (enum dma_data_direction)_dir) 643#define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 644 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 645 _offset, _size, (enum dma_data_direction)_dir) 646#define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 647 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 648 _dma_address, _size, (enum dma_data_direction)_dir) 649#define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 650#define pci_dma_mapping_error(_pdev, _dma_addr) \ 651 dma_mapping_error(&(_pdev)->dev, _dma_addr) 652#define pci_set_consistent_dma_mask(_pdev, _mask) \ 653 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 654#define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 655#define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 656#define pci_unmap_addr dma_unmap_addr 657#define pci_unmap_addr_set dma_unmap_addr_set 658#define pci_unmap_len dma_unmap_len 659#define pci_unmap_len_set dma_unmap_len_set 660 661typedef unsigned int __bitwise pci_channel_state_t; 662typedef unsigned int __bitwise pci_ers_result_t; 663 664enum pci_channel_state { 665 /* I/O channel is in normal state */ 666 pci_channel_io_normal = (__force pci_channel_state_t) 1, 667 668 /* I/O to channel is blocked */ 669 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 670 671 /* PCI card is dead */ 672 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 673}; 674 675enum pci_ers_result { 676 /* no result/none/not supported in device driver */ 677 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 678 679 /* Device driver can recover without slot reset */ 680 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 681 682 /* Device driver wants slot to be reset. */ 683 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 684 685 /* Device has completely failed, is unrecoverable */ 686 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 687 688 /* Device driver is fully recovered and operational */ 689 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 690}; 691 692 693/* PCI bus error event callbacks */ 694struct pci_error_handlers { 695 /* PCI bus error detected on this device */ 696 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 697 enum pci_channel_state error); 698 699 /* MMIO has been re-enabled, but not DMA */ 700 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 701 702 /* PCI Express link has been reset */ 703 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 704 705 /* PCI slot has been reset */ 706 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 707 708 /* Device driver may resume normal operations */ 709 void (*resume)(struct pci_dev *dev); 710}; 711 712/* freeBSD does not support SRIOV - yet */ 713static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 714{ 715 return dev; 716} 717 718static inline bool pci_is_pcie(struct pci_dev *dev) 719{ 720 return !!pci_pcie_cap(dev); 721} 722 723static inline u16 pcie_flags_reg(struct pci_dev *dev) 724{ 725 int pos; 726 u16 reg16; 727 728 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 729 if (!pos) 730 return 0; 731 732 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 733 734 return reg16; 735} 736 737 738static inline int pci_pcie_type(struct pci_dev *dev) 739{ 740 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 741} 742 743static inline int pcie_cap_version(struct pci_dev *dev) 744{ 745 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 746} 747 748static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 749{ 750 int type = pci_pcie_type(dev); 751 752 return pcie_cap_version(dev) > 1 || 753 type == PCI_EXP_TYPE_ROOT_PORT || 754 type == PCI_EXP_TYPE_ENDPOINT || 755 type == PCI_EXP_TYPE_LEG_END; 756} 757 758static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 759{ 760 return true; 761} 762 763static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 764{ 765 int type = pci_pcie_type(dev); 766 767 return pcie_cap_version(dev) > 1 || 768 type == PCI_EXP_TYPE_ROOT_PORT || 769 (type == PCI_EXP_TYPE_DOWNSTREAM && 770 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 771} 772 773static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 774{ 775 int type = pci_pcie_type(dev); 776 777 return pcie_cap_version(dev) > 1 || 778 type == PCI_EXP_TYPE_ROOT_PORT || 779 type == PCI_EXP_TYPE_RC_EC; 780} 781 782static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 783{ 784 if (!pci_is_pcie(dev)) 785 return false; 786 787 switch (pos) { 788 case PCI_EXP_FLAGS_TYPE: 789 return true; 790 case PCI_EXP_DEVCAP: 791 case PCI_EXP_DEVCTL: 792 case PCI_EXP_DEVSTA: 793 return pcie_cap_has_devctl(dev); 794 case PCI_EXP_LNKCAP: 795 case PCI_EXP_LNKCTL: 796 case PCI_EXP_LNKSTA: 797 return pcie_cap_has_lnkctl(dev); 798 case PCI_EXP_SLTCAP: 799 case PCI_EXP_SLTCTL: 800 case PCI_EXP_SLTSTA: 801 return pcie_cap_has_sltctl(dev); 802 case PCI_EXP_RTCTL: 803 case PCI_EXP_RTCAP: 804 case PCI_EXP_RTSTA: 805 return pcie_cap_has_rtctl(dev); 806 case PCI_EXP_DEVCAP2: 807 case PCI_EXP_DEVCTL2: 808 case PCI_EXP_LNKCAP2: 809 case PCI_EXP_LNKCTL2: 810 case PCI_EXP_LNKSTA2: 811 return pcie_cap_version(dev) > 1; 812 default: 813 return false; 814 } 815} 816 817 818static inline int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 819{ 820 if (pos & 1) 821 return -EINVAL; 822 823 if (!pcie_capability_reg_implemented(dev, pos)) 824 return 0; 825 826 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 827} 828 829 830#endif /* _LINUX_PCI_H_ */ 831