device.h revision 272407
1/* 2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33#ifndef MLX4_DEVICE_H 34#define MLX4_DEVICE_H 35 36#include <linux/pci.h> 37#include <linux/completion.h> 38#include <linux/radix-tree.h> 39#include <linux/types.h> 40#include <linux/bitops.h> 41#include <linux/workqueue.h> 42#include <asm/atomic.h> 43 44#include <linux/clocksource.h> 45 46#define MAX_MSIX_P_PORT 17 47#define MAX_MSIX 64 48#define MSIX_LEGACY_SZ 4 49#define MIN_MSIX_P_PORT 5 50 51#define MLX4_ROCE_MAX_GIDS 128 52#define MLX4_ROCE_PF_GIDS 16 53 54#define MLX4_NUM_UP 8 55#define MLX4_NUM_TC 8 56#define MLX4_MAX_100M_UNITS_VAL 255 /* 57 * work around: can't set values 58 * greater then this value when 59 * using 100 Mbps units. 60 */ 61#define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */ 62#define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */ 63#define MLX4_RATELIMIT_DEFAULT 0x00ff 64 65#define CORE_CLOCK_MASK 0xffffffffffffULL 66 67enum { 68 MLX4_FLAG_MSI_X = 1 << 0, 69 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, 70 MLX4_FLAG_MASTER = 1 << 2, 71 MLX4_FLAG_SLAVE = 1 << 3, 72 MLX4_FLAG_SRIOV = 1 << 4, 73 MLX4_FLAG_DEV_NUM_STR = 1 << 5, 74 MLX4_FLAG_OLD_REG_MAC = 1 << 6, 75}; 76 77enum { 78 MLX4_PORT_CAP_IS_SM = 1 << 1, 79 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19, 80}; 81 82enum { 83 MLX4_MAX_PORTS = 2, 84 MLX4_MAX_PORT_PKEYS = 128 85}; 86 87/* base qkey for use in sriov tunnel-qp/proxy-qp communication. 88 * These qkeys must not be allowed for general use. This is a 64k range, 89 * and to test for violation, we use the mask (protect against future chg). 90 */ 91#define MLX4_RESERVED_QKEY_BASE (0xFFFF0000) 92#define MLX4_RESERVED_QKEY_MASK (0xFFFF0000) 93 94enum { 95 MLX4_BOARD_ID_LEN = 64, 96 MLX4_VSD_LEN = 208 97}; 98 99enum { 100 MLX4_MAX_NUM_PF = 16, 101 MLX4_MAX_NUM_VF = 64, 102 MLX4_MFUNC_MAX = 80, 103 MLX4_MAX_EQ_NUM = 1024, 104 MLX4_MFUNC_EQ_NUM = 4, 105 MLX4_MFUNC_MAX_EQES = 8, 106 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1) 107}; 108 109/* Driver supports 3 diffrent device methods to manage traffic steering: 110 * -device managed - High level API for ib and eth flow steering. FW is 111 * managing flow steering tables. 112 * - B0 steering mode - Common low level API for ib and (if supported) eth. 113 * - A0 steering mode - Limited low level API for eth. In case of IB, 114 * B0 mode is in use. 115 */ 116enum { 117 MLX4_STEERING_MODE_A0, 118 MLX4_STEERING_MODE_B0, 119 MLX4_STEERING_MODE_DEVICE_MANAGED 120}; 121 122static inline const char *mlx4_steering_mode_str(int steering_mode) 123{ 124 switch (steering_mode) { 125 case MLX4_STEERING_MODE_A0: 126 return "A0 steering"; 127 128 case MLX4_STEERING_MODE_B0: 129 return "B0 steering"; 130 131 case MLX4_STEERING_MODE_DEVICE_MANAGED: 132 return "Device managed flow steering"; 133 134 default: 135 return "Unrecognize steering mode"; 136 } 137} 138 139enum { 140 MLX4_DEV_CAP_FLAG_RC = 1LL << 0, 141 MLX4_DEV_CAP_FLAG_UC = 1LL << 1, 142 MLX4_DEV_CAP_FLAG_UD = 1LL << 2, 143 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3, 144 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6, 145 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7, 146 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 147 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 148 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12, 149 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15, 150 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16, 151 MLX4_DEV_CAP_FLAG_APM = 1LL << 17, 152 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18, 153 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19, 154 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20, 155 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21, 156 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30, 157 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32, 158 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34, 159 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37, 160 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38, 161 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40, 162 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41, 163 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42, 164 MLX4_DEV_CAP_FLAG_CROSS_CHANNEL = 1LL << 44, 165 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48, 166 MLX4_DEV_CAP_FLAG_COUNTERS_EXT = 1LL << 49, 167 MLX4_DEV_CAP_FLAG_SET_PORT_ETH_SCHED = 1LL << 53, 168 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55, 169 MLX4_DEV_CAP_FLAG_FAST_DROP = 1LL << 57, 170 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59, 171 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61, 172 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62 173}; 174 175enum { 176 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0, 177 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1, 178 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2, 179 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3, 180 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 4, 181 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 5, 182 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 6, 183 MLX4_DEV_CAP_FLAG2_LB_SRC_CHK = 1LL << 7, 184 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 8, 185 MLX4_DEV_CAP_FLAG2_ETS_CFG = 1LL << 9, 186 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 10, 187 MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN = 1LL << 11, 188 MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 12, 189 MLX4_DEV_CAP_FLAG2_TS = 1LL << 13, 190 MLX4_DEV_CAP_FLAG2_DRIVER_VERSION_TO_FW = 1LL << 14 191}; 192 193/* bit enums for an 8-bit flags field indicating special use 194 * QPs which require special handling in qp_reserve_range. 195 * Currently, this only includes QPs used by the ETH interface, 196 * where we expect to use blueflame. These QPs must not have 197 * bits 6 and 7 set in their qp number. 198 * 199 * This enum may use only bits 0..7. 200 */ 201enum { 202 MLX4_RESERVE_BF_QP = 1 << 7, 203}; 204 205enum { 206 MLX4_DEV_CAP_CQ_FLAG_IO = 1 << 0 207}; 208 209enum { 210 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0, 211 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1 212}; 213 214enum { 215 MLX4_USER_DEV_CAP_64B_CQE = 1L << 0 216}; 217 218enum { 219 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0 220}; 221 222 223#define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 224 225enum { 226 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1, 227 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, 228 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, 229 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, 230 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, 231 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, 232}; 233 234enum mlx4_event { 235 MLX4_EVENT_TYPE_COMP = 0x00, 236 MLX4_EVENT_TYPE_PATH_MIG = 0x01, 237 MLX4_EVENT_TYPE_COMM_EST = 0x02, 238 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, 239 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, 240 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, 241 MLX4_EVENT_TYPE_CQ_ERROR = 0x04, 242 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 243 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, 244 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 245 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 246 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 247 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 248 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, 249 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, 250 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, 251 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, 252 MLX4_EVENT_TYPE_CMD = 0x0a, 253 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19, 254 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18, 255 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a, 256 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b, 257 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c, 258 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d, 259 MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT = 0x3e, 260 MLX4_EVENT_TYPE_NONE = 0xff, 261}; 262 263enum { 264 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, 265 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 266}; 267 268enum { 269 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE = 1, 270 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE = 2, 271}; 272 273enum { 274 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0, 275}; 276 277enum slave_port_state { 278 SLAVE_PORT_DOWN = 0, 279 SLAVE_PENDING_UP, 280 SLAVE_PORT_UP, 281}; 282 283enum slave_port_gen_event { 284 SLAVE_PORT_GEN_EVENT_DOWN = 0, 285 SLAVE_PORT_GEN_EVENT_UP, 286 SLAVE_PORT_GEN_EVENT_NONE, 287}; 288 289enum slave_port_state_event { 290 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, 291 MLX4_PORT_STATE_DEV_EVENT_PORT_UP, 292 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID, 293 MLX4_PORT_STATE_IB_EVENT_GID_INVALID, 294}; 295 296enum { 297 MLX4_PERM_LOCAL_READ = 1 << 10, 298 MLX4_PERM_LOCAL_WRITE = 1 << 11, 299 MLX4_PERM_REMOTE_READ = 1 << 12, 300 MLX4_PERM_REMOTE_WRITE = 1 << 13, 301 MLX4_PERM_ATOMIC = 1 << 14, 302 MLX4_PERM_BIND_MW = 1 << 15, 303}; 304 305enum { 306 MLX4_OPCODE_NOP = 0x00, 307 MLX4_OPCODE_SEND_INVAL = 0x01, 308 MLX4_OPCODE_RDMA_WRITE = 0x08, 309 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, 310 MLX4_OPCODE_SEND = 0x0a, 311 MLX4_OPCODE_SEND_IMM = 0x0b, 312 MLX4_OPCODE_LSO = 0x0e, 313 MLX4_OPCODE_RDMA_READ = 0x10, 314 MLX4_OPCODE_ATOMIC_CS = 0x11, 315 MLX4_OPCODE_ATOMIC_FA = 0x12, 316 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14, 317 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15, 318 MLX4_OPCODE_BIND_MW = 0x18, 319 MLX4_OPCODE_FMR = 0x19, 320 MLX4_OPCODE_LOCAL_INVAL = 0x1b, 321 MLX4_OPCODE_CONFIG_CMD = 0x1f, 322 323 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 324 MLX4_RECV_OPCODE_SEND = 0x01, 325 MLX4_RECV_OPCODE_SEND_IMM = 0x02, 326 MLX4_RECV_OPCODE_SEND_INVAL = 0x03, 327 328 MLX4_CQE_OPCODE_ERROR = 0x1e, 329 MLX4_CQE_OPCODE_RESIZE = 0x16, 330}; 331 332enum { 333 MLX4_STAT_RATE_OFFSET = 5 334}; 335 336enum mlx4_protocol { 337 MLX4_PROT_IB_IPV6 = 0, 338 MLX4_PROT_ETH, 339 MLX4_PROT_IB_IPV4, 340 MLX4_PROT_FCOE 341}; 342 343enum { 344 MLX4_MTT_FLAG_PRESENT = 1 345}; 346 347enum { 348 MLX4_MAX_MTT_SHIFT = 31 349}; 350 351enum mlx4_qp_region { 352 MLX4_QP_REGION_FW = 0, 353 MLX4_QP_REGION_ETH_ADDR, 354 MLX4_QP_REGION_FC_ADDR, 355 MLX4_QP_REGION_FC_EXCH, 356 MLX4_NUM_QP_REGION 357}; 358 359enum mlx4_port_type { 360 MLX4_PORT_TYPE_NONE = 0, 361 MLX4_PORT_TYPE_IB = 1, 362 MLX4_PORT_TYPE_ETH = 2, 363 MLX4_PORT_TYPE_AUTO = 3, 364 MLX4_PORT_TYPE_NA = 4 365}; 366 367enum mlx4_special_vlan_idx { 368 MLX4_NO_VLAN_IDX = 0, 369 MLX4_VLAN_MISS_IDX, 370 MLX4_VLAN_REGULAR 371}; 372 373enum mlx4_steer_type { 374 MLX4_MC_STEER = 0, 375 MLX4_UC_STEER, 376 MLX4_NUM_STEERS 377}; 378 379enum { 380 MLX4_NUM_FEXCH = 64 * 1024, 381}; 382 383enum { 384 MLX4_MAX_FAST_REG_PAGES = 511, 385}; 386 387enum { 388 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14, 389 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15, 390 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16, 391}; 392 393/* Port mgmt change event handling */ 394enum { 395 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0, 396 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1, 397 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2, 398 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3, 399 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4, 400}; 401 402#define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \ 403 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK) 404 405static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) 406{ 407 return (major << 32) | (minor << 16) | subminor; 408} 409 410struct mlx4_phys_caps { 411 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1]; 412 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1]; 413 u32 num_phys_eqs; 414 u32 base_sqpn; 415 u32 base_proxy_sqpn; 416 u32 base_tunnel_sqpn; 417}; 418 419struct mlx4_caps { 420 u64 fw_ver; 421 u32 function; 422 int num_ports; 423 int vl_cap[MLX4_MAX_PORTS + 1]; 424 int ib_mtu_cap[MLX4_MAX_PORTS + 1]; 425 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1]; 426 u64 def_mac[MLX4_MAX_PORTS + 1]; 427 int eth_mtu_cap[MLX4_MAX_PORTS + 1]; 428 int gid_table_len[MLX4_MAX_PORTS + 1]; 429 int pkey_table_len[MLX4_MAX_PORTS + 1]; 430 int trans_type[MLX4_MAX_PORTS + 1]; 431 int vendor_oui[MLX4_MAX_PORTS + 1]; 432 int wavelength[MLX4_MAX_PORTS + 1]; 433 u64 trans_code[MLX4_MAX_PORTS + 1]; 434 int local_ca_ack_delay; 435 int num_uars; 436 u32 uar_page_size; 437 int bf_reg_size; 438 int bf_regs_per_page; 439 int max_sq_sg; 440 int max_rq_sg; 441 int num_qps; 442 int max_wqes; 443 int max_sq_desc_sz; 444 int max_rq_desc_sz; 445 int max_qp_init_rdma; 446 int max_qp_dest_rdma; 447 u32 *qp0_proxy; 448 u32 *qp1_proxy; 449 u32 *qp0_tunnel; 450 u32 *qp1_tunnel; 451 int num_srqs; 452 int max_srq_wqes; 453 int max_srq_sge; 454 int reserved_srqs; 455 int num_cqs; 456 int max_cqes; 457 int reserved_cqs; 458 int num_eqs; 459 int reserved_eqs; 460 int num_comp_vectors; 461 int comp_pool; 462 int num_mpts; 463 int max_fmr_maps; 464 u64 num_mtts; 465 int fmr_reserved_mtts; 466 int reserved_mtts; 467 int reserved_mrws; 468 int reserved_uars; 469 int num_mgms; 470 int num_amgms; 471 int reserved_mcgs; 472 int num_qp_per_mgm; 473 int steering_mode; 474 int num_pds; 475 int reserved_pds; 476 int max_xrcds; 477 int reserved_xrcds; 478 int mtt_entry_sz; 479 u32 max_msg_sz; 480 u32 page_size_cap; 481 u64 flags; 482 u64 flags2; 483 u32 bmme_flags; 484 u32 reserved_lkey; 485 u16 stat_rate_support; 486 u8 cq_timestamp; 487 u8 port_width_cap[MLX4_MAX_PORTS + 1]; 488 int max_gso_sz; 489 int max_rss_tbl_sz; 490 int reserved_qps_cnt[MLX4_NUM_QP_REGION]; 491 int reserved_qps; 492 int reserved_qps_base[MLX4_NUM_QP_REGION]; 493 int log_num_macs; 494 int log_num_vlans; 495 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 496 u8 supported_type[MLX4_MAX_PORTS + 1]; 497 u8 suggested_type[MLX4_MAX_PORTS + 1]; 498 u8 default_sense[MLX4_MAX_PORTS + 1]; 499 u32 port_mask[MLX4_MAX_PORTS + 1]; 500 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; 501 u32 max_counters; 502 u8 port_ib_mtu[MLX4_MAX_PORTS + 1]; 503 u16 sqp_demux; 504 u32 sync_qp; 505 u32 cq_flags; 506 u32 eqe_size; 507 u32 cqe_size; 508 u8 eqe_factor; 509 u32 userspace_caps; /* userspace must be aware to */ 510 u32 function_caps; /* functions must be aware to */ 511 u8 fast_drop; 512 u16 hca_core_clock; 513 u32 max_basic_counters; 514 u32 max_extended_counters; 515 u8 def_counter_index[MLX4_MAX_PORTS + 1]; 516}; 517 518struct mlx4_buf_list { 519 void *buf; 520 dma_addr_t map; 521}; 522 523struct mlx4_buf { 524 struct mlx4_buf_list direct; 525 struct mlx4_buf_list *page_list; 526 int nbufs; 527 int npages; 528 int page_shift; 529}; 530 531struct mlx4_mtt { 532 u32 offset; 533 int order; 534 int page_shift; 535}; 536 537enum { 538 MLX4_DB_PER_PAGE = PAGE_SIZE / 4 539}; 540 541struct mlx4_db_pgdir { 542 struct list_head list; 543 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); 544 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); 545 unsigned long *bits[2]; 546 __be32 *db_page; 547 dma_addr_t db_dma; 548}; 549 550struct mlx4_ib_user_db_page; 551 552struct mlx4_db { 553 __be32 *db; 554 union { 555 struct mlx4_db_pgdir *pgdir; 556 struct mlx4_ib_user_db_page *user_page; 557 } u; 558 dma_addr_t dma; 559 int index; 560 int order; 561}; 562 563struct mlx4_hwq_resources { 564 struct mlx4_db db; 565 struct mlx4_mtt mtt; 566 struct mlx4_buf buf; 567}; 568 569struct mlx4_mr { 570 struct mlx4_mtt mtt; 571 u64 iova; 572 u64 size; 573 u32 key; 574 u32 pd; 575 u32 access; 576 int enabled; 577}; 578 579enum mlx4_mw_type { 580 MLX4_MW_TYPE_1 = 1, 581 MLX4_MW_TYPE_2 = 2, 582}; 583 584struct mlx4_mw { 585 u32 key; 586 u32 pd; 587 enum mlx4_mw_type type; 588 int enabled; 589}; 590 591struct mlx4_fmr { 592 struct mlx4_mr mr; 593 struct mlx4_mpt_entry *mpt; 594 __be64 *mtts; 595 dma_addr_t dma_handle; 596 int max_pages; 597 int max_maps; 598 int maps; 599 u8 page_shift; 600}; 601 602struct mlx4_uar { 603 unsigned long pfn; 604 int index; 605 struct list_head bf_list; 606 unsigned free_bf_bmap; 607 void __iomem *map; 608 void __iomem *bf_map; 609}; 610 611struct mlx4_bf { 612 unsigned long offset; 613 int buf_size; 614 struct mlx4_uar *uar; 615 void __iomem *reg; 616}; 617 618struct mlx4_cq { 619 void (*comp) (struct mlx4_cq *); 620 void (*event) (struct mlx4_cq *, enum mlx4_event); 621 622 struct mlx4_uar *uar; 623 624 u32 cons_index; 625 626 __be32 *set_ci_db; 627 __be32 *arm_db; 628 int arm_sn; 629 630 int cqn; 631 unsigned vector; 632 633 atomic_t refcount; 634 struct completion free; 635 int eqn; 636 u16 irq; 637}; 638 639struct mlx4_qp { 640 void (*event) (struct mlx4_qp *, enum mlx4_event); 641 642 int qpn; 643 644 atomic_t refcount; 645 struct completion free; 646}; 647 648struct mlx4_srq { 649 void (*event) (struct mlx4_srq *, enum mlx4_event); 650 651 int srqn; 652 int max; 653 int max_gs; 654 int wqe_shift; 655 656 atomic_t refcount; 657 struct completion free; 658}; 659 660struct mlx4_av { 661 __be32 port_pd; 662 u8 reserved1; 663 u8 g_slid; 664 __be16 dlid; 665 u8 reserved2; 666 u8 gid_index; 667 u8 stat_rate; 668 u8 hop_limit; 669 __be32 sl_tclass_flowlabel; 670 u8 dgid[16]; 671}; 672 673struct mlx4_eth_av { 674 __be32 port_pd; 675 u8 reserved1; 676 u8 smac_idx; 677 u16 reserved2; 678 u8 reserved3; 679 u8 gid_index; 680 u8 stat_rate; 681 u8 hop_limit; 682 __be32 sl_tclass_flowlabel; 683 u8 dgid[16]; 684 u8 s_mac[6]; 685 u8 reserved4[2]; 686 __be16 vlan; 687 u8 mac[6]; 688}; 689 690union mlx4_ext_av { 691 struct mlx4_av ib; 692 struct mlx4_eth_av eth; 693}; 694 695struct mlx4_if_stat_control { 696 u8 reserved1[3]; 697 /* Extended counters enabled */ 698 u8 cnt_mode; 699 /* Number of interfaces */ 700 __be32 num_of_if; 701 __be32 reserved[2]; 702}; 703 704struct mlx4_if_stat_basic { 705 struct mlx4_if_stat_control control; 706 struct { 707 __be64 IfRxFrames; 708 __be64 IfRxOctets; 709 __be64 IfTxFrames; 710 __be64 IfTxOctets; 711 } counters[]; 712}; 713#define MLX4_IF_STAT_BSC_SZ(ports)(sizeof(struct mlx4_if_stat_extended) +\ 714 sizeof(((struct mlx4_if_stat_extended *)0)->\ 715 counters[0]) * ports) 716 717struct mlx4_if_stat_extended { 718 struct mlx4_if_stat_control control; 719 struct { 720 __be64 IfRxUnicastFrames; 721 __be64 IfRxUnicastOctets; 722 __be64 IfRxMulticastFrames; 723 __be64 IfRxMulticastOctets; 724 __be64 IfRxBroadcastFrames; 725 __be64 IfRxBroadcastOctets; 726 __be64 IfRxNoBufferFrames; 727 __be64 IfRxNoBufferOctets; 728 __be64 IfRxErrorFrames; 729 __be64 IfRxErrorOctets; 730 __be32 reserved[39]; 731 __be64 IfTxUnicastFrames; 732 __be64 IfTxUnicastOctets; 733 __be64 IfTxMulticastFrames; 734 __be64 IfTxMulticastOctets; 735 __be64 IfTxBroadcastFrames; 736 __be64 IfTxBroadcastOctets; 737 __be64 IfTxDroppedFrames; 738 __be64 IfTxDroppedOctets; 739 __be64 IfTxRequestedFramesSent; 740 __be64 IfTxGeneratedFramesSent; 741 __be64 IfTxTsoOctets; 742 } __packed counters[]; 743}; 744#define MLX4_IF_STAT_EXT_SZ(ports) (sizeof(struct mlx4_if_stat_extended) +\ 745 sizeof(((struct mlx4_if_stat_extended *)\ 746 0)->counters[0]) * ports) 747 748union mlx4_counter { 749 struct mlx4_if_stat_control control; 750 struct mlx4_if_stat_basic basic; 751 struct mlx4_if_stat_extended ext; 752}; 753#define MLX4_IF_STAT_SZ(ports) MLX4_IF_STAT_EXT_SZ(ports) 754 755struct mlx4_quotas { 756 int qp; 757 int cq; 758 int srq; 759 int mpt; 760 int mtt; 761 int counter; 762 int xrcd; 763}; 764 765struct mlx4_dev { 766 struct pci_dev *pdev; 767 unsigned long flags; 768 unsigned long num_slaves; 769 struct mlx4_caps caps; 770 struct mlx4_phys_caps phys_caps; 771 struct mlx4_quotas quotas; 772 struct radix_tree_root qp_table_tree; 773 u8 rev_id; 774 char board_id[MLX4_BOARD_ID_LEN]; 775 u16 vsd_vendor_id; 776 char vsd[MLX4_VSD_LEN]; 777 int num_vfs; 778 int numa_node; 779 int oper_log_mgm_entry_size; 780 u64 regid_promisc_array[MLX4_MAX_PORTS + 1]; 781 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1]; 782}; 783 784struct mlx4_clock_params { 785 u64 offset; 786 u8 bar; 787 u8 size; 788}; 789 790struct mlx4_eqe { 791 u8 reserved1; 792 u8 type; 793 u8 reserved2; 794 u8 subtype; 795 union { 796 u32 raw[6]; 797 struct { 798 __be32 cqn; 799 } __packed comp; 800 struct { 801 u16 reserved1; 802 __be16 token; 803 u32 reserved2; 804 u8 reserved3[3]; 805 u8 status; 806 __be64 out_param; 807 } __packed cmd; 808 struct { 809 __be32 qpn; 810 } __packed qp; 811 struct { 812 __be32 srqn; 813 } __packed srq; 814 struct { 815 __be32 cqn; 816 u32 reserved1; 817 u8 reserved2[3]; 818 u8 syndrome; 819 } __packed cq_err; 820 struct { 821 u32 reserved1[2]; 822 __be32 port; 823 } __packed port_change; 824 struct { 825 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4 826 u32 reserved; 827 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE]; 828 } __packed comm_channel_arm; 829 struct { 830 u8 port; 831 u8 reserved[3]; 832 __be64 mac; 833 } __packed mac_update; 834 struct { 835 __be32 slave_id; 836 } __packed flr_event; 837 struct { 838 __be16 current_temperature; 839 __be16 warning_threshold; 840 } __packed warming; 841 struct { 842 u8 reserved[3]; 843 u8 port; 844 union { 845 struct { 846 __be16 mstr_sm_lid; 847 __be16 port_lid; 848 __be32 changed_attr; 849 u8 reserved[3]; 850 u8 mstr_sm_sl; 851 __be64 gid_prefix; 852 } __packed port_info; 853 struct { 854 __be32 block_ptr; 855 __be32 tbl_entries_mask; 856 } __packed tbl_change_info; 857 } params; 858 } __packed port_mgmt_change; 859 struct { 860 u8 reserved[3]; 861 u8 port; 862 u32 reserved1[5]; 863 } __packed bad_cable; 864 } event; 865 u8 slave_id; 866 u8 reserved3[2]; 867 u8 owner; 868} __packed; 869 870struct mlx4_init_port_param { 871 int set_guid0; 872 int set_node_guid; 873 int set_si_guid; 874 u16 mtu; 875 int port_width_cap; 876 u16 vl_cap; 877 u16 max_gid; 878 u16 max_pkey; 879 u64 guid0; 880 u64 node_guid; 881 u64 si_guid; 882}; 883 884#define mlx4_foreach_port(port, dev, type) \ 885 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 886 if ((type) == (dev)->caps.port_mask[(port)]) 887 888#define mlx4_foreach_non_ib_transport_port(port, dev) \ 889 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 890 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB)) 891 892#define mlx4_foreach_ib_transport_port(port, dev) \ 893 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 894 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \ 895 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) 896 897#define MLX4_INVALID_SLAVE_ID 0xFF 898 899#define MLX4_SINK_COUNTER_INDEX 0xff 900 901void handle_port_mgmt_change_event(struct work_struct *work); 902 903static inline int mlx4_master_func_num(struct mlx4_dev *dev) 904{ 905 return dev->caps.function; 906} 907 908static inline int mlx4_is_master(struct mlx4_dev *dev) 909{ 910 return dev->flags & MLX4_FLAG_MASTER; 911} 912 913static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev) 914{ 915 return dev->phys_caps.base_sqpn + 8 + 916 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev); 917} 918 919static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn) 920{ 921 return (qpn < dev->phys_caps.base_sqpn + 8 + 922 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev)); 923} 924 925static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn) 926{ 927 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8; 928 929 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8) 930 return 1; 931 932 return 0; 933} 934 935static inline int mlx4_is_mfunc(struct mlx4_dev *dev) 936{ 937 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER); 938} 939 940static inline int mlx4_is_slave(struct mlx4_dev *dev) 941{ 942 return dev->flags & MLX4_FLAG_SLAVE; 943} 944 945int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, 946 struct mlx4_buf *buf); 947void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); 948static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) 949{ 950 if (BITS_PER_LONG == 64 || buf->nbufs == 1) 951 return buf->direct.buf + offset; 952 else 953 return buf->page_list[offset >> PAGE_SHIFT].buf + 954 (offset & (PAGE_SIZE - 1)); 955} 956 957int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); 958void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); 959int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); 960void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); 961 962int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); 963void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); 964int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node); 965void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf); 966 967int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, 968 struct mlx4_mtt *mtt); 969void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 970u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 971 972int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, 973 int npages, int page_shift, struct mlx4_mr *mr); 974int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); 975int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); 976int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type, 977 struct mlx4_mw *mw); 978void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw); 979int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw); 980int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 981 int start_index, int npages, u64 *page_list); 982int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 983 struct mlx4_buf *buf); 984 985int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order); 986void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); 987 988int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, 989 int size, int max_direct); 990void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, 991 int size); 992 993int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, 994 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, 995 unsigned vector, int collapsed, int timestamp_en); 996void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); 997 998int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, 999 int *base, u8 flags); 1000void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 1001 1002int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp); 1003void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); 1004 1005int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn, 1006 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq); 1007void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); 1008int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); 1009int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); 1010 1011int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); 1012int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); 1013 1014int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1015 int block_mcast_loopback, enum mlx4_protocol prot); 1016int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1017 enum mlx4_protocol prot); 1018int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1019 u8 port, int block_mcast_loopback, 1020 enum mlx4_protocol protocol, u64 *reg_id); 1021int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1022 enum mlx4_protocol protocol, u64 reg_id); 1023 1024enum { 1025 MLX4_DOMAIN_UVERBS = 0x1000, 1026 MLX4_DOMAIN_ETHTOOL = 0x2000, 1027 MLX4_DOMAIN_RFS = 0x3000, 1028 MLX4_DOMAIN_NIC = 0x5000, 1029}; 1030 1031enum mlx4_net_trans_rule_id { 1032 MLX4_NET_TRANS_RULE_ID_ETH = 0, 1033 MLX4_NET_TRANS_RULE_ID_IB, 1034 MLX4_NET_TRANS_RULE_ID_IPV6, 1035 MLX4_NET_TRANS_RULE_ID_IPV4, 1036 MLX4_NET_TRANS_RULE_ID_TCP, 1037 MLX4_NET_TRANS_RULE_ID_UDP, 1038 MLX4_NET_TRANS_RULE_NUM, /* should be last */ 1039}; 1040 1041extern const u16 __sw_id_hw[]; 1042 1043static inline int map_hw_to_sw_id(u16 header_id) 1044{ 1045 1046 int i; 1047 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) { 1048 if (header_id == __sw_id_hw[i]) 1049 return i; 1050 } 1051 return -EINVAL; 1052} 1053 1054enum mlx4_net_trans_promisc_mode { 1055 MLX4_FS_REGULAR = 1, 1056 MLX4_FS_ALL_DEFAULT, 1057 MLX4_FS_MC_DEFAULT, 1058 MLX4_FS_UC_SNIFFER, 1059 MLX4_FS_MC_SNIFFER, 1060 MLX4_FS_MODE_NUM, /* should be last */ 1061}; 1062 1063struct mlx4_spec_eth { 1064 u8 dst_mac[6]; 1065 u8 dst_mac_msk[6]; 1066 u8 src_mac[6]; 1067 u8 src_mac_msk[6]; 1068 u8 ether_type_enable; 1069 __be16 ether_type; 1070 __be16 vlan_id_msk; 1071 __be16 vlan_id; 1072}; 1073 1074struct mlx4_spec_tcp_udp { 1075 __be16 dst_port; 1076 __be16 dst_port_msk; 1077 __be16 src_port; 1078 __be16 src_port_msk; 1079}; 1080 1081struct mlx4_spec_ipv4 { 1082 __be32 dst_ip; 1083 __be32 dst_ip_msk; 1084 __be32 src_ip; 1085 __be32 src_ip_msk; 1086}; 1087 1088struct mlx4_spec_ib { 1089 __be32 l3_qpn; 1090 __be32 qpn_msk; 1091 u8 dst_gid[16]; 1092 u8 dst_gid_msk[16]; 1093}; 1094 1095struct mlx4_spec_list { 1096 struct list_head list; 1097 enum mlx4_net_trans_rule_id id; 1098 union { 1099 struct mlx4_spec_eth eth; 1100 struct mlx4_spec_ib ib; 1101 struct mlx4_spec_ipv4 ipv4; 1102 struct mlx4_spec_tcp_udp tcp_udp; 1103 }; 1104}; 1105 1106enum mlx4_net_trans_hw_rule_queue { 1107 MLX4_NET_TRANS_Q_FIFO, 1108 MLX4_NET_TRANS_Q_LIFO, 1109}; 1110 1111struct mlx4_net_trans_rule { 1112 struct list_head list; 1113 enum mlx4_net_trans_hw_rule_queue queue_mode; 1114 bool exclusive; 1115 bool allow_loopback; 1116 enum mlx4_net_trans_promisc_mode promisc_mode; 1117 u8 port; 1118 u16 priority; 1119 u32 qpn; 1120}; 1121 1122struct mlx4_net_trans_rule_hw_ctrl { 1123 __be16 prio; 1124 u8 type; 1125 u8 flags; 1126 u8 rsvd1; 1127 u8 funcid; 1128 u8 vep; 1129 u8 port; 1130 __be32 qpn; 1131 __be32 rsvd2; 1132}; 1133 1134struct mlx4_net_trans_rule_hw_ib { 1135 u8 size; 1136 u8 rsvd1; 1137 __be16 id; 1138 u32 rsvd2; 1139 __be32 l3_qpn; 1140 __be32 qpn_mask; 1141 u8 dst_gid[16]; 1142 u8 dst_gid_msk[16]; 1143} __packed; 1144 1145struct mlx4_net_trans_rule_hw_eth { 1146 u8 size; 1147 u8 rsvd; 1148 __be16 id; 1149 u8 rsvd1[6]; 1150 u8 dst_mac[6]; 1151 u16 rsvd2; 1152 u8 dst_mac_msk[6]; 1153 u16 rsvd3; 1154 u8 src_mac[6]; 1155 u16 rsvd4; 1156 u8 src_mac_msk[6]; 1157 u8 rsvd5; 1158 u8 ether_type_enable; 1159 __be16 ether_type; 1160 __be16 vlan_tag_msk; 1161 __be16 vlan_tag; 1162} __packed; 1163 1164struct mlx4_net_trans_rule_hw_tcp_udp { 1165 u8 size; 1166 u8 rsvd; 1167 __be16 id; 1168 __be16 rsvd1[3]; 1169 __be16 dst_port; 1170 __be16 rsvd2; 1171 __be16 dst_port_msk; 1172 __be16 rsvd3; 1173 __be16 src_port; 1174 __be16 rsvd4; 1175 __be16 src_port_msk; 1176} __packed; 1177 1178struct mlx4_net_trans_rule_hw_ipv4 { 1179 u8 size; 1180 u8 rsvd; 1181 __be16 id; 1182 __be32 rsvd1; 1183 __be32 dst_ip; 1184 __be32 dst_ip_msk; 1185 __be32 src_ip; 1186 __be32 src_ip_msk; 1187} __packed; 1188 1189struct _rule_hw { 1190 union { 1191 struct { 1192 u8 size; 1193 u8 rsvd; 1194 __be16 id; 1195 }; 1196 struct mlx4_net_trans_rule_hw_eth eth; 1197 struct mlx4_net_trans_rule_hw_ib ib; 1198 struct mlx4_net_trans_rule_hw_ipv4 ipv4; 1199 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp; 1200 }; 1201}; 1202 1203int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn, 1204 enum mlx4_net_trans_promisc_mode mode); 1205int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port, 1206 enum mlx4_net_trans_promisc_mode mode); 1207int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 1208int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 1209int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 1210int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 1211int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 1212 1213int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1214void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1215int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port); 1216int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); 1217void mlx4_set_stats_bitmap(struct mlx4_dev *dev, unsigned long *stats_bitmap); 1218int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, 1219 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx); 1220int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, 1221 u8 promisc); 1222int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc); 1223int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw, 1224 u8 *pg, u16 *ratelimit); 1225int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); 1226int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); 1227void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); 1228 1229int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, 1230 int npages, u64 iova, u32 *lkey, u32 *rkey); 1231int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, 1232 int max_maps, u8 page_shift, struct mlx4_fmr *fmr); 1233int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 1234void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, 1235 u32 *lkey, u32 *rkey); 1236int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 1237int mlx4_SYNC_TPT(struct mlx4_dev *dev); 1238int mlx4_query_diag_counters(struct mlx4_dev *mlx4_dev, int array_length, 1239 u8 op_modifier, u32 in_offset[], 1240 u32 counter_out[]); 1241 1242int mlx4_test_interrupts(struct mlx4_dev *dev); 1243int mlx4_assign_eq(struct mlx4_dev *dev, char* name, int * vector); 1244void mlx4_release_eq(struct mlx4_dev *dev, int vec); 1245 1246int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port); 1247int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port); 1248 1249int mlx4_counter_alloc(struct mlx4_dev *dev, u8 port, u32 *idx); 1250void mlx4_counter_free(struct mlx4_dev *dev, u8 port, u32 idx); 1251 1252int mlx4_flow_attach(struct mlx4_dev *dev, 1253 struct mlx4_net_trans_rule *rule, u64 *reg_id); 1254int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id); 1255int map_sw_to_hw_steering_mode(struct mlx4_dev *dev, 1256 enum mlx4_net_trans_promisc_mode flow_type); 1257int map_sw_to_hw_steering_id(struct mlx4_dev *dev, 1258 enum mlx4_net_trans_rule_id id); 1259int hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id); 1260 1261void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, 1262 int i, int val); 1263 1264int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey); 1265 1266int mlx4_is_slave_active(struct mlx4_dev *dev, int slave); 1267int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port); 1268int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port); 1269int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr, u16 lid, u8 sl); 1270int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change); 1271enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port); 1272int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event); 1273 1274void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid); 1275__be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave); 1276int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid, int *slave_id); 1277int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id, u8 *gid); 1278 1279int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn, u32 max_range_qpn); 1280 1281int mlx4_read_clock(struct mlx4_dev *dev); 1282int mlx4_get_internal_clock_params(struct mlx4_dev *dev, 1283 struct mlx4_clock_params *params); 1284 1285#endif /* MLX4_DEVICE_H */ 1286