io.h revision 282513 
1/*-
2 * Copyright (c) 2010 Isilon Systems, Inc.
3 * Copyright (c) 2010 iX Systems, Inc.
4 * Copyright (c) 2010 Panasas, Inc.
5 * Copyright (c) 2013, 2014 Mellanox Technologies, Ltd.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice unmodified, this list of conditions, and the following
13 *    disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 *    notice, this list of conditions and the following disclaimer in the
16 *    documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30#ifndef	_LINUX_IO_H_
31#define	_LINUX_IO_H_
32
33#include <machine/vm.h>
34#include <sys/endian.h>
35
36static inline uint32_t
37__raw_readl(const volatile void *addr)
38{
39	return *(const volatile uint32_t *)addr;
40}
41
42static inline void
43__raw_writel(uint32_t b, volatile void *addr)
44{
45	*(volatile uint32_t *)addr = b;
46}
47
48static inline uint64_t
49__raw_readq(const volatile void *addr)
50{
51	return *(const volatile uint64_t *)addr;
52}
53
54static inline void
55__raw_writeq(uint64_t b, volatile void *addr)
56{
57	*(volatile uint64_t *)addr = b;
58}
59
60/*
61 * XXX This is all x86 specific.  It should be bus space access.
62 */
63#define mmiowb()
64
65#undef writel
66static inline void
67writel(uint32_t b, void *addr)
68{
69        *(volatile uint32_t *)addr = b;
70}
71
72#undef writeq
73static inline void
74writeq(uint64_t b, void *addr)
75{
76        *(volatile uint64_t *)addr = b;
77}
78
79#undef writeb
80static inline void
81writeb(uint8_t b, void *addr)
82{
83        *(volatile uint8_t *)addr = b;
84}
85
86#undef writew
87static inline void
88writew(uint16_t b, void *addr)
89{
90        *(volatile uint16_t *)addr = b;
91}
92
93#undef ioread32be
94static inline uint32_t
95ioread32be(const volatile void *addr)
96{
97	return be32toh(*(const volatile uint32_t *)addr);
98}
99
100#undef iowrite32be
101static inline void
102iowrite32be(uint32_t v, volatile void *addr)
103{
104	*(volatile uint32_t *)addr = htobe32(v);
105}
106
107void *_ioremap_attr(vm_paddr_t phys_addr, unsigned long size, int attr);
108#define	ioremap_nocache(addr, size)					\
109    _ioremap_attr((addr), (size), VM_MEMATTR_UNCACHEABLE)
110#define	ioremap_wc(addr, size)						\
111    _ioremap_attr((addr), (size), VM_MEMATTR_WRITE_COMBINING)
112#define	ioremap	ioremap_nocache
113void iounmap(void *addr);
114
115#define	memset_io(a, b, c)	memset((a), (b), (c))
116#define	memcpy_fromio(a, b, c)	memcpy((a), (b), (c))
117#define	memcpy_toio(a, b, c)	memcpy((a), (b), (c))
118
119static inline void
120__iowrite64_copy(void *to, void *from, size_t count)
121{
122#ifdef __LP64__
123	uint64_t *src;
124	uint64_t *dst;
125	int i;
126
127	for (i = 0, src = from, dst = to; i < count; i++, src++, dst++)
128		__raw_writeq(*src, dst);
129#else
130	uint32_t *src;
131	uint32_t *dst;
132	int i;
133
134	count *= 2;
135	for (i = 0, src = from, dst = to; i < count; i++, src++, dst++)
136		__raw_writel(*src, dst);
137#endif
138}
139
140
141#endif	/* _LINUX_IO_H_ */
142