qp.c revision 271127
1/* 2 * Copyright (c) 2004 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 5 * Copyright (c) 2004 Voltaire, Inc. All rights reserved. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * OpenIB.org BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or 14 * without modification, are permitted provided that the following 15 * conditions are met: 16 * 17 * - Redistributions of source code must retain the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer. 20 * 21 * - Redistributions in binary form must reproduce the above 22 * copyright notice, this list of conditions and the following 23 * disclaimer in the documentation and/or other materials 24 * provided with the distribution. 25 * 26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 33 * SOFTWARE. 34 */ 35 36#include <linux/mlx4/cmd.h> 37#include <linux/mlx4/qp.h> 38 39#include "mlx4.h" 40#include "icm.h" 41 42/* 43 * QP to support BF should have bits 6,7 cleared 44 */ 45#define MLX4_BF_QP_SKIP_MASK 0xc0 46#define MLX4_MAX_BF_QP_RANGE 0x40 47 48void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type) 49{ 50 struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table; 51 struct mlx4_qp *qp; 52 53 spin_lock(&qp_table->lock); 54 55 qp = __mlx4_qp_lookup(dev, qpn); 56 if (qp) 57 atomic_inc(&qp->refcount); 58 59 spin_unlock(&qp_table->lock); 60 61 if (!qp) { 62 mlx4_dbg(dev, "Async event for none existent QP %08x\n", qpn); 63 return; 64 } 65 66 qp->event(qp, event_type); 67 68 if (atomic_dec_and_test(&qp->refcount)) 69 complete(&qp->free); 70} 71 72/* used for INIT/CLOSE port logic */ 73static int is_master_qp0(struct mlx4_dev *dev, struct mlx4_qp *qp, int *real_qp0, int *proxy_qp0) 74{ 75 /* this procedure is called after we already know we are on the master */ 76 /* qp0 is either the proxy qp0, or the real qp0 */ 77 u32 pf_proxy_offset = dev->phys_caps.base_proxy_sqpn + 8 * mlx4_master_func_num(dev); 78 *proxy_qp0 = qp->qpn >= pf_proxy_offset && qp->qpn <= pf_proxy_offset + 1; 79 80 *real_qp0 = qp->qpn >= dev->phys_caps.base_sqpn && 81 qp->qpn <= dev->phys_caps.base_sqpn + 1; 82 83 return *real_qp0 || *proxy_qp0; 84} 85 86static int __mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 87 enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state, 88 struct mlx4_qp_context *context, 89 enum mlx4_qp_optpar optpar, 90 int sqd_event, struct mlx4_qp *qp, int native) 91{ 92 static const u16 op[MLX4_QP_NUM_STATE][MLX4_QP_NUM_STATE] = { 93 [MLX4_QP_STATE_RST] = { 94 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP, 95 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP, 96 [MLX4_QP_STATE_INIT] = MLX4_CMD_RST2INIT_QP, 97 }, 98 [MLX4_QP_STATE_INIT] = { 99 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP, 100 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP, 101 [MLX4_QP_STATE_INIT] = MLX4_CMD_INIT2INIT_QP, 102 [MLX4_QP_STATE_RTR] = MLX4_CMD_INIT2RTR_QP, 103 }, 104 [MLX4_QP_STATE_RTR] = { 105 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP, 106 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP, 107 [MLX4_QP_STATE_RTS] = MLX4_CMD_RTR2RTS_QP, 108 }, 109 [MLX4_QP_STATE_RTS] = { 110 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP, 111 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP, 112 [MLX4_QP_STATE_RTS] = MLX4_CMD_RTS2RTS_QP, 113 [MLX4_QP_STATE_SQD] = MLX4_CMD_RTS2SQD_QP, 114 }, 115 [MLX4_QP_STATE_SQD] = { 116 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP, 117 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP, 118 [MLX4_QP_STATE_RTS] = MLX4_CMD_SQD2RTS_QP, 119 [MLX4_QP_STATE_SQD] = MLX4_CMD_SQD2SQD_QP, 120 }, 121 [MLX4_QP_STATE_SQER] = { 122 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP, 123 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP, 124 [MLX4_QP_STATE_RTS] = MLX4_CMD_SQERR2RTS_QP, 125 }, 126 [MLX4_QP_STATE_ERR] = { 127 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP, 128 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP, 129 } 130 }; 131 132 struct mlx4_priv *priv = mlx4_priv(dev); 133 struct mlx4_cmd_mailbox *mailbox; 134 int ret = 0; 135 int real_qp0 = 0; 136 int proxy_qp0 = 0; 137 u8 port; 138 139 if (cur_state >= MLX4_QP_NUM_STATE || new_state >= MLX4_QP_NUM_STATE || 140 !op[cur_state][new_state]) 141 return -EINVAL; 142 143 if (op[cur_state][new_state] == MLX4_CMD_2RST_QP) { 144 ret = mlx4_cmd(dev, 0, qp->qpn, 2, 145 MLX4_CMD_2RST_QP, MLX4_CMD_TIME_CLASS_A, native); 146 if (mlx4_is_master(dev) && cur_state != MLX4_QP_STATE_ERR && 147 cur_state != MLX4_QP_STATE_RST && 148 is_master_qp0(dev, qp, &real_qp0, &proxy_qp0)) { 149 port = (qp->qpn & 1) + 1; 150 if (proxy_qp0) 151 priv->mfunc.master.qp0_state[port].proxy_qp0_active = 0; 152 else 153 priv->mfunc.master.qp0_state[port].qp0_active = 0; 154 } 155 return ret; 156 } 157 158 mailbox = mlx4_alloc_cmd_mailbox(dev); 159 if (IS_ERR(mailbox)) 160 return PTR_ERR(mailbox); 161 162 if (cur_state == MLX4_QP_STATE_RST && new_state == MLX4_QP_STATE_INIT) { 163 u64 mtt_addr = mlx4_mtt_addr(dev, mtt); 164 context->mtt_base_addr_h = mtt_addr >> 32; 165 context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff); 166 context->log_page_size = mtt->page_shift - MLX4_ICM_PAGE_SHIFT; 167 } 168 169 *(__be32 *) mailbox->buf = cpu_to_be32(optpar); 170 memcpy(mailbox->buf + 8, context, sizeof *context); 171 172 ((struct mlx4_qp_context *) (mailbox->buf + 8))->local_qpn = 173 cpu_to_be32(qp->qpn); 174 175 ret = mlx4_cmd(dev, mailbox->dma, 176 qp->qpn | (!!sqd_event << 31), 177 new_state == MLX4_QP_STATE_RST ? 2 : 0, 178 op[cur_state][new_state], MLX4_CMD_TIME_CLASS_C, native); 179 180 if (mlx4_is_master(dev) && is_master_qp0(dev, qp, &real_qp0, &proxy_qp0)) { 181 port = (qp->qpn & 1) + 1; 182 if (cur_state != MLX4_QP_STATE_ERR && 183 cur_state != MLX4_QP_STATE_RST && 184 new_state == MLX4_QP_STATE_ERR) { 185 if (proxy_qp0) 186 priv->mfunc.master.qp0_state[port].proxy_qp0_active = 0; 187 else 188 priv->mfunc.master.qp0_state[port].qp0_active = 0; 189 } else if (new_state == MLX4_QP_STATE_RTR) { 190 if (proxy_qp0) 191 priv->mfunc.master.qp0_state[port].proxy_qp0_active = 1; 192 else 193 priv->mfunc.master.qp0_state[port].qp0_active = 1; 194 } 195 } 196 197 mlx4_free_cmd_mailbox(dev, mailbox); 198 return ret; 199} 200 201int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 202 enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state, 203 struct mlx4_qp_context *context, 204 enum mlx4_qp_optpar optpar, 205 int sqd_event, struct mlx4_qp *qp) 206{ 207 return __mlx4_qp_modify(dev, mtt, cur_state, new_state, context, 208 optpar, sqd_event, qp, 0); 209} 210EXPORT_SYMBOL_GPL(mlx4_qp_modify); 211 212int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, 213 int *base, u8 bf_qp) 214{ 215 struct mlx4_priv *priv = mlx4_priv(dev); 216 struct mlx4_qp_table *qp_table = &priv->qp_table; 217 218 if (cnt > MLX4_MAX_BF_QP_RANGE && bf_qp) 219 return -ENOMEM; 220 221 *base = mlx4_bitmap_alloc_range(&qp_table->bitmap, cnt, align, 222 bf_qp ? MLX4_BF_QP_SKIP_MASK : 0); 223 if (*base == -1) 224 return -ENOMEM; 225 226 return 0; 227} 228 229int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, 230 int *base, u8 bf_qp) 231{ 232 u64 in_param = 0; 233 u64 out_param; 234 int err; 235 236 if (mlx4_is_mfunc(dev)) { 237 set_param_l(&in_param, (((!!bf_qp) << 31) | (u32)cnt)); 238 set_param_h(&in_param, align); 239 err = mlx4_cmd_imm(dev, in_param, &out_param, 240 RES_QP, RES_OP_RESERVE, 241 MLX4_CMD_ALLOC_RES, 242 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 243 if (err) 244 return err; 245 246 *base = get_param_l(&out_param); 247 return 0; 248 } 249 return __mlx4_qp_reserve_range(dev, cnt, align, base, bf_qp); 250} 251EXPORT_SYMBOL_GPL(mlx4_qp_reserve_range); 252 253void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt) 254{ 255 struct mlx4_priv *priv = mlx4_priv(dev); 256 struct mlx4_qp_table *qp_table = &priv->qp_table; 257 258 if (mlx4_is_qp_reserved(dev, (u32) base_qpn)) 259 return; 260 mlx4_bitmap_free_range(&qp_table->bitmap, base_qpn, cnt); 261} 262 263void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt) 264{ 265 u64 in_param = 0; 266 int err; 267 268 if (mlx4_is_mfunc(dev)) { 269 set_param_l(&in_param, base_qpn); 270 set_param_h(&in_param, cnt); 271 err = mlx4_cmd(dev, in_param, RES_QP, RES_OP_RESERVE, 272 MLX4_CMD_FREE_RES, 273 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 274 if (err) { 275 mlx4_warn(dev, "Failed to release qp range" 276 " base:%d cnt:%d\n", base_qpn, cnt); 277 } 278 } else 279 __mlx4_qp_release_range(dev, base_qpn, cnt); 280} 281EXPORT_SYMBOL_GPL(mlx4_qp_release_range); 282 283int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn) 284{ 285 struct mlx4_priv *priv = mlx4_priv(dev); 286 struct mlx4_qp_table *qp_table = &priv->qp_table; 287 int err; 288 289 err = mlx4_table_get(dev, &qp_table->qp_table, qpn); 290 if (err) 291 goto err_out; 292 293 err = mlx4_table_get(dev, &qp_table->auxc_table, qpn); 294 if (err) 295 goto err_put_qp; 296 297 err = mlx4_table_get(dev, &qp_table->altc_table, qpn); 298 if (err) 299 goto err_put_auxc; 300 301 err = mlx4_table_get(dev, &qp_table->rdmarc_table, qpn); 302 if (err) 303 goto err_put_altc; 304 305 err = mlx4_table_get(dev, &qp_table->cmpt_table, qpn); 306 if (err) 307 goto err_put_rdmarc; 308 309 return 0; 310 311err_put_rdmarc: 312 mlx4_table_put(dev, &qp_table->rdmarc_table, qpn); 313 314err_put_altc: 315 mlx4_table_put(dev, &qp_table->altc_table, qpn); 316 317err_put_auxc: 318 mlx4_table_put(dev, &qp_table->auxc_table, qpn); 319 320err_put_qp: 321 mlx4_table_put(dev, &qp_table->qp_table, qpn); 322 323err_out: 324 return err; 325} 326 327static int mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn) 328{ 329 u64 param = 0; 330 331 if (mlx4_is_mfunc(dev)) { 332 set_param_l(¶m, qpn); 333 return mlx4_cmd_imm(dev, param, ¶m, RES_QP, RES_OP_MAP_ICM, 334 MLX4_CMD_ALLOC_RES, MLX4_CMD_TIME_CLASS_A, 335 MLX4_CMD_WRAPPED); 336 } 337 return __mlx4_qp_alloc_icm(dev, qpn); 338} 339 340void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn) 341{ 342 struct mlx4_priv *priv = mlx4_priv(dev); 343 struct mlx4_qp_table *qp_table = &priv->qp_table; 344 345 mlx4_table_put(dev, &qp_table->cmpt_table, qpn); 346 mlx4_table_put(dev, &qp_table->rdmarc_table, qpn); 347 mlx4_table_put(dev, &qp_table->altc_table, qpn); 348 mlx4_table_put(dev, &qp_table->auxc_table, qpn); 349 mlx4_table_put(dev, &qp_table->qp_table, qpn); 350} 351 352static void mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn) 353{ 354 u64 in_param = 0; 355 356 if (mlx4_is_mfunc(dev)) { 357 set_param_l(&in_param, qpn); 358 if (mlx4_cmd(dev, in_param, RES_QP, RES_OP_MAP_ICM, 359 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A, 360 MLX4_CMD_WRAPPED)) 361 mlx4_warn(dev, "Failed to free icm of qp:%d\n", qpn); 362 } else 363 __mlx4_qp_free_icm(dev, qpn); 364} 365 366int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp) 367{ 368 struct mlx4_priv *priv = mlx4_priv(dev); 369 struct mlx4_qp_table *qp_table = &priv->qp_table; 370 int err; 371 372 if (!qpn) 373 return -EINVAL; 374 375 qp->qpn = qpn; 376 377 err = mlx4_qp_alloc_icm(dev, qpn); 378 if (err) 379 return err; 380 381 spin_lock_irq(&qp_table->lock); 382 err = radix_tree_insert(&dev->qp_table_tree, qp->qpn & 383 (dev->caps.num_qps - 1), qp); 384 spin_unlock_irq(&qp_table->lock); 385 if (err) 386 goto err_icm; 387 388 atomic_set(&qp->refcount, 1); 389 init_completion(&qp->free); 390 391 return 0; 392 393err_icm: 394 mlx4_qp_free_icm(dev, qpn); 395 return err; 396} 397 398EXPORT_SYMBOL_GPL(mlx4_qp_alloc); 399 400void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp) 401{ 402 struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table; 403 unsigned long flags; 404 405 spin_lock_irqsave(&qp_table->lock, flags); 406 radix_tree_delete(&dev->qp_table_tree, qp->qpn & (dev->caps.num_qps - 1)); 407 spin_unlock_irqrestore(&qp_table->lock, flags); 408} 409EXPORT_SYMBOL_GPL(mlx4_qp_remove); 410 411void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp) 412{ 413 if (atomic_dec_and_test(&qp->refcount)) 414 complete(&qp->free); 415 wait_for_completion(&qp->free); 416 417 mlx4_qp_free_icm(dev, qp->qpn); 418} 419EXPORT_SYMBOL_GPL(mlx4_qp_free); 420 421static int mlx4_CONF_SPECIAL_QP(struct mlx4_dev *dev, u32 base_qpn) 422{ 423 return mlx4_cmd(dev, 0, base_qpn, 0, MLX4_CMD_CONF_SPECIAL_QP, 424 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 425} 426 427int mlx4_init_qp_table(struct mlx4_dev *dev) 428{ 429 struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table; 430 int err; 431 int reserved_from_top = 0; 432 int reserved_from_bot; 433 int k; 434 435 spin_lock_init(&qp_table->lock); 436 INIT_RADIX_TREE(&dev->qp_table_tree, GFP_ATOMIC); 437 if (mlx4_is_slave(dev)) 438 return 0; 439 440 /* 441 * We reserve 2 extra QPs per port for the special QPs. The 442 * block of special QPs must be aligned to a multiple of 8, so 443 * round up. 444 * 445 * We also reserve the MSB of the 24-bit QP number to indicate 446 * that a QP is an XRC QP. 447 */ 448 dev->phys_caps.base_sqpn = 449 ALIGN(dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 8); 450 451 { 452 int sort[MLX4_NUM_QP_REGION]; 453 int i, j, tmp; 454 int last_base = dev->caps.num_qps; 455 456 for (i = 1; i < MLX4_NUM_QP_REGION; ++i) 457 sort[i] = i; 458 459 for (i = MLX4_NUM_QP_REGION; i > 0; --i) { 460 for (j = 2; j < i; ++j) { 461 if (dev->caps.reserved_qps_cnt[sort[j]] > 462 dev->caps.reserved_qps_cnt[sort[j - 1]]) { 463 tmp = sort[j]; 464 sort[j] = sort[j - 1]; 465 sort[j - 1] = tmp; 466 } 467 } 468 } 469 470 for (i = 1; i < MLX4_NUM_QP_REGION; ++i) { 471 last_base -= dev->caps.reserved_qps_cnt[sort[i]]; 472 dev->caps.reserved_qps_base[sort[i]] = last_base; 473 reserved_from_top += 474 dev->caps.reserved_qps_cnt[sort[i]]; 475 } 476 477 } 478 479 /* Reserve 8 real SQPs in both native and SRIOV modes. 480 * In addition, in SRIOV mode, reserve 8 proxy SQPs per function 481 * (for all PFs and VFs), and 8 corresponding tunnel QPs. 482 * Each proxy SQP works opposite its own tunnel QP. 483 * 484 * The QPs are arranged as follows: 485 * a. 8 real SQPs 486 * b. All the proxy SQPs (8 per function) 487 * c. All the tunnel QPs (8 per function) 488 */ 489 reserved_from_bot = mlx4_num_reserved_sqps(dev); 490 if (reserved_from_bot + reserved_from_top > dev->caps.num_qps) { 491 mlx4_err(dev, "Number of reserved QPs is higher than number " 492 "of QPs, increase the value of log_num_qp\n"); 493 return -EINVAL; 494 } 495 496 err = mlx4_bitmap_init(&qp_table->bitmap, dev->caps.num_qps, 497 (1 << 23) - 1, reserved_from_bot, 498 reserved_from_top); 499 if (err) 500 return err; 501 502 if (mlx4_is_mfunc(dev)) { 503 /* for PPF use */ 504 dev->phys_caps.base_proxy_sqpn = dev->phys_caps.base_sqpn + 8; 505 dev->phys_caps.base_tunnel_sqpn = dev->phys_caps.base_sqpn + 8 + 8 * MLX4_MFUNC_MAX; 506 507 /* In mfunc, calculate proxy and tunnel qp offsets for the PF here, 508 * since the PF does not call mlx4_slave_caps */ 509 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); 510 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); 511 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); 512 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); 513 514 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy || 515 !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy) { 516 err = -ENOMEM; 517 goto err_mem; 518 } 519 520 for (k = 0; k < dev->caps.num_ports; k++) { 521 dev->caps.qp0_proxy[k] = dev->phys_caps.base_proxy_sqpn + 522 8 * mlx4_master_func_num(dev) + k; 523 dev->caps.qp0_tunnel[k] = dev->caps.qp0_proxy[k] + 8 * MLX4_MFUNC_MAX; 524 dev->caps.qp1_proxy[k] = dev->phys_caps.base_proxy_sqpn + 525 8 * mlx4_master_func_num(dev) + MLX4_MAX_PORTS + k; 526 dev->caps.qp1_tunnel[k] = dev->caps.qp1_proxy[k] + 8 * MLX4_MFUNC_MAX; 527 } 528 } 529 530 531 err = mlx4_CONF_SPECIAL_QP(dev, dev->phys_caps.base_sqpn); 532 if (err) 533 goto err_mem; 534 return 0; 535 536err_mem: 537 kfree(dev->caps.qp0_tunnel); 538 kfree(dev->caps.qp0_proxy); 539 kfree(dev->caps.qp1_tunnel); 540 kfree(dev->caps.qp1_proxy); 541 dev->caps.qp0_tunnel = dev->caps.qp0_proxy = 542 dev->caps.qp1_tunnel = dev->caps.qp1_proxy = NULL; 543 return err; 544} 545 546void mlx4_cleanup_qp_table(struct mlx4_dev *dev) 547{ 548 if (mlx4_is_slave(dev)) 549 return; 550 551 mlx4_CONF_SPECIAL_QP(dev, 0); 552 mlx4_bitmap_cleanup(&mlx4_priv(dev)->qp_table.bitmap); 553} 554 555int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp, 556 struct mlx4_qp_context *context) 557{ 558 struct mlx4_cmd_mailbox *mailbox; 559 int err; 560 561 mailbox = mlx4_alloc_cmd_mailbox(dev); 562 if (IS_ERR(mailbox)) 563 return PTR_ERR(mailbox); 564 565 err = mlx4_cmd_box(dev, 0, mailbox->dma, qp->qpn, 0, 566 MLX4_CMD_QUERY_QP, MLX4_CMD_TIME_CLASS_A, 567 MLX4_CMD_WRAPPED); 568 if (!err) 569 memcpy(context, mailbox->buf + 8, sizeof *context); 570 571 mlx4_free_cmd_mailbox(dev, mailbox); 572 return err; 573} 574EXPORT_SYMBOL_GPL(mlx4_qp_query); 575 576int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 577 struct mlx4_qp_context *context, 578 struct mlx4_qp *qp, enum mlx4_qp_state *qp_state) 579{ 580 int err; 581 int i; 582 enum mlx4_qp_state states[] = { 583 MLX4_QP_STATE_RST, 584 MLX4_QP_STATE_INIT, 585 MLX4_QP_STATE_RTR, 586 MLX4_QP_STATE_RTS 587 }; 588 589 for (i = 0; i < ARRAY_SIZE(states) - 1; i++) { 590 context->flags &= cpu_to_be32(~(0xf << 28)); 591 context->flags |= cpu_to_be32(states[i + 1] << 28); 592 err = mlx4_qp_modify(dev, mtt, states[i], states[i + 1], 593 context, 0, 0, qp); 594 if (err) { 595 mlx4_err(dev, "Failed to bring QP to state: " 596 "%d with error: %d\n", 597 states[i + 1], err); 598 return err; 599 } 600 601 *qp_state = states[i + 1]; 602 } 603 604 return 0; 605} 606EXPORT_SYMBOL_GPL(mlx4_qp_to_ready); 607