mlx4_en.h revision 318540 
1/*
2 * Copyright (c) 2007, 2014 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses.  You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 *     Redistribution and use in source and binary forms, with or
11 *     without modification, are permitted provided that the following
12 *     conditions are met:
13 *
14 *      - Redistributions of source code must retain the above
15 *        copyright notice, this list of conditions and the following
16 *        disclaimer.
17 *
18 *      - Redistributions in binary form must reproduce the above
19 *        copyright notice, this list of conditions and the following
20 *        disclaimer in the documentation and/or other materials
21 *        provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34#ifndef _MLX4_EN_H_
35#define _MLX4_EN_H_
36
37#include <linux/bitops.h>
38#include <linux/compiler.h>
39#include <linux/list.h>
40#include <linux/mutex.h>
41#include <linux/kobject.h>
42#include <linux/netdevice.h>
43#include <linux/if_vlan.h>
44#include <linux/if_ether.h>
45#ifdef CONFIG_MLX4_EN_DCB
46#include <linux/dcbnl.h>
47#endif
48
49#include <linux/mlx4/device.h>
50#include <linux/mlx4/qp.h>
51#include <linux/mlx4/cq.h>
52#include <linux/mlx4/srq.h>
53#include <linux/mlx4/doorbell.h>
54#include <linux/mlx4/cmd.h>
55
56#include <netinet/tcp_lro.h>
57
58#include "en_port.h"
59#include "mlx4_stats.h"
60
61#define DRV_NAME	"mlx4_en"
62
63#define MLX4_EN_MSG_LEVEL	(NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
64
65/*
66 * Device constants
67 */
68
69
70#define MLX4_EN_PAGE_SHIFT	12
71#define MLX4_EN_PAGE_SIZE	(1 << MLX4_EN_PAGE_SHIFT)
72#define	MLX4_NET_IP_ALIGN	2	/* bytes */
73#define DEF_RX_RINGS		16
74#define MAX_RX_RINGS		128
75#define MIN_RX_RINGS		4
76#define TXBB_SIZE		64
77#define HEADROOM		(2048 / TXBB_SIZE + 1)
78#define STAMP_STRIDE		64
79#define STAMP_DWORDS		(STAMP_STRIDE / 4)
80#define STAMP_SHIFT		31
81#define STAMP_VAL		0x7fffffff
82#define STATS_DELAY		(HZ / 4)
83#define SERVICE_TASK_DELAY	(HZ / 4)
84#define MAX_NUM_OF_FS_RULES	256
85
86#define MLX4_EN_FILTER_HASH_SHIFT 4
87#define MLX4_EN_FILTER_EXPIRY_QUOTA 60
88
89#ifdef CONFIG_NET_RX_BUSY_POLL
90#define LL_EXTENDED_STATS
91#endif
92
93/* vlan valid range */
94#define VLAN_MIN_VALUE		1
95#define VLAN_MAX_VALUE		4094
96
97/*
98 * OS related constants and tunables
99 */
100
101#define MLX4_EN_WATCHDOG_TIMEOUT	(15 * HZ)
102
103#define MLX4_EN_ALLOC_SIZE     PAGE_ALIGN(PAGE_SIZE)
104#define MLX4_EN_ALLOC_ORDER    get_order(MLX4_EN_ALLOC_SIZE)
105
106enum mlx4_en_alloc_type {
107	MLX4_EN_ALLOC_NEW = 0,
108	MLX4_EN_ALLOC_REPLACEMENT = 1,
109};
110
111/* Maximum ring sizes */
112#define MLX4_EN_DEF_TX_QUEUE_SIZE       4096
113
114/* Minimum packet number till arming the CQ */
115#define MLX4_EN_MIN_RX_ARM	2048
116#define MLX4_EN_MIN_TX_ARM	2048
117
118/* Maximum ring sizes */
119#define MLX4_EN_MAX_TX_SIZE	8192
120#define MLX4_EN_MAX_RX_SIZE	8192
121
122/* Minimum ring sizes */
123#define MLX4_EN_MIN_RX_SIZE	(4096 / TXBB_SIZE)
124#define MLX4_EN_MIN_TX_SIZE	(4096 / TXBB_SIZE)
125
126#define MLX4_EN_SMALL_PKT_SIZE		64
127
128#define MLX4_EN_MAX_TX_RING_P_UP	32
129#define MLX4_EN_NUM_UP			1
130
131#define MAX_TX_RINGS			(MLX4_EN_MAX_TX_RING_P_UP * \
132					MLX4_EN_NUM_UP)
133
134#define MLX4_EN_DEF_TX_RING_SIZE	1024
135#define MLX4_EN_DEF_RX_RING_SIZE  	1024
136
137/* Target number of bytes to coalesce with interrupt moderation */
138#define MLX4_EN_RX_COAL_TARGET	0x20000
139#define MLX4_EN_RX_COAL_TIME	0x10
140
141#define MLX4_EN_TX_COAL_PKTS	64
142#define MLX4_EN_TX_COAL_TIME	64
143
144#define MLX4_EN_RX_RATE_LOW		400000
145#define MLX4_EN_RX_COAL_TIME_LOW	0
146#define MLX4_EN_RX_RATE_HIGH		450000
147#define MLX4_EN_RX_COAL_TIME_HIGH	128
148#define MLX4_EN_RX_SIZE_THRESH		1024
149#define MLX4_EN_RX_RATE_THRESH		(1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
150#define MLX4_EN_SAMPLE_INTERVAL		0
151#define MLX4_EN_AVG_PKT_SMALL		256
152
153#define MLX4_EN_AUTO_CONF	0xffff
154
155#define MLX4_EN_DEF_RX_PAUSE	1
156#define MLX4_EN_DEF_TX_PAUSE	1
157
158/* Interval between successive polls in the Tx routine when polling is used
159   instead of interrupts (in per-core Tx rings) - should be power of 2 */
160#define MLX4_EN_TX_POLL_MODER	16
161#define MLX4_EN_TX_POLL_TIMEOUT	(HZ / 4)
162
163#define MLX4_EN_64_ALIGN	(64 - NET_SKB_PAD)
164#define SMALL_PACKET_SIZE      (256 - NET_IP_ALIGN)
165#define HEADER_COPY_SIZE       (128)
166#define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETHER_HDR_LEN)
167
168#define MLX4_EN_MIN_MTU		46
169#define ETH_BCAST		0xffffffffffffULL
170
171#define MLX4_EN_LOOPBACK_RETRIES	5
172#define MLX4_EN_LOOPBACK_TIMEOUT	100
173
174#ifdef MLX4_EN_PERF_STAT
175/* Number of samples to 'average' */
176#define AVG_SIZE			128
177#define AVG_FACTOR			1024
178
179#define INC_PERF_COUNTER(cnt)		(++(cnt))
180#define ADD_PERF_COUNTER(cnt, add)	((cnt) += (add))
181#define AVG_PERF_COUNTER(cnt, sample) \
182	((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
183#define GET_PERF_COUNTER(cnt)		(cnt)
184#define GET_AVG_PERF_COUNTER(cnt)	((cnt) / AVG_FACTOR)
185
186#else
187
188#define INC_PERF_COUNTER(cnt)		do {} while (0)
189#define ADD_PERF_COUNTER(cnt, add)	do {} while (0)
190#define AVG_PERF_COUNTER(cnt, sample)	do {} while (0)
191#define GET_PERF_COUNTER(cnt)		(0)
192#define GET_AVG_PERF_COUNTER(cnt)	(0)
193#endif /* MLX4_EN_PERF_STAT */
194
195/*
196 * Configurables
197 */
198
199enum cq_type {
200	RX = 0,
201	TX = 1,
202};
203
204
205/*
206 * Useful macros
207 */
208#define ROUNDUP_LOG2(x)		ilog2(roundup_pow_of_two(x))
209#define XNOR(x, y)		(!(x) == !(y))
210#define ILLEGAL_MAC(addr)	(addr == 0xffffffffffffULL || addr == 0x0)
211
212struct mlx4_en_tx_info {
213	bus_dmamap_t dma_map;
214        struct mbuf *mb;
215        u32 nr_txbb;
216	u32 nr_bytes;
217};
218
219
220#define MLX4_EN_BIT_DESC_OWN	0x80000000
221#define CTRL_SIZE	sizeof(struct mlx4_wqe_ctrl_seg)
222#define MLX4_EN_MEMTYPE_PAD	0x100
223#define DS_SIZE		sizeof(struct mlx4_wqe_data_seg)
224
225
226struct mlx4_en_tx_desc {
227	struct mlx4_wqe_ctrl_seg ctrl;
228	union {
229		struct mlx4_wqe_data_seg data; /* at least one data segment */
230		struct mlx4_wqe_lso_seg lso;
231		struct mlx4_wqe_inline_seg inl;
232	};
233};
234
235#define MLX4_EN_USE_SRQ		0x01000000
236
237#define MLX4_EN_RX_BUDGET 64
238
239#define	MLX4_EN_TX_MAX_DESC_SIZE 512	/* bytes */
240#define	MLX4_EN_TX_MAX_MBUF_SIZE 65536	/* bytes */
241#define	MLX4_EN_TX_MAX_PAYLOAD_SIZE 65536	/* bytes */
242#define	MLX4_EN_TX_MAX_MBUF_FRAGS \
243    ((MLX4_EN_TX_MAX_DESC_SIZE - 128) / DS_SIZE_ALIGNMENT) /* units */
244#define	MLX4_EN_TX_WQE_MAX_WQEBBS			\
245    (MLX4_EN_TX_MAX_DESC_SIZE / TXBB_SIZE) /* units */
246
247#define MLX4_EN_CX3_LOW_ID	0x1000
248#define MLX4_EN_CX3_HIGH_ID	0x1005
249
250struct mlx4_en_tx_ring {
251        spinlock_t tx_lock;
252	bus_dma_tag_t dma_tag;
253	struct mlx4_hwq_resources wqres;
254	u32 size ; /* number of TXBBs */
255	u32 size_mask;
256	u16 stride;
257	u16 cqn;	/* index of port CQ associated with this ring */
258	u32 prod;
259	u32 cons;
260	u32 buf_size;
261	u32 doorbell_qpn;
262	u8 *buf;
263	u16 poll_cnt;
264	int blocked;
265	struct mlx4_en_tx_info *tx_info;
266	u8 queue_index;
267	cpuset_t affinity_mask;
268	struct buf_ring *br;
269	u32 last_nr_txbb;
270	struct mlx4_qp qp;
271	struct mlx4_qp_context context;
272	int qpn;
273	enum mlx4_qp_state qp_state;
274	struct mlx4_srq dummy;
275	unsigned long bytes;
276	unsigned long packets;
277	unsigned long tx_csum;
278	unsigned long queue_stopped;
279	unsigned long oversized_packets;
280	unsigned long wake_queue;
281	struct mlx4_bf bf;
282	bool bf_enabled;
283	int hwtstamp_tx_type;
284	spinlock_t comp_lock;
285	int inline_thold;
286	u64 watchdog_time;
287};
288
289struct mlx4_en_rx_desc {
290	/* actual number of entries depends on rx ring stride */
291	struct mlx4_wqe_data_seg data[0];
292};
293
294struct mlx4_en_rx_mbuf {
295	bus_dmamap_t dma_map;
296	struct mbuf *mbuf;
297};
298
299struct mlx4_en_rx_spare {
300	bus_dmamap_t dma_map;
301	struct mbuf *mbuf;
302	u64 paddr_be;
303};
304
305struct mlx4_en_rx_ring {
306	struct mlx4_hwq_resources wqres;
307	bus_dma_tag_t dma_tag;
308	struct mlx4_en_rx_spare spare;
309	u32 size ;	/* number of Rx descs*/
310	u32 actual_size;
311	u32 size_mask;
312	u16 stride;
313	u16 log_stride;
314	u16 cqn;	/* index of port CQ associated with this ring */
315	u32 prod;
316	u32 cons;
317	u32 buf_size;
318	u8  fcs_del;
319	u32 rx_mb_size;
320	int qpn;
321	u8 *buf;
322	struct mlx4_en_rx_mbuf *mbuf;
323	unsigned long errors;
324	unsigned long bytes;
325	unsigned long packets;
326#ifdef LL_EXTENDED_STATS
327	unsigned long yields;
328	unsigned long misses;
329	unsigned long cleaned;
330#endif
331	unsigned long csum_ok;
332	unsigned long csum_none;
333	int hwtstamp_rx_filter;
334	int numa_node;
335	struct lro_ctrl lro;
336};
337
338static inline int mlx4_en_can_lro(__be16 status)
339{
340	const __be16 status_all = cpu_to_be16(
341			MLX4_CQE_STATUS_IPV4    |
342			MLX4_CQE_STATUS_IPV4F   |
343			MLX4_CQE_STATUS_IPV6    |
344			MLX4_CQE_STATUS_IPV4OPT |
345			MLX4_CQE_STATUS_TCP     |
346			MLX4_CQE_STATUS_UDP     |
347			MLX4_CQE_STATUS_IPOK);
348	const __be16 status_ipv4_ipok_tcp = cpu_to_be16(
349			MLX4_CQE_STATUS_IPV4    |
350			MLX4_CQE_STATUS_IPOK    |
351			MLX4_CQE_STATUS_TCP);
352	const __be16 status_ipv6_ipok_tcp = cpu_to_be16(
353			MLX4_CQE_STATUS_IPV6    |
354			MLX4_CQE_STATUS_IPOK    |
355			MLX4_CQE_STATUS_TCP);
356
357	status &= status_all;
358	return (status == status_ipv4_ipok_tcp ||
359			status == status_ipv6_ipok_tcp);
360}
361
362struct mlx4_en_cq {
363	struct mlx4_cq          mcq;
364	struct mlx4_hwq_resources wqres;
365	int                     ring;
366	spinlock_t              lock;
367	struct net_device      *dev;
368        /* Per-core Tx cq processing support */
369        struct timer_list timer;
370	int size;
371	int buf_size;
372	unsigned vector;
373	enum cq_type is_tx;
374	u16 moder_time;
375	u16 moder_cnt;
376	struct mlx4_cqe *buf;
377	struct task cq_task;
378	struct taskqueue *tq;
379#define MLX4_EN_OPCODE_ERROR	0x1e
380	u32 tot_rx;
381	u32 tot_tx;
382	u32 curr_poll_rx_cpu_id;
383
384#ifdef CONFIG_NET_RX_BUSY_POLL
385	unsigned int state;
386#define MLX4_EN_CQ_STATEIDLE        0
387#define MLX4_EN_CQ_STATENAPI     1    /* NAPI owns this CQ */
388#define MLX4_EN_CQ_STATEPOLL     2    /* poll owns this CQ */
389#define MLX4_CQ_LOCKED (MLX4_EN_CQ_STATENAPI | MLX4_EN_CQ_STATEPOLL)
390#define MLX4_EN_CQ_STATENAPI_YIELD  4    /* NAPI yielded this CQ */
391#define MLX4_EN_CQ_STATEPOLL_YIELD  8    /* poll yielded this CQ */
392#define CQ_YIELD (MLX4_EN_CQ_STATENAPI_YIELD | MLX4_EN_CQ_STATEPOLL_YIELD)
393#define CQ_USER_PEND (MLX4_EN_CQ_STATEPOLL | MLX4_EN_CQ_STATEPOLL_YIELD)
394	spinlock_t poll_lock; /* protects from LLS/napi conflicts */
395#endif  /* CONFIG_NET_RX_BUSY_POLL */
396};
397
398struct mlx4_en_port_profile {
399	u32 flags;
400	u32 tx_ring_num;
401	u32 rx_ring_num;
402	u32 tx_ring_size;
403	u32 rx_ring_size;
404	u8 rx_pause;
405	u8 rx_ppp;
406	u8 tx_pause;
407	u8 tx_ppp;
408	int rss_rings;
409};
410
411struct mlx4_en_profile {
412	int rss_xor;
413	int udp_rss;
414	u8 rss_mask;
415	u32 active_ports;
416	u32 small_pkt_int;
417	u8 no_reset;
418	u8 num_tx_rings_p_up;
419	struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
420};
421
422struct mlx4_en_dev {
423	struct mlx4_dev		*dev;
424	struct pci_dev		*pdev;
425	struct mutex		state_lock;
426	struct net_device	*pndev[MLX4_MAX_PORTS + 1];
427	u32			port_cnt;
428	bool			device_up;
429	struct mlx4_en_profile	profile;
430	u32			LSO_support;
431	struct workqueue_struct *workqueue;
432	struct device		*dma_device;
433	void __iomem		*uar_map;
434	struct mlx4_uar		priv_uar;
435	struct mlx4_mr		mr;
436	u32			priv_pdn;
437	spinlock_t		uar_lock;
438	u8			mac_removed[MLX4_MAX_PORTS + 1];
439	unsigned long		last_overflow_check;
440	unsigned long		overflow_period;
441};
442
443
444struct mlx4_en_rss_map {
445	int base_qpn;
446	struct mlx4_qp qps[MAX_RX_RINGS];
447	enum mlx4_qp_state state[MAX_RX_RINGS];
448	struct mlx4_qp indir_qp;
449	enum mlx4_qp_state indir_state;
450};
451
452struct mlx4_en_port_state {
453	int link_state;
454	int link_speed;
455	int transciver;
456	int autoneg;
457};
458
459enum mlx4_en_mclist_act {
460	MCLIST_NONE,
461	MCLIST_REM,
462	MCLIST_ADD,
463};
464
465struct mlx4_en_mc_list {
466	struct list_head	list;
467	enum mlx4_en_mclist_act	action;
468	u8			addr[ETH_ALEN];
469	u64			reg_id;
470};
471
472#ifdef CONFIG_MLX4_EN_DCB
473/* Minimal TC BW - setting to 0 will block traffic */
474#define MLX4_EN_BW_MIN 1
475#define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
476
477#define MLX4_EN_TC_ETS 7
478
479#endif
480
481
482enum {
483	MLX4_EN_FLAG_PROMISC		= (1 << 0),
484	MLX4_EN_FLAG_MC_PROMISC		= (1 << 1),
485	/* whether we need to enable hardware loopback by putting dmac
486	 * in Tx WQE
487	 */
488	MLX4_EN_FLAG_ENABLE_HW_LOOPBACK	= (1 << 2),
489	/* whether we need to drop packets that hardware loopback-ed */
490	MLX4_EN_FLAG_RX_FILTER_NEEDED	= (1 << 3),
491	MLX4_EN_FLAG_FORCE_PROMISC	= (1 << 4),
492#ifdef CONFIG_MLX4_EN_DCB
493	MLX4_EN_FLAG_DCB_ENABLED	= (1 << 5)
494#endif
495};
496
497#define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE)
498#define MLX4_EN_MAC_HASH_IDX 5
499
500struct en_port {
501	struct kobject		kobj;
502	struct mlx4_dev		*dev;
503	u8			port_num;
504	u8			vport_num;
505};
506
507struct mlx4_en_priv {
508	struct mlx4_en_dev *mdev;
509	struct mlx4_en_port_profile *prof;
510	struct net_device *dev;
511	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
512	struct mlx4_en_port_state port_state;
513	spinlock_t stats_lock;
514	/* To allow rules removal while port is going down */
515	struct list_head ethtool_list;
516
517	unsigned long last_moder_packets[MAX_RX_RINGS];
518	unsigned long last_moder_tx_packets;
519	unsigned long last_moder_bytes[MAX_RX_RINGS];
520	unsigned long last_moder_jiffies;
521	int last_moder_time[MAX_RX_RINGS];
522	u16 rx_usecs;
523	u16 rx_frames;
524	u16 tx_usecs;
525	u16 tx_frames;
526	u32 pkt_rate_low;
527	u32 rx_usecs_low;
528	u32 pkt_rate_high;
529	u32 rx_usecs_high;
530	u32 sample_interval;
531	u32 adaptive_rx_coal;
532	u32 msg_enable;
533	u32 loopback_ok;
534	u32 validate_loopback;
535
536	struct mlx4_hwq_resources res;
537	int link_state;
538	int last_link_state;
539	bool port_up;
540	int port;
541	int registered;
542	int allocated;
543	int stride;
544	unsigned char current_mac[ETH_ALEN + 2];
545        u64 mac;
546	int mac_index;
547	unsigned max_mtu;
548	int base_qpn;
549	int cqe_factor;
550
551	struct mlx4_en_rss_map rss_map;
552	u32 flags;
553	u8 num_tx_rings_p_up;
554	u32 tx_ring_num;
555	u32 rx_ring_num;
556	u32 rx_mb_size;
557
558	struct mlx4_en_tx_ring **tx_ring;
559	struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS];
560	struct mlx4_en_cq **tx_cq;
561	struct mlx4_en_cq *rx_cq[MAX_RX_RINGS];
562	struct mlx4_qp drop_qp;
563	struct work_struct rx_mode_task;
564	struct work_struct watchdog_task;
565	struct work_struct linkstate_task;
566	struct delayed_work stats_task;
567	struct delayed_work service_task;
568	struct mlx4_en_perf_stats pstats;
569	struct mlx4_en_pkt_stats pkstats;
570	struct mlx4_en_flow_stats flowstats[MLX4_NUM_PRIORITIES];
571	struct mlx4_en_port_stats port_stats;
572	struct mlx4_en_vport_stats vport_stats;
573	struct mlx4_en_vf_stats vf_stats;
574	DECLARE_BITMAP(stats_bitmap, NUM_ALL_STATS);
575	struct list_head mc_list;
576	struct list_head curr_list;
577	u64 broadcast_id;
578	struct mlx4_en_stat_out_mbox hw_stats;
579	int vids[128];
580	bool wol;
581	struct device *ddev;
582	struct dentry *dev_root;
583	u32 counter_index;
584	eventhandler_tag vlan_attach;
585	eventhandler_tag vlan_detach;
586	struct callout watchdog_timer;
587        struct ifmedia media;
588	volatile int blocked;
589	struct sysctl_oid *conf_sysctl;
590	struct sysctl_oid *stat_sysctl;
591	struct sysctl_ctx_list conf_ctx;
592	struct sysctl_ctx_list stat_ctx;
593#define MLX4_EN_MAC_HASH_IDX 5
594	struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE];
595
596#ifdef CONFIG_MLX4_EN_DCB
597	struct ieee_ets ets;
598	u16 maxrate[IEEE_8021QAZ_MAX_TCS];
599	u8 dcbx_cap;
600#endif
601#ifdef CONFIG_RFS_ACCEL
602	spinlock_t filters_lock;
603	int last_filter_id;
604	struct list_head filters;
605	struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT];
606#endif
607	struct en_port *vf_ports[MLX4_MAX_NUM_VF];
608	unsigned long last_ifq_jiffies;
609	u64 if_counters_rx_errors;
610	u64 if_counters_rx_no_buffer;
611};
612
613enum mlx4_en_wol {
614	MLX4_EN_WOL_MAGIC = (1ULL << 61),
615	MLX4_EN_WOL_ENABLED = (1ULL << 62),
616};
617
618struct mlx4_mac_entry {
619	struct hlist_node hlist;
620	unsigned char mac[ETH_ALEN + 2];
621	u64 reg_id;
622};
623
624#ifdef CONFIG_NET_RX_BUSY_POLL
625static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq)
626{
627	spin_lock_init(&cq->poll_lock);
628	cq->state = MLX4_EN_CQ_STATEIDLE;
629}
630
631/* called from the device poll rutine to get ownership of a cq */
632static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq)
633{
634	int rc = true;
635	spin_lock(&cq->poll_lock);
636	if (cq->state & MLX4_CQ_LOCKED) {
637		WARN_ON(cq->state & MLX4_EN_CQ_STATENAPI);
638		cq->state |= MLX4_EN_CQ_STATENAPI_YIELD;
639		rc = false;
640	} else
641		/* we don't care if someone yielded */
642		cq->state = MLX4_EN_CQ_STATENAPI;
643	spin_unlock(&cq->poll_lock);
644	return rc;
645}
646
647/* returns true is someone tried to get the cq while napi had it */
648static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq)
649{
650	int rc = false;
651	spin_lock(&cq->poll_lock);
652	WARN_ON(cq->state & (MLX4_EN_CQ_STATEPOLL |
653			     MLX4_EN_CQ_STATENAPI_YIELD));
654
655	if (cq->state & MLX4_EN_CQ_STATEPOLL_YIELD)
656		rc = true;
657	cq->state = MLX4_EN_CQ_STATEIDLE;
658	spin_unlock(&cq->poll_lock);
659	return rc;
660}
661
662/* called from mlx4_en_low_latency_poll() */
663static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq)
664{
665	int rc = true;
666	spin_lock_bh(&cq->poll_lock);
667	if ((cq->state & MLX4_CQ_LOCKED)) {
668		struct net_device *dev = cq->dev;
669		struct mlx4_en_priv *priv = netdev_priv(dev);
670		struct mlx4_en_rx_ring *rx_ring = priv->rx_ring[cq->ring];
671
672		cq->state |= MLX4_EN_CQ_STATEPOLL_YIELD;
673		rc = false;
674#ifdef LL_EXTENDED_STATS
675		rx_ring->yields++;
676#endif
677	} else
678		/* preserve yield marks */
679		cq->state |= MLX4_EN_CQ_STATEPOLL;
680	spin_unlock_bh(&cq->poll_lock);
681	return rc;
682}
683
684/* returns true if someone tried to get the cq while it was locked */
685static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq)
686{
687	int rc = false;
688	spin_lock_bh(&cq->poll_lock);
689	WARN_ON(cq->state & (MLX4_EN_CQ_STATENAPI));
690
691	if (cq->state & MLX4_EN_CQ_STATEPOLL_YIELD)
692		rc = true;
693	cq->state = MLX4_EN_CQ_STATEIDLE;
694	spin_unlock_bh(&cq->poll_lock);
695	return rc;
696}
697
698/* true if a socket is polling, even if it did not get the lock */
699static inline bool mlx4_en_cq_ll_polling(struct mlx4_en_cq *cq)
700{
701	WARN_ON(!(cq->state & MLX4_CQ_LOCKED));
702	return cq->state & CQ_USER_PEND;
703}
704#else
705static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq)
706{
707}
708
709static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq)
710{
711	return true;
712}
713
714static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq)
715{
716	return false;
717}
718
719static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq)
720{
721	return false;
722}
723
724static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq)
725{
726	return false;
727}
728
729static inline bool mlx4_en_cq_ll_polling(struct mlx4_en_cq *cq)
730{
731	return false;
732}
733#endif /* CONFIG_NET_RX_BUSY_POLL */
734
735#define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
736
737void mlx4_en_destroy_netdev(struct net_device *dev);
738int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
739			struct mlx4_en_port_profile *prof);
740
741int mlx4_en_start_port(struct net_device *dev);
742void mlx4_en_stop_port(struct net_device *dev);
743
744void mlx4_en_free_resources(struct mlx4_en_priv *priv);
745int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
746
747int mlx4_en_pre_config(struct mlx4_en_priv *priv);
748int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq,
749		      int entries, int ring, enum cq_type mode, int node);
750void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq);
751int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
752			int cq_idx);
753void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
754int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
755int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
756
757void mlx4_en_tx_irq(struct mlx4_cq *mcq);
758u16 mlx4_en_select_queue(struct net_device *dev, struct mbuf *mb);
759
760int mlx4_en_transmit(struct ifnet *dev, struct mbuf *m);
761int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
762			   struct mlx4_en_tx_ring **pring,
763			   u32 size, u16 stride, int node, int queue_idx);
764void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
765			     struct mlx4_en_tx_ring **pring);
766int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
767			     struct mlx4_en_tx_ring *ring,
768			     int cq, int user_prio);
769void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
770				struct mlx4_en_tx_ring *ring);
771void mlx4_en_qflush(struct ifnet *dev);
772
773int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
774			   struct mlx4_en_rx_ring **pring,
775			   u32 size, int node);
776void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
777			     struct mlx4_en_rx_ring **pring,
778			     u32 size, u16 stride);
779void mlx4_en_tx_que(void *context, int pending);
780void mlx4_en_rx_que(void *context, int pending);
781int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
782void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
783				struct mlx4_en_rx_ring *ring);
784int mlx4_en_process_rx_cq(struct net_device *dev,
785			  struct mlx4_en_cq *cq,
786			  int budget);
787void mlx4_en_poll_tx_cq(unsigned long data);
788void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
789		int is_tx, int rss, int qpn, int cqn, int user_prio,
790		struct mlx4_qp_context *context);
791void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
792int mlx4_en_map_buffer(struct mlx4_buf *buf);
793void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
794void mlx4_en_calc_rx_buf(struct net_device *dev);
795
796int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
797void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
798int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);
799void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);
800int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
801void mlx4_en_rx_irq(struct mlx4_cq *mcq);
802
803int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
804int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
805
806int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
807int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
808int mlx4_en_get_vport_stats(struct mlx4_en_dev *mdev, u8 port);
809void mlx4_en_create_debug_files(struct mlx4_en_priv *priv);
810void mlx4_en_delete_debug_files(struct mlx4_en_priv *priv);
811int mlx4_en_register_debugfs(void);
812void mlx4_en_unregister_debugfs(void);
813
814#ifdef CONFIG_MLX4_EN_DCB
815extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
816extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops;
817#endif
818
819int mlx4_en_setup_tc(struct net_device *dev, u8 up);
820
821#ifdef CONFIG_RFS_ACCEL
822void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv,
823			     struct mlx4_en_rx_ring *rx_ring);
824#endif
825
826#define MLX4_EN_NUM_SELF_TEST	5
827void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
828void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev);
829
830/*
831 * Functions for time stamping
832 */
833#define SKBTX_HW_TSTAMP (1 << 0)
834#define SKBTX_IN_PROGRESS (1 << 2)
835
836u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe);
837
838/* Functions for caching and restoring statistics */
839int mlx4_en_get_sset_count(struct net_device *dev, int sset);
840void mlx4_en_restore_ethtool_stats(struct mlx4_en_priv *priv,
841				    u64 *data);
842
843/*
844 * Globals
845 */
846extern const struct ethtool_ops mlx4_en_ethtool_ops;
847
848/*
849 * Defines for link speed - needed by selftest
850 */
851#define MLX4_EN_LINK_SPEED_1G	1000
852#define MLX4_EN_LINK_SPEED_10G	10000
853#define MLX4_EN_LINK_SPEED_40G	40000
854
855enum {
856        NETIF_MSG_DRV           = 0x0001,
857        NETIF_MSG_PROBE         = 0x0002,
858        NETIF_MSG_LINK          = 0x0004,
859        NETIF_MSG_TIMER         = 0x0008,
860        NETIF_MSG_IFDOWN        = 0x0010,
861        NETIF_MSG_IFUP          = 0x0020,
862        NETIF_MSG_RX_ERR        = 0x0040,
863        NETIF_MSG_TX_ERR        = 0x0080,
864        NETIF_MSG_TX_QUEUED     = 0x0100,
865        NETIF_MSG_INTR          = 0x0200,
866        NETIF_MSG_TX_DONE       = 0x0400,
867        NETIF_MSG_RX_STATUS     = 0x0800,
868        NETIF_MSG_PKTDATA       = 0x1000,
869        NETIF_MSG_HW            = 0x2000,
870        NETIF_MSG_WOL           = 0x4000,
871};
872
873
874/*
875 * printk / logging functions
876 */
877
878#define en_print(level, priv, format, arg...)                   \
879        {                                                       \
880        if ((priv)->registered)                                 \
881                printk(level "%s: %s: " format, DRV_NAME,       \
882                        (priv->dev)->if_xname, ## arg); \
883        else                                                    \
884                printk(level "%s: %s: Port %d: " format,        \
885                        DRV_NAME, dev_name(&priv->mdev->pdev->dev), \
886                        (priv)->port, ## arg);                  \
887        }
888
889
890#define en_dbg(mlevel, priv, format, arg...)			\
891do {								\
892	if (NETIF_MSG_##mlevel & priv->msg_enable)		\
893		en_print(KERN_DEBUG, priv, format, ##arg);	\
894} while (0)
895#define en_warn(priv, format, arg...)			\
896	en_print(KERN_WARNING, priv, format, ##arg)
897#define en_err(priv, format, arg...)			\
898	en_print(KERN_ERR, priv, format, ##arg)
899#define en_info(priv, format, arg...)			\
900	en_print(KERN_INFO, priv, format, ## arg)
901
902#define mlx4_err(mdev, format, arg...)			\
903	pr_err("%s %s: " format, DRV_NAME,		\
904	       dev_name(&mdev->pdev->dev), ##arg)
905#define mlx4_info(mdev, format, arg...)			\
906	pr_info("%s %s: " format, DRV_NAME,		\
907		dev_name(&mdev->pdev->dev), ##arg)
908#define mlx4_warn(mdev, format, arg...)			\
909	pr_warning("%s %s: " format, DRV_NAME,		\
910		   dev_name(&mdev->pdev->dev), ##arg)
911
912#endif
913