main.c revision 272407
1/* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007, 2008, 2014 Mellanox Technologies. All rights reserved. 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * OpenIB.org BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or 14 * without modification, are permitted provided that the following 15 * conditions are met: 16 * 17 * - Redistributions of source code must retain the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer. 20 * 21 * - Redistributions in binary form must reproduce the above 22 * copyright notice, this list of conditions and the following 23 * disclaimer in the documentation and/or other materials 24 * provided with the distribution. 25 * 26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 33 * SOFTWARE. 34 */ 35 36#include <linux/kmod.h> 37/* 38 * kmod.h must be included before module.h since it includes (indirectly) sys/module.h 39 * To use the FBSD macro sys/module.h should define MODULE_VERSION before linux/module does. 40*/ 41#include <linux/module.h> 42#include <linux/errno.h> 43#include <linux/pci.h> 44#include <linux/dma-mapping.h> 45#include <linux/slab.h> 46#include <linux/io-mapping.h> 47#include <linux/delay.h> 48#include <linux/netdevice.h> 49#include <linux/string.h> 50#include <linux/fs.h> 51 52#include <linux/mlx4/device.h> 53#include <linux/mlx4/doorbell.h> 54 55#include "mlx4.h" 56#include "fw.h" 57#include "icm.h" 58#include "mlx4_stats.h" 59 60MODULE_AUTHOR("Roland Dreier"); 61MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver"); 62MODULE_LICENSE("Dual BSD/GPL"); 63 64struct workqueue_struct *mlx4_wq; 65 66#ifdef CONFIG_MLX4_DEBUG 67 68int mlx4_debug_level = 0; 69module_param_named(debug_level, mlx4_debug_level, int, 0644); 70MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0"); 71 72#endif /* CONFIG_MLX4_DEBUG */ 73 74#ifdef CONFIG_PCI_MSI 75 76static int msi_x = 1; 77module_param(msi_x, int, 0444); 78MODULE_PARM_DESC(msi_x, "0 - don't use MSI-X, 1 - use MSI-X, >1 - limit number of MSI-X irqs to msi_x (non-SRIOV only)"); 79 80#else /* CONFIG_PCI_MSI */ 81 82#define msi_x (0) 83 84#endif /* CONFIG_PCI_MSI */ 85 86static int enable_sys_tune = 0; 87module_param(enable_sys_tune, int, 0444); 88MODULE_PARM_DESC(enable_sys_tune, "Tune the cpu's for better performance (default 0)"); 89 90int mlx4_blck_lb = 1; 91module_param_named(block_loopback, mlx4_blck_lb, int, 0644); 92MODULE_PARM_DESC(block_loopback, "Block multicast loopback packets if > 0 " 93 "(default: 1)"); 94enum { 95 DEFAULT_DOMAIN = 0, 96 BDF_STR_SIZE = 8, /* bb:dd.f- */ 97 DBDF_STR_SIZE = 13 /* mmmm:bb:dd.f- */ 98}; 99 100enum { 101 NUM_VFS, 102 PROBE_VF, 103 PORT_TYPE_ARRAY 104}; 105 106enum { 107 VALID_DATA, 108 INVALID_DATA, 109 INVALID_STR 110}; 111 112struct param_data { 113 int id; 114 struct mlx4_dbdf2val_lst dbdf2val; 115}; 116 117static struct param_data num_vfs = { 118 .id = NUM_VFS, 119 .dbdf2val = { 120 .name = "num_vfs param", 121 .num_vals = 1, 122 .def_val = {0}, 123 .range = {0, MLX4_MAX_NUM_VF} 124 } 125}; 126module_param_string(num_vfs, num_vfs.dbdf2val.str, 127 sizeof(num_vfs.dbdf2val.str), 0444); 128MODULE_PARM_DESC(num_vfs, 129 "Either single value (e.g. '5') to define uniform num_vfs value for all devices functions\n" 130 "\t\tor a string to map device function numbers to their num_vfs values (e.g. '0000:04:00.0-5,002b:1c:0b.a-15').\n" 131 "\t\tHexadecimal digits for the device function (e.g. 002b:1c:0b.a) and decimal for num_vfs value (e.g. 15)."); 132 133static struct param_data probe_vf = { 134 .id = PROBE_VF, 135 .dbdf2val = { 136 .name = "probe_vf param", 137 .num_vals = 1, 138 .def_val = {0}, 139 .range = {0, MLX4_MAX_NUM_VF} 140 } 141}; 142module_param_string(probe_vf, probe_vf.dbdf2val.str, 143 sizeof(probe_vf.dbdf2val.str), 0444); 144MODULE_PARM_DESC(probe_vf, 145 "Either single value (e.g. '3') to define uniform number of VFs to probe by the pf driver for all devices functions\n" 146 "\t\tor a string to map device function numbers to their probe_vf values (e.g. '0000:04:00.0-3,002b:1c:0b.a-13').\n" 147 "\t\tHexadecimal digits for the device function (e.g. 002b:1c:0b.a) and decimal for probe_vf value (e.g. 13)."); 148 149int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; 150 151module_param_named(log_num_mgm_entry_size, 152 mlx4_log_num_mgm_entry_size, int, 0444); 153MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num" 154 " of qp per mcg, for example:" 155 " 10 gives 248.range: 7 <=" 156 " log_num_mgm_entry_size <= 12." 157 " To activate device managed" 158 " flow steering when available, set to -1"); 159 160static int high_rate_steer; 161module_param(high_rate_steer, int, 0444); 162MODULE_PARM_DESC(high_rate_steer, "Enable steering mode for higher packet rate" 163 " (default off)"); 164 165static int fast_drop; 166module_param_named(fast_drop, fast_drop, int, 0444); 167MODULE_PARM_DESC(fast_drop, 168 "Enable fast packet drop when no recieve WQEs are posted"); 169 170int mlx4_enable_64b_cqe_eqe = 1; 171module_param_named(enable_64b_cqe_eqe, mlx4_enable_64b_cqe_eqe, int, 0644); 172MODULE_PARM_DESC(enable_64b_cqe_eqe, 173 "Enable 64 byte CQEs/EQEs when the the FW supports this if non-zero (default: 1)"); 174 175#define HCA_GLOBAL_CAP_MASK 0 176 177#define PF_CONTEXT_BEHAVIOUR_MASK MLX4_FUNC_CAP_64B_EQE_CQE 178 179static char mlx4_version[] __devinitdata = 180 DRV_NAME ": Mellanox ConnectX core driver v" 181 DRV_VERSION " (" DRV_RELDATE ")\n"; 182 183static int log_num_mac = 7; 184module_param_named(log_num_mac, log_num_mac, int, 0444); 185MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)"); 186 187static int log_num_vlan; 188module_param_named(log_num_vlan, log_num_vlan, int, 0444); 189MODULE_PARM_DESC(log_num_vlan, 190 "(Obsolete) Log2 max number of VLANs per ETH port (0-7)"); 191/* Log2 max number of VLANs per ETH port (0-7) */ 192#define MLX4_LOG_NUM_VLANS 7 193 194int log_mtts_per_seg = ilog2(1); 195module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444); 196MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment " 197 "(0-7) (default: 0)"); 198 199static struct param_data port_type_array = { 200 .id = PORT_TYPE_ARRAY, 201 .dbdf2val = { 202 .name = "port_type_array param", 203 .num_vals = 2, 204 .def_val = {MLX4_PORT_TYPE_ETH, MLX4_PORT_TYPE_ETH}, 205 .range = {MLX4_PORT_TYPE_IB, MLX4_PORT_TYPE_NA} 206 } 207}; 208module_param_string(port_type_array, port_type_array.dbdf2val.str, 209 sizeof(port_type_array.dbdf2val.str), 0444); 210MODULE_PARM_DESC(port_type_array, 211 "Either pair of values (e.g. '1,2') to define uniform port1/port2 types configuration for all devices functions\n" 212 "\t\tor a string to map device function numbers to their pair of port types values (e.g. '0000:04:00.0-1;2,002b:1c:0b.a-1;1').\n" 213 "\t\tValid port types: 1-ib, 2-eth, 3-auto, 4-N/A\n" 214 "\t\tIn case that only one port is available use the N/A port type for port2 (e.g '1,4')."); 215 216 217struct mlx4_port_config { 218 struct list_head list; 219 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 220 struct pci_dev *pdev; 221}; 222 223#define MLX4_LOG_NUM_MTT 20 224/* We limit to 30 as of a bit map issue which uses int and not uint. 225 see mlx4_buddy_init -> bitmap_zero which gets int. 226*/ 227#define MLX4_MAX_LOG_NUM_MTT 30 228static struct mlx4_profile mod_param_profile = { 229 .num_qp = 19, 230 .num_srq = 16, 231 .rdmarc_per_qp = 4, 232 .num_cq = 16, 233 .num_mcg = 13, 234 .num_mpt = 19, 235 .num_mtt_segs = 0, /* max(20, 2*MTTs for host memory)) */ 236}; 237 238module_param_named(log_num_qp, mod_param_profile.num_qp, int, 0444); 239MODULE_PARM_DESC(log_num_qp, "log maximum number of QPs per HCA (default: 19)"); 240 241module_param_named(log_num_srq, mod_param_profile.num_srq, int, 0444); 242MODULE_PARM_DESC(log_num_srq, "log maximum number of SRQs per HCA " 243 "(default: 16)"); 244 245module_param_named(log_rdmarc_per_qp, mod_param_profile.rdmarc_per_qp, int, 246 0444); 247MODULE_PARM_DESC(log_rdmarc_per_qp, "log number of RDMARC buffers per QP " 248 "(default: 4)"); 249 250module_param_named(log_num_cq, mod_param_profile.num_cq, int, 0444); 251MODULE_PARM_DESC(log_num_cq, "log maximum number of CQs per HCA (default: 16)"); 252 253module_param_named(log_num_mcg, mod_param_profile.num_mcg, int, 0444); 254MODULE_PARM_DESC(log_num_mcg, "log maximum number of multicast groups per HCA " 255 "(default: 13)"); 256 257module_param_named(log_num_mpt, mod_param_profile.num_mpt, int, 0444); 258MODULE_PARM_DESC(log_num_mpt, 259 "log maximum number of memory protection table entries per " 260 "HCA (default: 19)"); 261 262module_param_named(log_num_mtt, mod_param_profile.num_mtt_segs, int, 0444); 263MODULE_PARM_DESC(log_num_mtt, 264 "log maximum number of memory translation table segments per " 265 "HCA (default: max(20, 2*MTTs for register all of the host memory limited to 30))"); 266 267enum { 268 MLX4_IF_STATE_BASIC, 269 MLX4_IF_STATE_EXTENDED 270}; 271 272static inline u64 dbdf_to_u64(int domain, int bus, int dev, int fn) 273{ 274 return (domain << 20) | (bus << 12) | (dev << 4) | fn; 275} 276 277static inline void pr_bdf_err(const char *dbdf, const char *pname) 278{ 279 pr_warn("mlx4_core: '%s' is not valid bdf in '%s'\n", dbdf, pname); 280} 281 282static inline void pr_val_err(const char *dbdf, const char *pname, 283 const char *val) 284{ 285 pr_warn("mlx4_core: value '%s' of bdf '%s' in '%s' is not valid\n" 286 , val, dbdf, pname); 287} 288 289static inline void pr_out_of_range_bdf(const char *dbdf, int val, 290 struct mlx4_dbdf2val_lst *dbdf2val) 291{ 292 pr_warn("mlx4_core: value %d in bdf '%s' of '%s' is out of its valid range (%d,%d)\n" 293 , val, dbdf, dbdf2val->name , dbdf2val->range.min, 294 dbdf2val->range.max); 295} 296 297static inline void pr_out_of_range(struct mlx4_dbdf2val_lst *dbdf2val) 298{ 299 pr_warn("mlx4_core: value of '%s' is out of its valid range (%d,%d)\n" 300 , dbdf2val->name , dbdf2val->range.min, dbdf2val->range.max); 301} 302 303static inline int is_in_range(int val, struct mlx4_range *r) 304{ 305 return (val >= r->min && val <= r->max); 306} 307 308static int update_defaults(struct param_data *pdata) 309{ 310 long int val[MLX4_MAX_BDF_VALS]; 311 int ret; 312 char *t, *p = pdata->dbdf2val.str; 313 char sval[32]; 314 int val_len; 315 316 if (!strlen(p) || strchr(p, ':') || strchr(p, '.') || strchr(p, ';')) 317 return INVALID_STR; 318 319 switch (pdata->id) { 320 case PORT_TYPE_ARRAY: 321 t = strchr(p, ','); 322 if (!t || t == p || (t - p) > sizeof(sval)) 323 return INVALID_STR; 324 325 val_len = t - p; 326 strncpy(sval, p, val_len); 327 sval[val_len] = 0; 328 329 ret = kstrtol(sval, 0, &val[0]); 330 if (ret == -EINVAL) 331 return INVALID_STR; 332 if (ret || !is_in_range(val[0], &pdata->dbdf2val.range)) { 333 pr_out_of_range(&pdata->dbdf2val); 334 return INVALID_DATA; 335 } 336 337 ret = kstrtol(t + 1, 0, &val[1]); 338 if (ret == -EINVAL) 339 return INVALID_STR; 340 if (ret || !is_in_range(val[1], &pdata->dbdf2val.range)) { 341 pr_out_of_range(&pdata->dbdf2val); 342 return INVALID_DATA; 343 } 344 345 pdata->dbdf2val.tbl[0].val[0] = val[0]; 346 pdata->dbdf2val.tbl[0].val[1] = val[1]; 347 break; 348 349 case NUM_VFS: 350 case PROBE_VF: 351 ret = kstrtol(p, 0, &val[0]); 352 if (ret == -EINVAL) 353 return INVALID_STR; 354 if (ret || !is_in_range(val[0], &pdata->dbdf2val.range)) { 355 pr_out_of_range(&pdata->dbdf2val); 356 return INVALID_DATA; 357 } 358 pdata->dbdf2val.tbl[0].val[0] = val[0]; 359 break; 360 } 361 pdata->dbdf2val.tbl[1].dbdf = MLX4_ENDOF_TBL; 362 363 return VALID_DATA; 364} 365 366int mlx4_fill_dbdf2val_tbl(struct mlx4_dbdf2val_lst *dbdf2val_lst) 367{ 368 int domain, bus, dev, fn; 369 u64 dbdf; 370 char *p, *t, *v; 371 char tmp[32]; 372 char sbdf[32]; 373 char sep = ','; 374 int j, k, str_size, i = 1; 375 int prfx_size; 376 377 p = dbdf2val_lst->str; 378 379 for (j = 0; j < dbdf2val_lst->num_vals; j++) 380 dbdf2val_lst->tbl[0].val[j] = dbdf2val_lst->def_val[j]; 381 dbdf2val_lst->tbl[1].dbdf = MLX4_ENDOF_TBL; 382 383 str_size = strlen(dbdf2val_lst->str); 384 385 if (str_size == 0) 386 return 0; 387 388 while (strlen(p)) { 389 prfx_size = BDF_STR_SIZE; 390 sbdf[prfx_size] = 0; 391 strncpy(sbdf, p, prfx_size); 392 domain = DEFAULT_DOMAIN; 393 if (sscanf(sbdf, "%02x:%02x.%x-", &bus, &dev, &fn) != 3) { 394 prfx_size = DBDF_STR_SIZE; 395 sbdf[prfx_size] = 0; 396 strncpy(sbdf, p, prfx_size); 397 if (sscanf(sbdf, "%04x:%02x:%02x.%x-", &domain, &bus, 398 &dev, &fn) != 4) { 399 pr_bdf_err(sbdf, dbdf2val_lst->name); 400 goto err; 401 } 402 sprintf(tmp, "%04x:%02x:%02x.%x-", domain, bus, dev, 403 fn); 404 } else { 405 sprintf(tmp, "%02x:%02x.%x-", bus, dev, fn); 406 } 407 408 if (strnicmp(sbdf, tmp, sizeof(tmp))) { 409 pr_bdf_err(sbdf, dbdf2val_lst->name); 410 goto err; 411 } 412 413 dbdf = dbdf_to_u64(domain, bus, dev, fn); 414 415 for (j = 1; j < i; j++) 416 if (dbdf2val_lst->tbl[j].dbdf == dbdf) { 417 pr_warn("mlx4_core: in '%s', %s appears multiple times\n" 418 , dbdf2val_lst->name, sbdf); 419 goto err; 420 } 421 422 if (i >= MLX4_DEVS_TBL_SIZE) { 423 pr_warn("mlx4_core: Too many devices in '%s'\n" 424 , dbdf2val_lst->name); 425 goto err; 426 } 427 428 p += prfx_size; 429 t = strchr(p, sep); 430 t = t ? t : p + strlen(p); 431 if (p >= t) { 432 pr_val_err(sbdf, dbdf2val_lst->name, ""); 433 goto err; 434 } 435 436 for (k = 0; k < dbdf2val_lst->num_vals; k++) { 437 char sval[32]; 438 long int val; 439 int ret, val_len; 440 char vsep = ';'; 441 442 v = (k == dbdf2val_lst->num_vals - 1) ? t : strchr(p, vsep); 443 if (!v || v > t || v == p || (v - p) > sizeof(sval)) { 444 pr_val_err(sbdf, dbdf2val_lst->name, p); 445 goto err; 446 } 447 val_len = v - p; 448 strncpy(sval, p, val_len); 449 sval[val_len] = 0; 450 451 ret = kstrtol(sval, 0, &val); 452 if (ret) { 453 if (strchr(p, vsep)) 454 pr_warn("mlx4_core: too many vals in bdf '%s' of '%s'\n" 455 , sbdf, dbdf2val_lst->name); 456 else 457 pr_val_err(sbdf, dbdf2val_lst->name, 458 sval); 459 goto err; 460 } 461 if (!is_in_range(val, &dbdf2val_lst->range)) { 462 pr_out_of_range_bdf(sbdf, val, dbdf2val_lst); 463 goto err; 464 } 465 466 dbdf2val_lst->tbl[i].val[k] = val; 467 p = v; 468 if (p[0] == vsep) 469 p++; 470 } 471 472 dbdf2val_lst->tbl[i].dbdf = dbdf; 473 if (strlen(p)) { 474 if (p[0] != sep) { 475 pr_warn("mlx4_core: expect separator '%c' before '%s' in '%s'\n" 476 , sep, p, dbdf2val_lst->name); 477 goto err; 478 } 479 p++; 480 } 481 i++; 482 if (i < MLX4_DEVS_TBL_SIZE) 483 dbdf2val_lst->tbl[i].dbdf = MLX4_ENDOF_TBL; 484 } 485 486 return 0; 487 488err: 489 dbdf2val_lst->tbl[1].dbdf = MLX4_ENDOF_TBL; 490 pr_warn("mlx4_core: The value of '%s' is incorrect. The value is discarded!\n" 491 , dbdf2val_lst->name); 492 493 return -EINVAL; 494} 495EXPORT_SYMBOL(mlx4_fill_dbdf2val_tbl); 496 497int mlx4_get_val(struct mlx4_dbdf2val *tbl, struct pci_dev *pdev, int idx, 498 int *val) 499{ 500 u64 dbdf; 501 int i = 1; 502 503 *val = tbl[0].val[idx]; 504 if (!pdev) 505 return -EINVAL; 506 507 if (!pdev->bus) { 508 return -EINVAL; 509 } 510 511 dbdf = dbdf_to_u64(pci_get_domain(pdev->dev.bsddev), pci_get_bus(pdev->dev.bsddev), 512 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); 513 514 while ((i < MLX4_DEVS_TBL_SIZE) && (tbl[i].dbdf != MLX4_ENDOF_TBL)) { 515 if (tbl[i].dbdf == dbdf) { 516 *val = tbl[i].val[idx]; 517 return 0; 518 } 519 i++; 520 } 521 522 return 0; 523} 524EXPORT_SYMBOL(mlx4_get_val); 525 526static void process_mod_param_profile(struct mlx4_profile *profile) 527{ 528 vm_size_t hwphyssz; 529 hwphyssz = 0; 530 TUNABLE_ULONG_FETCH("hw.realmem", (u_long *) &hwphyssz); 531 532 profile->num_qp = 1 << mod_param_profile.num_qp; 533 profile->num_srq = 1 << mod_param_profile.num_srq; 534 profile->rdmarc_per_qp = 1 << mod_param_profile.rdmarc_per_qp; 535 profile->num_cq = 1 << mod_param_profile.num_cq; 536 profile->num_mcg = 1 << mod_param_profile.num_mcg; 537 profile->num_mpt = 1 << mod_param_profile.num_mpt; 538 /* 539 * We want to scale the number of MTTs with the size of the 540 * system memory, since it makes sense to register a lot of 541 * memory on a system with a lot of memory. As a heuristic, 542 * make sure we have enough MTTs to register twice the system 543 * memory (with PAGE_SIZE entries). 544 * 545 * This number has to be a power of two and fit into 32 bits 546 * due to device limitations. We cap this at 2^30 as of bit map 547 * limitation to work with int instead of uint (mlx4_buddy_init -> bitmap_zero) 548 * That limits us to 4TB of memory registration per HCA with 549 * 4KB pages, which is probably OK for the next few months. 550 */ 551 if (mod_param_profile.num_mtt_segs) 552 profile->num_mtt_segs = 1 << mod_param_profile.num_mtt_segs; 553 else { 554 profile->num_mtt_segs = 555 roundup_pow_of_two(max_t(unsigned, 556 1 << (MLX4_LOG_NUM_MTT - log_mtts_per_seg), 557 min(1UL << 558 (MLX4_MAX_LOG_NUM_MTT - 559 log_mtts_per_seg), 560 (hwphyssz << 1) 561 >> log_mtts_per_seg))); 562 /* set the actual value, so it will be reflected to the user 563 using the sysfs */ 564 mod_param_profile.num_mtt_segs = ilog2(profile->num_mtt_segs); 565 } 566} 567 568int mlx4_check_port_params(struct mlx4_dev *dev, 569 enum mlx4_port_type *port_type) 570{ 571 int i; 572 573 for (i = 0; i < dev->caps.num_ports - 1; i++) { 574 if (port_type[i] != port_type[i + 1]) { 575 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) { 576 mlx4_err(dev, "Only same port types supported " 577 "on this HCA, aborting.\n"); 578 return -EINVAL; 579 } 580 } 581 } 582 583 for (i = 0; i < dev->caps.num_ports; i++) { 584 if (!(port_type[i] & dev->caps.supported_type[i+1])) { 585 mlx4_err(dev, "Requested port type for port %d is not " 586 "supported on this HCA\n", i + 1); 587 return -EINVAL; 588 } 589 } 590 return 0; 591} 592 593static void mlx4_set_port_mask(struct mlx4_dev *dev) 594{ 595 int i; 596 597 for (i = 1; i <= dev->caps.num_ports; ++i) 598 dev->caps.port_mask[i] = dev->caps.port_type[i]; 599} 600 601static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 602{ 603 int err; 604 int i; 605 606 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 607 if (err) { 608 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 609 return err; 610 } 611 612 if (dev_cap->min_page_sz > PAGE_SIZE) { 613 mlx4_err(dev, "HCA minimum page size of %d bigger than " 614 "kernel PAGE_SIZE of %d, aborting.\n", 615 dev_cap->min_page_sz, PAGE_SIZE); 616 return -ENODEV; 617 } 618 if (dev_cap->num_ports > MLX4_MAX_PORTS) { 619 mlx4_err(dev, "HCA has %d ports, but we only support %d, " 620 "aborting.\n", 621 dev_cap->num_ports, MLX4_MAX_PORTS); 622 return -ENODEV; 623 } 624 625 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) { 626 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than " 627 "PCI resource 2 size of 0x%llx, aborting.\n", 628 dev_cap->uar_size, 629 (unsigned long long) pci_resource_len(dev->pdev, 2)); 630 return -ENODEV; 631 } 632 633 dev->caps.num_ports = dev_cap->num_ports; 634 dev->phys_caps.num_phys_eqs = MLX4_MAX_EQ_NUM; 635 for (i = 1; i <= dev->caps.num_ports; ++i) { 636 dev->caps.vl_cap[i] = dev_cap->max_vl[i]; 637 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i]; 638 dev->phys_caps.gid_phys_table_len[i] = dev_cap->max_gids[i]; 639 dev->phys_caps.pkey_phys_table_len[i] = dev_cap->max_pkeys[i]; 640 /* set gid and pkey table operating lengths by default 641 * to non-sriov values */ 642 dev->caps.gid_table_len[i] = dev_cap->max_gids[i]; 643 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i]; 644 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i]; 645 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i]; 646 dev->caps.def_mac[i] = dev_cap->def_mac[i]; 647 dev->caps.supported_type[i] = dev_cap->supported_port_types[i]; 648 dev->caps.suggested_type[i] = dev_cap->suggested_type[i]; 649 dev->caps.default_sense[i] = dev_cap->default_sense[i]; 650 dev->caps.trans_type[i] = dev_cap->trans_type[i]; 651 dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i]; 652 dev->caps.wavelength[i] = dev_cap->wavelength[i]; 653 dev->caps.trans_code[i] = dev_cap->trans_code[i]; 654 } 655 656 dev->caps.uar_page_size = PAGE_SIZE; 657 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE; 658 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay; 659 dev->caps.bf_reg_size = dev_cap->bf_reg_size; 660 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page; 661 dev->caps.max_sq_sg = dev_cap->max_sq_sg; 662 dev->caps.max_rq_sg = dev_cap->max_rq_sg; 663 dev->caps.max_wqes = dev_cap->max_qp_sz; 664 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp; 665 dev->caps.max_srq_wqes = dev_cap->max_srq_sz; 666 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1; 667 dev->caps.reserved_srqs = dev_cap->reserved_srqs; 668 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz; 669 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz; 670 /* 671 * Subtract 1 from the limit because we need to allocate a 672 * spare CQE to enable resizing the CQ 673 */ 674 dev->caps.max_cqes = dev_cap->max_cq_sz - 1; 675 dev->caps.reserved_cqs = dev_cap->reserved_cqs; 676 dev->caps.reserved_eqs = dev_cap->reserved_eqs; 677 dev->caps.reserved_mtts = dev_cap->reserved_mtts; 678 dev->caps.reserved_mrws = dev_cap->reserved_mrws; 679 680 /* The first 128 UARs are used for EQ doorbells */ 681 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars); 682 dev->caps.reserved_pds = dev_cap->reserved_pds; 683 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? 684 dev_cap->reserved_xrcds : 0; 685 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? 686 dev_cap->max_xrcds : 0; 687 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz; 688 689 dev->caps.max_msg_sz = dev_cap->max_msg_sz; 690 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1); 691 dev->caps.flags = dev_cap->flags; 692 dev->caps.flags2 = dev_cap->flags2; 693 dev->caps.bmme_flags = dev_cap->bmme_flags; 694 dev->caps.reserved_lkey = dev_cap->reserved_lkey; 695 dev->caps.stat_rate_support = dev_cap->stat_rate_support; 696 dev->caps.cq_timestamp = dev_cap->timestamp_support; 697 dev->caps.max_gso_sz = dev_cap->max_gso_sz; 698 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz; 699 700 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */ 701 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT) 702 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; 703 /* Don't do sense port on multifunction devices (for now at least) */ 704 if (mlx4_is_mfunc(dev)) 705 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; 706 707 dev->caps.log_num_macs = log_num_mac; 708 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS; 709 710 dev->caps.fast_drop = fast_drop ? 711 !!(dev->caps.flags & MLX4_DEV_CAP_FLAG_FAST_DROP) : 712 0; 713 714 for (i = 1; i <= dev->caps.num_ports; ++i) { 715 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE; 716 if (dev->caps.supported_type[i]) { 717 /* if only ETH is supported - assign ETH */ 718 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH) 719 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH; 720 /* if only IB is supported, assign IB */ 721 else if (dev->caps.supported_type[i] == 722 MLX4_PORT_TYPE_IB) 723 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB; 724 else { 725 /* 726 * if IB and ETH are supported, we set the port 727 * type according to user selection of port type; 728 * if there is no user selection, take the FW hint 729 */ 730 int pta; 731 mlx4_get_val(port_type_array.dbdf2val.tbl, 732 pci_physfn(dev->pdev), i - 1, 733 &pta); 734 if (pta == MLX4_PORT_TYPE_NONE) { 735 dev->caps.port_type[i] = dev->caps.suggested_type[i] ? 736 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB; 737 } else if (pta == MLX4_PORT_TYPE_NA) { 738 mlx4_err(dev, "Port %d is valid port. " 739 "It is not allowed to configure its type to N/A(%d)\n", 740 i, MLX4_PORT_TYPE_NA); 741 return -EINVAL; 742 } else { 743 dev->caps.port_type[i] = pta; 744 } 745 } 746 } 747 /* 748 * Link sensing is allowed on the port if 3 conditions are true: 749 * 1. Both protocols are supported on the port. 750 * 2. Different types are supported on the port 751 * 3. FW declared that it supports link sensing 752 */ 753 mlx4_priv(dev)->sense.sense_allowed[i] = 754 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) && 755 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && 756 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)); 757 758 /* Disablling auto sense for default Eth ports support */ 759 mlx4_priv(dev)->sense.sense_allowed[i] = 0; 760 761 /* 762 * If "default_sense" bit is set, we move the port to "AUTO" mode 763 * and perform sense_port FW command to try and set the correct 764 * port type from beginning 765 */ 766 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) { 767 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE; 768 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO; 769 mlx4_SENSE_PORT(dev, i, &sensed_port); 770 if (sensed_port != MLX4_PORT_TYPE_NONE) 771 dev->caps.port_type[i] = sensed_port; 772 } else { 773 dev->caps.possible_type[i] = dev->caps.port_type[i]; 774 } 775 776 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) { 777 dev->caps.log_num_macs = dev_cap->log_max_macs[i]; 778 mlx4_warn(dev, "Requested number of MACs is too much " 779 "for port %d, reducing to %d.\n", 780 i, 1 << dev->caps.log_num_macs); 781 } 782 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) { 783 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i]; 784 mlx4_warn(dev, "Requested number of VLANs is too much " 785 "for port %d, reducing to %d.\n", 786 i, 1 << dev->caps.log_num_vlans); 787 } 788 } 789 790 dev->caps.max_basic_counters = dev_cap->max_basic_counters; 791 dev->caps.max_extended_counters = dev_cap->max_extended_counters; 792 /* support extended counters if available */ 793 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS_EXT) 794 dev->caps.max_counters = dev->caps.max_extended_counters; 795 else 796 dev->caps.max_counters = dev->caps.max_basic_counters; 797 798 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps; 799 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] = 800 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] = 801 (1 << dev->caps.log_num_macs) * 802 (1 << dev->caps.log_num_vlans) * 803 dev->caps.num_ports; 804 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH; 805 806 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] + 807 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] + 808 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] + 809 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH]; 810 811 dev->caps.sync_qp = dev_cap->sync_qp; 812 if (dev->pdev->device == 0x1003) 813 dev->caps.cq_flags |= MLX4_DEV_CAP_CQ_FLAG_IO; 814 815 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0; 816 817 if (!mlx4_enable_64b_cqe_eqe && !mlx4_is_slave(dev)) { 818 if (dev_cap->flags & 819 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) { 820 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n"); 821 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE; 822 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE; 823 } 824 } 825 826 if ((dev->caps.flags & 827 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) && 828 mlx4_is_master(dev)) 829 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE; 830 831 if (!mlx4_is_slave(dev)) { 832 for (i = 0; i < dev->caps.num_ports; ++i) 833 dev->caps.def_counter_index[i] = i << 1; 834 } 835 836 return 0; 837} 838/*The function checks if there are live vf, return the num of them*/ 839static int mlx4_how_many_lives_vf(struct mlx4_dev *dev) 840{ 841 struct mlx4_priv *priv = mlx4_priv(dev); 842 struct mlx4_slave_state *s_state; 843 int i; 844 int ret = 0; 845 846 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) { 847 s_state = &priv->mfunc.master.slave_state[i]; 848 if (s_state->active && s_state->last_cmd != 849 MLX4_COMM_CMD_RESET) { 850 mlx4_warn(dev, "%s: slave: %d is still active\n", 851 __func__, i); 852 ret++; 853 } 854 } 855 return ret; 856} 857 858int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey) 859{ 860 u32 qk = MLX4_RESERVED_QKEY_BASE; 861 862 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX || 863 qpn < dev->phys_caps.base_proxy_sqpn) 864 return -EINVAL; 865 866 if (qpn >= dev->phys_caps.base_tunnel_sqpn) 867 /* tunnel qp */ 868 qk += qpn - dev->phys_caps.base_tunnel_sqpn; 869 else 870 qk += qpn - dev->phys_caps.base_proxy_sqpn; 871 *qkey = qk; 872 return 0; 873} 874EXPORT_SYMBOL(mlx4_get_parav_qkey); 875 876void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val) 877{ 878 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 879 880 if (!mlx4_is_master(dev)) 881 return; 882 883 priv->virt2phys_pkey[slave][port - 1][i] = val; 884} 885EXPORT_SYMBOL(mlx4_sync_pkey_table); 886 887void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid) 888{ 889 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 890 891 if (!mlx4_is_master(dev)) 892 return; 893 894 priv->slave_node_guids[slave] = guid; 895} 896EXPORT_SYMBOL(mlx4_put_slave_node_guid); 897 898__be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave) 899{ 900 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 901 902 if (!mlx4_is_master(dev)) 903 return 0; 904 905 return priv->slave_node_guids[slave]; 906} 907EXPORT_SYMBOL(mlx4_get_slave_node_guid); 908 909int mlx4_is_slave_active(struct mlx4_dev *dev, int slave) 910{ 911 struct mlx4_priv *priv = mlx4_priv(dev); 912 struct mlx4_slave_state *s_slave; 913 914 if (!mlx4_is_master(dev)) 915 return 0; 916 917 s_slave = &priv->mfunc.master.slave_state[slave]; 918 return !!s_slave->active; 919} 920EXPORT_SYMBOL(mlx4_is_slave_active); 921 922static void slave_adjust_steering_mode(struct mlx4_dev *dev, 923 struct mlx4_dev_cap *dev_cap, 924 struct mlx4_init_hca_param *hca_param) 925{ 926 dev->caps.steering_mode = hca_param->steering_mode; 927 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) 928 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; 929 else 930 dev->caps.num_qp_per_mgm = 931 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2); 932 933 mlx4_dbg(dev, "Steering mode is: %s\n", 934 mlx4_steering_mode_str(dev->caps.steering_mode)); 935} 936 937static int mlx4_slave_cap(struct mlx4_dev *dev) 938{ 939 int err; 940 u32 page_size; 941 struct mlx4_dev_cap dev_cap; 942 struct mlx4_func_cap func_cap; 943 struct mlx4_init_hca_param hca_param; 944 int i; 945 946 memset(&hca_param, 0, sizeof(hca_param)); 947 err = mlx4_QUERY_HCA(dev, &hca_param); 948 if (err) { 949 mlx4_err(dev, "QUERY_HCA command failed, aborting.\n"); 950 return err; 951 } 952 953 /*fail if the hca has an unknown capability */ 954 if ((hca_param.global_caps | HCA_GLOBAL_CAP_MASK) != 955 HCA_GLOBAL_CAP_MASK) { 956 mlx4_err(dev, "Unknown hca global capabilities\n"); 957 return -ENOSYS; 958 } 959 960 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz; 961 962 dev->caps.hca_core_clock = hca_param.hca_core_clock; 963 964 memset(&dev_cap, 0, sizeof(dev_cap)); 965 dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp; 966 err = mlx4_dev_cap(dev, &dev_cap); 967 if (err) { 968 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 969 return err; 970 } 971 972 err = mlx4_QUERY_FW(dev); 973 if (err) 974 mlx4_err(dev, "QUERY_FW command failed: could not get FW version.\n"); 975 976 if (!hca_param.mw_enable) { 977 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW; 978 dev->caps.bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN; 979 } 980 981 page_size = ~dev->caps.page_size_cap + 1; 982 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size); 983 if (page_size > PAGE_SIZE) { 984 mlx4_err(dev, "HCA minimum page size of %d bigger than " 985 "kernel PAGE_SIZE of %d, aborting.\n", 986 page_size, PAGE_SIZE); 987 return -ENODEV; 988 } 989 990 /* slave gets uar page size from QUERY_HCA fw command */ 991 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12); 992 993 /* TODO: relax this assumption */ 994 if (dev->caps.uar_page_size != PAGE_SIZE) { 995 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %d\n", 996 dev->caps.uar_page_size, PAGE_SIZE); 997 return -ENODEV; 998 } 999 1000 memset(&func_cap, 0, sizeof(func_cap)); 1001 err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap); 1002 if (err) { 1003 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d).\n", 1004 err); 1005 return err; 1006 } 1007 1008 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) != 1009 PF_CONTEXT_BEHAVIOUR_MASK) { 1010 mlx4_err(dev, "Unknown pf context behaviour\n"); 1011 return -ENOSYS; 1012 } 1013 1014 dev->caps.num_ports = func_cap.num_ports; 1015 dev->quotas.qp = func_cap.qp_quota; 1016 dev->quotas.srq = func_cap.srq_quota; 1017 dev->quotas.cq = func_cap.cq_quota; 1018 dev->quotas.mpt = func_cap.mpt_quota; 1019 dev->quotas.mtt = func_cap.mtt_quota; 1020 dev->caps.num_qps = 1 << hca_param.log_num_qps; 1021 dev->caps.num_srqs = 1 << hca_param.log_num_srqs; 1022 dev->caps.num_cqs = 1 << hca_param.log_num_cqs; 1023 dev->caps.num_mpts = 1 << hca_param.log_mpt_sz; 1024 dev->caps.num_eqs = func_cap.max_eq; 1025 dev->caps.reserved_eqs = func_cap.reserved_eq; 1026 dev->caps.num_pds = MLX4_NUM_PDS; 1027 dev->caps.num_mgms = 0; 1028 dev->caps.num_amgms = 0; 1029 1030 if (dev->caps.num_ports > MLX4_MAX_PORTS) { 1031 mlx4_err(dev, "HCA has %d ports, but we only support %d, " 1032 "aborting.\n", dev->caps.num_ports, MLX4_MAX_PORTS); 1033 return -ENODEV; 1034 } 1035 1036 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); 1037 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); 1038 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); 1039 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); 1040 1041 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy || 1042 !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy) { 1043 err = -ENOMEM; 1044 goto err_mem; 1045 } 1046 1047 for (i = 1; i <= dev->caps.num_ports; ++i) { 1048 err = mlx4_QUERY_FUNC_CAP(dev, (u32) i, &func_cap); 1049 if (err) { 1050 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for" 1051 " port %d, aborting (%d).\n", i, err); 1052 goto err_mem; 1053 } 1054 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn; 1055 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn; 1056 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn; 1057 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn; 1058 dev->caps.def_counter_index[i - 1] = func_cap.def_counter_index; 1059 1060 dev->caps.port_mask[i] = dev->caps.port_type[i]; 1061 err = mlx4_get_slave_pkey_gid_tbl_len(dev, i, 1062 &dev->caps.gid_table_len[i], 1063 &dev->caps.pkey_table_len[i]); 1064 if (err) 1065 goto err_mem; 1066 } 1067 1068 if (dev->caps.uar_page_size * (dev->caps.num_uars - 1069 dev->caps.reserved_uars) > 1070 pci_resource_len(dev->pdev, 2)) { 1071 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than " 1072 "PCI resource 2 size of 0x%llx, aborting.\n", 1073 dev->caps.uar_page_size * dev->caps.num_uars, 1074 (unsigned long long) pci_resource_len(dev->pdev, 2)); 1075 err = -ENOMEM; 1076 goto err_mem; 1077 } 1078 1079 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) { 1080 dev->caps.eqe_size = 64; 1081 dev->caps.eqe_factor = 1; 1082 } else { 1083 dev->caps.eqe_size = 32; 1084 dev->caps.eqe_factor = 0; 1085 } 1086 1087 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) { 1088 dev->caps.cqe_size = 64; 1089 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE; 1090 } else { 1091 dev->caps.cqe_size = 32; 1092 } 1093 1094 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 1095 mlx4_warn(dev, "Timestamping is not supported in slave mode.\n"); 1096 1097 slave_adjust_steering_mode(dev, &dev_cap, &hca_param); 1098 1099 return 0; 1100 1101err_mem: 1102 kfree(dev->caps.qp0_tunnel); 1103 kfree(dev->caps.qp0_proxy); 1104 kfree(dev->caps.qp1_tunnel); 1105 kfree(dev->caps.qp1_proxy); 1106 dev->caps.qp0_tunnel = dev->caps.qp0_proxy = 1107 dev->caps.qp1_tunnel = dev->caps.qp1_proxy = NULL; 1108 1109 return err; 1110} 1111 1112static void mlx4_request_modules(struct mlx4_dev *dev) 1113{ 1114 int port; 1115 int has_ib_port = false; 1116 int has_eth_port = false; 1117#define EN_DRV_NAME "mlx4_en" 1118#define IB_DRV_NAME "mlx4_ib" 1119 1120 for (port = 1; port <= dev->caps.num_ports; port++) { 1121 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB) 1122 has_ib_port = true; 1123 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) 1124 has_eth_port = true; 1125 } 1126 1127 if (has_ib_port) 1128 request_module_nowait(IB_DRV_NAME); 1129 if (has_eth_port) 1130 request_module_nowait(EN_DRV_NAME); 1131} 1132 1133/* 1134 * Change the port configuration of the device. 1135 * Every user of this function must hold the port mutex. 1136 */ 1137int mlx4_change_port_types(struct mlx4_dev *dev, 1138 enum mlx4_port_type *port_types) 1139{ 1140 int err = 0; 1141 int change = 0; 1142 int port; 1143 1144 for (port = 0; port < dev->caps.num_ports; port++) { 1145 /* Change the port type only if the new type is different 1146 * from the current, and not set to Auto */ 1147 if (port_types[port] != dev->caps.port_type[port + 1]) 1148 change = 1; 1149 } 1150 if (change) { 1151 mlx4_unregister_device(dev); 1152 for (port = 1; port <= dev->caps.num_ports; port++) { 1153 mlx4_CLOSE_PORT(dev, port); 1154 dev->caps.port_type[port] = port_types[port - 1]; 1155 err = mlx4_SET_PORT(dev, port, -1); 1156 if (err) { 1157 mlx4_err(dev, "Failed to set port %d, " 1158 "aborting\n", port); 1159 goto out; 1160 } 1161 } 1162 mlx4_set_port_mask(dev); 1163 err = mlx4_register_device(dev); 1164 if (err) { 1165 mlx4_err(dev, "Failed to register device\n"); 1166 goto out; 1167 } 1168 mlx4_request_modules(dev); 1169 } 1170 1171out: 1172 return err; 1173} 1174 1175static ssize_t show_port_type(struct device *dev, 1176 struct device_attribute *attr, 1177 char *buf) 1178{ 1179 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1180 port_attr); 1181 struct mlx4_dev *mdev = info->dev; 1182 char type[8]; 1183 1184 sprintf(type, "%s", 1185 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ? 1186 "ib" : "eth"); 1187 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO) 1188 sprintf(buf, "auto (%s)\n", type); 1189 else 1190 sprintf(buf, "%s\n", type); 1191 1192 return strlen(buf); 1193} 1194 1195static ssize_t set_port_type(struct device *dev, 1196 struct device_attribute *attr, 1197 const char *buf, size_t count) 1198{ 1199 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1200 port_attr); 1201 struct mlx4_dev *mdev = info->dev; 1202 struct mlx4_priv *priv = mlx4_priv(mdev); 1203 enum mlx4_port_type types[MLX4_MAX_PORTS]; 1204 enum mlx4_port_type new_types[MLX4_MAX_PORTS]; 1205 int i; 1206 int err = 0; 1207 1208 if (!strcmp(buf, "ib\n")) 1209 info->tmp_type = MLX4_PORT_TYPE_IB; 1210 else if (!strcmp(buf, "eth\n")) 1211 info->tmp_type = MLX4_PORT_TYPE_ETH; 1212 else if (!strcmp(buf, "auto\n")) 1213 info->tmp_type = MLX4_PORT_TYPE_AUTO; 1214 else { 1215 mlx4_err(mdev, "%s is not supported port type\n", buf); 1216 return -EINVAL; 1217 } 1218 1219 if ((info->tmp_type & mdev->caps.supported_type[info->port]) != 1220 info->tmp_type) { 1221 mlx4_err(mdev, "Requested port type for port %d is not supported on this HCA\n", 1222 info->port); 1223 return -EINVAL; 1224 } 1225 1226 mlx4_stop_sense(mdev); 1227 mutex_lock(&priv->port_mutex); 1228 /* Possible type is always the one that was delivered */ 1229 mdev->caps.possible_type[info->port] = info->tmp_type; 1230 1231 for (i = 0; i < mdev->caps.num_ports; i++) { 1232 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type : 1233 mdev->caps.possible_type[i+1]; 1234 if (types[i] == MLX4_PORT_TYPE_AUTO) 1235 types[i] = mdev->caps.port_type[i+1]; 1236 } 1237 1238 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && 1239 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) { 1240 for (i = 1; i <= mdev->caps.num_ports; i++) { 1241 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) { 1242 mdev->caps.possible_type[i] = mdev->caps.port_type[i]; 1243 err = -EINVAL; 1244 } 1245 } 1246 } 1247 if (err) { 1248 mlx4_err(mdev, "Auto sensing is not supported on this HCA. " 1249 "Set only 'eth' or 'ib' for both ports " 1250 "(should be the same)\n"); 1251 goto out; 1252 } 1253 1254 mlx4_do_sense_ports(mdev, new_types, types); 1255 1256 err = mlx4_check_port_params(mdev, new_types); 1257 if (err) 1258 goto out; 1259 1260 /* We are about to apply the changes after the configuration 1261 * was verified, no need to remember the temporary types 1262 * any more */ 1263 for (i = 0; i < mdev->caps.num_ports; i++) 1264 priv->port[i + 1].tmp_type = 0; 1265 1266 err = mlx4_change_port_types(mdev, new_types); 1267 1268out: 1269 mlx4_start_sense(mdev); 1270 mutex_unlock(&priv->port_mutex); 1271 return err ? err : count; 1272} 1273 1274enum ibta_mtu { 1275 IB_MTU_256 = 1, 1276 IB_MTU_512 = 2, 1277 IB_MTU_1024 = 3, 1278 IB_MTU_2048 = 4, 1279 IB_MTU_4096 = 5 1280}; 1281 1282static inline int int_to_ibta_mtu(int mtu) 1283{ 1284 switch (mtu) { 1285 case 256: return IB_MTU_256; 1286 case 512: return IB_MTU_512; 1287 case 1024: return IB_MTU_1024; 1288 case 2048: return IB_MTU_2048; 1289 case 4096: return IB_MTU_4096; 1290 default: return -1; 1291 } 1292} 1293 1294static inline int ibta_mtu_to_int(enum ibta_mtu mtu) 1295{ 1296 switch (mtu) { 1297 case IB_MTU_256: return 256; 1298 case IB_MTU_512: return 512; 1299 case IB_MTU_1024: return 1024; 1300 case IB_MTU_2048: return 2048; 1301 case IB_MTU_4096: return 4096; 1302 default: return -1; 1303 } 1304} 1305 1306static ssize_t show_port_ib_mtu(struct device *dev, 1307 struct device_attribute *attr, 1308 char *buf) 1309{ 1310 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1311 port_mtu_attr); 1312 struct mlx4_dev *mdev = info->dev; 1313 1314 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) 1315 mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); 1316 1317 sprintf(buf, "%d\n", 1318 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port])); 1319 return strlen(buf); 1320} 1321 1322static ssize_t set_port_ib_mtu(struct device *dev, 1323 struct device_attribute *attr, 1324 const char *buf, size_t count) 1325{ 1326 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1327 port_mtu_attr); 1328 struct mlx4_dev *mdev = info->dev; 1329 struct mlx4_priv *priv = mlx4_priv(mdev); 1330 int err, port, mtu, ibta_mtu = -1; 1331 1332 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) { 1333 mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); 1334 return -EINVAL; 1335 } 1336 1337 mtu = (int) simple_strtol(buf, NULL, 0); 1338 ibta_mtu = int_to_ibta_mtu(mtu); 1339 1340 if (ibta_mtu < 0) { 1341 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf); 1342 return -EINVAL; 1343 } 1344 1345 mdev->caps.port_ib_mtu[info->port] = ibta_mtu; 1346 1347 mlx4_stop_sense(mdev); 1348 mutex_lock(&priv->port_mutex); 1349 mlx4_unregister_device(mdev); 1350 for (port = 1; port <= mdev->caps.num_ports; port++) { 1351 mlx4_CLOSE_PORT(mdev, port); 1352 err = mlx4_SET_PORT(mdev, port, -1); 1353 if (err) { 1354 mlx4_err(mdev, "Failed to set port %d, " 1355 "aborting\n", port); 1356 goto err_set_port; 1357 } 1358 } 1359 err = mlx4_register_device(mdev); 1360err_set_port: 1361 mutex_unlock(&priv->port_mutex); 1362 mlx4_start_sense(mdev); 1363 return err ? err : count; 1364} 1365 1366static int mlx4_load_fw(struct mlx4_dev *dev) 1367{ 1368 struct mlx4_priv *priv = mlx4_priv(dev); 1369 int err, unmap_flag = 0; 1370 1371 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages, 1372 GFP_HIGHUSER | __GFP_NOWARN, 0); 1373 if (!priv->fw.fw_icm) { 1374 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n"); 1375 return -ENOMEM; 1376 } 1377 1378 err = mlx4_MAP_FA(dev, priv->fw.fw_icm); 1379 if (err) { 1380 mlx4_err(dev, "MAP_FA command failed, aborting.\n"); 1381 goto err_free; 1382 } 1383 1384 err = mlx4_RUN_FW(dev); 1385 if (err) { 1386 mlx4_err(dev, "RUN_FW command failed, aborting.\n"); 1387 goto err_unmap_fa; 1388 } 1389 1390 return 0; 1391 1392err_unmap_fa: 1393 unmap_flag = mlx4_UNMAP_FA(dev); 1394 if (unmap_flag) 1395 pr_warn("mlx4_core: mlx4_UNMAP_FA failed.\n"); 1396 1397err_free: 1398 if (!unmap_flag) 1399 mlx4_free_icm(dev, priv->fw.fw_icm, 0); 1400 return err; 1401} 1402 1403static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base, 1404 int cmpt_entry_sz) 1405{ 1406 struct mlx4_priv *priv = mlx4_priv(dev); 1407 int err; 1408 int num_eqs; 1409 1410 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table, 1411 cmpt_base + 1412 ((u64) (MLX4_CMPT_TYPE_QP * 1413 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1414 cmpt_entry_sz, dev->caps.num_qps, 1415 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1416 0, 0); 1417 if (err) 1418 goto err; 1419 1420 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table, 1421 cmpt_base + 1422 ((u64) (MLX4_CMPT_TYPE_SRQ * 1423 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1424 cmpt_entry_sz, dev->caps.num_srqs, 1425 dev->caps.reserved_srqs, 0, 0); 1426 if (err) 1427 goto err_qp; 1428 1429 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table, 1430 cmpt_base + 1431 ((u64) (MLX4_CMPT_TYPE_CQ * 1432 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1433 cmpt_entry_sz, dev->caps.num_cqs, 1434 dev->caps.reserved_cqs, 0, 0); 1435 if (err) 1436 goto err_srq; 1437 1438 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs : 1439 dev->caps.num_eqs; 1440 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table, 1441 cmpt_base + 1442 ((u64) (MLX4_CMPT_TYPE_EQ * 1443 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1444 cmpt_entry_sz, num_eqs, num_eqs, 0, 0); 1445 if (err) 1446 goto err_cq; 1447 1448 return 0; 1449 1450err_cq: 1451 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1452 1453err_srq: 1454 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1455 1456err_qp: 1457 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1458 1459err: 1460 return err; 1461} 1462 1463static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap, 1464 struct mlx4_init_hca_param *init_hca, u64 icm_size) 1465{ 1466 struct mlx4_priv *priv = mlx4_priv(dev); 1467 u64 aux_pages; 1468 int num_eqs; 1469 int err, unmap_flag = 0; 1470 1471 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages); 1472 if (err) { 1473 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n"); 1474 return err; 1475 } 1476 1477 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n", 1478 (unsigned long long) icm_size >> 10, 1479 (unsigned long long) aux_pages << 2); 1480 1481 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages, 1482 GFP_HIGHUSER | __GFP_NOWARN, 0); 1483 if (!priv->fw.aux_icm) { 1484 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n"); 1485 return -ENOMEM; 1486 } 1487 1488 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm); 1489 if (err) { 1490 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n"); 1491 goto err_free_aux; 1492 } 1493 1494 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz); 1495 if (err) { 1496 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n"); 1497 goto err_unmap_aux; 1498 } 1499 1500 1501 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs : 1502 dev->caps.num_eqs; 1503 err = mlx4_init_icm_table(dev, &priv->eq_table.table, 1504 init_hca->eqc_base, dev_cap->eqc_entry_sz, 1505 num_eqs, num_eqs, 0, 0); 1506 if (err) { 1507 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n"); 1508 goto err_unmap_cmpt; 1509 } 1510 1511 /* 1512 * Reserved MTT entries must be aligned up to a cacheline 1513 * boundary, since the FW will write to them, while the driver 1514 * writes to all other MTT entries. (The variable 1515 * dev->caps.mtt_entry_sz below is really the MTT segment 1516 * size, not the raw entry size) 1517 */ 1518 dev->caps.reserved_mtts = 1519 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz, 1520 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz; 1521 1522 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table, 1523 init_hca->mtt_base, 1524 dev->caps.mtt_entry_sz, 1525 dev->caps.num_mtts, 1526 dev->caps.reserved_mtts, 1, 0); 1527 if (err) { 1528 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n"); 1529 goto err_unmap_eq; 1530 } 1531 1532 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table, 1533 init_hca->dmpt_base, 1534 dev_cap->dmpt_entry_sz, 1535 dev->caps.num_mpts, 1536 dev->caps.reserved_mrws, 1, 1); 1537 if (err) { 1538 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n"); 1539 goto err_unmap_mtt; 1540 } 1541 1542 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table, 1543 init_hca->qpc_base, 1544 dev_cap->qpc_entry_sz, 1545 dev->caps.num_qps, 1546 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1547 0, 0); 1548 if (err) { 1549 mlx4_err(dev, "Failed to map QP context memory, aborting.\n"); 1550 goto err_unmap_dmpt; 1551 } 1552 1553 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table, 1554 init_hca->auxc_base, 1555 dev_cap->aux_entry_sz, 1556 dev->caps.num_qps, 1557 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1558 0, 0); 1559 if (err) { 1560 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n"); 1561 goto err_unmap_qp; 1562 } 1563 1564 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table, 1565 init_hca->altc_base, 1566 dev_cap->altc_entry_sz, 1567 dev->caps.num_qps, 1568 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1569 0, 0); 1570 if (err) { 1571 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n"); 1572 goto err_unmap_auxc; 1573 } 1574 1575 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table, 1576 init_hca->rdmarc_base, 1577 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift, 1578 dev->caps.num_qps, 1579 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1580 0, 0); 1581 if (err) { 1582 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n"); 1583 goto err_unmap_altc; 1584 } 1585 1586 err = mlx4_init_icm_table(dev, &priv->cq_table.table, 1587 init_hca->cqc_base, 1588 dev_cap->cqc_entry_sz, 1589 dev->caps.num_cqs, 1590 dev->caps.reserved_cqs, 0, 0); 1591 if (err) { 1592 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n"); 1593 goto err_unmap_rdmarc; 1594 } 1595 1596 err = mlx4_init_icm_table(dev, &priv->srq_table.table, 1597 init_hca->srqc_base, 1598 dev_cap->srq_entry_sz, 1599 dev->caps.num_srqs, 1600 dev->caps.reserved_srqs, 0, 0); 1601 if (err) { 1602 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n"); 1603 goto err_unmap_cq; 1604 } 1605 1606 /* 1607 * For flow steering device managed mode it is required to use 1608 * mlx4_init_icm_table. For B0 steering mode it's not strictly 1609 * required, but for simplicity just map the whole multicast 1610 * group table now. The table isn't very big and it's a lot 1611 * easier than trying to track ref counts. 1612 */ 1613 err = mlx4_init_icm_table(dev, &priv->mcg_table.table, 1614 init_hca->mc_base, 1615 mlx4_get_mgm_entry_size(dev), 1616 dev->caps.num_mgms + dev->caps.num_amgms, 1617 dev->caps.num_mgms + dev->caps.num_amgms, 1618 0, 0); 1619 if (err) { 1620 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n"); 1621 goto err_unmap_srq; 1622 } 1623 1624 return 0; 1625 1626err_unmap_srq: 1627 mlx4_cleanup_icm_table(dev, &priv->srq_table.table); 1628 1629err_unmap_cq: 1630 mlx4_cleanup_icm_table(dev, &priv->cq_table.table); 1631 1632err_unmap_rdmarc: 1633 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); 1634 1635err_unmap_altc: 1636 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); 1637 1638err_unmap_auxc: 1639 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); 1640 1641err_unmap_qp: 1642 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); 1643 1644err_unmap_dmpt: 1645 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); 1646 1647err_unmap_mtt: 1648 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); 1649 1650err_unmap_eq: 1651 mlx4_cleanup_icm_table(dev, &priv->eq_table.table); 1652 1653err_unmap_cmpt: 1654 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); 1655 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1656 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1657 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1658 1659err_unmap_aux: 1660 unmap_flag = mlx4_UNMAP_ICM_AUX(dev); 1661 if (unmap_flag) 1662 pr_warn("mlx4_core: mlx4_UNMAP_ICM_AUX failed.\n"); 1663 1664err_free_aux: 1665 if (!unmap_flag) 1666 mlx4_free_icm(dev, priv->fw.aux_icm, 0); 1667 1668 return err; 1669} 1670 1671static void mlx4_free_icms(struct mlx4_dev *dev) 1672{ 1673 struct mlx4_priv *priv = mlx4_priv(dev); 1674 1675 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table); 1676 mlx4_cleanup_icm_table(dev, &priv->srq_table.table); 1677 mlx4_cleanup_icm_table(dev, &priv->cq_table.table); 1678 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); 1679 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); 1680 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); 1681 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); 1682 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); 1683 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); 1684 mlx4_cleanup_icm_table(dev, &priv->eq_table.table); 1685 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); 1686 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1687 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1688 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1689 1690 if (!mlx4_UNMAP_ICM_AUX(dev)) 1691 mlx4_free_icm(dev, priv->fw.aux_icm, 0); 1692 else 1693 pr_warn("mlx4_core: mlx4_UNMAP_ICM_AUX failed.\n"); 1694} 1695 1696static void mlx4_slave_exit(struct mlx4_dev *dev) 1697{ 1698 struct mlx4_priv *priv = mlx4_priv(dev); 1699 1700 mutex_lock(&priv->cmd.slave_cmd_mutex); 1701 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME)) 1702 mlx4_warn(dev, "Failed to close slave function.\n"); 1703 mutex_unlock(&priv->cmd.slave_cmd_mutex); 1704} 1705 1706static int map_bf_area(struct mlx4_dev *dev) 1707{ 1708 struct mlx4_priv *priv = mlx4_priv(dev); 1709 resource_size_t bf_start; 1710 resource_size_t bf_len; 1711 int err = 0; 1712 1713 if (!dev->caps.bf_reg_size) 1714 return -ENXIO; 1715 1716 bf_start = pci_resource_start(dev->pdev, 2) + 1717 (dev->caps.num_uars << PAGE_SHIFT); 1718 bf_len = pci_resource_len(dev->pdev, 2) - 1719 (dev->caps.num_uars << PAGE_SHIFT); 1720 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len); 1721 if (!priv->bf_mapping) 1722 err = -ENOMEM; 1723 1724 return err; 1725} 1726 1727static void unmap_bf_area(struct mlx4_dev *dev) 1728{ 1729 if (mlx4_priv(dev)->bf_mapping) 1730 io_mapping_free(mlx4_priv(dev)->bf_mapping); 1731} 1732 1733int mlx4_read_clock(struct mlx4_dev *dev) 1734{ 1735 u32 clockhi, clocklo, clockhi1; 1736 cycle_t cycles; 1737 int i; 1738 struct mlx4_priv *priv = mlx4_priv(dev); 1739 1740 if (!priv->clock_mapping) 1741 return -ENOTSUPP; 1742 1743 for (i = 0; i < 10; i++) { 1744 clockhi = swab32(readl(priv->clock_mapping)); 1745 clocklo = swab32(readl(priv->clock_mapping + 4)); 1746 clockhi1 = swab32(readl(priv->clock_mapping)); 1747 if (clockhi == clockhi1) 1748 break; 1749 } 1750 1751 cycles = (u64) clockhi << 32 | (u64) clocklo; 1752 1753 return cycles; 1754} 1755EXPORT_SYMBOL_GPL(mlx4_read_clock); 1756 1757 1758static int map_internal_clock(struct mlx4_dev *dev) 1759{ 1760 struct mlx4_priv *priv = mlx4_priv(dev); 1761 1762 priv->clock_mapping = ioremap(pci_resource_start(dev->pdev, 1763 priv->fw.clock_bar) + 1764 priv->fw.clock_offset, MLX4_CLOCK_SIZE); 1765 1766 if (!priv->clock_mapping) 1767 return -ENOMEM; 1768 1769 return 0; 1770} 1771 1772 1773int mlx4_get_internal_clock_params(struct mlx4_dev *dev, 1774 struct mlx4_clock_params *params) 1775{ 1776 struct mlx4_priv *priv = mlx4_priv(dev); 1777 1778 if (mlx4_is_slave(dev)) 1779 return -ENOTSUPP; 1780 if (!params) 1781 return -EINVAL; 1782 1783 params->bar = priv->fw.clock_bar; 1784 params->offset = priv->fw.clock_offset; 1785 params->size = MLX4_CLOCK_SIZE; 1786 1787 return 0; 1788} 1789EXPORT_SYMBOL_GPL(mlx4_get_internal_clock_params); 1790 1791static void unmap_internal_clock(struct mlx4_dev *dev) 1792{ 1793 struct mlx4_priv *priv = mlx4_priv(dev); 1794 1795 if (priv->clock_mapping) 1796 iounmap(priv->clock_mapping); 1797} 1798 1799static void mlx4_close_hca(struct mlx4_dev *dev) 1800{ 1801 unmap_internal_clock(dev); 1802 unmap_bf_area(dev); 1803 if (mlx4_is_slave(dev)) { 1804 mlx4_slave_exit(dev); 1805 } else { 1806 mlx4_CLOSE_HCA(dev, 0); 1807 mlx4_free_icms(dev); 1808 1809 if (!mlx4_UNMAP_FA(dev)) 1810 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0); 1811 else 1812 pr_warn("mlx4_core: mlx4_UNMAP_FA failed.\n"); 1813 } 1814} 1815 1816static int mlx4_init_slave(struct mlx4_dev *dev) 1817{ 1818 struct mlx4_priv *priv = mlx4_priv(dev); 1819 u64 dma = (u64) priv->mfunc.vhcr_dma; 1820 int num_of_reset_retries = NUM_OF_RESET_RETRIES; 1821 int ret_from_reset = 0; 1822 u32 slave_read; 1823 u32 cmd_channel_ver; 1824 1825 mutex_lock(&priv->cmd.slave_cmd_mutex); 1826 priv->cmd.max_cmds = 1; 1827 mlx4_warn(dev, "Sending reset\n"); 1828 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 1829 MLX4_COMM_TIME); 1830 /* if we are in the middle of flr the slave will try 1831 * NUM_OF_RESET_RETRIES times before leaving.*/ 1832 if (ret_from_reset) { 1833 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) { 1834 msleep(SLEEP_TIME_IN_RESET); 1835 while (ret_from_reset && num_of_reset_retries) { 1836 mlx4_warn(dev, "slave is currently in the" 1837 "middle of FLR. retrying..." 1838 "(try num:%d)\n", 1839 (NUM_OF_RESET_RETRIES - 1840 num_of_reset_retries + 1)); 1841 ret_from_reset = 1842 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 1843 0, MLX4_COMM_TIME); 1844 num_of_reset_retries = num_of_reset_retries - 1; 1845 } 1846 } else 1847 goto err; 1848 } 1849 1850 /* check the driver version - the slave I/F revision 1851 * must match the master's */ 1852 slave_read = swab32(readl(&priv->mfunc.comm->slave_read)); 1853 cmd_channel_ver = mlx4_comm_get_version(); 1854 1855 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) != 1856 MLX4_COMM_GET_IF_REV(slave_read)) { 1857 mlx4_err(dev, "slave driver version is not supported" 1858 " by the master\n"); 1859 goto err; 1860 } 1861 1862 mlx4_warn(dev, "Sending vhcr0\n"); 1863 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48, 1864 MLX4_COMM_TIME)) 1865 goto err; 1866 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32, 1867 MLX4_COMM_TIME)) 1868 goto err; 1869 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16, 1870 MLX4_COMM_TIME)) 1871 goto err; 1872 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME)) 1873 goto err; 1874 1875 mutex_unlock(&priv->cmd.slave_cmd_mutex); 1876 return 0; 1877 1878err: 1879 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0); 1880 mutex_unlock(&priv->cmd.slave_cmd_mutex); 1881 return -EIO; 1882} 1883 1884static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev) 1885{ 1886 int i; 1887 1888 for (i = 1; i <= dev->caps.num_ports; i++) { 1889 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) 1890 dev->caps.gid_table_len[i] = 1891 mlx4_get_slave_num_gids(dev, 0); 1892 else 1893 dev->caps.gid_table_len[i] = 1; 1894 dev->caps.pkey_table_len[i] = 1895 dev->phys_caps.pkey_phys_table_len[i] - 1; 1896 } 1897} 1898 1899static int choose_log_fs_mgm_entry_size(int qp_per_entry) 1900{ 1901 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; 1902 1903 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE; 1904 i++) { 1905 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2)) 1906 break; 1907 } 1908 1909 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1; 1910} 1911 1912static void choose_steering_mode(struct mlx4_dev *dev, 1913 struct mlx4_dev_cap *dev_cap) 1914{ 1915 int nvfs; 1916 1917 mlx4_get_val(num_vfs.dbdf2val.tbl, pci_physfn(dev->pdev), 0, &nvfs); 1918 if (high_rate_steer && !mlx4_is_mfunc(dev)) { 1919 dev->caps.flags &= ~(MLX4_DEV_CAP_FLAG_VEP_MC_STEER | 1920 MLX4_DEV_CAP_FLAG_VEP_UC_STEER); 1921 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_FS_EN; 1922 } 1923 1924 if (mlx4_log_num_mgm_entry_size == -1 && 1925 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN && 1926 (!mlx4_is_mfunc(dev) || 1927 (dev_cap->fs_max_num_qp_per_entry >= (nvfs + 1))) && 1928 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >= 1929 MLX4_MIN_MGM_LOG_ENTRY_SIZE) { 1930 dev->oper_log_mgm_entry_size = 1931 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry); 1932 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; 1933 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; 1934 } else { 1935 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER && 1936 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) 1937 dev->caps.steering_mode = MLX4_STEERING_MODE_B0; 1938 else { 1939 dev->caps.steering_mode = MLX4_STEERING_MODE_A0; 1940 1941 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER || 1942 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) 1943 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags " 1944 "set to use B0 steering. Falling back to A0 steering mode.\n"); 1945 } 1946 dev->oper_log_mgm_entry_size = 1947 mlx4_log_num_mgm_entry_size > 0 ? 1948 mlx4_log_num_mgm_entry_size : 1949 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; 1950 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev); 1951 } 1952 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, " 1953 "log_num_mgm_entry_size = %d\n", 1954 mlx4_steering_mode_str(dev->caps.steering_mode), 1955 dev->oper_log_mgm_entry_size, mlx4_log_num_mgm_entry_size); 1956} 1957 1958static int mlx4_init_hca(struct mlx4_dev *dev) 1959{ 1960 struct mlx4_priv *priv = mlx4_priv(dev); 1961 struct mlx4_dev_cap *dev_cap = NULL; 1962 struct mlx4_adapter adapter; 1963 struct mlx4_mod_stat_cfg mlx4_cfg; 1964 struct mlx4_profile profile; 1965 struct mlx4_init_hca_param init_hca; 1966 u64 icm_size; 1967 int err; 1968 1969 if (!mlx4_is_slave(dev)) { 1970 err = mlx4_QUERY_FW(dev); 1971 if (err) { 1972 if (err == -EACCES) 1973 mlx4_info(dev, "non-primary physical function, skipping.\n"); 1974 else 1975 mlx4_err(dev, "QUERY_FW command failed, aborting.\n"); 1976 return err; 1977 } 1978 1979 err = mlx4_load_fw(dev); 1980 if (err) { 1981 mlx4_err(dev, "Failed to start FW, aborting.\n"); 1982 return err; 1983 } 1984 1985 mlx4_cfg.log_pg_sz_m = 1; 1986 mlx4_cfg.log_pg_sz = 0; 1987 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg); 1988 if (err) 1989 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n"); 1990 1991 dev_cap = kzalloc(sizeof *dev_cap, GFP_KERNEL); 1992 if (!dev_cap) { 1993 mlx4_err(dev, "Failed to allocate memory for dev_cap\n"); 1994 err = -ENOMEM; 1995 goto err_stop_fw; 1996 } 1997 1998 err = mlx4_dev_cap(dev, dev_cap); 1999 if (err) { 2000 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 2001 goto err_stop_fw; 2002 } 2003 2004 choose_steering_mode(dev, dev_cap); 2005 2006 if (mlx4_is_master(dev)) 2007 mlx4_parav_master_pf_caps(dev); 2008 2009 process_mod_param_profile(&profile); 2010 if (dev->caps.steering_mode == 2011 MLX4_STEERING_MODE_DEVICE_MANAGED) 2012 profile.num_mcg = MLX4_FS_NUM_MCG; 2013 2014 icm_size = mlx4_make_profile(dev, &profile, dev_cap, 2015 &init_hca); 2016 if ((long long) icm_size < 0) { 2017 err = icm_size; 2018 goto err_stop_fw; 2019 } 2020 2021 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1; 2022 2023 init_hca.log_uar_sz = ilog2(dev->caps.num_uars); 2024 init_hca.uar_page_sz = PAGE_SHIFT - 12; 2025 2026 err = mlx4_init_icm(dev, dev_cap, &init_hca, icm_size); 2027 if (err) 2028 goto err_stop_fw; 2029 2030 init_hca.mw_enable = 1; 2031 2032 err = mlx4_INIT_HCA(dev, &init_hca); 2033 if (err) { 2034 mlx4_err(dev, "INIT_HCA command failed, aborting.\n"); 2035 goto err_free_icm; 2036 } 2037 2038 /* 2039 * Read HCA frequency by QUERY_HCA command 2040 */ 2041 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) { 2042 memset(&init_hca, 0, sizeof(init_hca)); 2043 err = mlx4_QUERY_HCA(dev, &init_hca); 2044 if (err) { 2045 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp.\n"); 2046 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 2047 } else { 2048 dev->caps.hca_core_clock = 2049 init_hca.hca_core_clock; 2050 } 2051 2052 /* In case we got HCA frequency 0 - disable timestamping 2053 * to avoid dividing by zero 2054 */ 2055 if (!dev->caps.hca_core_clock) { 2056 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 2057 mlx4_err(dev, "HCA frequency is 0. Timestamping is not supported."); 2058 } else if (map_internal_clock(dev)) { 2059 /* Map internal clock, 2060 * in case of failure disable timestamping 2061 */ 2062 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 2063 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported.\n"); 2064 } 2065 } 2066 } else { 2067 err = mlx4_init_slave(dev); 2068 if (err) { 2069 mlx4_err(dev, "Failed to initialize slave\n"); 2070 return err; 2071 } 2072 2073 err = mlx4_slave_cap(dev); 2074 if (err) { 2075 mlx4_err(dev, "Failed to obtain slave caps\n"); 2076 goto err_close; 2077 } 2078 } 2079 2080 if (map_bf_area(dev)) 2081 mlx4_dbg(dev, "Failed to map blue flame area\n"); 2082 2083 /* Only the master set the ports, all the rest got it from it.*/ 2084 if (!mlx4_is_slave(dev)) 2085 mlx4_set_port_mask(dev); 2086 2087 err = mlx4_QUERY_ADAPTER(dev, &adapter); 2088 if (err) { 2089 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n"); 2090 goto unmap_bf; 2091 } 2092 2093 priv->eq_table.inta_pin = adapter.inta_pin; 2094 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id); 2095 memcpy(dev->vsd, adapter.vsd, sizeof(dev->vsd)); 2096 dev->vsd_vendor_id = adapter.vsd_vendor_id; 2097 2098 if (!mlx4_is_slave(dev)) 2099 kfree(dev_cap); 2100 2101 return 0; 2102 2103unmap_bf: 2104 if (!mlx4_is_slave(dev)) 2105 unmap_internal_clock(dev); 2106 unmap_bf_area(dev); 2107 2108 if (mlx4_is_slave(dev)) { 2109 kfree(dev->caps.qp0_tunnel); 2110 kfree(dev->caps.qp0_proxy); 2111 kfree(dev->caps.qp1_tunnel); 2112 kfree(dev->caps.qp1_proxy); 2113 } 2114 2115err_close: 2116 if (mlx4_is_slave(dev)) 2117 mlx4_slave_exit(dev); 2118 else 2119 mlx4_CLOSE_HCA(dev, 0); 2120 2121err_free_icm: 2122 if (!mlx4_is_slave(dev)) 2123 mlx4_free_icms(dev); 2124 2125err_stop_fw: 2126 if (!mlx4_is_slave(dev)) { 2127 if (!mlx4_UNMAP_FA(dev)) 2128 mlx4_free_icm(dev, priv->fw.fw_icm, 0); 2129 else 2130 pr_warn("mlx4_core: mlx4_UNMAP_FA failed.\n"); 2131 kfree(dev_cap); 2132 } 2133 return err; 2134} 2135 2136static int mlx4_init_counters_table(struct mlx4_dev *dev) 2137{ 2138 struct mlx4_priv *priv = mlx4_priv(dev); 2139 int nent_pow2, port_indx, vf_index, num_counters; 2140 int res, index = 0; 2141 struct counter_index *new_counter_index; 2142 2143 2144 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2145 return -ENOENT; 2146 2147 if (!mlx4_is_slave(dev) && 2148 dev->caps.max_counters == dev->caps.max_extended_counters) { 2149 res = mlx4_cmd(dev, MLX4_IF_STATE_EXTENDED, 0, 0, 2150 MLX4_CMD_SET_IF_STAT, 2151 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2152 if (res) { 2153 mlx4_err(dev, "Failed to set extended counters (err=%d)\n", res); 2154 return res; 2155 } 2156 } 2157 2158 mutex_init(&priv->counters_table.mutex); 2159 2160 if (mlx4_is_slave(dev)) { 2161 for (port_indx = 0; port_indx < dev->caps.num_ports; port_indx++) { 2162 INIT_LIST_HEAD(&priv->counters_table.global_port_list[port_indx]); 2163 if (dev->caps.def_counter_index[port_indx] != 0xFF) { 2164 new_counter_index = kmalloc(sizeof(struct counter_index), GFP_KERNEL); 2165 if (!new_counter_index) 2166 return -ENOMEM; 2167 new_counter_index->index = dev->caps.def_counter_index[port_indx]; 2168 list_add_tail(&new_counter_index->list, &priv->counters_table.global_port_list[port_indx]); 2169 } 2170 } 2171 mlx4_dbg(dev, "%s: slave allocated %d counters for %d ports\n", 2172 __func__, dev->caps.num_ports, dev->caps.num_ports); 2173 return 0; 2174 } 2175 2176 nent_pow2 = roundup_pow_of_two(dev->caps.max_counters); 2177 2178 for (port_indx = 0; port_indx < dev->caps.num_ports; port_indx++) { 2179 INIT_LIST_HEAD(&priv->counters_table.global_port_list[port_indx]); 2180 /* allocating 2 counters per port for PFs */ 2181 /* For the PF, the ETH default counters are 0,2; */ 2182 /* and the RoCE default counters are 1,3 */ 2183 for (num_counters = 0; num_counters < 2; num_counters++, index++) { 2184 new_counter_index = kmalloc(sizeof(struct counter_index), GFP_KERNEL); 2185 if (!new_counter_index) 2186 return -ENOMEM; 2187 new_counter_index->index = index; 2188 list_add_tail(&new_counter_index->list, 2189 &priv->counters_table.global_port_list[port_indx]); 2190 } 2191 } 2192 2193 if (mlx4_is_master(dev)) { 2194 for (vf_index = 0; vf_index < dev->num_vfs; vf_index++) { 2195 for (port_indx = 0; port_indx < dev->caps.num_ports; port_indx++) { 2196 INIT_LIST_HEAD(&priv->counters_table.vf_list[vf_index][port_indx]); 2197 new_counter_index = kmalloc(sizeof(struct counter_index), GFP_KERNEL); 2198 if (!new_counter_index) 2199 return -ENOMEM; 2200 if (index < nent_pow2 - 2) { 2201 new_counter_index->index = index; 2202 index++; 2203 } else { 2204 new_counter_index->index = MLX4_SINK_COUNTER_INDEX; 2205 } 2206 2207 list_add_tail(&new_counter_index->list, 2208 &priv->counters_table.vf_list[vf_index][port_indx]); 2209 } 2210 } 2211 2212 res = mlx4_bitmap_init(&priv->counters_table.bitmap, 2213 nent_pow2, nent_pow2 - 1, 2214 index, 1); 2215 mlx4_dbg(dev, "%s: master allocated %d counters for %d VFs\n", 2216 __func__, index, dev->num_vfs); 2217 } else { 2218 res = mlx4_bitmap_init(&priv->counters_table.bitmap, 2219 nent_pow2, nent_pow2 - 1, 2220 index, 1); 2221 mlx4_dbg(dev, "%s: native allocated %d counters for %d ports\n", 2222 __func__, index, dev->caps.num_ports); 2223 } 2224 2225 return 0; 2226 2227} 2228 2229static void mlx4_cleanup_counters_table(struct mlx4_dev *dev) 2230{ 2231 struct mlx4_priv *priv = mlx4_priv(dev); 2232 int i, j; 2233 struct counter_index *port, *tmp_port; 2234 struct counter_index *vf, *tmp_vf; 2235 2236 mutex_lock(&priv->counters_table.mutex); 2237 2238 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS) { 2239 for (i = 0; i < dev->caps.num_ports; i++) { 2240 list_for_each_entry_safe(port, tmp_port, 2241 &priv->counters_table.global_port_list[i], 2242 list) { 2243 list_del(&port->list); 2244 kfree(port); 2245 } 2246 } 2247 if (!mlx4_is_slave(dev)) { 2248 for (i = 0; i < dev->num_vfs; i++) { 2249 for (j = 0; j < dev->caps.num_ports; j++) { 2250 list_for_each_entry_safe(vf, tmp_vf, 2251 &priv->counters_table.vf_list[i][j], 2252 list) { 2253 /* clear the counter statistic */ 2254 if (__mlx4_clear_if_stat(dev, vf->index)) 2255 mlx4_dbg(dev, "%s: reset counter %d failed\n", 2256 __func__, vf->index); 2257 list_del(&vf->list); 2258 kfree(vf); 2259 } 2260 } 2261 } 2262 mlx4_bitmap_cleanup(&priv->counters_table.bitmap); 2263 } 2264 } 2265 mutex_unlock(&priv->counters_table.mutex); 2266} 2267 2268int __mlx4_slave_counters_free(struct mlx4_dev *dev, int slave) 2269{ 2270 struct mlx4_priv *priv = mlx4_priv(dev); 2271 int i, first; 2272 struct counter_index *vf, *tmp_vf; 2273 2274 /* clean VF's counters for the next useg */ 2275 if (slave > 0 && slave <= dev->num_vfs) { 2276 mlx4_dbg(dev, "%s: free counters of slave(%d)\n" 2277 , __func__, slave); 2278 2279 mutex_lock(&priv->counters_table.mutex); 2280 for (i = 0; i < dev->caps.num_ports; i++) { 2281 first = 0; 2282 list_for_each_entry_safe(vf, tmp_vf, 2283 &priv->counters_table.vf_list[slave - 1][i], 2284 list) { 2285 /* clear the counter statistic */ 2286 if (__mlx4_clear_if_stat(dev, vf->index)) 2287 mlx4_dbg(dev, "%s: reset counter %d failed\n", 2288 __func__, vf->index); 2289 if (first++ && vf->index != MLX4_SINK_COUNTER_INDEX) { 2290 mlx4_dbg(dev, "%s: delete counter index %d for slave %d and port %d\n" 2291 , __func__, vf->index, slave, i + 1); 2292 mlx4_bitmap_free(&priv->counters_table.bitmap, vf->index, MLX4_USE_RR); 2293 list_del(&vf->list); 2294 kfree(vf); 2295 } else { 2296 mlx4_dbg(dev, "%s: can't delete default counter index %d for slave %d and port %d\n" 2297 , __func__, vf->index, slave, i + 1); 2298 } 2299 } 2300 } 2301 mutex_unlock(&priv->counters_table.mutex); 2302 } 2303 2304 return 0; 2305} 2306 2307int __mlx4_counter_alloc(struct mlx4_dev *dev, int slave, int port, u32 *idx) 2308{ 2309 struct mlx4_priv *priv = mlx4_priv(dev); 2310 struct counter_index *new_counter_index; 2311 2312 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2313 return -ENOENT; 2314 2315 if ((slave > MLX4_MAX_NUM_VF) || (slave < 0) || 2316 (port < 0) || (port > MLX4_MAX_PORTS)) { 2317 mlx4_dbg(dev, "%s: invalid slave(%d) or port(%d) index\n", 2318 __func__, slave, port); 2319 return -EINVAL; 2320 } 2321 2322 /* handle old guest request does not support request by port index */ 2323 if (port == 0) { 2324 *idx = MLX4_SINK_COUNTER_INDEX; 2325 mlx4_dbg(dev, "%s: allocated default counter index %d for slave %d port %d\n" 2326 , __func__, *idx, slave, port); 2327 return 0; 2328 } 2329 2330 mutex_lock(&priv->counters_table.mutex); 2331 2332 *idx = mlx4_bitmap_alloc(&priv->counters_table.bitmap); 2333 /* if no resources return the default counter of the slave and port */ 2334 if (*idx == -1) { 2335 if (slave == 0) { /* its the ethernet counter ?????? */ 2336 new_counter_index = list_entry(priv->counters_table.global_port_list[port - 1].next, 2337 struct counter_index, 2338 list); 2339 } else { 2340 new_counter_index = list_entry(priv->counters_table.vf_list[slave - 1][port - 1].next, 2341 struct counter_index, 2342 list); 2343 } 2344 2345 *idx = new_counter_index->index; 2346 mlx4_dbg(dev, "%s: allocated defualt counter index %d for slave %d port %d\n" 2347 , __func__, *idx, slave, port); 2348 goto out; 2349 } 2350 2351 if (slave == 0) { /* native or master */ 2352 new_counter_index = kmalloc(sizeof(struct counter_index), GFP_KERNEL); 2353 if (!new_counter_index) 2354 goto no_mem; 2355 new_counter_index->index = *idx; 2356 list_add_tail(&new_counter_index->list, &priv->counters_table.global_port_list[port - 1]); 2357 } else { 2358 new_counter_index = kmalloc(sizeof(struct counter_index), GFP_KERNEL); 2359 if (!new_counter_index) 2360 goto no_mem; 2361 new_counter_index->index = *idx; 2362 list_add_tail(&new_counter_index->list, &priv->counters_table.vf_list[slave - 1][port - 1]); 2363 } 2364 2365 mlx4_dbg(dev, "%s: allocated counter index %d for slave %d port %d\n" 2366 , __func__, *idx, slave, port); 2367out: 2368 mutex_unlock(&priv->counters_table.mutex); 2369 return 0; 2370 2371no_mem: 2372 mlx4_bitmap_free(&priv->counters_table.bitmap, *idx, MLX4_USE_RR); 2373 mutex_unlock(&priv->counters_table.mutex); 2374 *idx = MLX4_SINK_COUNTER_INDEX; 2375 mlx4_dbg(dev, "%s: failed err (%d)\n" 2376 , __func__, -ENOMEM); 2377 return -ENOMEM; 2378} 2379 2380int mlx4_counter_alloc(struct mlx4_dev *dev, u8 port, u32 *idx) 2381{ 2382 u64 out_param; 2383 int err; 2384 struct mlx4_priv *priv = mlx4_priv(dev); 2385 struct counter_index *new_counter_index, *c_index; 2386 2387 if (mlx4_is_mfunc(dev)) { 2388 err = mlx4_cmd_imm(dev, 0, &out_param, 2389 ((u32) port) << 8 | (u32) RES_COUNTER, 2390 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES, 2391 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 2392 if (!err) { 2393 *idx = get_param_l(&out_param); 2394 if (*idx == MLX4_SINK_COUNTER_INDEX) 2395 return -ENOSPC; 2396 2397 mutex_lock(&priv->counters_table.mutex); 2398 c_index = list_entry(priv->counters_table.global_port_list[port - 1].next, 2399 struct counter_index, 2400 list); 2401 mutex_unlock(&priv->counters_table.mutex); 2402 if (c_index->index == *idx) 2403 return -EEXIST; 2404 2405 if (mlx4_is_slave(dev)) { 2406 new_counter_index = kmalloc(sizeof(struct counter_index), GFP_KERNEL); 2407 if (!new_counter_index) { 2408 mlx4_counter_free(dev, port, *idx); 2409 return -ENOMEM; 2410 } 2411 new_counter_index->index = *idx; 2412 mutex_lock(&priv->counters_table.mutex); 2413 list_add_tail(&new_counter_index->list, &priv->counters_table.global_port_list[port - 1]); 2414 mutex_unlock(&priv->counters_table.mutex); 2415 mlx4_dbg(dev, "%s: allocated counter index %d for port %d\n" 2416 , __func__, *idx, port); 2417 } 2418 } 2419 return err; 2420 } 2421 return __mlx4_counter_alloc(dev, 0, port, idx); 2422} 2423EXPORT_SYMBOL_GPL(mlx4_counter_alloc); 2424 2425void __mlx4_counter_free(struct mlx4_dev *dev, int slave, int port, u32 idx) 2426{ 2427 /* check if native or slave and deletes acordingly */ 2428 struct mlx4_priv *priv = mlx4_priv(dev); 2429 struct counter_index *pf, *tmp_pf; 2430 struct counter_index *vf, *tmp_vf; 2431 int first; 2432 2433 2434 if (idx == MLX4_SINK_COUNTER_INDEX) { 2435 mlx4_dbg(dev, "%s: try to delete default counter index %d for port %d\n" 2436 , __func__, idx, port); 2437 return; 2438 } 2439 2440 if ((slave > MLX4_MAX_NUM_VF) || (slave < 0) || 2441 (port < 0) || (port > MLX4_MAX_PORTS)) { 2442 mlx4_warn(dev, "%s: deletion failed due to invalid slave(%d) or port(%d) index\n" 2443 , __func__, slave, idx); 2444 return; 2445 } 2446 2447 mutex_lock(&priv->counters_table.mutex); 2448 if (slave == 0) { 2449 first = 0; 2450 list_for_each_entry_safe(pf, tmp_pf, 2451 &priv->counters_table.global_port_list[port - 1], 2452 list) { 2453 /* the first 2 counters are reserved */ 2454 if (pf->index == idx) { 2455 /* clear the counter statistic */ 2456 if (__mlx4_clear_if_stat(dev, pf->index)) 2457 mlx4_dbg(dev, "%s: reset counter %d failed\n", 2458 __func__, pf->index); 2459 if (1 < first && idx != MLX4_SINK_COUNTER_INDEX) { 2460 list_del(&pf->list); 2461 kfree(pf); 2462 mlx4_dbg(dev, "%s: delete counter index %d for native device (%d) port %d\n" 2463 , __func__, idx, slave, port); 2464 mlx4_bitmap_free(&priv->counters_table.bitmap, idx, MLX4_USE_RR); 2465 goto out; 2466 } else { 2467 mlx4_dbg(dev, "%s: can't delete default counter index %d for native device (%d) port %d\n" 2468 , __func__, idx, slave, port); 2469 goto out; 2470 } 2471 } 2472 first++; 2473 } 2474 mlx4_dbg(dev, "%s: can't delete counter index %d for native device (%d) port %d\n" 2475 , __func__, idx, slave, port); 2476 } else { 2477 first = 0; 2478 list_for_each_entry_safe(vf, tmp_vf, 2479 &priv->counters_table.vf_list[slave - 1][port - 1], 2480 list) { 2481 /* the first element is reserved */ 2482 if (vf->index == idx) { 2483 /* clear the counter statistic */ 2484 if (__mlx4_clear_if_stat(dev, vf->index)) 2485 mlx4_dbg(dev, "%s: reset counter %d failed\n", 2486 __func__, vf->index); 2487 if (first) { 2488 list_del(&vf->list); 2489 kfree(vf); 2490 mlx4_dbg(dev, "%s: delete counter index %d for slave %d port %d\n", 2491 __func__, idx, slave, port); 2492 mlx4_bitmap_free(&priv->counters_table.bitmap, idx, MLX4_USE_RR); 2493 goto out; 2494 } else { 2495 mlx4_dbg(dev, "%s: can't delete default slave (%d) counter index %d for port %d\n" 2496 , __func__, slave, idx, port); 2497 goto out; 2498 } 2499 } 2500 first++; 2501 } 2502 mlx4_dbg(dev, "%s: can't delete slave (%d) counter index %d for port %d\n" 2503 , __func__, slave, idx, port); 2504 } 2505 2506out: 2507 mutex_unlock(&priv->counters_table.mutex); 2508} 2509 2510void mlx4_counter_free(struct mlx4_dev *dev, u8 port, u32 idx) 2511{ 2512 u64 in_param = 0; 2513 struct mlx4_priv *priv = mlx4_priv(dev); 2514 struct counter_index *counter, *tmp_counter; 2515 int first = 0; 2516 2517 if (mlx4_is_mfunc(dev)) { 2518 set_param_l(&in_param, idx); 2519 mlx4_cmd(dev, in_param, 2520 ((u32) port) << 8 | (u32) RES_COUNTER, 2521 RES_OP_RESERVE, 2522 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A, 2523 MLX4_CMD_WRAPPED); 2524 2525 if (mlx4_is_slave(dev) && idx != MLX4_SINK_COUNTER_INDEX) { 2526 mutex_lock(&priv->counters_table.mutex); 2527 list_for_each_entry_safe(counter, tmp_counter, 2528 &priv->counters_table.global_port_list[port - 1], 2529 list) { 2530 if (counter->index == idx && first++) { 2531 list_del(&counter->list); 2532 kfree(counter); 2533 mlx4_dbg(dev, "%s: delete counter index %d for port %d\n" 2534 , __func__, idx, port); 2535 mutex_unlock(&priv->counters_table.mutex); 2536 return; 2537 } 2538 } 2539 mutex_unlock(&priv->counters_table.mutex); 2540 } 2541 2542 return; 2543 } 2544 __mlx4_counter_free(dev, 0, port, idx); 2545} 2546EXPORT_SYMBOL_GPL(mlx4_counter_free); 2547 2548int __mlx4_clear_if_stat(struct mlx4_dev *dev, 2549 u8 counter_index) 2550{ 2551 struct mlx4_cmd_mailbox *if_stat_mailbox = NULL; 2552 int err = 0; 2553 u32 if_stat_in_mod = (counter_index & 0xff) | (1 << 31); 2554 2555 if (counter_index == MLX4_SINK_COUNTER_INDEX) 2556 return -EINVAL; 2557 2558 if (mlx4_is_slave(dev)) 2559 return 0; 2560 2561 if_stat_mailbox = mlx4_alloc_cmd_mailbox(dev); 2562 if (IS_ERR(if_stat_mailbox)) { 2563 err = PTR_ERR(if_stat_mailbox); 2564 return err; 2565 } 2566 2567 err = mlx4_cmd_box(dev, 0, if_stat_mailbox->dma, if_stat_in_mod, 0, 2568 MLX4_CMD_QUERY_IF_STAT, MLX4_CMD_TIME_CLASS_C, 2569 MLX4_CMD_NATIVE); 2570 2571 mlx4_free_cmd_mailbox(dev, if_stat_mailbox); 2572 return err; 2573} 2574 2575u8 mlx4_get_default_counter_index(struct mlx4_dev *dev, int slave, int port) 2576{ 2577 struct mlx4_priv *priv = mlx4_priv(dev); 2578 struct counter_index *new_counter_index; 2579 2580 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB) { 2581 mlx4_dbg(dev, "%s: return counter index %d for slave %d port (MLX4_PORT_TYPE_IB) %d\n", 2582 __func__, MLX4_SINK_COUNTER_INDEX, slave, port); 2583 return (u8)MLX4_SINK_COUNTER_INDEX; 2584 } 2585 2586 mutex_lock(&priv->counters_table.mutex); 2587 if (slave == 0) { 2588 new_counter_index = list_entry(priv->counters_table.global_port_list[port - 1].next, 2589 struct counter_index, 2590 list); 2591 } else { 2592 new_counter_index = list_entry(priv->counters_table.vf_list[slave - 1][port - 1].next, 2593 struct counter_index, 2594 list); 2595 } 2596 mutex_unlock(&priv->counters_table.mutex); 2597 2598 mlx4_dbg(dev, "%s: return counter index %d for slave %d port %d\n", 2599 __func__, new_counter_index->index, slave, port); 2600 2601 2602 return (u8)new_counter_index->index; 2603} 2604 2605int mlx4_get_vport_ethtool_stats(struct mlx4_dev *dev, int port, 2606 struct mlx4_en_vport_stats *vport_stats, 2607 int reset) 2608{ 2609 struct mlx4_priv *priv = mlx4_priv(dev); 2610 struct mlx4_cmd_mailbox *if_stat_mailbox = NULL; 2611 union mlx4_counter *counter; 2612 int err = 0; 2613 u32 if_stat_in_mod; 2614 struct counter_index *vport, *tmp_vport; 2615 2616 if (!vport_stats) 2617 return -EINVAL; 2618 2619 if_stat_mailbox = mlx4_alloc_cmd_mailbox(dev); 2620 if (IS_ERR(if_stat_mailbox)) { 2621 err = PTR_ERR(if_stat_mailbox); 2622 return err; 2623 } 2624 2625 mutex_lock(&priv->counters_table.mutex); 2626 list_for_each_entry_safe(vport, tmp_vport, 2627 &priv->counters_table.global_port_list[port - 1], 2628 list) { 2629 if (vport->index == MLX4_SINK_COUNTER_INDEX) 2630 continue; 2631 2632 memset(if_stat_mailbox->buf, 0, sizeof(union mlx4_counter)); 2633 if_stat_in_mod = (vport->index & 0xff) | ((reset & 1) << 31); 2634 err = mlx4_cmd_box(dev, 0, if_stat_mailbox->dma, 2635 if_stat_in_mod, 0, 2636 MLX4_CMD_QUERY_IF_STAT, 2637 MLX4_CMD_TIME_CLASS_C, 2638 MLX4_CMD_NATIVE); 2639 if (err) { 2640 mlx4_dbg(dev, "%s: failed to read statistics for counter index %d\n", 2641 __func__, vport->index); 2642 goto if_stat_out; 2643 } 2644 counter = (union mlx4_counter *)if_stat_mailbox->buf; 2645 if ((counter->control.cnt_mode & 0xf) == 1) { 2646 vport_stats->rx_broadcast_packets += be64_to_cpu(counter->ext.counters[0].IfRxBroadcastFrames); 2647 vport_stats->rx_unicast_packets += be64_to_cpu(counter->ext.counters[0].IfRxUnicastFrames); 2648 vport_stats->rx_multicast_packets += be64_to_cpu(counter->ext.counters[0].IfRxMulticastFrames); 2649 vport_stats->tx_broadcast_packets += be64_to_cpu(counter->ext.counters[0].IfTxBroadcastFrames); 2650 vport_stats->tx_unicast_packets += be64_to_cpu(counter->ext.counters[0].IfTxUnicastFrames); 2651 vport_stats->tx_multicast_packets += be64_to_cpu(counter->ext.counters[0].IfTxMulticastFrames); 2652 vport_stats->rx_broadcast_bytes += be64_to_cpu(counter->ext.counters[0].IfRxBroadcastOctets); 2653 vport_stats->rx_unicast_bytes += be64_to_cpu(counter->ext.counters[0].IfRxUnicastOctets); 2654 vport_stats->rx_multicast_bytes += be64_to_cpu(counter->ext.counters[0].IfRxMulticastOctets); 2655 vport_stats->tx_broadcast_bytes += be64_to_cpu(counter->ext.counters[0].IfTxBroadcastOctets); 2656 vport_stats->tx_unicast_bytes += be64_to_cpu(counter->ext.counters[0].IfTxUnicastOctets); 2657 vport_stats->tx_multicast_bytes += be64_to_cpu(counter->ext.counters[0].IfTxMulticastOctets); 2658 vport_stats->rx_errors += be64_to_cpu(counter->ext.counters[0].IfRxErrorFrames); 2659 vport_stats->rx_dropped += be64_to_cpu(counter->ext.counters[0].IfRxNoBufferFrames); 2660 vport_stats->tx_errors += be64_to_cpu(counter->ext.counters[0].IfTxDroppedFrames); 2661 } 2662 } 2663 2664if_stat_out: 2665 mutex_unlock(&priv->counters_table.mutex); 2666 mlx4_free_cmd_mailbox(dev, if_stat_mailbox); 2667 2668 return err; 2669} 2670EXPORT_SYMBOL_GPL(mlx4_get_vport_ethtool_stats); 2671 2672static int mlx4_setup_hca(struct mlx4_dev *dev) 2673{ 2674 struct mlx4_priv *priv = mlx4_priv(dev); 2675 int err; 2676 int port; 2677 __be32 ib_port_default_caps; 2678 2679 err = mlx4_init_uar_table(dev); 2680 if (err) { 2681 mlx4_err(dev, "Failed to initialize " 2682 "user access region table (err=%d), aborting.\n", 2683 err); 2684 return err; 2685 } 2686 2687 err = mlx4_uar_alloc(dev, &priv->driver_uar); 2688 if (err) { 2689 mlx4_err(dev, "Failed to allocate driver access region " 2690 "(err=%d), aborting.\n", err); 2691 goto err_uar_table_free; 2692 } 2693 2694 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE); 2695 if (!priv->kar) { 2696 mlx4_err(dev, "Couldn't map kernel access region, " 2697 "aborting.\n"); 2698 err = -ENOMEM; 2699 goto err_uar_free; 2700 } 2701 2702 err = mlx4_init_pd_table(dev); 2703 if (err) { 2704 mlx4_err(dev, "Failed to initialize " 2705 "protection domain table (err=%d), aborting.\n", err); 2706 goto err_kar_unmap; 2707 } 2708 2709 err = mlx4_init_xrcd_table(dev); 2710 if (err) { 2711 mlx4_err(dev, "Failed to initialize " 2712 "reliable connection domain table (err=%d), " 2713 "aborting.\n", err); 2714 goto err_pd_table_free; 2715 } 2716 2717 err = mlx4_init_mr_table(dev); 2718 if (err) { 2719 mlx4_err(dev, "Failed to initialize " 2720 "memory region table (err=%d), aborting.\n", err); 2721 goto err_xrcd_table_free; 2722 } 2723 2724 if (!mlx4_is_slave(dev)) { 2725 err = mlx4_init_mcg_table(dev); 2726 if (err) { 2727 mlx4_err(dev, "Failed to initialize " 2728 "multicast group table (err=%d), aborting.\n", 2729 err); 2730 goto err_mr_table_free; 2731 } 2732 } 2733 2734 err = mlx4_init_eq_table(dev); 2735 if (err) { 2736 mlx4_err(dev, "Failed to initialize " 2737 "event queue table (err=%d), aborting.\n", err); 2738 goto err_mcg_table_free; 2739 } 2740 2741 err = mlx4_cmd_use_events(dev); 2742 if (err) { 2743 mlx4_err(dev, "Failed to switch to event-driven " 2744 "firmware commands (err=%d), aborting.\n", err); 2745 goto err_eq_table_free; 2746 } 2747 2748 err = mlx4_NOP(dev); 2749 if (err) { 2750 if (dev->flags & MLX4_FLAG_MSI_X) { 2751 mlx4_warn(dev, "NOP command failed to generate MSI-X " 2752 "interrupt IRQ %d).\n", 2753 priv->eq_table.eq[dev->caps.num_comp_vectors].irq); 2754 mlx4_warn(dev, "Trying again without MSI-X.\n"); 2755 } else { 2756 mlx4_err(dev, "NOP command failed to generate interrupt " 2757 "(IRQ %d), aborting.\n", 2758 priv->eq_table.eq[dev->caps.num_comp_vectors].irq); 2759 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n"); 2760 } 2761 2762 goto err_cmd_poll; 2763 } 2764 2765 mlx4_dbg(dev, "NOP command IRQ test passed\n"); 2766 2767 err = mlx4_init_cq_table(dev); 2768 if (err) { 2769 mlx4_err(dev, "Failed to initialize " 2770 "completion queue table (err=%d), aborting.\n", err); 2771 goto err_cmd_poll; 2772 } 2773 2774 err = mlx4_init_srq_table(dev); 2775 if (err) { 2776 mlx4_err(dev, "Failed to initialize " 2777 "shared receive queue table (err=%d), aborting.\n", 2778 err); 2779 goto err_cq_table_free; 2780 } 2781 2782 err = mlx4_init_qp_table(dev); 2783 if (err) { 2784 mlx4_err(dev, "Failed to initialize " 2785 "queue pair table (err=%d), aborting.\n", err); 2786 goto err_srq_table_free; 2787 } 2788 2789 err = mlx4_init_counters_table(dev); 2790 if (err && err != -ENOENT) { 2791 mlx4_err(dev, "Failed to initialize counters table (err=%d), " 2792 "aborting.\n", err); 2793 goto err_qp_table_free; 2794 } 2795 2796 if (!mlx4_is_slave(dev)) { 2797 for (port = 1; port <= dev->caps.num_ports; port++) { 2798 ib_port_default_caps = 0; 2799 err = mlx4_get_port_ib_caps(dev, port, 2800 &ib_port_default_caps); 2801 if (err) 2802 mlx4_warn(dev, "failed to get port %d default " 2803 "ib capabilities (%d). Continuing " 2804 "with caps = 0\n", port, err); 2805 dev->caps.ib_port_def_cap[port] = ib_port_default_caps; 2806 2807 /* initialize per-slave default ib port capabilities */ 2808 if (mlx4_is_master(dev)) { 2809 int i; 2810 for (i = 0; i < dev->num_slaves; i++) { 2811 if (i == mlx4_master_func_num(dev)) 2812 continue; 2813 priv->mfunc.master.slave_state[i].ib_cap_mask[port] = 2814 ib_port_default_caps; 2815 } 2816 } 2817 2818 dev->caps.port_ib_mtu[port] = IB_MTU_4096; 2819 2820 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ? 2821 dev->caps.pkey_table_len[port] : -1); 2822 if (err) { 2823 mlx4_err(dev, "Failed to set port %d (err=%d), " 2824 "aborting\n", port, err); 2825 goto err_counters_table_free; 2826 } 2827 } 2828 } 2829 2830 return 0; 2831 2832err_counters_table_free: 2833 mlx4_cleanup_counters_table(dev); 2834 2835err_qp_table_free: 2836 mlx4_cleanup_qp_table(dev); 2837 2838err_srq_table_free: 2839 mlx4_cleanup_srq_table(dev); 2840 2841err_cq_table_free: 2842 mlx4_cleanup_cq_table(dev); 2843 2844err_cmd_poll: 2845 mlx4_cmd_use_polling(dev); 2846 2847err_eq_table_free: 2848 mlx4_cleanup_eq_table(dev); 2849 2850err_mcg_table_free: 2851 if (!mlx4_is_slave(dev)) 2852 mlx4_cleanup_mcg_table(dev); 2853 2854err_mr_table_free: 2855 mlx4_cleanup_mr_table(dev); 2856 2857err_xrcd_table_free: 2858 mlx4_cleanup_xrcd_table(dev); 2859 2860err_pd_table_free: 2861 mlx4_cleanup_pd_table(dev); 2862 2863err_kar_unmap: 2864 iounmap(priv->kar); 2865 2866err_uar_free: 2867 mlx4_uar_free(dev, &priv->driver_uar); 2868 2869err_uar_table_free: 2870 mlx4_cleanup_uar_table(dev); 2871 return err; 2872} 2873 2874static void mlx4_enable_msi_x(struct mlx4_dev *dev) 2875{ 2876 struct mlx4_priv *priv = mlx4_priv(dev); 2877 struct msix_entry *entries; 2878 int nreq = min_t(int, dev->caps.num_ports * 2879 min_t(int, num_possible_cpus() + 1, MAX_MSIX_P_PORT) 2880 + MSIX_LEGACY_SZ, MAX_MSIX); 2881 int err; 2882 int i; 2883 2884 if (msi_x) { 2885 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs, 2886 nreq); 2887 2888 if (msi_x > 1 && !mlx4_is_mfunc(dev)) 2889 nreq = min_t(int, nreq, msi_x); 2890 2891 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL); 2892 if (!entries) 2893 goto no_msi; 2894 2895 for (i = 0; i < nreq; ++i) 2896 entries[i].entry = i; 2897 2898 retry: 2899 err = pci_enable_msix(dev->pdev, entries, nreq); 2900 if (err) { 2901 /* Try again if at least 2 vectors are available */ 2902 if (err > 1) { 2903 mlx4_info(dev, "Requested %d vectors, " 2904 "but only %d MSI-X vectors available, " 2905 "trying again\n", nreq, err); 2906 nreq = err; 2907 goto retry; 2908 } 2909 kfree(entries); 2910 goto no_msi; 2911 } 2912 2913 if (nreq < 2914 MSIX_LEGACY_SZ + dev->caps.num_ports * MIN_MSIX_P_PORT) { 2915 /*Working in legacy mode , all EQ's shared*/ 2916 dev->caps.comp_pool = 0; 2917 dev->caps.num_comp_vectors = nreq - 1; 2918 } else { 2919 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ; 2920 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1; 2921 } 2922 for (i = 0; i < nreq; ++i) 2923 priv->eq_table.eq[i].irq = entries[i].vector; 2924 2925 dev->flags |= MLX4_FLAG_MSI_X; 2926 2927 kfree(entries); 2928 return; 2929 } 2930 2931no_msi: 2932 dev->caps.num_comp_vectors = 1; 2933 dev->caps.comp_pool = 0; 2934 2935 for (i = 0; i < 2; ++i) 2936 priv->eq_table.eq[i].irq = dev->pdev->irq; 2937} 2938 2939static int mlx4_init_port_info(struct mlx4_dev *dev, int port) 2940{ 2941 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port]; 2942 int err = 0; 2943 2944 info->dev = dev; 2945 info->port = port; 2946 if (!mlx4_is_slave(dev)) { 2947 mlx4_init_mac_table(dev, &info->mac_table); 2948 mlx4_init_vlan_table(dev, &info->vlan_table); 2949 info->base_qpn = mlx4_get_base_qpn(dev, port); 2950 } 2951 2952 sprintf(info->dev_name, "mlx4_port%d", port); 2953 info->port_attr.attr.name = info->dev_name; 2954 if (mlx4_is_mfunc(dev)) 2955 info->port_attr.attr.mode = S_IRUGO; 2956 else { 2957 info->port_attr.attr.mode = S_IRUGO | S_IWUSR; 2958 info->port_attr.store = set_port_type; 2959 } 2960 info->port_attr.show = show_port_type; 2961 sysfs_attr_init(&info->port_attr.attr); 2962 2963 err = device_create_file(&dev->pdev->dev, &info->port_attr); 2964 if (err) { 2965 mlx4_err(dev, "Failed to create file for port %d\n", port); 2966 info->port = -1; 2967 } 2968 2969 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port); 2970 info->port_mtu_attr.attr.name = info->dev_mtu_name; 2971 if (mlx4_is_mfunc(dev)) 2972 info->port_mtu_attr.attr.mode = S_IRUGO; 2973 else { 2974 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR; 2975 info->port_mtu_attr.store = set_port_ib_mtu; 2976 } 2977 info->port_mtu_attr.show = show_port_ib_mtu; 2978 sysfs_attr_init(&info->port_mtu_attr.attr); 2979 2980 err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr); 2981 if (err) { 2982 mlx4_err(dev, "Failed to create mtu file for port %d\n", port); 2983 device_remove_file(&info->dev->pdev->dev, &info->port_attr); 2984 info->port = -1; 2985 } 2986 2987 return err; 2988} 2989 2990static void mlx4_cleanup_port_info(struct mlx4_port_info *info) 2991{ 2992 if (info->port < 0) 2993 return; 2994 2995 device_remove_file(&info->dev->pdev->dev, &info->port_attr); 2996 device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr); 2997} 2998 2999static int mlx4_init_steering(struct mlx4_dev *dev) 3000{ 3001 struct mlx4_priv *priv = mlx4_priv(dev); 3002 int num_entries = dev->caps.num_ports; 3003 int i, j; 3004 3005 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL); 3006 if (!priv->steer) 3007 return -ENOMEM; 3008 3009 for (i = 0; i < num_entries; i++) 3010 for (j = 0; j < MLX4_NUM_STEERS; j++) { 3011 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]); 3012 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]); 3013 } 3014 return 0; 3015} 3016 3017static void mlx4_clear_steering(struct mlx4_dev *dev) 3018{ 3019 struct mlx4_priv *priv = mlx4_priv(dev); 3020 struct mlx4_steer_index *entry, *tmp_entry; 3021 struct mlx4_promisc_qp *pqp, *tmp_pqp; 3022 int num_entries = dev->caps.num_ports; 3023 int i, j; 3024 3025 for (i = 0; i < num_entries; i++) { 3026 for (j = 0; j < MLX4_NUM_STEERS; j++) { 3027 list_for_each_entry_safe(pqp, tmp_pqp, 3028 &priv->steer[i].promisc_qps[j], 3029 list) { 3030 list_del(&pqp->list); 3031 kfree(pqp); 3032 } 3033 list_for_each_entry_safe(entry, tmp_entry, 3034 &priv->steer[i].steer_entries[j], 3035 list) { 3036 list_del(&entry->list); 3037 list_for_each_entry_safe(pqp, tmp_pqp, 3038 &entry->duplicates, 3039 list) { 3040 list_del(&pqp->list); 3041 kfree(pqp); 3042 } 3043 kfree(entry); 3044 } 3045 } 3046 } 3047 kfree(priv->steer); 3048} 3049 3050static int extended_func_num(struct pci_dev *pdev) 3051{ 3052 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn); 3053} 3054 3055#define MLX4_OWNER_BASE 0x8069c 3056#define MLX4_OWNER_SIZE 4 3057 3058static int mlx4_get_ownership(struct mlx4_dev *dev) 3059{ 3060 void __iomem *owner; 3061 u32 ret; 3062 3063 if (pci_channel_offline(dev->pdev)) 3064 return -EIO; 3065 3066 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE, 3067 MLX4_OWNER_SIZE); 3068 if (!owner) { 3069 mlx4_err(dev, "Failed to obtain ownership bit\n"); 3070 return -ENOMEM; 3071 } 3072 3073 ret = readl(owner); 3074 iounmap(owner); 3075 return (int) !!ret; 3076} 3077 3078static void mlx4_free_ownership(struct mlx4_dev *dev) 3079{ 3080 void __iomem *owner; 3081 3082 if (pci_channel_offline(dev->pdev)) 3083 return; 3084 3085 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE, 3086 MLX4_OWNER_SIZE); 3087 if (!owner) { 3088 mlx4_err(dev, "Failed to obtain ownership bit\n"); 3089 return; 3090 } 3091 writel(0, owner); 3092 msleep(1000); 3093 iounmap(owner); 3094} 3095 3096static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data) 3097{ 3098 struct mlx4_priv *priv; 3099 struct mlx4_dev *dev; 3100 int err; 3101 int port; 3102 int nvfs, prb_vf; 3103 3104 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev)); 3105 3106 err = pci_enable_device(pdev); 3107 if (err) { 3108 dev_err(&pdev->dev, "Cannot enable PCI device, " 3109 "aborting.\n"); 3110 return err; 3111 } 3112 3113 mlx4_get_val(num_vfs.dbdf2val.tbl, pci_physfn(pdev), 0, &nvfs); 3114 mlx4_get_val(probe_vf.dbdf2val.tbl, pci_physfn(pdev), 0, &prb_vf); 3115 if (nvfs > MLX4_MAX_NUM_VF) { 3116 dev_err(&pdev->dev, "There are more VF's (%d) than allowed(%d)\n", 3117 nvfs, MLX4_MAX_NUM_VF); 3118 return -EINVAL; 3119 } 3120 3121 if (nvfs < 0) { 3122 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n"); 3123 return -EINVAL; 3124 } 3125 /* 3126 * Check for BARs. 3127 */ 3128 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) && 3129 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 3130 dev_err(&pdev->dev, "Missing DCS, aborting." 3131 "(driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%x)\n", 3132 pci_dev_data, pci_resource_flags(pdev, 0)); 3133 err = -ENODEV; 3134 goto err_disable_pdev; 3135 } 3136 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 3137 dev_err(&pdev->dev, "Missing UAR, aborting.\n"); 3138 err = -ENODEV; 3139 goto err_disable_pdev; 3140 } 3141 3142 err = pci_request_regions(pdev, DRV_NAME); 3143 if (err) { 3144 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 3145 goto err_disable_pdev; 3146 } 3147 3148 pci_set_master(pdev); 3149 3150 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 3151 if (err) { 3152 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n"); 3153 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 3154 if (err) { 3155 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n"); 3156 goto err_release_regions; 3157 } 3158 } 3159 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 3160 if (err) { 3161 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit " 3162 "consistent PCI DMA mask.\n"); 3163 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 3164 if (err) { 3165 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, " 3166 "aborting.\n"); 3167 goto err_release_regions; 3168 } 3169 } 3170 3171 /* Allow large DMA segments, up to the firmware limit of 1 GB */ 3172 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024); 3173 3174 priv = kzalloc(sizeof *priv, GFP_KERNEL); 3175 if (!priv) { 3176 dev_err(&pdev->dev, "Device struct alloc failed, " 3177 "aborting.\n"); 3178 err = -ENOMEM; 3179 goto err_release_regions; 3180 } 3181 3182 dev = &priv->dev; 3183 dev->pdev = pdev; 3184 INIT_LIST_HEAD(&priv->dev_list); 3185 INIT_LIST_HEAD(&priv->ctx_list); 3186 spin_lock_init(&priv->ctx_lock); 3187 3188 mutex_init(&priv->port_mutex); 3189 3190 INIT_LIST_HEAD(&priv->pgdir_list); 3191 mutex_init(&priv->pgdir_mutex); 3192 3193 INIT_LIST_HEAD(&priv->bf_list); 3194 mutex_init(&priv->bf_mutex); 3195 3196 dev->rev_id = pdev->revision; 3197 dev->numa_node = dev_to_node(&pdev->dev); 3198 /* Detect if this device is a virtual function */ 3199 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) { 3200 /* When acting as pf, we normally skip vfs unless explicitly 3201 * requested to probe them. */ 3202 if (nvfs && extended_func_num(pdev) > prb_vf) { 3203 mlx4_warn(dev, "Skipping virtual function:%d\n", 3204 extended_func_num(pdev)); 3205 err = -ENODEV; 3206 goto err_free_dev; 3207 } 3208 mlx4_warn(dev, "Detected virtual function - running in slave mode\n"); 3209 dev->flags |= MLX4_FLAG_SLAVE; 3210 } else { 3211 /* We reset the device and enable SRIOV only for physical 3212 * devices. Try to claim ownership on the device; 3213 * if already taken, skip -- do not allow multiple PFs */ 3214 err = mlx4_get_ownership(dev); 3215 if (err) { 3216 if (err < 0) 3217 goto err_free_dev; 3218 else { 3219 mlx4_warn(dev, "Multiple PFs not yet supported." 3220 " Skipping PF.\n"); 3221 err = -EINVAL; 3222 goto err_free_dev; 3223 } 3224 } 3225 3226 if (nvfs) { 3227 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", nvfs); 3228 err = pci_enable_sriov(pdev, nvfs); 3229 if (err) { 3230 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d).\n", 3231 err); 3232 err = 0; 3233 } else { 3234 mlx4_warn(dev, "Running in master mode\n"); 3235 dev->flags |= MLX4_FLAG_SRIOV | 3236 MLX4_FLAG_MASTER; 3237 dev->num_vfs = nvfs; 3238 } 3239 } 3240 3241 atomic_set(&priv->opreq_count, 0); 3242 INIT_WORK(&priv->opreq_task, mlx4_opreq_action); 3243 3244 /* 3245 * Now reset the HCA before we touch the PCI capabilities or 3246 * attempt a firmware command, since a boot ROM may have left 3247 * the HCA in an undefined state. 3248 */ 3249 err = mlx4_reset(dev); 3250 if (err) { 3251 mlx4_err(dev, "Failed to reset HCA, aborting.\n"); 3252 goto err_sriov; 3253 } 3254 } 3255 3256slave_start: 3257 err = mlx4_cmd_init(dev); 3258 if (err) { 3259 mlx4_err(dev, "Failed to init command interface, aborting.\n"); 3260 goto err_sriov; 3261 } 3262 3263 /* In slave functions, the communication channel must be initialized 3264 * before posting commands. Also, init num_slaves before calling 3265 * mlx4_init_hca */ 3266 if (mlx4_is_mfunc(dev)) { 3267 if (mlx4_is_master(dev)) 3268 dev->num_slaves = MLX4_MAX_NUM_SLAVES; 3269 else { 3270 dev->num_slaves = 0; 3271 err = mlx4_multi_func_init(dev); 3272 if (err) { 3273 mlx4_err(dev, "Failed to init slave mfunc" 3274 " interface, aborting.\n"); 3275 goto err_cmd; 3276 } 3277 } 3278 } 3279 3280 err = mlx4_init_hca(dev); 3281 if (err) { 3282 if (err == -EACCES) { 3283 /* Not primary Physical function 3284 * Running in slave mode */ 3285 mlx4_cmd_cleanup(dev); 3286 dev->flags |= MLX4_FLAG_SLAVE; 3287 dev->flags &= ~MLX4_FLAG_MASTER; 3288 goto slave_start; 3289 } else 3290 goto err_mfunc; 3291 } 3292 3293 /* In master functions, the communication channel must be initialized 3294 * after obtaining its address from fw */ 3295 if (mlx4_is_master(dev)) { 3296 err = mlx4_multi_func_init(dev); 3297 if (err) { 3298 mlx4_err(dev, "Failed to init master mfunc" 3299 "interface, aborting.\n"); 3300 goto err_close; 3301 } 3302 } 3303 3304 err = mlx4_alloc_eq_table(dev); 3305 if (err) 3306 goto err_master_mfunc; 3307 3308 priv->msix_ctl.pool_bm = 0; 3309 mutex_init(&priv->msix_ctl.pool_lock); 3310 3311 mlx4_enable_msi_x(dev); 3312 if ((mlx4_is_mfunc(dev)) && 3313 !(dev->flags & MLX4_FLAG_MSI_X)) { 3314 err = -ENOSYS; 3315 mlx4_err(dev, "INTx is not supported in multi-function mode." 3316 " aborting.\n"); 3317 goto err_free_eq; 3318 } 3319 3320 if (!mlx4_is_slave(dev)) { 3321 err = mlx4_init_steering(dev); 3322 if (err) 3323 goto err_free_eq; 3324 } 3325 3326 err = mlx4_setup_hca(dev); 3327 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) && 3328 !mlx4_is_mfunc(dev)) { 3329 dev->flags &= ~MLX4_FLAG_MSI_X; 3330 dev->caps.num_comp_vectors = 1; 3331 dev->caps.comp_pool = 0; 3332 pci_disable_msix(pdev); 3333 err = mlx4_setup_hca(dev); 3334 } 3335 3336 if (err) 3337 goto err_steer; 3338 3339 mlx4_init_quotas(dev); 3340 3341 for (port = 1; port <= dev->caps.num_ports; port++) { 3342 err = mlx4_init_port_info(dev, port); 3343 if (err) 3344 goto err_port; 3345 } 3346 3347 err = mlx4_register_device(dev); 3348 if (err) 3349 goto err_port; 3350 3351 mlx4_request_modules(dev); 3352 3353 mlx4_sense_init(dev); 3354 mlx4_start_sense(dev); 3355 3356 priv->pci_dev_data = pci_dev_data; 3357 pci_set_drvdata(pdev, dev); 3358 3359 return 0; 3360 3361err_port: 3362 for (--port; port >= 1; --port) 3363 mlx4_cleanup_port_info(&priv->port[port]); 3364 3365 mlx4_cleanup_counters_table(dev); 3366 mlx4_cleanup_qp_table(dev); 3367 mlx4_cleanup_srq_table(dev); 3368 mlx4_cleanup_cq_table(dev); 3369 mlx4_cmd_use_polling(dev); 3370 mlx4_cleanup_eq_table(dev); 3371 mlx4_cleanup_mcg_table(dev); 3372 mlx4_cleanup_mr_table(dev); 3373 mlx4_cleanup_xrcd_table(dev); 3374 mlx4_cleanup_pd_table(dev); 3375 mlx4_cleanup_uar_table(dev); 3376 3377err_steer: 3378 if (!mlx4_is_slave(dev)) 3379 mlx4_clear_steering(dev); 3380 3381err_free_eq: 3382 mlx4_free_eq_table(dev); 3383 3384err_master_mfunc: 3385 if (mlx4_is_master(dev)) { 3386 mlx4_free_resource_tracker(dev, RES_TR_FREE_STRUCTS_ONLY); 3387 mlx4_multi_func_cleanup(dev); 3388 } 3389 3390 if (mlx4_is_slave(dev)) { 3391 kfree(dev->caps.qp0_tunnel); 3392 kfree(dev->caps.qp0_proxy); 3393 kfree(dev->caps.qp1_tunnel); 3394 kfree(dev->caps.qp1_proxy); 3395 } 3396 3397err_close: 3398 if (dev->flags & MLX4_FLAG_MSI_X) 3399 pci_disable_msix(pdev); 3400 3401 mlx4_close_hca(dev); 3402 3403err_mfunc: 3404 if (mlx4_is_slave(dev)) 3405 mlx4_multi_func_cleanup(dev); 3406 3407err_cmd: 3408 mlx4_cmd_cleanup(dev); 3409 3410err_sriov: 3411 if (dev->flags & MLX4_FLAG_SRIOV) 3412 pci_disable_sriov(pdev); 3413 3414 if (!mlx4_is_slave(dev)) 3415 mlx4_free_ownership(dev); 3416 3417err_free_dev: 3418 kfree(priv); 3419 3420err_release_regions: 3421 pci_release_regions(pdev); 3422 3423err_disable_pdev: 3424 pci_disable_device(pdev); 3425 pci_set_drvdata(pdev, NULL); 3426 return err; 3427} 3428 3429static int __devinit mlx4_init_one(struct pci_dev *pdev, 3430 const struct pci_device_id *id) 3431{ 3432 printk_once(KERN_INFO "%s", mlx4_version); 3433 3434 return __mlx4_init_one(pdev, id->driver_data); 3435} 3436 3437static void mlx4_remove_one(struct pci_dev *pdev) 3438{ 3439 struct mlx4_dev *dev = pci_get_drvdata(pdev); 3440 struct mlx4_priv *priv = mlx4_priv(dev); 3441 int p; 3442 3443 if (dev) { 3444 /* in SRIOV it is not allowed to unload the pf's 3445 * driver while there are alive vf's */ 3446 if (mlx4_is_master(dev)) { 3447 if (mlx4_how_many_lives_vf(dev)) 3448 mlx4_err(dev, "Removing PF when there are assigned VF's !!!\n"); 3449 } 3450 mlx4_stop_sense(dev); 3451 mlx4_unregister_device(dev); 3452 3453 for (p = 1; p <= dev->caps.num_ports; p++) { 3454 mlx4_cleanup_port_info(&priv->port[p]); 3455 mlx4_CLOSE_PORT(dev, p); 3456 } 3457 3458 if (mlx4_is_master(dev)) 3459 mlx4_free_resource_tracker(dev, 3460 RES_TR_FREE_SLAVES_ONLY); 3461 3462 mlx4_cleanup_counters_table(dev); 3463 mlx4_cleanup_qp_table(dev); 3464 mlx4_cleanup_srq_table(dev); 3465 mlx4_cleanup_cq_table(dev); 3466 mlx4_cmd_use_polling(dev); 3467 mlx4_cleanup_eq_table(dev); 3468 mlx4_cleanup_mcg_table(dev); 3469 mlx4_cleanup_mr_table(dev); 3470 mlx4_cleanup_xrcd_table(dev); 3471 mlx4_cleanup_pd_table(dev); 3472 3473 if (mlx4_is_master(dev)) 3474 mlx4_free_resource_tracker(dev, 3475 RES_TR_FREE_STRUCTS_ONLY); 3476 3477 iounmap(priv->kar); 3478 mlx4_uar_free(dev, &priv->driver_uar); 3479 mlx4_cleanup_uar_table(dev); 3480 if (!mlx4_is_slave(dev)) 3481 mlx4_clear_steering(dev); 3482 mlx4_free_eq_table(dev); 3483 if (mlx4_is_master(dev)) 3484 mlx4_multi_func_cleanup(dev); 3485 mlx4_close_hca(dev); 3486 if (mlx4_is_slave(dev)) 3487 mlx4_multi_func_cleanup(dev); 3488 mlx4_cmd_cleanup(dev); 3489 3490 if (dev->flags & MLX4_FLAG_MSI_X) 3491 pci_disable_msix(pdev); 3492 if (dev->flags & MLX4_FLAG_SRIOV) { 3493 mlx4_warn(dev, "Disabling SR-IOV\n"); 3494 pci_disable_sriov(pdev); 3495 } 3496 3497 if (!mlx4_is_slave(dev)) 3498 mlx4_free_ownership(dev); 3499 3500 kfree(dev->caps.qp0_tunnel); 3501 kfree(dev->caps.qp0_proxy); 3502 kfree(dev->caps.qp1_tunnel); 3503 kfree(dev->caps.qp1_proxy); 3504 3505 kfree(priv); 3506 pci_release_regions(pdev); 3507 pci_disable_device(pdev); 3508 pci_set_drvdata(pdev, NULL); 3509 } 3510} 3511 3512static int restore_current_port_types(struct mlx4_dev *dev, 3513 enum mlx4_port_type *types, 3514 enum mlx4_port_type *poss_types) 3515{ 3516 struct mlx4_priv *priv = mlx4_priv(dev); 3517 int err, i; 3518 3519 mlx4_stop_sense(dev); 3520 mutex_lock(&priv->port_mutex); 3521 for (i = 0; i < dev->caps.num_ports; i++) 3522 dev->caps.possible_type[i + 1] = poss_types[i]; 3523 err = mlx4_change_port_types(dev, types); 3524 mlx4_start_sense(dev); 3525 mutex_unlock(&priv->port_mutex); 3526 return err; 3527} 3528 3529int mlx4_restart_one(struct pci_dev *pdev) 3530{ 3531 struct mlx4_dev *dev = pci_get_drvdata(pdev); 3532 struct mlx4_priv *priv = mlx4_priv(dev); 3533 enum mlx4_port_type curr_type[MLX4_MAX_PORTS]; 3534 enum mlx4_port_type poss_type[MLX4_MAX_PORTS]; 3535 int pci_dev_data, err, i; 3536 3537 pci_dev_data = priv->pci_dev_data; 3538 for (i = 0; i < dev->caps.num_ports; i++) { 3539 curr_type[i] = dev->caps.port_type[i + 1]; 3540 poss_type[i] = dev->caps.possible_type[i + 1]; 3541 } 3542 3543 mlx4_remove_one(pdev); 3544 err = __mlx4_init_one(pdev, pci_dev_data); 3545 if (err) 3546 return err; 3547 3548 dev = pci_get_drvdata(pdev); 3549 err = restore_current_port_types(dev, curr_type, poss_type); 3550 if (err) 3551 mlx4_err(dev, "mlx4_restart_one: could not restore original port types (%d)\n", 3552 err); 3553 return 0; 3554} 3555 3556static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = { 3557 /* MT25408 "Hermon" SDR */ 3558 { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3559 /* MT25408 "Hermon" DDR */ 3560 { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3561 /* MT25408 "Hermon" QDR */ 3562 { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3563 /* MT25408 "Hermon" DDR PCIe gen2 */ 3564 { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3565 /* MT25408 "Hermon" QDR PCIe gen2 */ 3566 { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3567 /* MT25408 "Hermon" EN 10GigE */ 3568 { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3569 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */ 3570 { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3571 /* MT25458 ConnectX EN 10GBASE-T 10GigE */ 3572 { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3573 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */ 3574 { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3575 /* MT26468 ConnectX EN 10GigE PCIe gen2*/ 3576 { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3577 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */ 3578 { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3579 /* MT26478 ConnectX2 40GigE PCIe gen2 */ 3580 { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3581 /* MT25400 Family [ConnectX-2 Virtual Function] */ 3582 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF }, 3583 /* MT27500 Family [ConnectX-3] */ 3584 { PCI_VDEVICE(MELLANOX, 0x1003), 0 }, 3585 /* MT27500 Family [ConnectX-3 Virtual Function] */ 3586 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF }, 3587 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */ 3588 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */ 3589 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */ 3590 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */ 3591 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */ 3592 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */ 3593 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */ 3594 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */ 3595 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */ 3596 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */ 3597 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */ 3598 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */ 3599 { 0, } 3600}; 3601 3602MODULE_DEVICE_TABLE(pci, mlx4_pci_table); 3603 3604static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev, 3605 pci_channel_state_t state) 3606{ 3607 mlx4_remove_one(pdev); 3608 3609 return state == pci_channel_io_perm_failure ? 3610 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 3611} 3612 3613static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev) 3614{ 3615 int ret = __mlx4_init_one(pdev, 0); 3616 3617 return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; 3618} 3619 3620static const struct pci_error_handlers mlx4_err_handler = { 3621 .error_detected = mlx4_pci_err_detected, 3622 .slot_reset = mlx4_pci_slot_reset, 3623}; 3624 3625static int suspend(struct pci_dev *pdev, pm_message_t state) 3626{ 3627 mlx4_remove_one(pdev); 3628 3629 return 0; 3630} 3631 3632static int resume(struct pci_dev *pdev) 3633{ 3634 return __mlx4_init_one(pdev, 0); 3635} 3636 3637static struct pci_driver mlx4_driver = { 3638 .name = DRV_NAME, 3639 .id_table = mlx4_pci_table, 3640 .probe = mlx4_init_one, 3641 .remove = __devexit_p(mlx4_remove_one), 3642 .suspend = suspend, 3643 .resume = resume, 3644 .err_handler = &mlx4_err_handler, 3645}; 3646 3647static int __init mlx4_verify_params(void) 3648{ 3649 int status; 3650 3651 status = update_defaults(&port_type_array); 3652 if (status == INVALID_STR) { 3653 if (mlx4_fill_dbdf2val_tbl(&port_type_array.dbdf2val)) 3654 return -1; 3655 } else if (status == INVALID_DATA) { 3656 return -1; 3657 } 3658 3659 status = update_defaults(&num_vfs); 3660 if (status == INVALID_STR) { 3661 if (mlx4_fill_dbdf2val_tbl(&num_vfs.dbdf2val)) 3662 return -1; 3663 } else if (status == INVALID_DATA) { 3664 return -1; 3665 } 3666 3667 status = update_defaults(&probe_vf); 3668 if (status == INVALID_STR) { 3669 if (mlx4_fill_dbdf2val_tbl(&probe_vf.dbdf2val)) 3670 return -1; 3671 } else if (status == INVALID_DATA) { 3672 return -1; 3673 } 3674 3675 if (msi_x < 0) { 3676 pr_warn("mlx4_core: bad msi_x: %d\n", msi_x); 3677 return -1; 3678 } 3679 3680 if ((log_num_mac < 0) || (log_num_mac > 7)) { 3681 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac); 3682 return -1; 3683 } 3684 3685 if (log_num_vlan != 0) 3686 pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n", 3687 MLX4_LOG_NUM_VLANS); 3688 3689 if (mlx4_set_4k_mtu != -1) 3690 pr_warning("mlx4_core: set_4k_mtu - obsolete module param\n"); 3691 3692 if ((log_mtts_per_seg < 0) || (log_mtts_per_seg > 7)) { 3693 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg); 3694 return -1; 3695 } 3696 3697 if (mlx4_log_num_mgm_entry_size != -1 && 3698 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE || 3699 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE)) { 3700 pr_warning("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not " 3701 "in legal range (-1 or %d..%d)\n", 3702 mlx4_log_num_mgm_entry_size, 3703 MLX4_MIN_MGM_LOG_ENTRY_SIZE, 3704 MLX4_MAX_MGM_LOG_ENTRY_SIZE); 3705 return -1; 3706 } 3707 3708 if (mod_param_profile.num_qp < 18 || mod_param_profile.num_qp > 23) { 3709 pr_warning("mlx4_core: bad log_num_qp: %d\n", 3710 mod_param_profile.num_qp); 3711 return -1; 3712 } 3713 3714 if (mod_param_profile.num_srq < 10) { 3715 pr_warning("mlx4_core: too low log_num_srq: %d\n", 3716 mod_param_profile.num_srq); 3717 return -1; 3718 } 3719 3720 if (mod_param_profile.num_cq < 10) { 3721 pr_warning("mlx4_core: too low log_num_cq: %d\n", 3722 mod_param_profile.num_cq); 3723 return -1; 3724 } 3725 3726 if (mod_param_profile.num_mpt < 10) { 3727 pr_warning("mlx4_core: too low log_num_mpt: %d\n", 3728 mod_param_profile.num_mpt); 3729 return -1; 3730 } 3731 3732 if (mod_param_profile.num_mtt_segs && 3733 mod_param_profile.num_mtt_segs < 15) { 3734 pr_warning("mlx4_core: too low log_num_mtt: %d\n", 3735 mod_param_profile.num_mtt_segs); 3736 return -1; 3737 } 3738 3739 if (mod_param_profile.num_mtt_segs > MLX4_MAX_LOG_NUM_MTT) { 3740 pr_warning("mlx4_core: too high log_num_mtt: %d\n", 3741 mod_param_profile.num_mtt_segs); 3742 return -1; 3743 } 3744 return 0; 3745} 3746 3747static int __init mlx4_init(void) 3748{ 3749 int ret; 3750 3751 if (mlx4_verify_params()) 3752 return -EINVAL; 3753 3754 mlx4_catas_init(); 3755 3756 mlx4_wq = create_singlethread_workqueue("mlx4"); 3757 if (!mlx4_wq) 3758 return -ENOMEM; 3759 3760 if (enable_sys_tune) 3761 sys_tune_init(); 3762 3763 ret = pci_register_driver(&mlx4_driver); 3764 if (ret < 0) 3765 goto err; 3766 3767 return 0; 3768 3769err: 3770 if (enable_sys_tune) 3771 sys_tune_fini(); 3772 3773 destroy_workqueue(mlx4_wq); 3774 3775 return ret; 3776} 3777 3778static void __exit mlx4_cleanup(void) 3779{ 3780 if (enable_sys_tune) 3781 sys_tune_fini(); 3782 3783 pci_unregister_driver(&mlx4_driver); 3784 destroy_workqueue(mlx4_wq); 3785} 3786 3787module_init_order(mlx4_init, SI_ORDER_MIDDLE); 3788module_exit(mlx4_cleanup); 3789 3790#include <sys/module.h> 3791static int 3792mlx4_evhand(module_t mod, int event, void *arg) 3793{ 3794 return (0); 3795} 3796 3797static moduledata_t mlx4_mod = { 3798 .name = "mlx4", 3799 .evhand = mlx4_evhand, 3800}; 3801MODULE_VERSION(mlx4, 1); 3802DECLARE_MODULE(mlx4, mlx4_mod, SI_SUB_OFED_PREINIT, SI_ORDER_ANY); 3803