pte.h revision 257523
1152851Sariff/*- 2152851Sariff * Copyright (c) 2004-2010 Juli Mallett <jmallett@FreeBSD.org> 3152851Sariff * All rights reserved. 4152851Sariff * 5152851Sariff * Redistribution and use in source and binary forms, with or without 6152851Sariff * modification, are permitted provided that the following conditions 7152851Sariff * are met: 8152851Sariff * 1. Redistributions of source code must retain the above copyright 9152851Sariff * notice, this list of conditions and the following disclaimer. 10152851Sariff * 2. Redistributions in binary form must reproduce the above copyright 11152851Sariff * notice, this list of conditions and the following disclaimer in the 12152851Sariff * documentation and/or other materials provided with the distribution. 13152851Sariff * 14152851Sariff * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15152851Sariff * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16152851Sariff * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17152851Sariff * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18152851Sariff * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19152851Sariff * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20152851Sariff * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21152851Sariff * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22152851Sariff * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23152851Sariff * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24152851Sariff * SUCH DAMAGE. 25152851Sariff * 26152851Sariff * $FreeBSD: stable/10/sys/mips/include/pte.h 257523 2013-11-01 20:30:19Z brooks $ 27152851Sariff */ 28152851Sariff 29152851Sariff#ifndef _MACHINE_PTE_H_ 30152851Sariff#define _MACHINE_PTE_H_ 31152851Sariff 32152851Sariff#ifndef _LOCORE 33155800Sariff#if defined(__mips_n64) || defined(__mips_n32) /* PHYSADDR_64_BIT */ 34152851Sarifftypedef uint64_t pt_entry_t; 35152851Sariff#else 36152851Sarifftypedef uint32_t pt_entry_t; 37152851Sariff#endif 38152851Sarifftypedef pt_entry_t *pd_entry_t; 39155800Sariff#endif 40155800Sariff 41152851Sariff/* 42152851Sariff * TLB and PTE management. Most things operate within the context of 43152851Sariff * EntryLo0,1, and begin with TLBLO_. Things which work with EntryHi 44152851Sariff * start with TLBHI_. PTE bits begin with PTE_. 45152851Sariff * 46152851Sariff * Note that we use the same size VM and TLB pages. 47152851Sariff */ 48152851Sariff#define TLB_PAGE_SHIFT (PAGE_SHIFT) 49152851Sariff#define TLB_PAGE_SIZE (1 << TLB_PAGE_SHIFT) 50152851Sariff#define TLB_PAGE_MASK (TLB_PAGE_SIZE - 1) 51152851Sariff 52152851Sariff/* 53152851Sariff * TLB PageMask register. Has mask bits set above the default, 4K, page mask. 54152851Sariff */ 55152851Sariff#define TLBMASK_SHIFT (13) 56193640Sariff#define TLBMASK_MASK ((PAGE_MASK >> TLBMASK_SHIFT) << TLBMASK_SHIFT) 57193640Sariff 58193640Sariff/* 59193640Sariff * FreeBSD/mips page-table entries take a near-identical format to MIPS TLB 60152851Sariff * entries, each consisting of two 32-bit or 64-bit values ("EntryHi" and 61152851Sariff * "EntryLo"). MIPS4k and MIPS64 both define certain bits in TLB entries as 62152851Sariff * reserved, and these must be zero-filled by software. We overload these 63152851Sariff * bits in PTE entries to hold PTE_ flags such as RO, W, and MANAGED. 64152851Sariff * However, we must mask these out when writing to TLB entries to ensure that 65152851Sariff * they do not become visible to hardware -- especially on MIPS64r2 which has 66152851Sariff * an extended physical memory space. 67152851Sariff * 68152851Sariff * When using n64 and n32, shift software-defined bits into the MIPS64r2 69152851Sariff * reserved range, which runs from bit 55 ... 63. In other configurations 70152851Sariff * (32-bit MIPS4k and compatible), shift them out to bits 29 ... 31. 71152851Sariff * 72167648Sariff * NOTE: This means that for 32-bit use of CP0, we aren't able to set the top 73162931Sariff * bit of PFN to a non-zero value, as software is using it! This physical 74167648Sariff * memory size limit may not be sufficiently enforced elsewhere. 75167648Sariff */ 76167648Sariff#if defined(__mips_n64) || defined(__mips_n32) /* PHYSADDR_64_BIT */ 77162931Sariff#define TLBLO_SWBITS_SHIFT (55) 78167648Sariff#define TLBLO_SWBITS_CLEAR_SHIFT (9) 79167648Sariff#define TLBLO_PFN_MASK 0x3FFFFFFC0ULL 80167648Sariff#else 81171329Sariff#define TLBLO_SWBITS_SHIFT (29) 82171329Sariff#define TLBLO_SWBITS_CLEAR_SHIFT (3) 83171329Sariff#define TLBLO_PFN_MASK (0x1FFFFFC0) 84152851Sariff#endif 85155800Sariff#define TLBLO_PFN_SHIFT (6) 86155800Sariff#define TLBLO_SWBITS_MASK ((pt_entry_t)0x7 << TLBLO_SWBITS_SHIFT) 87155800Sariff#define TLBLO_PA_TO_PFN(pa) ((((pa) >> TLB_PAGE_SHIFT) << TLBLO_PFN_SHIFT) & TLBLO_PFN_MASK) 88155800Sariff#define TLBLO_PFN_TO_PA(pfn) ((vm_paddr_t)((pfn) >> TLBLO_PFN_SHIFT) << TLB_PAGE_SHIFT) 89152851Sariff#define TLBLO_PTE_TO_PFN(pte) ((pte) & TLBLO_PFN_MASK) 90152851Sariff#define TLBLO_PTE_TO_PA(pte) (TLBLO_PFN_TO_PA(TLBLO_PTE_TO_PFN((pte)))) 91152851Sariff 92152851Sariff/* 93152851Sariff * XXX This comment is not correct for anything more modern than R4K. 94152851Sariff * 95152851Sariff * VPN for EntryHi register. Upper two bits select user, supervisor, 96152851Sariff * or kernel. Bits 61 to 40 copy bit 63. VPN2 is bits 39 and down to 97152851Sariff * as low as 13, down to PAGE_SHIFT, to index 2 TLB pages*. From bit 12 98152851Sariff * to bit 8 there is a 5-bit 0 field. Low byte is ASID. 99164614Sariff * 100164614Sariff * XXX This comment is not correct for FreeBSD. 101164614Sariff * Note that in FreeBSD, we map 2 TLB pages is equal to 1 VM page. 102153708Sariff */ 103171329Sariff#define TLBHI_ASID_MASK (0xff) 104171329Sariff#if defined(__mips_n64) 105152851Sariff#define TLBHI_R_SHIFT 62 106152851Sariff#define TLBHI_R_USER (0x00UL << TLBHI_R_SHIFT) 107152851Sariff#define TLBHI_R_SUPERVISOR (0x01UL << TLBHI_R_SHIFT) 108152851Sariff#define TLBHI_R_KERNEL (0x03UL << TLBHI_R_SHIFT) 109152851Sariff#define TLBHI_R_MASK (0x03UL << TLBHI_R_SHIFT) 110152851Sariff#define TLBHI_VA_R(va) ((va) & TLBHI_R_MASK) 111152851Sariff#define TLBHI_FILL_SHIFT 40 112152851Sariff#define TLBHI_VPN2_SHIFT (TLB_PAGE_SHIFT + 1) 113152851Sariff#define TLBHI_VPN2_MASK (((~((1UL << TLBHI_VPN2_SHIFT) - 1)) << (63 - TLBHI_FILL_SHIFT)) >> (63 - TLBHI_FILL_SHIFT)) 114152851Sariff#define TLBHI_VA_TO_VPN2(va) ((va) & TLBHI_VPN2_MASK) 115152851Sariff#define TLBHI_ENTRY(va, asid) ((TLBHI_VA_R((va))) /* Region. */ | \ 116152851Sariff (TLBHI_VA_TO_VPN2((va))) /* VPN2. */ | \ 117152851Sariff ((asid) & TLBHI_ASID_MASK)) 118152851Sariff#else /* !defined(__mips_n64) */ 119152851Sariff#define TLBHI_PAGE_MASK (2 * PAGE_SIZE - 1) 120152851Sariff#define TLBHI_ENTRY(va, asid) (((va) & ~TLBHI_PAGE_MASK) | ((asid) & TLBHI_ASID_MASK)) 121152851Sariff#endif /* defined(__mips_n64) */ 122152851Sariff 123152851Sariff/* 124152851Sariff * TLB flags managed in hardware: 125152851Sariff * C: Cache attribute. 126152851Sariff * D: Dirty bit. This means a page is writable. It is not 127152851Sariff * set at first, and a write is trapped, and the dirty 128152851Sariff * bit is set. See also PTE_RO. 129164614Sariff * V: Valid bit. Obvious, isn't it? 130152851Sariff * G: Global bit. This means that this mapping is present 131152851Sariff * in EVERY address space, and to ignore the ASID when 132152851Sariff * it is matched. 133164614Sariff */ 134164614Sariff#define PTE_C(attr) ((attr & 0x07) << 3) 135152851Sariff#define PTE_C_UNCACHED (PTE_C(MIPS_CCA_UNCACHED)) 136152851Sariff#define PTE_C_CACHE (PTE_C(MIPS_CCA_CACHED)) 137152851Sariff#define PTE_D 0x04 138152851Sariff#define PTE_V 0x02 139152851Sariff#define PTE_G 0x01 140152851Sariff 141152851Sariff/* 142152851Sariff * VM flags managed in software: 143152851Sariff * RO: Read only. Never set PTE_D on this page, and don't 144152851Sariff * listen to requests to write to it. 145152851Sariff * W: Wired. ??? 146152851Sariff * MANAGED:Managed. This PTE maps a managed page. 147193640Sariff * 148193640Sariff * These bits should not be written into the TLB, so must first be masked out 149152851Sariff * explicitly in C, or using CLEAR_PTE_SWBITS() in assembly. 150152851Sariff */ 151152851Sariff#define PTE_RO ((pt_entry_t)0x01 << TLBLO_SWBITS_SHIFT) 152152851Sariff#define PTE_W ((pt_entry_t)0x02 << TLBLO_SWBITS_SHIFT) 153193640Sariff#define PTE_MANAGED ((pt_entry_t)0x04 << TLBLO_SWBITS_SHIFT) 154152851Sariff 155152851Sariff/* 156152851Sariff * PTE management functions for bits defined above. 157152851Sariff */ 158152851Sariff#define pte_clear(pte, bit) (*(pte) &= ~(bit)) 159152851Sariff#define pte_set(pte, bit) (*(pte) |= (bit)) 160152851Sariff#define pte_test(pte, bit) ((*(pte) & (bit)) == (bit)) 161152851Sariff 162152851Sariff/* Assembly support for PTE access*/ 163152851Sariff#ifdef LOCORE 164152851Sariff#if defined(__mips_n64) || defined(__mips_n32) /* PHYSADDR_64_BIT */ 165162931Sariff#define PTESHIFT 3 166152851Sariff#define PTE2MASK 0xff0 /* for the 2-page lo0/lo1 */ 167152851Sariff#define PTEMASK 0xff8 168152851Sariff#define PTESIZE 8 169152851Sariff#define PTE_L ld 170152851Sariff#define PTE_MTC0 dmtc0 171152851Sariff#define CLEAR_PTE_SWBITS(pr) 172152851Sariff#else 173152851Sariff#define PTESHIFT 2 174152851Sariff#define PTE2MASK 0xff8 /* for the 2-page lo0/lo1 */ 175152851Sariff#define PTEMASK 0xffc 176152851Sariff#define PTESIZE 4 177173329Sariff#define PTE_L lw 178152851Sariff#define PTE_MTC0 mtc0 179152851Sariff#define CLEAR_PTE_SWBITS(r) LONG_SLL r, TLBLO_SWBITS_CLEAR_SHIFT; LONG_SRL r, TLBLO_SWBITS_CLEAR_SHIFT /* remove swbits */ 180152851Sariff#endif /* defined(__mips_n64) || defined(__mips_n32) */ 181152851Sariff 182152851Sariff#if defined(__mips_n64) 183162931Sariff#define PTRSHIFT 3 184162931Sariff#define PDEPTRMASK 0xff8 185162931Sariff#else 186152851Sariff#define PTRSHIFT 2 187152851Sariff#define PDEPTRMASK 0xffc 188152851Sariff#endif 189152851Sariff 190152851Sariff#endif /* LOCORE */ 191152851Sariff#endif /* !_MACHINE_PTE_H_ */ 192152851Sariff