mp_machdep.c revision 268195
1/*- 2 * Copyright (c) 2001-2005 Marcel Moolenaar 3 * Copyright (c) 2000 Doug Rabson 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: stable/10/sys/ia64/ia64/mp_machdep.c 268195 2014-07-02 23:23:18Z marcel $"); 30 31#include "opt_kstack_pages.h" 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/ktr.h> 36#include <sys/proc.h> 37#include <sys/bus.h> 38#include <sys/kthread.h> 39#include <sys/lock.h> 40#include <sys/malloc.h> 41#include <sys/mutex.h> 42#include <sys/kernel.h> 43#include <sys/pcpu.h> 44#include <sys/sched.h> 45#include <sys/smp.h> 46#include <sys/sysctl.h> 47#include <sys/uuid.h> 48 49#include <machine/atomic.h> 50#include <machine/bootinfo.h> 51#include <machine/cpu.h> 52#include <machine/fpu.h> 53#include <machine/intr.h> 54#include <machine/mca.h> 55#include <machine/md_var.h> 56#include <machine/pal.h> 57#include <machine/pcb.h> 58#include <machine/sal.h> 59#include <machine/smp.h> 60 61#include <vm/vm.h> 62#include <vm/pmap.h> 63#include <vm/vm_extern.h> 64#include <vm/vm_kern.h> 65 66extern uint64_t bdata[]; 67 68extern int smp_disabled; 69 70MALLOC_DEFINE(M_SMP, "SMP", "SMP related allocations"); 71 72void ia64_ap_startup(void); 73 74#define SAPIC_ID_GET_ID(x) ((u_int)((x) >> 8) & 0xff) 75#define SAPIC_ID_GET_EID(x) ((u_int)(x) & 0xff) 76#define SAPIC_ID_SET(id, eid) ((u_int)(((id) & 0xff) << 8) | ((eid) & 0xff)) 77 78/* State used to wake and bootstrap APs. */ 79struct ia64_ap_state ia64_ap_state; 80 81int ia64_ipi_ast; 82int ia64_ipi_hardclock; 83int ia64_ipi_highfp; 84int ia64_ipi_nmi; 85int ia64_ipi_preempt; 86int ia64_ipi_rndzvs; 87int ia64_ipi_stop; 88 89static u_int 90sz2shft(uint64_t sz) 91{ 92 uint64_t s; 93 u_int shft; 94 95 shft = 12; /* Start with 4K */ 96 s = 1 << shft; 97 while (s < sz) { 98 shft++; 99 s <<= 1; 100 } 101 return (shft); 102} 103 104static u_int 105ia64_ih_ast(struct thread *td, u_int xiv, struct trapframe *tf) 106{ 107 108 PCPU_INC(md.stats.pcs_nasts); 109 CTR1(KTR_SMP, "IPI_AST, cpuid=%d", PCPU_GET(cpuid)); 110 return (0); 111} 112 113static u_int 114ia64_ih_hardclock(struct thread *td, u_int xiv, struct trapframe *tf) 115{ 116 struct trapframe *stf; 117 118 PCPU_INC(md.stats.pcs_nhardclocks); 119 CTR1(KTR_SMP, "IPI_HARDCLOCK, cpuid=%d", PCPU_GET(cpuid)); 120 stf = td->td_intr_frame; 121 td->td_intr_frame = tf; 122 hardclockintr(); 123 td->td_intr_frame = stf; 124 return (0); 125} 126 127static u_int 128ia64_ih_highfp(struct thread *td, u_int xiv, struct trapframe *tf) 129{ 130 131 PCPU_INC(md.stats.pcs_nhighfps); 132 ia64_highfp_save_ipi(); 133 return (0); 134} 135 136static u_int 137ia64_ih_preempt(struct thread *td, u_int xiv, struct trapframe *tf) 138{ 139 140 PCPU_INC(md.stats.pcs_npreempts); 141 CTR1(KTR_SMP, "IPI_PREEMPT, cpuid=%d", PCPU_GET(cpuid)); 142 sched_preempt(curthread); 143 return (0); 144} 145 146static u_int 147ia64_ih_rndzvs(struct thread *td, u_int xiv, struct trapframe *tf) 148{ 149 150 PCPU_INC(md.stats.pcs_nrdvs); 151 CTR1(KTR_SMP, "IPI_RENDEZVOUS, cpuid=%d", PCPU_GET(cpuid)); 152 smp_rendezvous_action(); 153 return (0); 154} 155 156static u_int 157ia64_ih_stop(struct thread *td, u_int xiv, struct trapframe *tf) 158{ 159 u_int cpuid; 160 161 PCPU_INC(md.stats.pcs_nstops); 162 cpuid = PCPU_GET(cpuid); 163 164 savectx(PCPU_PTR(md.pcb)); 165 166 CPU_SET_ATOMIC(cpuid, &stopped_cpus); 167 while (!CPU_ISSET(cpuid, &started_cpus)) 168 cpu_spinwait(); 169 CPU_CLR_ATOMIC(cpuid, &started_cpus); 170 CPU_CLR_ATOMIC(cpuid, &stopped_cpus); 171 return (0); 172} 173 174struct cpu_group * 175cpu_topo(void) 176{ 177 178 return smp_topo_none(); 179} 180 181static void 182ia64_store_mca_state(void* arg) 183{ 184 struct pcpu *pc = arg; 185 struct thread *td = curthread; 186 187 /* 188 * ia64_mca_save_state() is CPU-sensitive, so bind ourself to our 189 * target CPU. 190 */ 191 thread_lock(td); 192 sched_bind(td, pc->pc_cpuid); 193 thread_unlock(td); 194 195 ia64_mca_init_ap(); 196 197 /* 198 * Get and save the CPU specific MCA records. Should we get the 199 * MCA state for each processor, or just the CMC state? 200 */ 201 ia64_mca_save_state(SAL_INFO_MCA); 202 ia64_mca_save_state(SAL_INFO_CMC); 203 204 kproc_exit(0); 205} 206 207void 208ia64_ap_startup(void) 209{ 210 uint64_t vhpt; 211 212 ia64_ap_state.as_trace = 0x100; 213 214 ia64_set_rr(IA64_RR_BASE(5), (5 << 8) | (PAGE_SHIFT << 2) | 1); 215 ia64_set_rr(IA64_RR_BASE(6), (6 << 8) | (LOG2_ID_PAGE_SIZE << 2)); 216 ia64_set_rr(IA64_RR_BASE(7), (7 << 8) | (LOG2_ID_PAGE_SIZE << 2)); 217 ia64_srlz_d(); 218 219 pcpup = ia64_ap_state.as_pcpu; 220 ia64_set_k4((intptr_t)pcpup); 221 222 ia64_ap_state.as_trace = 0x108; 223 224 vhpt = PCPU_GET(md.vhpt); 225 map_vhpt(vhpt); 226 ia64_set_pta(vhpt + (1 << 8) + (pmap_vhpt_log2size << 2) + 1); 227 ia64_srlz_i(); 228 229 ia64_ap_state.as_trace = 0x110; 230 231 ia64_ap_state.as_awake = 1; 232 ia64_ap_state.as_delay = 0; 233 234 map_pal_code(); 235 map_gateway_page(); 236 237 ia64_set_fpsr(IA64_FPSR_DEFAULT); 238 239 /* Wait until it's time for us to be unleashed */ 240 while (ia64_ap_state.as_spin) 241 cpu_spinwait(); 242 243 /* Initialize curthread. */ 244 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread")); 245 PCPU_SET(curthread, PCPU_GET(idlethread)); 246 247 pmap_invalidate_all(); 248 249 atomic_add_int(&ia64_ap_state.as_awake, 1); 250 while (!smp_started) 251 cpu_spinwait(); 252 253 CTR1(KTR_SMP, "SMP: cpu%d launched", PCPU_GET(cpuid)); 254 255 cpu_initclocks(); 256 257 ia64_set_tpr(0); 258 ia64_srlz_d(); 259 260 sched_throw(NULL); 261 /* NOTREACHED */ 262} 263 264void 265cpu_mp_setmaxid(void) 266{ 267 268 /* 269 * Count the number of processors in the system by walking the ACPI 270 * tables. Note that we record the actual number of processors, even 271 * if this is larger than MAXCPU. We only activate MAXCPU processors. 272 */ 273 mp_ncpus = ia64_count_cpus(); 274 275 /* 276 * Set the largest cpuid we're going to use. This is necessary for 277 * VM initialization. 278 */ 279 mp_maxid = min(mp_ncpus, MAXCPU) - 1; 280} 281 282int 283cpu_mp_probe(void) 284{ 285 286 /* 287 * If there's only 1 processor, or we don't have a wake-up vector, 288 * we're not going to enable SMP. Note that no wake-up vector can 289 * also mean that the wake-up mechanism is not supported. In this 290 * case we can have multiple processors, but we simply can't wake 291 * them up... 292 */ 293 return (mp_ncpus > 1 && ia64_ipi_wakeup != 0); 294} 295 296void 297cpu_mp_add(u_int acpi_id, u_int id, u_int eid) 298{ 299 struct pcpu *pc; 300 void *dpcpu; 301 u_int cpuid, sapic_id; 302 303 if (smp_disabled) 304 return; 305 306 sapic_id = SAPIC_ID_SET(id, eid); 307 cpuid = (IA64_LID_GET_SAPIC_ID(ia64_get_lid()) == sapic_id) 308 ? 0 : smp_cpus++; 309 310 KASSERT(!CPU_ISSET(cpuid, &all_cpus), 311 ("%s: cpu%d already in CPU map", __func__, acpi_id)); 312 313 if (cpuid != 0) { 314 pc = (struct pcpu *)malloc(sizeof(*pc), M_SMP, M_WAITOK); 315 pcpu_init(pc, cpuid, sizeof(*pc)); 316 dpcpu = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE, 317 M_WAITOK | M_ZERO); 318 dpcpu_init(dpcpu, cpuid); 319 } else 320 pc = pcpup; 321 322 cpu_pcpu_setup(pc, acpi_id, sapic_id); 323 324 CPU_SET(pc->pc_cpuid, &all_cpus); 325} 326 327void 328cpu_mp_announce() 329{ 330 struct pcpu *pc; 331 uint32_t sapic_id; 332 int i; 333 334 for (i = 0; i <= mp_maxid; i++) { 335 pc = pcpu_find(i); 336 if (pc != NULL) { 337 sapic_id = IA64_LID_GET_SAPIC_ID(pc->pc_md.lid); 338 printf("cpu%d: ACPI Id=%x, SAPIC Id=%x, SAPIC Eid=%x", 339 i, pc->pc_acpi_id, SAPIC_ID_GET_ID(sapic_id), 340 SAPIC_ID_GET_EID(sapic_id)); 341 if (i == 0) 342 printf(" (BSP)\n"); 343 else 344 printf("\n"); 345 } 346 } 347} 348 349void 350cpu_mp_start() 351{ 352 struct ia64_sal_result result; 353 struct ia64_fdesc *fd; 354 struct pcpu *pc; 355 uintptr_t state; 356 u_char *stp; 357 358 state = ia64_tpa((uintptr_t)&ia64_ap_state); 359 fd = (struct ia64_fdesc *) os_boot_rendez; 360 result = ia64_sal_entry(SAL_SET_VECTORS, SAL_OS_BOOT_RENDEZ, 361 ia64_tpa(fd->func), state, 0, 0, 0, 0); 362 363 ia64_ap_state.as_pgtbl_pte = PTE_PRESENT | PTE_MA_WB | 364 PTE_ACCESSED | PTE_DIRTY | PTE_PL_KERN | PTE_AR_RW | 365 (bootinfo->bi_pbvm_pgtbl & PTE_PPN_MASK); 366 ia64_ap_state.as_pgtbl_itir = sz2shft(bootinfo->bi_pbvm_pgtblsz) << 2; 367 ia64_ap_state.as_text_va = IA64_PBVM_BASE; 368 ia64_ap_state.as_text_pte = PTE_PRESENT | PTE_MA_WB | 369 PTE_ACCESSED | PTE_DIRTY | PTE_PL_KERN | PTE_AR_RX | 370 (ia64_tpa(IA64_PBVM_BASE) & PTE_PPN_MASK); 371 ia64_ap_state.as_text_itir = bootinfo->bi_text_mapped << 2; 372 ia64_ap_state.as_data_va = (uintptr_t)bdata; 373 ia64_ap_state.as_data_pte = PTE_PRESENT | PTE_MA_WB | 374 PTE_ACCESSED | PTE_DIRTY | PTE_PL_KERN | PTE_AR_RW | 375 (ia64_tpa((uintptr_t)bdata) & PTE_PPN_MASK); 376 ia64_ap_state.as_data_itir = bootinfo->bi_data_mapped << 2; 377 378 /* Keep 'em spinning until we unleash them... */ 379 ia64_ap_state.as_spin = 1; 380 381 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 382 pc->pc_md.current_pmap = kernel_pmap; 383 /* The BSP is obviously running already. */ 384 if (pc->pc_cpuid == 0) { 385 pc->pc_md.awake = 1; 386 continue; 387 } 388 389 ia64_ap_state.as_pcpu = pc; 390 pc->pc_md.vhpt = pmap_alloc_vhpt(); 391 if (pc->pc_md.vhpt == 0) { 392 printf("SMP: WARNING: unable to allocate VHPT" 393 " for cpu%d", pc->pc_cpuid); 394 continue; 395 } 396 397 stp = malloc(KSTACK_PAGES * PAGE_SIZE, M_SMP, M_WAITOK); 398 ia64_ap_state.as_kstack = stp; 399 ia64_ap_state.as_kstack_top = stp + KSTACK_PAGES * PAGE_SIZE; 400 401 ia64_ap_state.as_trace = 0; 402 ia64_ap_state.as_delay = 2000; 403 ia64_ap_state.as_awake = 0; 404 405 if (bootverbose) 406 printf("SMP: waking up cpu%d\n", pc->pc_cpuid); 407 408 /* Here she goes... */ 409 ipi_send(pc, ia64_ipi_wakeup); 410 do { 411 DELAY(1000); 412 } while (--ia64_ap_state.as_delay > 0); 413 414 pc->pc_md.awake = ia64_ap_state.as_awake; 415 416 if (!ia64_ap_state.as_awake) { 417 printf("SMP: WARNING: cpu%d did not wake up (code " 418 "%#lx)\n", pc->pc_cpuid, 419 ia64_ap_state.as_trace - state); 420 } 421 } 422} 423 424static void 425cpu_mp_unleash(void *dummy) 426{ 427 struct pcpu *pc; 428 int cpus; 429 430 if (mp_ncpus <= 1) 431 return; 432 433 /* Allocate XIVs for IPIs */ 434 ia64_ipi_ast = ia64_xiv_alloc(PI_DULL, IA64_XIV_IPI, ia64_ih_ast); 435 ia64_ipi_hardclock = ia64_xiv_alloc(PI_REALTIME, IA64_XIV_IPI, 436 ia64_ih_hardclock); 437 ia64_ipi_highfp = ia64_xiv_alloc(PI_AV, IA64_XIV_IPI, ia64_ih_highfp); 438 ia64_ipi_preempt = ia64_xiv_alloc(PI_SOFT, IA64_XIV_IPI, 439 ia64_ih_preempt); 440 ia64_ipi_rndzvs = ia64_xiv_alloc(PI_AV, IA64_XIV_IPI, ia64_ih_rndzvs); 441 ia64_ipi_stop = ia64_xiv_alloc(PI_REALTIME, IA64_XIV_IPI, ia64_ih_stop); 442 443 /* Reserve the NMI vector for IPI_STOP_HARD if possible */ 444 ia64_ipi_nmi = (ia64_xiv_reserve(2, IA64_XIV_IPI, ia64_ih_stop) != 0) 445 ? ia64_ipi_stop : 0x400; /* DM=NMI, Vector=n/a */ 446 447 cpus = 0; 448 smp_cpus = 0; 449 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 450 cpus++; 451 if (pc->pc_md.awake) { 452 kproc_create(ia64_store_mca_state, pc, NULL, 0, 0, 453 "mca %u", pc->pc_cpuid); 454 smp_cpus++; 455 } 456 } 457 458 ia64_ap_state.as_awake = 1; 459 ia64_ap_state.as_spin = 0; 460 461 while (ia64_ap_state.as_awake != smp_cpus) 462 cpu_spinwait(); 463 464 if (smp_cpus != cpus || cpus != mp_ncpus) { 465 printf("SMP: %d CPUs found; %d CPUs usable; %d CPUs woken\n", 466 mp_ncpus, cpus, smp_cpus); 467 } 468 469 /* XXX Atomic set operation? */ 470 smp_started = 1; 471 472 /* 473 * Now that all CPUs are up and running, bind interrupts to each of 474 * them. 475 */ 476 ia64_bind_intr(); 477} 478SYSINIT(start_aps, SI_SUB_KICK_SCHEDULER, SI_ORDER_ANY, cpu_mp_unleash, NULL); 479 480/* 481 * send an IPI to a set of cpus. 482 */ 483void 484ipi_selected(cpuset_t cpus, int ipi) 485{ 486 struct pcpu *pc; 487 488 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 489 if (CPU_ISSET(pc->pc_cpuid, &cpus)) 490 ipi_send(pc, ipi); 491 } 492} 493 494/* 495 * send an IPI to a specific CPU. 496 */ 497void 498ipi_cpu(int cpu, u_int ipi) 499{ 500 501 ipi_send(cpuid_to_pcpu[cpu], ipi); 502} 503 504/* 505 * send an IPI to all CPUs EXCEPT myself. 506 */ 507void 508ipi_all_but_self(int ipi) 509{ 510 struct pcpu *pc; 511 512 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 513 if (pc != pcpup) 514 ipi_send(pc, ipi); 515 } 516} 517 518/* 519 * Send an IPI to the specified processor. 520 */ 521void 522ipi_send(struct pcpu *cpu, int xiv) 523{ 524 u_int sapic_id; 525 526 KASSERT(xiv != 0, ("ipi_send")); 527 528 sapic_id = IA64_LID_GET_SAPIC_ID(cpu->pc_md.lid); 529 530 ia64_mf(); 531 ia64_st8(&(ia64_pib->ib_ipi[sapic_id][0]), xiv); 532 ia64_mf_a(); 533 CTR3(KTR_SMP, "ipi_send(%p, %d): cpuid=%d", cpu, xiv, PCPU_GET(cpuid)); 534} 535