pmap.c revision 270439
1/*- 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * Copyright (c) 2005 Alan L. Cox <alc@cs.rice.edu> 9 * All rights reserved. 10 * 11 * This code is derived from software contributed to Berkeley by 12 * the Systems Programming Group of the University of Utah Computer 13 * Science Department and William Jolitz of UUNET Technologies Inc. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 3. All advertising materials mentioning features or use of this software 24 * must display the following acknowledgement: 25 * This product includes software developed by the University of 26 * California, Berkeley and its contributors. 27 * 4. Neither the name of the University nor the names of its contributors 28 * may be used to endorse or promote products derived from this software 29 * without specific prior written permission. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 41 * SUCH DAMAGE. 42 * 43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 44 */ 45/*- 46 * Copyright (c) 2003 Networks Associates Technology, Inc. 47 * All rights reserved. 48 * 49 * This software was developed for the FreeBSD Project by Jake Burkholder, 50 * Safeport Network Services, and Network Associates Laboratories, the 51 * Security Research Division of Network Associates, Inc. under 52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA 53 * CHATS research program. 54 * 55 * Redistribution and use in source and binary forms, with or without 56 * modification, are permitted provided that the following conditions 57 * are met: 58 * 1. Redistributions of source code must retain the above copyright 59 * notice, this list of conditions and the following disclaimer. 60 * 2. Redistributions in binary form must reproduce the above copyright 61 * notice, this list of conditions and the following disclaimer in the 62 * documentation and/or other materials provided with the distribution. 63 * 64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 74 * SUCH DAMAGE. 75 */ 76 77#include <sys/cdefs.h> 78__FBSDID("$FreeBSD: stable/10/sys/i386/xen/pmap.c 270439 2014-08-24 07:53:15Z kib $"); 79 80/* 81 * Manages physical address maps. 82 * 83 * Since the information managed by this module is 84 * also stored by the logical address mapping module, 85 * this module may throw away valid virtual-to-physical 86 * mappings at almost any time. However, invalidations 87 * of virtual-to-physical mappings must be done as 88 * requested. 89 * 90 * In order to cope with hardware architectures which 91 * make virtual-to-physical map invalidates expensive, 92 * this module may delay invalidate or reduced protection 93 * operations until such time as they are actually 94 * necessary. This module is given full information as 95 * to which processors are currently using which maps, 96 * and to when physical maps must be made correct. 97 */ 98 99#include "opt_cpu.h" 100#include "opt_pmap.h" 101#include "opt_smp.h" 102#include "opt_xbox.h" 103 104#include <sys/param.h> 105#include <sys/systm.h> 106#include <sys/kernel.h> 107#include <sys/ktr.h> 108#include <sys/lock.h> 109#include <sys/malloc.h> 110#include <sys/mman.h> 111#include <sys/msgbuf.h> 112#include <sys/mutex.h> 113#include <sys/proc.h> 114#include <sys/rwlock.h> 115#include <sys/sf_buf.h> 116#include <sys/sx.h> 117#include <sys/vmmeter.h> 118#include <sys/sched.h> 119#include <sys/sysctl.h> 120#ifdef SMP 121#include <sys/smp.h> 122#else 123#include <sys/cpuset.h> 124#endif 125 126#include <vm/vm.h> 127#include <vm/vm_param.h> 128#include <vm/vm_kern.h> 129#include <vm/vm_page.h> 130#include <vm/vm_map.h> 131#include <vm/vm_object.h> 132#include <vm/vm_extern.h> 133#include <vm/vm_pageout.h> 134#include <vm/vm_pager.h> 135#include <vm/uma.h> 136 137#include <machine/cpu.h> 138#include <machine/cputypes.h> 139#include <machine/md_var.h> 140#include <machine/pcb.h> 141#include <machine/specialreg.h> 142#ifdef SMP 143#include <machine/smp.h> 144#endif 145 146#ifdef XBOX 147#include <machine/xbox.h> 148#endif 149 150#include <xen/interface/xen.h> 151#include <xen/hypervisor.h> 152#include <machine/xen/hypercall.h> 153#include <machine/xen/xenvar.h> 154#include <machine/xen/xenfunc.h> 155 156#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU) 157#define CPU_ENABLE_SSE 158#endif 159 160#ifndef PMAP_SHPGPERPROC 161#define PMAP_SHPGPERPROC 200 162#endif 163 164#define DIAGNOSTIC 165 166#if !defined(DIAGNOSTIC) 167#ifdef __GNUC_GNU_INLINE__ 168#define PMAP_INLINE __attribute__((__gnu_inline__)) inline 169#else 170#define PMAP_INLINE extern inline 171#endif 172#else 173#define PMAP_INLINE 174#endif 175 176#ifdef PV_STATS 177#define PV_STAT(x) do { x ; } while (0) 178#else 179#define PV_STAT(x) do { } while (0) 180#endif 181 182/* 183 * Get PDEs and PTEs for user/kernel address space 184 */ 185#define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT])) 186#define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT]) 187 188#define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0) 189#define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0) 190#define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0) 191#define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0) 192#define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0) 193 194#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v))) 195 196#define HAMFISTED_LOCKING 197#ifdef HAMFISTED_LOCKING 198static struct mtx createdelete_lock; 199#endif 200 201struct pmap kernel_pmap_store; 202LIST_HEAD(pmaplist, pmap); 203static struct pmaplist allpmaps; 204static struct mtx allpmaps_lock; 205 206vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 207vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 208int pgeflag = 0; /* PG_G or-in */ 209int pseflag = 0; /* PG_PS or-in */ 210 211int nkpt; 212vm_offset_t kernel_vm_end; 213extern u_int32_t KERNend; 214 215#ifdef PAE 216pt_entry_t pg_nx; 217#endif 218 219static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters"); 220 221static int pat_works; /* Is page attribute table sane? */ 222 223/* 224 * This lock is defined as static in other pmap implementations. It cannot, 225 * however, be defined as static here, because it is (ab)used to serialize 226 * queued page table changes in other sources files. 227 */ 228struct rwlock pvh_global_lock; 229 230/* 231 * Data for the pv entry allocation mechanism 232 */ 233static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks); 234static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 235static int shpgperproc = PMAP_SHPGPERPROC; 236 237struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */ 238int pv_maxchunks; /* How many chunks we have KVA for */ 239vm_offset_t pv_vafree; /* freelist stored in the PTE */ 240 241/* 242 * All those kernel PT submaps that BSD is so fond of 243 */ 244struct sysmaps { 245 struct mtx lock; 246 pt_entry_t *CMAP1; 247 pt_entry_t *CMAP2; 248 caddr_t CADDR1; 249 caddr_t CADDR2; 250}; 251static struct sysmaps sysmaps_pcpu[MAXCPU]; 252pt_entry_t *CMAP3; 253caddr_t ptvmmap = 0; 254caddr_t CADDR3; 255struct msgbuf *msgbufp = 0; 256 257/* 258 * Crashdump maps. 259 */ 260static caddr_t crashdumpmap; 261 262static pt_entry_t *PMAP1 = 0, *PMAP2; 263static pt_entry_t *PADDR1 = 0, *PADDR2; 264#ifdef SMP 265static int PMAP1cpu; 266static int PMAP1changedcpu; 267SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD, 268 &PMAP1changedcpu, 0, 269 "Number of times pmap_pte_quick changed CPU with same PMAP1"); 270#endif 271static int PMAP1changed; 272SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD, 273 &PMAP1changed, 0, 274 "Number of times pmap_pte_quick changed PMAP1"); 275static int PMAP1unchanged; 276SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD, 277 &PMAP1unchanged, 0, 278 "Number of times pmap_pte_quick didn't change PMAP1"); 279static struct mtx PMAP2mutex; 280 281static void free_pv_chunk(struct pv_chunk *pc); 282static void free_pv_entry(pmap_t pmap, pv_entry_t pv); 283static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try); 284static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va); 285static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, 286 vm_offset_t va); 287 288static vm_page_t pmap_enter_quick_locked(multicall_entry_t **mcl, int *count, pmap_t pmap, vm_offset_t va, 289 vm_page_t m, vm_prot_t prot, vm_page_t mpte); 290static void pmap_flush_page(vm_page_t m); 291static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode); 292static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva, 293 vm_page_t *free); 294static void pmap_remove_page(struct pmap *pmap, vm_offset_t va, 295 vm_page_t *free); 296static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, 297 vm_offset_t va); 298static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, 299 vm_page_t m); 300 301static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags); 302 303static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags); 304static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, vm_page_t *free); 305static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va); 306static void pmap_pte_release(pt_entry_t *pte); 307static int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t *); 308static boolean_t pmap_is_prefaultable_locked(pmap_t pmap, vm_offset_t addr); 309 310static __inline void pagezero(void *page); 311 312CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t)); 313CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t)); 314 315/* 316 * If you get an error here, then you set KVA_PAGES wrong! See the 317 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be 318 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE. 319 */ 320CTASSERT(KERNBASE % (1 << 24) == 0); 321 322void 323pd_set(struct pmap *pmap, int ptepindex, vm_paddr_t val, int type) 324{ 325 vm_paddr_t pdir_ma = vtomach(&pmap->pm_pdir[ptepindex]); 326 327 switch (type) { 328 case SH_PD_SET_VA: 329#if 0 330 xen_queue_pt_update(shadow_pdir_ma, 331 xpmap_ptom(val & ~(PG_RW))); 332#endif 333 xen_queue_pt_update(pdir_ma, 334 xpmap_ptom(val)); 335 break; 336 case SH_PD_SET_VA_MA: 337#if 0 338 xen_queue_pt_update(shadow_pdir_ma, 339 val & ~(PG_RW)); 340#endif 341 xen_queue_pt_update(pdir_ma, val); 342 break; 343 case SH_PD_SET_VA_CLEAR: 344#if 0 345 xen_queue_pt_update(shadow_pdir_ma, 0); 346#endif 347 xen_queue_pt_update(pdir_ma, 0); 348 break; 349 } 350} 351 352/* 353 * Bootstrap the system enough to run with virtual memory. 354 * 355 * On the i386 this is called after mapping has already been enabled 356 * and just syncs the pmap module with what has already been done. 357 * [We can't call it easily with mapping off since the kernel is not 358 * mapped with PA == VA, hence we would have to relocate every address 359 * from the linked base (virtual) address "KERNBASE" to the actual 360 * (physical) address starting relative to 0] 361 */ 362void 363pmap_bootstrap(vm_paddr_t firstaddr) 364{ 365 vm_offset_t va; 366 pt_entry_t *pte, *unused; 367 struct sysmaps *sysmaps; 368 int i; 369 370 /* 371 * Initialize the first available kernel virtual address. However, 372 * using "firstaddr" may waste a few pages of the kernel virtual 373 * address space, because locore may not have mapped every physical 374 * page that it allocated. Preferably, locore would provide a first 375 * unused virtual address in addition to "firstaddr". 376 */ 377 virtual_avail = (vm_offset_t) KERNBASE + firstaddr; 378 379 virtual_end = VM_MAX_KERNEL_ADDRESS; 380 381 /* 382 * Initialize the kernel pmap (which is statically allocated). 383 */ 384 PMAP_LOCK_INIT(kernel_pmap); 385 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD); 386#ifdef PAE 387 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT); 388#endif 389 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */ 390 TAILQ_INIT(&kernel_pmap->pm_pvchunk); 391 392 /* 393 * Initialize the global pv list lock. 394 */ 395 rw_init_flags(&pvh_global_lock, "pmap pv global", RW_RECURSE); 396 397 LIST_INIT(&allpmaps); 398 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN); 399 mtx_lock_spin(&allpmaps_lock); 400 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list); 401 mtx_unlock_spin(&allpmaps_lock); 402 if (nkpt == 0) 403 nkpt = NKPT; 404 405 /* 406 * Reserve some special page table entries/VA space for temporary 407 * mapping of pages. 408 */ 409#define SYSMAP(c, p, v, n) \ 410 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 411 412 va = virtual_avail; 413 pte = vtopte(va); 414 415 /* 416 * CMAP1/CMAP2 are used for zeroing and copying pages. 417 * CMAP3 is used for the idle process page zeroing. 418 */ 419 for (i = 0; i < MAXCPU; i++) { 420 sysmaps = &sysmaps_pcpu[i]; 421 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF); 422 SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1) 423 SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1) 424 PT_SET_MA(sysmaps->CADDR1, 0); 425 PT_SET_MA(sysmaps->CADDR2, 0); 426 } 427 SYSMAP(caddr_t, CMAP3, CADDR3, 1) 428 PT_SET_MA(CADDR3, 0); 429 430 /* 431 * Crashdump maps. 432 */ 433 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS) 434 435 /* 436 * ptvmmap is used for reading arbitrary physical pages via /dev/mem. 437 */ 438 SYSMAP(caddr_t, unused, ptvmmap, 1) 439 440 /* 441 * msgbufp is used to map the system message buffer. 442 */ 443 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize))) 444 445 /* 446 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(), 447 * respectively. 448 */ 449 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1) 450 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1) 451 452 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF); 453 454 virtual_avail = va; 455 456 /* 457 * Leave in place an identity mapping (virt == phys) for the low 1 MB 458 * physical memory region that is used by the ACPI wakeup code. This 459 * mapping must not have PG_G set. 460 */ 461#ifndef XEN 462 /* 463 * leave here deliberately to show that this is not supported 464 */ 465#ifdef XBOX 466 /* FIXME: This is gross, but needed for the XBOX. Since we are in such 467 * an early stadium, we cannot yet neatly map video memory ... :-( 468 * Better fixes are very welcome! */ 469 if (!arch_i386_is_xbox) 470#endif 471 for (i = 1; i < NKPT; i++) 472 PTD[i] = 0; 473 474 /* Initialize the PAT MSR if present. */ 475 pmap_init_pat(); 476 477 /* Turn on PG_G on kernel page(s) */ 478 pmap_set_pg(); 479#endif 480 481#ifdef HAMFISTED_LOCKING 482 mtx_init(&createdelete_lock, "pmap create/delete", NULL, MTX_DEF); 483#endif 484} 485 486/* 487 * Setup the PAT MSR. 488 */ 489void 490pmap_init_pat(void) 491{ 492 uint64_t pat_msr; 493 494 /* Bail if this CPU doesn't implement PAT. */ 495 if (!(cpu_feature & CPUID_PAT)) 496 return; 497 498 if (cpu_vendor_id != CPU_VENDOR_INTEL || 499 (CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe)) { 500 /* 501 * Leave the indices 0-3 at the default of WB, WT, UC, and UC-. 502 * Program 4 and 5 as WP and WC. 503 * Leave 6 and 7 as UC and UC-. 504 */ 505 pat_msr = rdmsr(MSR_PAT); 506 pat_msr &= ~(PAT_MASK(4) | PAT_MASK(5)); 507 pat_msr |= PAT_VALUE(4, PAT_WRITE_PROTECTED) | 508 PAT_VALUE(5, PAT_WRITE_COMBINING); 509 pat_works = 1; 510 } else { 511 /* 512 * Due to some Intel errata, we can only safely use the lower 4 513 * PAT entries. Thus, just replace PAT Index 2 with WC instead 514 * of UC-. 515 * 516 * Intel Pentium III Processor Specification Update 517 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B 518 * or Mode C Paging) 519 * 520 * Intel Pentium IV Processor Specification Update 521 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly) 522 */ 523 pat_msr = rdmsr(MSR_PAT); 524 pat_msr &= ~PAT_MASK(2); 525 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING); 526 pat_works = 0; 527 } 528 wrmsr(MSR_PAT, pat_msr); 529} 530 531/* 532 * Initialize a vm_page's machine-dependent fields. 533 */ 534void 535pmap_page_init(vm_page_t m) 536{ 537 538 TAILQ_INIT(&m->md.pv_list); 539 m->md.pat_mode = PAT_WRITE_BACK; 540} 541 542/* 543 * ABuse the pte nodes for unmapped kva to thread a kva freelist through. 544 * Requirements: 545 * - Must deal with pages in order to ensure that none of the PG_* bits 546 * are ever set, PG_V in particular. 547 * - Assumes we can write to ptes without pte_store() atomic ops, even 548 * on PAE systems. This should be ok. 549 * - Assumes nothing will ever test these addresses for 0 to indicate 550 * no mapping instead of correctly checking PG_V. 551 * - Assumes a vm_offset_t will fit in a pte (true for i386). 552 * Because PG_V is never set, there can be no mappings to invalidate. 553 */ 554static int ptelist_count = 0; 555static vm_offset_t 556pmap_ptelist_alloc(vm_offset_t *head) 557{ 558 vm_offset_t va; 559 vm_offset_t *phead = (vm_offset_t *)*head; 560 561 if (ptelist_count == 0) { 562 printf("out of memory!!!!!!\n"); 563 return (0); /* Out of memory */ 564 } 565 ptelist_count--; 566 va = phead[ptelist_count]; 567 return (va); 568} 569 570static void 571pmap_ptelist_free(vm_offset_t *head, vm_offset_t va) 572{ 573 vm_offset_t *phead = (vm_offset_t *)*head; 574 575 phead[ptelist_count++] = va; 576} 577 578static void 579pmap_ptelist_init(vm_offset_t *head, void *base, int npages) 580{ 581 int i, nstackpages; 582 vm_offset_t va; 583 vm_page_t m; 584 585 nstackpages = (npages + PAGE_SIZE/sizeof(vm_offset_t) - 1)/ (PAGE_SIZE/sizeof(vm_offset_t)); 586 for (i = 0; i < nstackpages; i++) { 587 va = (vm_offset_t)base + i * PAGE_SIZE; 588 m = vm_page_alloc(NULL, i, 589 VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 590 VM_ALLOC_ZERO); 591 pmap_qenter(va, &m, 1); 592 } 593 594 *head = (vm_offset_t)base; 595 for (i = npages - 1; i >= nstackpages; i--) { 596 va = (vm_offset_t)base + i * PAGE_SIZE; 597 pmap_ptelist_free(head, va); 598 } 599} 600 601 602/* 603 * Initialize the pmap module. 604 * Called by vm_init, to initialize any structures that the pmap 605 * system needs to map virtual memory. 606 */ 607void 608pmap_init(void) 609{ 610 611 /* 612 * Initialize the address space (zone) for the pv entries. Set a 613 * high water mark so that the system can recover from excessive 614 * numbers of pv entries. 615 */ 616 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 617 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 618 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 619 pv_entry_max = roundup(pv_entry_max, _NPCPV); 620 pv_entry_high_water = 9 * (pv_entry_max / 10); 621 622 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc); 623 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks); 624 if (pv_chunkbase == NULL) 625 panic("pmap_init: not enough kvm for pv chunks"); 626 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks); 627} 628 629 630SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0, 631 "Max number of PV entries"); 632SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0, 633 "Page share factor per proc"); 634 635static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0, 636 "2/4MB page mapping counters"); 637 638static u_long pmap_pde_mappings; 639SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD, 640 &pmap_pde_mappings, 0, "2/4MB page mappings"); 641 642/*************************************************** 643 * Low level helper routines..... 644 ***************************************************/ 645 646/* 647 * Determine the appropriate bits to set in a PTE or PDE for a specified 648 * caching mode. 649 */ 650int 651pmap_cache_bits(int mode, boolean_t is_pde) 652{ 653 int pat_flag, pat_index, cache_bits; 654 655 /* The PAT bit is different for PTE's and PDE's. */ 656 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT; 657 658 /* If we don't support PAT, map extended modes to older ones. */ 659 if (!(cpu_feature & CPUID_PAT)) { 660 switch (mode) { 661 case PAT_UNCACHEABLE: 662 case PAT_WRITE_THROUGH: 663 case PAT_WRITE_BACK: 664 break; 665 case PAT_UNCACHED: 666 case PAT_WRITE_COMBINING: 667 case PAT_WRITE_PROTECTED: 668 mode = PAT_UNCACHEABLE; 669 break; 670 } 671 } 672 673 /* Map the caching mode to a PAT index. */ 674 if (pat_works) { 675 switch (mode) { 676 case PAT_UNCACHEABLE: 677 pat_index = 3; 678 break; 679 case PAT_WRITE_THROUGH: 680 pat_index = 1; 681 break; 682 case PAT_WRITE_BACK: 683 pat_index = 0; 684 break; 685 case PAT_UNCACHED: 686 pat_index = 2; 687 break; 688 case PAT_WRITE_COMBINING: 689 pat_index = 5; 690 break; 691 case PAT_WRITE_PROTECTED: 692 pat_index = 4; 693 break; 694 default: 695 panic("Unknown caching mode %d\n", mode); 696 } 697 } else { 698 switch (mode) { 699 case PAT_UNCACHED: 700 case PAT_UNCACHEABLE: 701 case PAT_WRITE_PROTECTED: 702 pat_index = 3; 703 break; 704 case PAT_WRITE_THROUGH: 705 pat_index = 1; 706 break; 707 case PAT_WRITE_BACK: 708 pat_index = 0; 709 break; 710 case PAT_WRITE_COMBINING: 711 pat_index = 2; 712 break; 713 default: 714 panic("Unknown caching mode %d\n", mode); 715 } 716 } 717 718 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */ 719 cache_bits = 0; 720 if (pat_index & 0x4) 721 cache_bits |= pat_flag; 722 if (pat_index & 0x2) 723 cache_bits |= PG_NC_PCD; 724 if (pat_index & 0x1) 725 cache_bits |= PG_NC_PWT; 726 return (cache_bits); 727} 728#ifdef SMP 729/* 730 * For SMP, these functions have to use the IPI mechanism for coherence. 731 * 732 * N.B.: Before calling any of the following TLB invalidation functions, 733 * the calling processor must ensure that all stores updating a non- 734 * kernel page table are globally performed. Otherwise, another 735 * processor could cache an old, pre-update entry without being 736 * invalidated. This can happen one of two ways: (1) The pmap becomes 737 * active on another processor after its pm_active field is checked by 738 * one of the following functions but before a store updating the page 739 * table is globally performed. (2) The pmap becomes active on another 740 * processor before its pm_active field is checked but due to 741 * speculative loads one of the following functions stills reads the 742 * pmap as inactive on the other processor. 743 * 744 * The kernel page table is exempt because its pm_active field is 745 * immutable. The kernel page table is always active on every 746 * processor. 747 */ 748void 749pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 750{ 751 cpuset_t other_cpus; 752 u_int cpuid; 753 754 CTR2(KTR_PMAP, "pmap_invalidate_page: pmap=%p va=0x%x", 755 pmap, va); 756 757 sched_pin(); 758 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 759 invlpg(va); 760 smp_invlpg(va); 761 } else { 762 cpuid = PCPU_GET(cpuid); 763 other_cpus = all_cpus; 764 CPU_CLR(cpuid, &other_cpus); 765 if (CPU_ISSET(cpuid, &pmap->pm_active)) 766 invlpg(va); 767 CPU_AND(&other_cpus, &pmap->pm_active); 768 if (!CPU_EMPTY(&other_cpus)) 769 smp_masked_invlpg(other_cpus, va); 770 } 771 sched_unpin(); 772 PT_UPDATES_FLUSH(); 773} 774 775void 776pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 777{ 778 cpuset_t other_cpus; 779 vm_offset_t addr; 780 u_int cpuid; 781 782 CTR3(KTR_PMAP, "pmap_invalidate_page: pmap=%p eva=0x%x sva=0x%x", 783 pmap, sva, eva); 784 785 sched_pin(); 786 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 787 for (addr = sva; addr < eva; addr += PAGE_SIZE) 788 invlpg(addr); 789 smp_invlpg_range(sva, eva); 790 } else { 791 cpuid = PCPU_GET(cpuid); 792 other_cpus = all_cpus; 793 CPU_CLR(cpuid, &other_cpus); 794 if (CPU_ISSET(cpuid, &pmap->pm_active)) 795 for (addr = sva; addr < eva; addr += PAGE_SIZE) 796 invlpg(addr); 797 CPU_AND(&other_cpus, &pmap->pm_active); 798 if (!CPU_EMPTY(&other_cpus)) 799 smp_masked_invlpg_range(other_cpus, sva, eva); 800 } 801 sched_unpin(); 802 PT_UPDATES_FLUSH(); 803} 804 805void 806pmap_invalidate_all(pmap_t pmap) 807{ 808 cpuset_t other_cpus; 809 u_int cpuid; 810 811 CTR1(KTR_PMAP, "pmap_invalidate_page: pmap=%p", pmap); 812 813 sched_pin(); 814 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 815 invltlb(); 816 smp_invltlb(); 817 } else { 818 cpuid = PCPU_GET(cpuid); 819 other_cpus = all_cpus; 820 CPU_CLR(cpuid, &other_cpus); 821 if (CPU_ISSET(cpuid, &pmap->pm_active)) 822 invltlb(); 823 CPU_AND(&other_cpus, &pmap->pm_active); 824 if (!CPU_EMPTY(&other_cpus)) 825 smp_masked_invltlb(other_cpus); 826 } 827 sched_unpin(); 828} 829 830void 831pmap_invalidate_cache(void) 832{ 833 834 sched_pin(); 835 wbinvd(); 836 smp_cache_flush(); 837 sched_unpin(); 838} 839#else /* !SMP */ 840/* 841 * Normal, non-SMP, 486+ invalidation functions. 842 * We inline these within pmap.c for speed. 843 */ 844PMAP_INLINE void 845pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 846{ 847 CTR2(KTR_PMAP, "pmap_invalidate_page: pmap=%p va=0x%x", 848 pmap, va); 849 850 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 851 invlpg(va); 852 PT_UPDATES_FLUSH(); 853} 854 855PMAP_INLINE void 856pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 857{ 858 vm_offset_t addr; 859 860 if (eva - sva > PAGE_SIZE) 861 CTR3(KTR_PMAP, "pmap_invalidate_range: pmap=%p sva=0x%x eva=0x%x", 862 pmap, sva, eva); 863 864 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 865 for (addr = sva; addr < eva; addr += PAGE_SIZE) 866 invlpg(addr); 867 PT_UPDATES_FLUSH(); 868} 869 870PMAP_INLINE void 871pmap_invalidate_all(pmap_t pmap) 872{ 873 874 CTR1(KTR_PMAP, "pmap_invalidate_all: pmap=%p", pmap); 875 876 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 877 invltlb(); 878} 879 880PMAP_INLINE void 881pmap_invalidate_cache(void) 882{ 883 884 wbinvd(); 885} 886#endif /* !SMP */ 887 888#define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024) 889 890void 891pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva) 892{ 893 894 KASSERT((sva & PAGE_MASK) == 0, 895 ("pmap_invalidate_cache_range: sva not page-aligned")); 896 KASSERT((eva & PAGE_MASK) == 0, 897 ("pmap_invalidate_cache_range: eva not page-aligned")); 898 899 if (cpu_feature & CPUID_SS) 900 ; /* If "Self Snoop" is supported, do nothing. */ 901 else if ((cpu_feature & CPUID_CLFSH) != 0 && 902 eva - sva < PMAP_CLFLUSH_THRESHOLD) { 903 904 /* 905 * Otherwise, do per-cache line flush. Use the mfence 906 * instruction to insure that previous stores are 907 * included in the write-back. The processor 908 * propagates flush to other processors in the cache 909 * coherence domain. 910 */ 911 mfence(); 912 for (; sva < eva; sva += cpu_clflush_line_size) 913 clflush(sva); 914 mfence(); 915 } else { 916 917 /* 918 * No targeted cache flush methods are supported by CPU, 919 * or the supplied range is bigger than 2MB. 920 * Globally invalidate cache. 921 */ 922 pmap_invalidate_cache(); 923 } 924} 925 926void 927pmap_invalidate_cache_pages(vm_page_t *pages, int count) 928{ 929 int i; 930 931 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE || 932 (cpu_feature & CPUID_CLFSH) == 0) { 933 pmap_invalidate_cache(); 934 } else { 935 for (i = 0; i < count; i++) 936 pmap_flush_page(pages[i]); 937 } 938} 939 940/* 941 * Are we current address space or kernel? N.B. We return FALSE when 942 * a pmap's page table is in use because a kernel thread is borrowing 943 * it. The borrowed page table can change spontaneously, making any 944 * dependence on its continued use subject to a race condition. 945 */ 946static __inline int 947pmap_is_current(pmap_t pmap) 948{ 949 950 return (pmap == kernel_pmap || 951 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace) && 952 (pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & PG_FRAME))); 953} 954 955/* 956 * If the given pmap is not the current or kernel pmap, the returned pte must 957 * be released by passing it to pmap_pte_release(). 958 */ 959pt_entry_t * 960pmap_pte(pmap_t pmap, vm_offset_t va) 961{ 962 pd_entry_t newpf; 963 pd_entry_t *pde; 964 965 pde = pmap_pde(pmap, va); 966 if (*pde & PG_PS) 967 return (pde); 968 if (*pde != 0) { 969 /* are we current address space or kernel? */ 970 if (pmap_is_current(pmap)) 971 return (vtopte(va)); 972 mtx_lock(&PMAP2mutex); 973 newpf = *pde & PG_FRAME; 974 if ((*PMAP2 & PG_FRAME) != newpf) { 975 PT_SET_MA(PADDR2, newpf | PG_V | PG_A | PG_M); 976 CTR3(KTR_PMAP, "pmap_pte: pmap=%p va=0x%x newpte=0x%08x", 977 pmap, va, (*PMAP2 & 0xffffffff)); 978 } 979 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1))); 980 } 981 return (NULL); 982} 983 984/* 985 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte 986 * being NULL. 987 */ 988static __inline void 989pmap_pte_release(pt_entry_t *pte) 990{ 991 992 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2) { 993 CTR1(KTR_PMAP, "pmap_pte_release: pte=0x%jx", 994 *PMAP2); 995 rw_wlock(&pvh_global_lock); 996 PT_SET_VA(PMAP2, 0, TRUE); 997 rw_wunlock(&pvh_global_lock); 998 mtx_unlock(&PMAP2mutex); 999 } 1000} 1001 1002static __inline void 1003invlcaddr(void *caddr) 1004{ 1005 1006 invlpg((u_int)caddr); 1007 PT_UPDATES_FLUSH(); 1008} 1009 1010/* 1011 * Super fast pmap_pte routine best used when scanning 1012 * the pv lists. This eliminates many coarse-grained 1013 * invltlb calls. Note that many of the pv list 1014 * scans are across different pmaps. It is very wasteful 1015 * to do an entire invltlb for checking a single mapping. 1016 * 1017 * If the given pmap is not the current pmap, pvh_global_lock 1018 * must be held and curthread pinned to a CPU. 1019 */ 1020static pt_entry_t * 1021pmap_pte_quick(pmap_t pmap, vm_offset_t va) 1022{ 1023 pd_entry_t newpf; 1024 pd_entry_t *pde; 1025 1026 pde = pmap_pde(pmap, va); 1027 if (*pde & PG_PS) 1028 return (pde); 1029 if (*pde != 0) { 1030 /* are we current address space or kernel? */ 1031 if (pmap_is_current(pmap)) 1032 return (vtopte(va)); 1033 rw_assert(&pvh_global_lock, RA_WLOCKED); 1034 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 1035 newpf = *pde & PG_FRAME; 1036 if ((*PMAP1 & PG_FRAME) != newpf) { 1037 PT_SET_MA(PADDR1, newpf | PG_V | PG_A | PG_M); 1038 CTR3(KTR_PMAP, "pmap_pte_quick: pmap=%p va=0x%x newpte=0x%08x", 1039 pmap, va, (u_long)*PMAP1); 1040 1041#ifdef SMP 1042 PMAP1cpu = PCPU_GET(cpuid); 1043#endif 1044 PMAP1changed++; 1045 } else 1046#ifdef SMP 1047 if (PMAP1cpu != PCPU_GET(cpuid)) { 1048 PMAP1cpu = PCPU_GET(cpuid); 1049 invlcaddr(PADDR1); 1050 PMAP1changedcpu++; 1051 } else 1052#endif 1053 PMAP1unchanged++; 1054 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1))); 1055 } 1056 return (0); 1057} 1058 1059/* 1060 * Routine: pmap_extract 1061 * Function: 1062 * Extract the physical page address associated 1063 * with the given map/virtual_address pair. 1064 */ 1065vm_paddr_t 1066pmap_extract(pmap_t pmap, vm_offset_t va) 1067{ 1068 vm_paddr_t rtval; 1069 pt_entry_t *pte; 1070 pd_entry_t pde; 1071 pt_entry_t pteval; 1072 1073 rtval = 0; 1074 PMAP_LOCK(pmap); 1075 pde = pmap->pm_pdir[va >> PDRSHIFT]; 1076 if (pde != 0) { 1077 if ((pde & PG_PS) != 0) { 1078 rtval = xpmap_mtop(pde & PG_PS_FRAME) | (va & PDRMASK); 1079 PMAP_UNLOCK(pmap); 1080 return rtval; 1081 } 1082 pte = pmap_pte(pmap, va); 1083 pteval = *pte ? xpmap_mtop(*pte) : 0; 1084 rtval = (pteval & PG_FRAME) | (va & PAGE_MASK); 1085 pmap_pte_release(pte); 1086 } 1087 PMAP_UNLOCK(pmap); 1088 return (rtval); 1089} 1090 1091/* 1092 * Routine: pmap_extract_ma 1093 * Function: 1094 * Like pmap_extract, but returns machine address 1095 */ 1096vm_paddr_t 1097pmap_extract_ma(pmap_t pmap, vm_offset_t va) 1098{ 1099 vm_paddr_t rtval; 1100 pt_entry_t *pte; 1101 pd_entry_t pde; 1102 1103 rtval = 0; 1104 PMAP_LOCK(pmap); 1105 pde = pmap->pm_pdir[va >> PDRSHIFT]; 1106 if (pde != 0) { 1107 if ((pde & PG_PS) != 0) { 1108 rtval = (pde & ~PDRMASK) | (va & PDRMASK); 1109 PMAP_UNLOCK(pmap); 1110 return rtval; 1111 } 1112 pte = pmap_pte(pmap, va); 1113 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK); 1114 pmap_pte_release(pte); 1115 } 1116 PMAP_UNLOCK(pmap); 1117 return (rtval); 1118} 1119 1120/* 1121 * Routine: pmap_extract_and_hold 1122 * Function: 1123 * Atomically extract and hold the physical page 1124 * with the given pmap and virtual address pair 1125 * if that mapping permits the given protection. 1126 */ 1127vm_page_t 1128pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1129{ 1130 pd_entry_t pde; 1131 pt_entry_t pte, *ptep; 1132 vm_page_t m; 1133 vm_paddr_t pa; 1134 1135 pa = 0; 1136 m = NULL; 1137 PMAP_LOCK(pmap); 1138retry: 1139 pde = PT_GET(pmap_pde(pmap, va)); 1140 if (pde != 0) { 1141 if (pde & PG_PS) { 1142 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) { 1143 if (vm_page_pa_tryrelock(pmap, (pde & 1144 PG_PS_FRAME) | (va & PDRMASK), &pa)) 1145 goto retry; 1146 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) | 1147 (va & PDRMASK)); 1148 vm_page_hold(m); 1149 } 1150 } else { 1151 ptep = pmap_pte(pmap, va); 1152 pte = PT_GET(ptep); 1153 pmap_pte_release(ptep); 1154 if (pte != 0 && 1155 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) { 1156 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME, 1157 &pa)) 1158 goto retry; 1159 m = PHYS_TO_VM_PAGE(pte & PG_FRAME); 1160 vm_page_hold(m); 1161 } 1162 } 1163 } 1164 PA_UNLOCK_COND(pa); 1165 PMAP_UNLOCK(pmap); 1166 return (m); 1167} 1168 1169/*************************************************** 1170 * Low level mapping routines..... 1171 ***************************************************/ 1172 1173/* 1174 * Add a wired page to the kva. 1175 * Note: not SMP coherent. 1176 * 1177 * This function may be used before pmap_bootstrap() is called. 1178 */ 1179void 1180pmap_kenter(vm_offset_t va, vm_paddr_t pa) 1181{ 1182 1183 PT_SET_MA(va, xpmap_ptom(pa)| PG_RW | PG_V | pgeflag); 1184} 1185 1186void 1187pmap_kenter_ma(vm_offset_t va, vm_paddr_t ma) 1188{ 1189 pt_entry_t *pte; 1190 1191 pte = vtopte(va); 1192 pte_store_ma(pte, ma | PG_RW | PG_V | pgeflag); 1193} 1194 1195static __inline void 1196pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode) 1197{ 1198 1199 PT_SET_MA(va, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0)); 1200} 1201 1202/* 1203 * Remove a page from the kernel pagetables. 1204 * Note: not SMP coherent. 1205 * 1206 * This function may be used before pmap_bootstrap() is called. 1207 */ 1208PMAP_INLINE void 1209pmap_kremove(vm_offset_t va) 1210{ 1211 pt_entry_t *pte; 1212 1213 pte = vtopte(va); 1214 PT_CLEAR_VA(pte, FALSE); 1215} 1216 1217/* 1218 * Used to map a range of physical addresses into kernel 1219 * virtual address space. 1220 * 1221 * The value passed in '*virt' is a suggested virtual address for 1222 * the mapping. Architectures which can support a direct-mapped 1223 * physical to virtual region can return the appropriate address 1224 * within that region, leaving '*virt' unchanged. Other 1225 * architectures should map the pages starting at '*virt' and 1226 * update '*virt' with the first usable address after the mapped 1227 * region. 1228 */ 1229vm_offset_t 1230pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) 1231{ 1232 vm_offset_t va, sva; 1233 1234 va = sva = *virt; 1235 CTR4(KTR_PMAP, "pmap_map: va=0x%x start=0x%jx end=0x%jx prot=0x%x", 1236 va, start, end, prot); 1237 while (start < end) { 1238 pmap_kenter(va, start); 1239 va += PAGE_SIZE; 1240 start += PAGE_SIZE; 1241 } 1242 pmap_invalidate_range(kernel_pmap, sva, va); 1243 *virt = va; 1244 return (sva); 1245} 1246 1247 1248/* 1249 * Add a list of wired pages to the kva 1250 * this routine is only used for temporary 1251 * kernel mappings that do not need to have 1252 * page modification or references recorded. 1253 * Note that old mappings are simply written 1254 * over. The page *must* be wired. 1255 * Note: SMP coherent. Uses a ranged shootdown IPI. 1256 */ 1257void 1258pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count) 1259{ 1260 pt_entry_t *endpte, *pte; 1261 vm_paddr_t pa; 1262 vm_offset_t va = sva; 1263 int mclcount = 0; 1264 multicall_entry_t mcl[16]; 1265 multicall_entry_t *mclp = mcl; 1266 int error; 1267 1268 CTR2(KTR_PMAP, "pmap_qenter:sva=0x%x count=%d", va, count); 1269 pte = vtopte(sva); 1270 endpte = pte + count; 1271 while (pte < endpte) { 1272 pa = VM_PAGE_TO_MACH(*ma) | pgeflag | PG_RW | PG_V | PG_M | PG_A; 1273 1274 mclp->op = __HYPERVISOR_update_va_mapping; 1275 mclp->args[0] = va; 1276 mclp->args[1] = (uint32_t)(pa & 0xffffffff); 1277 mclp->args[2] = (uint32_t)(pa >> 32); 1278 mclp->args[3] = (*pte & PG_V) ? UVMF_INVLPG|UVMF_ALL : 0; 1279 1280 va += PAGE_SIZE; 1281 pte++; 1282 ma++; 1283 mclp++; 1284 mclcount++; 1285 if (mclcount == 16) { 1286 error = HYPERVISOR_multicall(mcl, mclcount); 1287 mclp = mcl; 1288 mclcount = 0; 1289 KASSERT(error == 0, ("bad multicall %d", error)); 1290 } 1291 } 1292 if (mclcount) { 1293 error = HYPERVISOR_multicall(mcl, mclcount); 1294 KASSERT(error == 0, ("bad multicall %d", error)); 1295 } 1296 1297#ifdef INVARIANTS 1298 for (pte = vtopte(sva), mclcount = 0; mclcount < count; mclcount++, pte++) 1299 KASSERT(*pte, ("pte not set for va=0x%x", sva + mclcount*PAGE_SIZE)); 1300#endif 1301} 1302 1303/* 1304 * This routine tears out page mappings from the 1305 * kernel -- it is meant only for temporary mappings. 1306 * Note: SMP coherent. Uses a ranged shootdown IPI. 1307 */ 1308void 1309pmap_qremove(vm_offset_t sva, int count) 1310{ 1311 vm_offset_t va; 1312 1313 CTR2(KTR_PMAP, "pmap_qremove: sva=0x%x count=%d", sva, count); 1314 va = sva; 1315 rw_wlock(&pvh_global_lock); 1316 critical_enter(); 1317 while (count-- > 0) { 1318 pmap_kremove(va); 1319 va += PAGE_SIZE; 1320 } 1321 PT_UPDATES_FLUSH(); 1322 pmap_invalidate_range(kernel_pmap, sva, va); 1323 critical_exit(); 1324 rw_wunlock(&pvh_global_lock); 1325} 1326 1327/*************************************************** 1328 * Page table page management routines..... 1329 ***************************************************/ 1330static __inline void 1331pmap_free_zero_pages(vm_page_t free) 1332{ 1333 vm_page_t m; 1334 1335 while (free != NULL) { 1336 m = free; 1337 free = (void *)m->object; 1338 m->object = NULL; 1339 vm_page_free_zero(m); 1340 } 1341} 1342 1343/* 1344 * Decrements a page table page's wire count, which is used to record the 1345 * number of valid page table entries within the page. If the wire count 1346 * drops to zero, then the page table page is unmapped. Returns TRUE if the 1347 * page table page was unmapped and FALSE otherwise. 1348 */ 1349static inline boolean_t 1350pmap_unwire_ptp(pmap_t pmap, vm_page_t m, vm_page_t *free) 1351{ 1352 1353 --m->wire_count; 1354 if (m->wire_count == 0) { 1355 _pmap_unwire_ptp(pmap, m, free); 1356 return (TRUE); 1357 } else 1358 return (FALSE); 1359} 1360 1361static void 1362_pmap_unwire_ptp(pmap_t pmap, vm_page_t m, vm_page_t *free) 1363{ 1364 vm_offset_t pteva; 1365 1366 PT_UPDATES_FLUSH(); 1367 /* 1368 * unmap the page table page 1369 */ 1370 xen_pt_unpin(pmap->pm_pdir[m->pindex]); 1371 /* 1372 * page *might* contain residual mapping :-/ 1373 */ 1374 PD_CLEAR_VA(pmap, m->pindex, TRUE); 1375 pmap_zero_page(m); 1376 --pmap->pm_stats.resident_count; 1377 1378 /* 1379 * This is a release store so that the ordinary store unmapping 1380 * the page table page is globally performed before TLB shoot- 1381 * down is begun. 1382 */ 1383 atomic_subtract_rel_int(&cnt.v_wire_count, 1); 1384 1385 /* 1386 * Do an invltlb to make the invalidated mapping 1387 * take effect immediately. 1388 */ 1389 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex); 1390 pmap_invalidate_page(pmap, pteva); 1391 1392 /* 1393 * Put page on a list so that it is released after 1394 * *ALL* TLB shootdown is done 1395 */ 1396 m->object = (void *)*free; 1397 *free = m; 1398} 1399 1400/* 1401 * After removing a page table entry, this routine is used to 1402 * conditionally free the page, and manage the hold/wire counts. 1403 */ 1404static int 1405pmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t *free) 1406{ 1407 pd_entry_t ptepde; 1408 vm_page_t mpte; 1409 1410 if (va >= VM_MAXUSER_ADDRESS) 1411 return (0); 1412 ptepde = PT_GET(pmap_pde(pmap, va)); 1413 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME); 1414 return (pmap_unwire_ptp(pmap, mpte, free)); 1415} 1416 1417/* 1418 * Initialize the pmap for the swapper process. 1419 */ 1420void 1421pmap_pinit0(pmap_t pmap) 1422{ 1423 1424 PMAP_LOCK_INIT(pmap); 1425 /* 1426 * Since the page table directory is shared with the kernel pmap, 1427 * which is already included in the list "allpmaps", this pmap does 1428 * not need to be inserted into that list. 1429 */ 1430 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD); 1431#ifdef PAE 1432 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT); 1433#endif 1434 CPU_ZERO(&pmap->pm_active); 1435 PCPU_SET(curpmap, pmap); 1436 TAILQ_INIT(&pmap->pm_pvchunk); 1437 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1438} 1439 1440/* 1441 * Initialize a preallocated and zeroed pmap structure, 1442 * such as one in a vmspace structure. 1443 */ 1444int 1445pmap_pinit(pmap_t pmap) 1446{ 1447 vm_page_t m, ptdpg[NPGPTD + 1]; 1448 int npgptd = NPGPTD + 1; 1449 int i; 1450 1451#ifdef HAMFISTED_LOCKING 1452 mtx_lock(&createdelete_lock); 1453#endif 1454 1455 /* 1456 * No need to allocate page table space yet but we do need a valid 1457 * page directory table. 1458 */ 1459 if (pmap->pm_pdir == NULL) { 1460 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD); 1461 if (pmap->pm_pdir == NULL) { 1462 PMAP_LOCK_DESTROY(pmap); 1463#ifdef HAMFISTED_LOCKING 1464 mtx_unlock(&createdelete_lock); 1465#endif 1466 return (0); 1467 } 1468#ifdef PAE 1469 pmap->pm_pdpt = (pd_entry_t *)kva_alloc(1); 1470#endif 1471 } 1472 1473 /* 1474 * allocate the page directory page(s) 1475 */ 1476 for (i = 0; i < npgptd;) { 1477 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | 1478 VM_ALLOC_WIRED | VM_ALLOC_ZERO); 1479 if (m == NULL) 1480 VM_WAIT; 1481 else { 1482 ptdpg[i++] = m; 1483 } 1484 } 1485 1486 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD); 1487 1488 for (i = 0; i < NPGPTD; i++) 1489 if ((ptdpg[i]->flags & PG_ZERO) == 0) 1490 pagezero(pmap->pm_pdir + (i * NPDEPG)); 1491 1492 mtx_lock_spin(&allpmaps_lock); 1493 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1494 /* Copy the kernel page table directory entries. */ 1495 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t)); 1496 mtx_unlock_spin(&allpmaps_lock); 1497 1498#ifdef PAE 1499 pmap_qenter((vm_offset_t)pmap->pm_pdpt, &ptdpg[NPGPTD], 1); 1500 if ((ptdpg[NPGPTD]->flags & PG_ZERO) == 0) 1501 bzero(pmap->pm_pdpt, PAGE_SIZE); 1502 for (i = 0; i < NPGPTD; i++) { 1503 vm_paddr_t ma; 1504 1505 ma = VM_PAGE_TO_MACH(ptdpg[i]); 1506 pmap->pm_pdpt[i] = ma | PG_V; 1507 1508 } 1509#endif 1510 for (i = 0; i < NPGPTD; i++) { 1511 pt_entry_t *pd; 1512 vm_paddr_t ma; 1513 1514 ma = VM_PAGE_TO_MACH(ptdpg[i]); 1515 pd = pmap->pm_pdir + (i * NPDEPG); 1516 PT_SET_MA(pd, *vtopte((vm_offset_t)pd) & ~(PG_M|PG_A|PG_U|PG_RW)); 1517#if 0 1518 xen_pgd_pin(ma); 1519#endif 1520 } 1521 1522#ifdef PAE 1523 PT_SET_MA(pmap->pm_pdpt, *vtopte((vm_offset_t)pmap->pm_pdpt) & ~PG_RW); 1524#endif 1525 rw_wlock(&pvh_global_lock); 1526 xen_flush_queue(); 1527 xen_pgdpt_pin(VM_PAGE_TO_MACH(ptdpg[NPGPTD])); 1528 for (i = 0; i < NPGPTD; i++) { 1529 vm_paddr_t ma = VM_PAGE_TO_MACH(ptdpg[i]); 1530 PT_SET_VA_MA(&pmap->pm_pdir[PTDPTDI + i], ma | PG_V | PG_A, FALSE); 1531 } 1532 xen_flush_queue(); 1533 rw_wunlock(&pvh_global_lock); 1534 CPU_ZERO(&pmap->pm_active); 1535 TAILQ_INIT(&pmap->pm_pvchunk); 1536 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1537 1538#ifdef HAMFISTED_LOCKING 1539 mtx_unlock(&createdelete_lock); 1540#endif 1541 return (1); 1542} 1543 1544/* 1545 * this routine is called if the page table page is not 1546 * mapped correctly. 1547 */ 1548static vm_page_t 1549_pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags) 1550{ 1551 vm_paddr_t ptema; 1552 vm_page_t m; 1553 1554 /* 1555 * Allocate a page table page. 1556 */ 1557 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ | 1558 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) { 1559 if ((flags & PMAP_ENTER_NOSLEEP) == 0) { 1560 PMAP_UNLOCK(pmap); 1561 rw_wunlock(&pvh_global_lock); 1562 VM_WAIT; 1563 rw_wlock(&pvh_global_lock); 1564 PMAP_LOCK(pmap); 1565 } 1566 1567 /* 1568 * Indicate the need to retry. While waiting, the page table 1569 * page may have been allocated. 1570 */ 1571 return (NULL); 1572 } 1573 if ((m->flags & PG_ZERO) == 0) 1574 pmap_zero_page(m); 1575 1576 /* 1577 * Map the pagetable page into the process address space, if 1578 * it isn't already there. 1579 */ 1580 1581 pmap->pm_stats.resident_count++; 1582 1583 ptema = VM_PAGE_TO_MACH(m); 1584 xen_pt_pin(ptema); 1585 PT_SET_VA_MA(&pmap->pm_pdir[ptepindex], 1586 (ptema | PG_U | PG_RW | PG_V | PG_A | PG_M), TRUE); 1587 1588 KASSERT(pmap->pm_pdir[ptepindex], 1589 ("_pmap_allocpte: ptepindex=%d did not get mapped", ptepindex)); 1590 return (m); 1591} 1592 1593static vm_page_t 1594pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags) 1595{ 1596 u_int ptepindex; 1597 pd_entry_t ptema; 1598 vm_page_t m; 1599 1600 /* 1601 * Calculate pagetable page index 1602 */ 1603 ptepindex = va >> PDRSHIFT; 1604retry: 1605 /* 1606 * Get the page directory entry 1607 */ 1608 ptema = pmap->pm_pdir[ptepindex]; 1609 1610 /* 1611 * This supports switching from a 4MB page to a 1612 * normal 4K page. 1613 */ 1614 if (ptema & PG_PS) { 1615 /* 1616 * XXX 1617 */ 1618 pmap->pm_pdir[ptepindex] = 0; 1619 ptema = 0; 1620 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 1621 pmap_invalidate_all(kernel_pmap); 1622 } 1623 1624 /* 1625 * If the page table page is mapped, we just increment the 1626 * hold count, and activate it. 1627 */ 1628 if (ptema & PG_V) { 1629 m = PHYS_TO_VM_PAGE(xpmap_mtop(ptema) & PG_FRAME); 1630 m->wire_count++; 1631 } else { 1632 /* 1633 * Here if the pte page isn't mapped, or if it has 1634 * been deallocated. 1635 */ 1636 CTR3(KTR_PMAP, "pmap_allocpte: pmap=%p va=0x%08x flags=0x%x", 1637 pmap, va, flags); 1638 m = _pmap_allocpte(pmap, ptepindex, flags); 1639 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0) 1640 goto retry; 1641 1642 KASSERT(pmap->pm_pdir[ptepindex], ("ptepindex=%d did not get mapped", ptepindex)); 1643 } 1644 return (m); 1645} 1646 1647 1648/*************************************************** 1649* Pmap allocation/deallocation routines. 1650 ***************************************************/ 1651 1652#ifdef SMP 1653/* 1654 * Deal with a SMP shootdown of other users of the pmap that we are 1655 * trying to dispose of. This can be a bit hairy. 1656 */ 1657static cpuset_t *lazymask; 1658static u_int lazyptd; 1659static volatile u_int lazywait; 1660 1661void pmap_lazyfix_action(void); 1662 1663void 1664pmap_lazyfix_action(void) 1665{ 1666 1667#ifdef COUNT_IPIS 1668 (*ipi_lazypmap_counts[PCPU_GET(cpuid)])++; 1669#endif 1670 if (rcr3() == lazyptd) 1671 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1672 CPU_CLR_ATOMIC(PCPU_GET(cpuid), lazymask); 1673 atomic_store_rel_int(&lazywait, 1); 1674} 1675 1676static void 1677pmap_lazyfix_self(u_int cpuid) 1678{ 1679 1680 if (rcr3() == lazyptd) 1681 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1682 CPU_CLR_ATOMIC(cpuid, lazymask); 1683} 1684 1685 1686static void 1687pmap_lazyfix(pmap_t pmap) 1688{ 1689 cpuset_t mymask, mask; 1690 u_int cpuid, spins; 1691 int lsb; 1692 1693 mask = pmap->pm_active; 1694 while (!CPU_EMPTY(&mask)) { 1695 spins = 50000000; 1696 1697 /* Find least significant set bit. */ 1698 lsb = CPU_FFS(&mask); 1699 MPASS(lsb != 0); 1700 lsb--; 1701 CPU_SETOF(lsb, &mask); 1702 mtx_lock_spin(&smp_ipi_mtx); 1703#ifdef PAE 1704 lazyptd = vtophys(pmap->pm_pdpt); 1705#else 1706 lazyptd = vtophys(pmap->pm_pdir); 1707#endif 1708 cpuid = PCPU_GET(cpuid); 1709 1710 /* Use a cpuset just for having an easy check. */ 1711 CPU_SETOF(cpuid, &mymask); 1712 if (!CPU_CMP(&mask, &mymask)) { 1713 lazymask = &pmap->pm_active; 1714 pmap_lazyfix_self(cpuid); 1715 } else { 1716 atomic_store_rel_int((u_int *)&lazymask, 1717 (u_int)&pmap->pm_active); 1718 atomic_store_rel_int(&lazywait, 0); 1719 ipi_selected(mask, IPI_LAZYPMAP); 1720 while (lazywait == 0) { 1721 ia32_pause(); 1722 if (--spins == 0) 1723 break; 1724 } 1725 } 1726 mtx_unlock_spin(&smp_ipi_mtx); 1727 if (spins == 0) 1728 printf("pmap_lazyfix: spun for 50000000\n"); 1729 mask = pmap->pm_active; 1730 } 1731} 1732 1733#else /* SMP */ 1734 1735/* 1736 * Cleaning up on uniprocessor is easy. For various reasons, we're 1737 * unlikely to have to even execute this code, including the fact 1738 * that the cleanup is deferred until the parent does a wait(2), which 1739 * means that another userland process has run. 1740 */ 1741static void 1742pmap_lazyfix(pmap_t pmap) 1743{ 1744 u_int cr3; 1745 1746 cr3 = vtophys(pmap->pm_pdir); 1747 if (cr3 == rcr3()) { 1748 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1749 CPU_CLR(PCPU_GET(cpuid), &pmap->pm_active); 1750 } 1751} 1752#endif /* SMP */ 1753 1754/* 1755 * Release any resources held by the given physical map. 1756 * Called when a pmap initialized by pmap_pinit is being released. 1757 * Should only be called if the map contains no valid mappings. 1758 */ 1759void 1760pmap_release(pmap_t pmap) 1761{ 1762 vm_page_t m, ptdpg[2*NPGPTD+1]; 1763 vm_paddr_t ma; 1764 int i; 1765#ifdef PAE 1766 int npgptd = NPGPTD + 1; 1767#else 1768 int npgptd = NPGPTD; 1769#endif 1770 1771 KASSERT(pmap->pm_stats.resident_count == 0, 1772 ("pmap_release: pmap resident count %ld != 0", 1773 pmap->pm_stats.resident_count)); 1774 PT_UPDATES_FLUSH(); 1775 1776#ifdef HAMFISTED_LOCKING 1777 mtx_lock(&createdelete_lock); 1778#endif 1779 1780 pmap_lazyfix(pmap); 1781 mtx_lock_spin(&allpmaps_lock); 1782 LIST_REMOVE(pmap, pm_list); 1783 mtx_unlock_spin(&allpmaps_lock); 1784 1785 for (i = 0; i < NPGPTD; i++) 1786 ptdpg[i] = PHYS_TO_VM_PAGE(vtophys(pmap->pm_pdir + (i*NPDEPG)) & PG_FRAME); 1787 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD); 1788#ifdef PAE 1789 ptdpg[NPGPTD] = PHYS_TO_VM_PAGE(vtophys(pmap->pm_pdpt)); 1790#endif 1791 1792 for (i = 0; i < npgptd; i++) { 1793 m = ptdpg[i]; 1794 ma = VM_PAGE_TO_MACH(m); 1795 /* unpinning L1 and L2 treated the same */ 1796#if 0 1797 xen_pgd_unpin(ma); 1798#else 1799 if (i == NPGPTD) 1800 xen_pgd_unpin(ma); 1801#endif 1802#ifdef PAE 1803 if (i < NPGPTD) 1804 KASSERT(VM_PAGE_TO_MACH(m) == (pmap->pm_pdpt[i] & PG_FRAME), 1805 ("pmap_release: got wrong ptd page")); 1806#endif 1807 m->wire_count--; 1808 atomic_subtract_int(&cnt.v_wire_count, 1); 1809 vm_page_free(m); 1810 } 1811#ifdef PAE 1812 pmap_qremove((vm_offset_t)pmap->pm_pdpt, 1); 1813#endif 1814 1815#ifdef HAMFISTED_LOCKING 1816 mtx_unlock(&createdelete_lock); 1817#endif 1818} 1819 1820static int 1821kvm_size(SYSCTL_HANDLER_ARGS) 1822{ 1823 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE; 1824 1825 return (sysctl_handle_long(oidp, &ksize, 0, req)); 1826} 1827SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD, 1828 0, 0, kvm_size, "IU", "Size of KVM"); 1829 1830static int 1831kvm_free(SYSCTL_HANDLER_ARGS) 1832{ 1833 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end; 1834 1835 return (sysctl_handle_long(oidp, &kfree, 0, req)); 1836} 1837SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD, 1838 0, 0, kvm_free, "IU", "Amount of KVM free"); 1839 1840/* 1841 * grow the number of kernel page table entries, if needed 1842 */ 1843void 1844pmap_growkernel(vm_offset_t addr) 1845{ 1846 struct pmap *pmap; 1847 vm_paddr_t ptppaddr; 1848 vm_page_t nkpg; 1849 pd_entry_t newpdir; 1850 1851 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 1852 if (kernel_vm_end == 0) { 1853 kernel_vm_end = KERNBASE; 1854 nkpt = 0; 1855 while (pdir_pde(PTD, kernel_vm_end)) { 1856 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1857 nkpt++; 1858 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1859 kernel_vm_end = kernel_map->max_offset; 1860 break; 1861 } 1862 } 1863 } 1864 addr = roundup2(addr, NBPDR); 1865 if (addr - 1 >= kernel_map->max_offset) 1866 addr = kernel_map->max_offset; 1867 while (kernel_vm_end < addr) { 1868 if (pdir_pde(PTD, kernel_vm_end)) { 1869 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 1870 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1871 kernel_vm_end = kernel_map->max_offset; 1872 break; 1873 } 1874 continue; 1875 } 1876 1877 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT, 1878 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 1879 VM_ALLOC_ZERO); 1880 if (nkpg == NULL) 1881 panic("pmap_growkernel: no memory to grow kernel"); 1882 1883 nkpt++; 1884 1885 if ((nkpg->flags & PG_ZERO) == 0) 1886 pmap_zero_page(nkpg); 1887 ptppaddr = VM_PAGE_TO_PHYS(nkpg); 1888 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M); 1889 rw_wlock(&pvh_global_lock); 1890 PD_SET_VA(kernel_pmap, (kernel_vm_end >> PDRSHIFT), newpdir, TRUE); 1891 mtx_lock_spin(&allpmaps_lock); 1892 LIST_FOREACH(pmap, &allpmaps, pm_list) 1893 PD_SET_VA(pmap, (kernel_vm_end >> PDRSHIFT), newpdir, TRUE); 1894 1895 mtx_unlock_spin(&allpmaps_lock); 1896 rw_wunlock(&pvh_global_lock); 1897 1898 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 1899 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1900 kernel_vm_end = kernel_map->max_offset; 1901 break; 1902 } 1903 } 1904} 1905 1906 1907/*************************************************** 1908 * page management routines. 1909 ***************************************************/ 1910 1911CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE); 1912CTASSERT(_NPCM == 11); 1913CTASSERT(_NPCPV == 336); 1914 1915static __inline struct pv_chunk * 1916pv_to_chunk(pv_entry_t pv) 1917{ 1918 1919 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK)); 1920} 1921 1922#define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap) 1923 1924#define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */ 1925#define PC_FREE10 0x0000fffful /* Free values for index 10 */ 1926 1927static const uint32_t pc_freemask[_NPCM] = { 1928 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1929 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1930 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1931 PC_FREE0_9, PC_FREE10 1932}; 1933 1934SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0, 1935 "Current number of pv entries"); 1936 1937#ifdef PV_STATS 1938static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail; 1939 1940SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0, 1941 "Current number of pv entry chunks"); 1942SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0, 1943 "Current number of pv entry chunks allocated"); 1944SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0, 1945 "Current number of pv entry chunks frees"); 1946SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0, 1947 "Number of times tried to get a chunk page but failed."); 1948 1949static long pv_entry_frees, pv_entry_allocs; 1950static int pv_entry_spare; 1951 1952SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0, 1953 "Current number of pv entry frees"); 1954SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0, 1955 "Current number of pv entry allocs"); 1956SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0, 1957 "Current number of spare pv entries"); 1958#endif 1959 1960/* 1961 * We are in a serious low memory condition. Resort to 1962 * drastic measures to free some pages so we can allocate 1963 * another pv entry chunk. 1964 */ 1965static vm_page_t 1966pmap_pv_reclaim(pmap_t locked_pmap) 1967{ 1968 struct pch newtail; 1969 struct pv_chunk *pc; 1970 pmap_t pmap; 1971 pt_entry_t *pte, tpte; 1972 pv_entry_t pv; 1973 vm_offset_t va; 1974 vm_page_t free, m, m_pc; 1975 uint32_t inuse; 1976 int bit, field, freed; 1977 1978 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED); 1979 pmap = NULL; 1980 free = m_pc = NULL; 1981 TAILQ_INIT(&newtail); 1982 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 || 1983 free == NULL)) { 1984 TAILQ_REMOVE(&pv_chunks, pc, pc_lru); 1985 if (pmap != pc->pc_pmap) { 1986 if (pmap != NULL) { 1987 pmap_invalidate_all(pmap); 1988 if (pmap != locked_pmap) 1989 PMAP_UNLOCK(pmap); 1990 } 1991 pmap = pc->pc_pmap; 1992 /* Avoid deadlock and lock recursion. */ 1993 if (pmap > locked_pmap) 1994 PMAP_LOCK(pmap); 1995 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) { 1996 pmap = NULL; 1997 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 1998 continue; 1999 } 2000 } 2001 2002 /* 2003 * Destroy every non-wired, 4 KB page mapping in the chunk. 2004 */ 2005 freed = 0; 2006 for (field = 0; field < _NPCM; field++) { 2007 for (inuse = ~pc->pc_map[field] & pc_freemask[field]; 2008 inuse != 0; inuse &= ~(1UL << bit)) { 2009 bit = bsfl(inuse); 2010 pv = &pc->pc_pventry[field * 32 + bit]; 2011 va = pv->pv_va; 2012 pte = pmap_pte(pmap, va); 2013 tpte = *pte; 2014 if ((tpte & PG_W) == 0) 2015 tpte = pte_load_clear(pte); 2016 pmap_pte_release(pte); 2017 if ((tpte & PG_W) != 0) 2018 continue; 2019 KASSERT(tpte != 0, 2020 ("pmap_pv_reclaim: pmap %p va %x zero pte", 2021 pmap, va)); 2022 if ((tpte & PG_G) != 0) 2023 pmap_invalidate_page(pmap, va); 2024 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 2025 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2026 vm_page_dirty(m); 2027 if ((tpte & PG_A) != 0) 2028 vm_page_aflag_set(m, PGA_REFERENCED); 2029 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 2030 if (TAILQ_EMPTY(&m->md.pv_list)) 2031 vm_page_aflag_clear(m, PGA_WRITEABLE); 2032 pc->pc_map[field] |= 1UL << bit; 2033 pmap_unuse_pt(pmap, va, &free); 2034 freed++; 2035 } 2036 } 2037 if (freed == 0) { 2038 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 2039 continue; 2040 } 2041 /* Every freed mapping is for a 4 KB page. */ 2042 pmap->pm_stats.resident_count -= freed; 2043 PV_STAT(pv_entry_frees += freed); 2044 PV_STAT(pv_entry_spare += freed); 2045 pv_entry_count -= freed; 2046 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2047 for (field = 0; field < _NPCM; field++) 2048 if (pc->pc_map[field] != pc_freemask[field]) { 2049 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, 2050 pc_list); 2051 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 2052 2053 /* 2054 * One freed pv entry in locked_pmap is 2055 * sufficient. 2056 */ 2057 if (pmap == locked_pmap) 2058 goto out; 2059 break; 2060 } 2061 if (field == _NPCM) { 2062 PV_STAT(pv_entry_spare -= _NPCPV); 2063 PV_STAT(pc_chunk_count--); 2064 PV_STAT(pc_chunk_frees++); 2065 /* Entire chunk is free; return it. */ 2066 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 2067 pmap_qremove((vm_offset_t)pc, 1); 2068 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 2069 break; 2070 } 2071 } 2072out: 2073 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru); 2074 if (pmap != NULL) { 2075 pmap_invalidate_all(pmap); 2076 if (pmap != locked_pmap) 2077 PMAP_UNLOCK(pmap); 2078 } 2079 if (m_pc == NULL && pv_vafree != 0 && free != NULL) { 2080 m_pc = free; 2081 free = (void *)m_pc->object; 2082 /* Recycle a freed page table page. */ 2083 m_pc->wire_count = 1; 2084 atomic_add_int(&cnt.v_wire_count, 1); 2085 } 2086 pmap_free_zero_pages(free); 2087 return (m_pc); 2088} 2089 2090/* 2091 * free the pv_entry back to the free list 2092 */ 2093static void 2094free_pv_entry(pmap_t pmap, pv_entry_t pv) 2095{ 2096 struct pv_chunk *pc; 2097 int idx, field, bit; 2098 2099 rw_assert(&pvh_global_lock, RA_WLOCKED); 2100 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2101 PV_STAT(pv_entry_frees++); 2102 PV_STAT(pv_entry_spare++); 2103 pv_entry_count--; 2104 pc = pv_to_chunk(pv); 2105 idx = pv - &pc->pc_pventry[0]; 2106 field = idx / 32; 2107 bit = idx % 32; 2108 pc->pc_map[field] |= 1ul << bit; 2109 for (idx = 0; idx < _NPCM; idx++) 2110 if (pc->pc_map[idx] != pc_freemask[idx]) { 2111 /* 2112 * 98% of the time, pc is already at the head of the 2113 * list. If it isn't already, move it to the head. 2114 */ 2115 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) != 2116 pc)) { 2117 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2118 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, 2119 pc_list); 2120 } 2121 return; 2122 } 2123 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2124 free_pv_chunk(pc); 2125} 2126 2127static void 2128free_pv_chunk(struct pv_chunk *pc) 2129{ 2130 vm_page_t m; 2131 2132 TAILQ_REMOVE(&pv_chunks, pc, pc_lru); 2133 PV_STAT(pv_entry_spare -= _NPCPV); 2134 PV_STAT(pc_chunk_count--); 2135 PV_STAT(pc_chunk_frees++); 2136 /* entire chunk is free, return it */ 2137 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 2138 pmap_qremove((vm_offset_t)pc, 1); 2139 vm_page_unwire(m, 0); 2140 vm_page_free(m); 2141 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 2142} 2143 2144/* 2145 * get a new pv_entry, allocating a block from the system 2146 * when needed. 2147 */ 2148static pv_entry_t 2149get_pv_entry(pmap_t pmap, boolean_t try) 2150{ 2151 static const struct timeval printinterval = { 60, 0 }; 2152 static struct timeval lastprint; 2153 int bit, field; 2154 pv_entry_t pv; 2155 struct pv_chunk *pc; 2156 vm_page_t m; 2157 2158 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2159 rw_assert(&pvh_global_lock, RA_WLOCKED); 2160 PV_STAT(pv_entry_allocs++); 2161 pv_entry_count++; 2162 if (pv_entry_count > pv_entry_high_water) 2163 if (ratecheck(&lastprint, &printinterval)) 2164 printf("Approaching the limit on PV entries, consider " 2165 "increasing either the vm.pmap.shpgperproc or the " 2166 "vm.pmap.pv_entry_max tunable.\n"); 2167retry: 2168 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 2169 if (pc != NULL) { 2170 for (field = 0; field < _NPCM; field++) { 2171 if (pc->pc_map[field]) { 2172 bit = bsfl(pc->pc_map[field]); 2173 break; 2174 } 2175 } 2176 if (field < _NPCM) { 2177 pv = &pc->pc_pventry[field * 32 + bit]; 2178 pc->pc_map[field] &= ~(1ul << bit); 2179 /* If this was the last item, move it to tail */ 2180 for (field = 0; field < _NPCM; field++) 2181 if (pc->pc_map[field] != 0) { 2182 PV_STAT(pv_entry_spare--); 2183 return (pv); /* not full, return */ 2184 } 2185 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2186 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 2187 PV_STAT(pv_entry_spare--); 2188 return (pv); 2189 } 2190 } 2191 /* 2192 * Access to the ptelist "pv_vafree" is synchronized by the page 2193 * queues lock. If "pv_vafree" is currently non-empty, it will 2194 * remain non-empty until pmap_ptelist_alloc() completes. 2195 */ 2196 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | 2197 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 2198 if (try) { 2199 pv_entry_count--; 2200 PV_STAT(pc_chunk_tryfail++); 2201 return (NULL); 2202 } 2203 m = pmap_pv_reclaim(pmap); 2204 if (m == NULL) 2205 goto retry; 2206 } 2207 PV_STAT(pc_chunk_count++); 2208 PV_STAT(pc_chunk_allocs++); 2209 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree); 2210 pmap_qenter((vm_offset_t)pc, &m, 1); 2211 if ((m->flags & PG_ZERO) == 0) 2212 pagezero(pc); 2213 pc->pc_pmap = pmap; 2214 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */ 2215 for (field = 1; field < _NPCM; field++) 2216 pc->pc_map[field] = pc_freemask[field]; 2217 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru); 2218 pv = &pc->pc_pventry[0]; 2219 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2220 PV_STAT(pv_entry_spare += _NPCPV - 1); 2221 return (pv); 2222} 2223 2224static __inline pv_entry_t 2225pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2226{ 2227 pv_entry_t pv; 2228 2229 rw_assert(&pvh_global_lock, RA_WLOCKED); 2230 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 2231 if (pmap == PV_PMAP(pv) && va == pv->pv_va) { 2232 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next); 2233 break; 2234 } 2235 } 2236 return (pv); 2237} 2238 2239static void 2240pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2241{ 2242 pv_entry_t pv; 2243 2244 pv = pmap_pvh_remove(pvh, pmap, va); 2245 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found")); 2246 free_pv_entry(pmap, pv); 2247} 2248 2249static void 2250pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va) 2251{ 2252 2253 rw_assert(&pvh_global_lock, RA_WLOCKED); 2254 pmap_pvh_free(&m->md, pmap, va); 2255 if (TAILQ_EMPTY(&m->md.pv_list)) 2256 vm_page_aflag_clear(m, PGA_WRITEABLE); 2257} 2258 2259/* 2260 * Conditionally create a pv entry. 2261 */ 2262static boolean_t 2263pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2264{ 2265 pv_entry_t pv; 2266 2267 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2268 rw_assert(&pvh_global_lock, RA_WLOCKED); 2269 if (pv_entry_count < pv_entry_high_water && 2270 (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2271 pv->pv_va = va; 2272 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 2273 return (TRUE); 2274 } else 2275 return (FALSE); 2276} 2277 2278/* 2279 * pmap_remove_pte: do the things to unmap a page in a process 2280 */ 2281static int 2282pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va, vm_page_t *free) 2283{ 2284 pt_entry_t oldpte; 2285 vm_page_t m; 2286 2287 CTR3(KTR_PMAP, "pmap_remove_pte: pmap=%p *ptq=0x%x va=0x%x", 2288 pmap, (u_long)*ptq, va); 2289 2290 rw_assert(&pvh_global_lock, RA_WLOCKED); 2291 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2292 oldpte = *ptq; 2293 PT_SET_VA_MA(ptq, 0, TRUE); 2294 KASSERT(oldpte != 0, 2295 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va)); 2296 if (oldpte & PG_W) 2297 pmap->pm_stats.wired_count -= 1; 2298 /* 2299 * Machines that don't support invlpg, also don't support 2300 * PG_G. 2301 */ 2302 if (oldpte & PG_G) 2303 pmap_invalidate_page(kernel_pmap, va); 2304 pmap->pm_stats.resident_count -= 1; 2305 if (oldpte & PG_MANAGED) { 2306 m = PHYS_TO_VM_PAGE(xpmap_mtop(oldpte) & PG_FRAME); 2307 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2308 vm_page_dirty(m); 2309 if (oldpte & PG_A) 2310 vm_page_aflag_set(m, PGA_REFERENCED); 2311 pmap_remove_entry(pmap, m, va); 2312 } 2313 return (pmap_unuse_pt(pmap, va, free)); 2314} 2315 2316/* 2317 * Remove a single page from a process address space 2318 */ 2319static void 2320pmap_remove_page(pmap_t pmap, vm_offset_t va, vm_page_t *free) 2321{ 2322 pt_entry_t *pte; 2323 2324 CTR2(KTR_PMAP, "pmap_remove_page: pmap=%p va=0x%x", 2325 pmap, va); 2326 2327 rw_assert(&pvh_global_lock, RA_WLOCKED); 2328 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 2329 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2330 if ((pte = pmap_pte_quick(pmap, va)) == NULL || (*pte & PG_V) == 0) 2331 return; 2332 pmap_remove_pte(pmap, pte, va, free); 2333 pmap_invalidate_page(pmap, va); 2334 if (*PMAP1) 2335 PT_SET_MA(PADDR1, 0); 2336 2337} 2338 2339/* 2340 * Remove the given range of addresses from the specified map. 2341 * 2342 * It is assumed that the start and end are properly 2343 * rounded to the page size. 2344 */ 2345void 2346pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2347{ 2348 vm_offset_t pdnxt; 2349 pd_entry_t ptpaddr; 2350 pt_entry_t *pte; 2351 vm_page_t free = NULL; 2352 int anyvalid; 2353 2354 CTR3(KTR_PMAP, "pmap_remove: pmap=%p sva=0x%x eva=0x%x", 2355 pmap, sva, eva); 2356 2357 /* 2358 * Perform an unsynchronized read. This is, however, safe. 2359 */ 2360 if (pmap->pm_stats.resident_count == 0) 2361 return; 2362 2363 anyvalid = 0; 2364 2365 rw_wlock(&pvh_global_lock); 2366 sched_pin(); 2367 PMAP_LOCK(pmap); 2368 2369 /* 2370 * special handling of removing one page. a very 2371 * common operation and easy to short circuit some 2372 * code. 2373 */ 2374 if ((sva + PAGE_SIZE == eva) && 2375 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) { 2376 pmap_remove_page(pmap, sva, &free); 2377 goto out; 2378 } 2379 2380 for (; sva < eva; sva = pdnxt) { 2381 u_int pdirindex; 2382 2383 /* 2384 * Calculate index for next page table. 2385 */ 2386 pdnxt = (sva + NBPDR) & ~PDRMASK; 2387 if (pdnxt < sva) 2388 pdnxt = eva; 2389 if (pmap->pm_stats.resident_count == 0) 2390 break; 2391 2392 pdirindex = sva >> PDRSHIFT; 2393 ptpaddr = pmap->pm_pdir[pdirindex]; 2394 2395 /* 2396 * Weed out invalid mappings. Note: we assume that the page 2397 * directory table is always allocated, and in kernel virtual. 2398 */ 2399 if (ptpaddr == 0) 2400 continue; 2401 2402 /* 2403 * Check for large page. 2404 */ 2405 if ((ptpaddr & PG_PS) != 0) { 2406 PD_CLEAR_VA(pmap, pdirindex, TRUE); 2407 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 2408 anyvalid = 1; 2409 continue; 2410 } 2411 2412 /* 2413 * Limit our scan to either the end of the va represented 2414 * by the current page table page, or to the end of the 2415 * range being removed. 2416 */ 2417 if (pdnxt > eva) 2418 pdnxt = eva; 2419 2420 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2421 sva += PAGE_SIZE) { 2422 if ((*pte & PG_V) == 0) 2423 continue; 2424 2425 /* 2426 * The TLB entry for a PG_G mapping is invalidated 2427 * by pmap_remove_pte(). 2428 */ 2429 if ((*pte & PG_G) == 0) 2430 anyvalid = 1; 2431 if (pmap_remove_pte(pmap, pte, sva, &free)) 2432 break; 2433 } 2434 } 2435 PT_UPDATES_FLUSH(); 2436 if (*PMAP1) 2437 PT_SET_VA_MA(PMAP1, 0, TRUE); 2438out: 2439 if (anyvalid) 2440 pmap_invalidate_all(pmap); 2441 sched_unpin(); 2442 rw_wunlock(&pvh_global_lock); 2443 PMAP_UNLOCK(pmap); 2444 pmap_free_zero_pages(free); 2445} 2446 2447/* 2448 * Routine: pmap_remove_all 2449 * Function: 2450 * Removes this physical page from 2451 * all physical maps in which it resides. 2452 * Reflects back modify bits to the pager. 2453 * 2454 * Notes: 2455 * Original versions of this routine were very 2456 * inefficient because they iteratively called 2457 * pmap_remove (slow...) 2458 */ 2459 2460void 2461pmap_remove_all(vm_page_t m) 2462{ 2463 pv_entry_t pv; 2464 pmap_t pmap; 2465 pt_entry_t *pte, tpte; 2466 vm_page_t free; 2467 2468 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2469 ("pmap_remove_all: page %p is not managed", m)); 2470 free = NULL; 2471 rw_wlock(&pvh_global_lock); 2472 sched_pin(); 2473 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 2474 pmap = PV_PMAP(pv); 2475 PMAP_LOCK(pmap); 2476 pmap->pm_stats.resident_count--; 2477 pte = pmap_pte_quick(pmap, pv->pv_va); 2478 tpte = *pte; 2479 PT_SET_VA_MA(pte, 0, TRUE); 2480 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte", 2481 pmap, pv->pv_va)); 2482 if (tpte & PG_W) 2483 pmap->pm_stats.wired_count--; 2484 if (tpte & PG_A) 2485 vm_page_aflag_set(m, PGA_REFERENCED); 2486 2487 /* 2488 * Update the vm_page_t clean and reference bits. 2489 */ 2490 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2491 vm_page_dirty(m); 2492 pmap_unuse_pt(pmap, pv->pv_va, &free); 2493 pmap_invalidate_page(pmap, pv->pv_va); 2494 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 2495 free_pv_entry(pmap, pv); 2496 PMAP_UNLOCK(pmap); 2497 } 2498 vm_page_aflag_clear(m, PGA_WRITEABLE); 2499 PT_UPDATES_FLUSH(); 2500 if (*PMAP1) 2501 PT_SET_MA(PADDR1, 0); 2502 sched_unpin(); 2503 rw_wunlock(&pvh_global_lock); 2504 pmap_free_zero_pages(free); 2505} 2506 2507/* 2508 * Set the physical protection on the 2509 * specified range of this map as requested. 2510 */ 2511void 2512pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 2513{ 2514 vm_offset_t pdnxt; 2515 pd_entry_t ptpaddr; 2516 pt_entry_t *pte; 2517 int anychanged; 2518 2519 CTR4(KTR_PMAP, "pmap_protect: pmap=%p sva=0x%x eva=0x%x prot=0x%x", 2520 pmap, sva, eva, prot); 2521 2522 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2523 pmap_remove(pmap, sva, eva); 2524 return; 2525 } 2526 2527#ifdef PAE 2528 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) == 2529 (VM_PROT_WRITE|VM_PROT_EXECUTE)) 2530 return; 2531#else 2532 if (prot & VM_PROT_WRITE) 2533 return; 2534#endif 2535 2536 anychanged = 0; 2537 2538 rw_wlock(&pvh_global_lock); 2539 sched_pin(); 2540 PMAP_LOCK(pmap); 2541 for (; sva < eva; sva = pdnxt) { 2542 pt_entry_t obits, pbits; 2543 u_int pdirindex; 2544 2545 pdnxt = (sva + NBPDR) & ~PDRMASK; 2546 if (pdnxt < sva) 2547 pdnxt = eva; 2548 2549 pdirindex = sva >> PDRSHIFT; 2550 ptpaddr = pmap->pm_pdir[pdirindex]; 2551 2552 /* 2553 * Weed out invalid mappings. Note: we assume that the page 2554 * directory table is always allocated, and in kernel virtual. 2555 */ 2556 if (ptpaddr == 0) 2557 continue; 2558 2559 /* 2560 * Check for large page. 2561 */ 2562 if ((ptpaddr & PG_PS) != 0) { 2563 if ((prot & VM_PROT_WRITE) == 0) 2564 pmap->pm_pdir[pdirindex] &= ~(PG_M|PG_RW); 2565#ifdef PAE 2566 if ((prot & VM_PROT_EXECUTE) == 0) 2567 pmap->pm_pdir[pdirindex] |= pg_nx; 2568#endif 2569 anychanged = 1; 2570 continue; 2571 } 2572 2573 if (pdnxt > eva) 2574 pdnxt = eva; 2575 2576 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2577 sva += PAGE_SIZE) { 2578 vm_page_t m; 2579 2580retry: 2581 /* 2582 * Regardless of whether a pte is 32 or 64 bits in 2583 * size, PG_RW, PG_A, and PG_M are among the least 2584 * significant 32 bits. 2585 */ 2586 obits = pbits = *pte; 2587 if ((pbits & PG_V) == 0) 2588 continue; 2589 2590 if ((prot & VM_PROT_WRITE) == 0) { 2591 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) == 2592 (PG_MANAGED | PG_M | PG_RW)) { 2593 m = PHYS_TO_VM_PAGE(xpmap_mtop(pbits) & 2594 PG_FRAME); 2595 vm_page_dirty(m); 2596 } 2597 pbits &= ~(PG_RW | PG_M); 2598 } 2599#ifdef PAE 2600 if ((prot & VM_PROT_EXECUTE) == 0) 2601 pbits |= pg_nx; 2602#endif 2603 2604 if (pbits != obits) { 2605 obits = *pte; 2606 PT_SET_VA_MA(pte, pbits, TRUE); 2607 if (*pte != pbits) 2608 goto retry; 2609 if (obits & PG_G) 2610 pmap_invalidate_page(pmap, sva); 2611 else 2612 anychanged = 1; 2613 } 2614 } 2615 } 2616 PT_UPDATES_FLUSH(); 2617 if (*PMAP1) 2618 PT_SET_VA_MA(PMAP1, 0, TRUE); 2619 if (anychanged) 2620 pmap_invalidate_all(pmap); 2621 sched_unpin(); 2622 rw_wunlock(&pvh_global_lock); 2623 PMAP_UNLOCK(pmap); 2624} 2625 2626/* 2627 * Insert the given physical page (p) at 2628 * the specified virtual address (v) in the 2629 * target physical map with the protection requested. 2630 * 2631 * If specified, the page will be wired down, meaning 2632 * that the related pte can not be reclaimed. 2633 * 2634 * NB: This is the only routine which MAY NOT lazy-evaluate 2635 * or lose information. That is, this routine must actually 2636 * insert this page into the given map NOW. 2637 */ 2638int 2639pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 2640 u_int flags, int8_t psind __unused) 2641{ 2642 pd_entry_t *pde; 2643 pt_entry_t *pte; 2644 pt_entry_t newpte, origpte; 2645 pv_entry_t pv; 2646 vm_paddr_t opa, pa; 2647 vm_page_t mpte, om; 2648 boolean_t invlva, wired; 2649 2650 CTR5(KTR_PMAP, 2651 "pmap_enter: pmap=%08p va=0x%08x ma=0x%08x prot=0x%x flags=0x%x", 2652 pmap, va, VM_PAGE_TO_MACH(m), prot, flags); 2653 va = trunc_page(va); 2654 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig")); 2655 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS, 2656 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)", 2657 va)); 2658 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 2659 VM_OBJECT_ASSERT_LOCKED(m->object); 2660 2661 mpte = NULL; 2662 wired = (flags & PMAP_ENTER_WIRED) != 0; 2663 2664 rw_wlock(&pvh_global_lock); 2665 PMAP_LOCK(pmap); 2666 sched_pin(); 2667 2668 /* 2669 * In the case that a page table page is not 2670 * resident, we are creating it here. 2671 */ 2672 if (va < VM_MAXUSER_ADDRESS) { 2673 mpte = pmap_allocpte(pmap, va, flags); 2674 if (mpte == NULL) { 2675 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0, 2676 ("pmap_allocpte failed with sleep allowed")); 2677 sched_unpin(); 2678 rw_wunlock(&pvh_global_lock); 2679 PMAP_UNLOCK(pmap); 2680 return (KERN_RESOURCE_SHORTAGE); 2681 } 2682 } 2683 2684 pde = pmap_pde(pmap, va); 2685 if ((*pde & PG_PS) != 0) 2686 panic("pmap_enter: attempted pmap_enter on 4MB page"); 2687 pte = pmap_pte_quick(pmap, va); 2688 2689 /* 2690 * Page Directory table entry not valid, we need a new PT page 2691 */ 2692 if (pte == NULL) { 2693 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x", 2694 (uintmax_t)pmap->pm_pdir[va >> PDRSHIFT], va); 2695 } 2696 2697 pa = VM_PAGE_TO_PHYS(m); 2698 om = NULL; 2699 opa = origpte = 0; 2700 2701#if 0 2702 KASSERT((*pte & PG_V) || (*pte == 0), ("address set but not valid pte=%p *pte=0x%016jx", 2703 pte, *pte)); 2704#endif 2705 origpte = *pte; 2706 if (origpte) 2707 origpte = xpmap_mtop(origpte); 2708 opa = origpte & PG_FRAME; 2709 2710 /* 2711 * Mapping has not changed, must be protection or wiring change. 2712 */ 2713 if (origpte && (opa == pa)) { 2714 /* 2715 * Wiring change, just update stats. We don't worry about 2716 * wiring PT pages as they remain resident as long as there 2717 * are valid mappings in them. Hence, if a user page is wired, 2718 * the PT page will be also. 2719 */ 2720 if (wired && ((origpte & PG_W) == 0)) 2721 pmap->pm_stats.wired_count++; 2722 else if (!wired && (origpte & PG_W)) 2723 pmap->pm_stats.wired_count--; 2724 2725 /* 2726 * Remove extra pte reference 2727 */ 2728 if (mpte) 2729 mpte->wire_count--; 2730 2731 if (origpte & PG_MANAGED) { 2732 om = m; 2733 pa |= PG_MANAGED; 2734 } 2735 goto validate; 2736 } 2737 2738 pv = NULL; 2739 2740 /* 2741 * Mapping has changed, invalidate old range and fall through to 2742 * handle validating new mapping. 2743 */ 2744 if (opa) { 2745 if (origpte & PG_W) 2746 pmap->pm_stats.wired_count--; 2747 if (origpte & PG_MANAGED) { 2748 om = PHYS_TO_VM_PAGE(opa); 2749 pv = pmap_pvh_remove(&om->md, pmap, va); 2750 } else if (va < VM_MAXUSER_ADDRESS) 2751 printf("va=0x%x is unmanaged :-( \n", va); 2752 2753 if (mpte != NULL) { 2754 mpte->wire_count--; 2755 KASSERT(mpte->wire_count > 0, 2756 ("pmap_enter: missing reference to page table page," 2757 " va: 0x%x", va)); 2758 } 2759 } else 2760 pmap->pm_stats.resident_count++; 2761 2762 /* 2763 * Enter on the PV list if part of our managed memory. 2764 */ 2765 if ((m->oflags & VPO_UNMANAGED) == 0) { 2766 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 2767 ("pmap_enter: managed mapping within the clean submap")); 2768 if (pv == NULL) 2769 pv = get_pv_entry(pmap, FALSE); 2770 pv->pv_va = va; 2771 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 2772 pa |= PG_MANAGED; 2773 } else if (pv != NULL) 2774 free_pv_entry(pmap, pv); 2775 2776 /* 2777 * Increment counters 2778 */ 2779 if (wired) 2780 pmap->pm_stats.wired_count++; 2781 2782validate: 2783 /* 2784 * Now validate mapping with desired protection/wiring. 2785 */ 2786 newpte = (pt_entry_t)(pa | PG_V); 2787 if ((prot & VM_PROT_WRITE) != 0) { 2788 newpte |= PG_RW; 2789 if ((newpte & PG_MANAGED) != 0) 2790 vm_page_aflag_set(m, PGA_WRITEABLE); 2791 } 2792#ifdef PAE 2793 if ((prot & VM_PROT_EXECUTE) == 0) 2794 newpte |= pg_nx; 2795#endif 2796 if (wired) 2797 newpte |= PG_W; 2798 if (va < VM_MAXUSER_ADDRESS) 2799 newpte |= PG_U; 2800 if (pmap == kernel_pmap) 2801 newpte |= pgeflag; 2802 2803 critical_enter(); 2804 /* 2805 * if the mapping or permission bits are different, we need 2806 * to update the pte. 2807 */ 2808 if ((origpte & ~(PG_M|PG_A)) != newpte) { 2809 if (origpte) { 2810 invlva = FALSE; 2811 origpte = *pte; 2812 PT_SET_VA(pte, newpte | PG_A, FALSE); 2813 if (origpte & PG_A) { 2814 if (origpte & PG_MANAGED) 2815 vm_page_aflag_set(om, PGA_REFERENCED); 2816 if (opa != VM_PAGE_TO_PHYS(m)) 2817 invlva = TRUE; 2818#ifdef PAE 2819 if ((origpte & PG_NX) == 0 && 2820 (newpte & PG_NX) != 0) 2821 invlva = TRUE; 2822#endif 2823 } 2824 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 2825 if ((origpte & PG_MANAGED) != 0) 2826 vm_page_dirty(om); 2827 if ((prot & VM_PROT_WRITE) == 0) 2828 invlva = TRUE; 2829 } 2830 if ((origpte & PG_MANAGED) != 0 && 2831 TAILQ_EMPTY(&om->md.pv_list)) 2832 vm_page_aflag_clear(om, PGA_WRITEABLE); 2833 if (invlva) 2834 pmap_invalidate_page(pmap, va); 2835 } else{ 2836 PT_SET_VA(pte, newpte | PG_A, FALSE); 2837 } 2838 2839 } 2840 PT_UPDATES_FLUSH(); 2841 critical_exit(); 2842 if (*PMAP1) 2843 PT_SET_VA_MA(PMAP1, 0, TRUE); 2844 sched_unpin(); 2845 rw_wunlock(&pvh_global_lock); 2846 PMAP_UNLOCK(pmap); 2847 return (KERN_SUCCESS); 2848} 2849 2850/* 2851 * Maps a sequence of resident pages belonging to the same object. 2852 * The sequence begins with the given page m_start. This page is 2853 * mapped at the given virtual address start. Each subsequent page is 2854 * mapped at a virtual address that is offset from start by the same 2855 * amount as the page is offset from m_start within the object. The 2856 * last page in the sequence is the page with the largest offset from 2857 * m_start that can be mapped at a virtual address less than the given 2858 * virtual address end. Not every virtual page between start and end 2859 * is mapped; only those for which a resident page exists with the 2860 * corresponding offset from m_start are mapped. 2861 */ 2862void 2863pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 2864 vm_page_t m_start, vm_prot_t prot) 2865{ 2866 vm_page_t m, mpte; 2867 vm_pindex_t diff, psize; 2868 multicall_entry_t mcl[16]; 2869 multicall_entry_t *mclp = mcl; 2870 int error, count = 0; 2871 2872 VM_OBJECT_ASSERT_LOCKED(m_start->object); 2873 2874 psize = atop(end - start); 2875 mpte = NULL; 2876 m = m_start; 2877 rw_wlock(&pvh_global_lock); 2878 PMAP_LOCK(pmap); 2879 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 2880 mpte = pmap_enter_quick_locked(&mclp, &count, pmap, start + ptoa(diff), m, 2881 prot, mpte); 2882 m = TAILQ_NEXT(m, listq); 2883 if (count == 16) { 2884 error = HYPERVISOR_multicall(mcl, count); 2885 KASSERT(error == 0, ("bad multicall %d", error)); 2886 mclp = mcl; 2887 count = 0; 2888 } 2889 } 2890 if (count) { 2891 error = HYPERVISOR_multicall(mcl, count); 2892 KASSERT(error == 0, ("bad multicall %d", error)); 2893 } 2894 rw_wunlock(&pvh_global_lock); 2895 PMAP_UNLOCK(pmap); 2896} 2897 2898/* 2899 * this code makes some *MAJOR* assumptions: 2900 * 1. Current pmap & pmap exists. 2901 * 2. Not wired. 2902 * 3. Read access. 2903 * 4. No page table pages. 2904 * but is *MUCH* faster than pmap_enter... 2905 */ 2906 2907void 2908pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 2909{ 2910 multicall_entry_t mcl, *mclp; 2911 int count = 0; 2912 mclp = &mcl; 2913 2914 CTR4(KTR_PMAP, "pmap_enter_quick: pmap=%p va=0x%x m=%p prot=0x%x", 2915 pmap, va, m, prot); 2916 2917 rw_wlock(&pvh_global_lock); 2918 PMAP_LOCK(pmap); 2919 (void)pmap_enter_quick_locked(&mclp, &count, pmap, va, m, prot, NULL); 2920 if (count) 2921 HYPERVISOR_multicall(&mcl, count); 2922 rw_wunlock(&pvh_global_lock); 2923 PMAP_UNLOCK(pmap); 2924} 2925 2926#ifdef notyet 2927void 2928pmap_enter_quick_range(pmap_t pmap, vm_offset_t *addrs, vm_page_t *pages, vm_prot_t *prots, int count) 2929{ 2930 int i, error, index = 0; 2931 multicall_entry_t mcl[16]; 2932 multicall_entry_t *mclp = mcl; 2933 2934 PMAP_LOCK(pmap); 2935 for (i = 0; i < count; i++, addrs++, pages++, prots++) { 2936 if (!pmap_is_prefaultable_locked(pmap, *addrs)) 2937 continue; 2938 2939 (void) pmap_enter_quick_locked(&mclp, &index, pmap, *addrs, *pages, *prots, NULL); 2940 if (index == 16) { 2941 error = HYPERVISOR_multicall(mcl, index); 2942 mclp = mcl; 2943 index = 0; 2944 KASSERT(error == 0, ("bad multicall %d", error)); 2945 } 2946 } 2947 if (index) { 2948 error = HYPERVISOR_multicall(mcl, index); 2949 KASSERT(error == 0, ("bad multicall %d", error)); 2950 } 2951 2952 PMAP_UNLOCK(pmap); 2953} 2954#endif 2955 2956static vm_page_t 2957pmap_enter_quick_locked(multicall_entry_t **mclpp, int *count, pmap_t pmap, vm_offset_t va, vm_page_t m, 2958 vm_prot_t prot, vm_page_t mpte) 2959{ 2960 pt_entry_t *pte; 2961 vm_paddr_t pa; 2962 vm_page_t free; 2963 multicall_entry_t *mcl = *mclpp; 2964 2965 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 2966 (m->oflags & VPO_UNMANAGED) != 0, 2967 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 2968 rw_assert(&pvh_global_lock, RA_WLOCKED); 2969 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2970 2971 /* 2972 * In the case that a page table page is not 2973 * resident, we are creating it here. 2974 */ 2975 if (va < VM_MAXUSER_ADDRESS) { 2976 u_int ptepindex; 2977 pd_entry_t ptema; 2978 2979 /* 2980 * Calculate pagetable page index 2981 */ 2982 ptepindex = va >> PDRSHIFT; 2983 if (mpte && (mpte->pindex == ptepindex)) { 2984 mpte->wire_count++; 2985 } else { 2986 /* 2987 * Get the page directory entry 2988 */ 2989 ptema = pmap->pm_pdir[ptepindex]; 2990 2991 /* 2992 * If the page table page is mapped, we just increment 2993 * the hold count, and activate it. 2994 */ 2995 if (ptema & PG_V) { 2996 if (ptema & PG_PS) 2997 panic("pmap_enter_quick: unexpected mapping into 4MB page"); 2998 mpte = PHYS_TO_VM_PAGE(xpmap_mtop(ptema) & PG_FRAME); 2999 mpte->wire_count++; 3000 } else { 3001 mpte = _pmap_allocpte(pmap, ptepindex, 3002 PMAP_ENTER_NOSLEEP); 3003 if (mpte == NULL) 3004 return (mpte); 3005 } 3006 } 3007 } else { 3008 mpte = NULL; 3009 } 3010 3011 /* 3012 * This call to vtopte makes the assumption that we are 3013 * entering the page into the current pmap. In order to support 3014 * quick entry into any pmap, one would likely use pmap_pte_quick. 3015 * But that isn't as quick as vtopte. 3016 */ 3017 KASSERT(pmap_is_current(pmap), ("entering pages in non-current pmap")); 3018 pte = vtopte(va); 3019 if (*pte & PG_V) { 3020 if (mpte != NULL) { 3021 mpte->wire_count--; 3022 mpte = NULL; 3023 } 3024 return (mpte); 3025 } 3026 3027 /* 3028 * Enter on the PV list if part of our managed memory. 3029 */ 3030 if ((m->oflags & VPO_UNMANAGED) == 0 && 3031 !pmap_try_insert_pv_entry(pmap, va, m)) { 3032 if (mpte != NULL) { 3033 free = NULL; 3034 if (pmap_unwire_ptp(pmap, mpte, &free)) { 3035 pmap_invalidate_page(pmap, va); 3036 pmap_free_zero_pages(free); 3037 } 3038 3039 mpte = NULL; 3040 } 3041 return (mpte); 3042 } 3043 3044 /* 3045 * Increment counters 3046 */ 3047 pmap->pm_stats.resident_count++; 3048 3049 pa = VM_PAGE_TO_PHYS(m); 3050#ifdef PAE 3051 if ((prot & VM_PROT_EXECUTE) == 0) 3052 pa |= pg_nx; 3053#endif 3054 3055#if 0 3056 /* 3057 * Now validate mapping with RO protection 3058 */ 3059 if ((m->oflags & VPO_UNMANAGED) != 0) 3060 pte_store(pte, pa | PG_V | PG_U); 3061 else 3062 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED); 3063#else 3064 /* 3065 * Now validate mapping with RO protection 3066 */ 3067 if ((m->oflags & VPO_UNMANAGED) != 0) 3068 pa = xpmap_ptom(pa | PG_V | PG_U); 3069 else 3070 pa = xpmap_ptom(pa | PG_V | PG_U | PG_MANAGED); 3071 3072 mcl->op = __HYPERVISOR_update_va_mapping; 3073 mcl->args[0] = va; 3074 mcl->args[1] = (uint32_t)(pa & 0xffffffff); 3075 mcl->args[2] = (uint32_t)(pa >> 32); 3076 mcl->args[3] = 0; 3077 *mclpp = mcl + 1; 3078 *count = *count + 1; 3079#endif 3080 return (mpte); 3081} 3082 3083/* 3084 * Make a temporary mapping for a physical address. This is only intended 3085 * to be used for panic dumps. 3086 */ 3087void * 3088pmap_kenter_temporary(vm_paddr_t pa, int i) 3089{ 3090 vm_offset_t va; 3091 vm_paddr_t ma = xpmap_ptom(pa); 3092 3093 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE); 3094 PT_SET_MA(va, (ma & ~PAGE_MASK) | PG_V | pgeflag); 3095 invlpg(va); 3096 return ((void *)crashdumpmap); 3097} 3098 3099/* 3100 * This code maps large physical mmap regions into the 3101 * processor address space. Note that some shortcuts 3102 * are taken, but the code works. 3103 */ 3104void 3105pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object, 3106 vm_pindex_t pindex, vm_size_t size) 3107{ 3108 pd_entry_t *pde; 3109 vm_paddr_t pa, ptepa; 3110 vm_page_t p; 3111 int pat_mode; 3112 3113 VM_OBJECT_ASSERT_WLOCKED(object); 3114 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 3115 ("pmap_object_init_pt: non-device object")); 3116 if (pseflag && 3117 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) { 3118 if (!vm_object_populate(object, pindex, pindex + atop(size))) 3119 return; 3120 p = vm_page_lookup(object, pindex); 3121 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3122 ("pmap_object_init_pt: invalid page %p", p)); 3123 pat_mode = p->md.pat_mode; 3124 3125 /* 3126 * Abort the mapping if the first page is not physically 3127 * aligned to a 2/4MB page boundary. 3128 */ 3129 ptepa = VM_PAGE_TO_PHYS(p); 3130 if (ptepa & (NBPDR - 1)) 3131 return; 3132 3133 /* 3134 * Skip the first page. Abort the mapping if the rest of 3135 * the pages are not physically contiguous or have differing 3136 * memory attributes. 3137 */ 3138 p = TAILQ_NEXT(p, listq); 3139 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size; 3140 pa += PAGE_SIZE) { 3141 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3142 ("pmap_object_init_pt: invalid page %p", p)); 3143 if (pa != VM_PAGE_TO_PHYS(p) || 3144 pat_mode != p->md.pat_mode) 3145 return; 3146 p = TAILQ_NEXT(p, listq); 3147 } 3148 3149 /* 3150 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and 3151 * "size" is a multiple of 2/4M, adding the PAT setting to 3152 * "pa" will not affect the termination of this loop. 3153 */ 3154 PMAP_LOCK(pmap); 3155 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa + 3156 size; pa += NBPDR) { 3157 pde = pmap_pde(pmap, addr); 3158 if (*pde == 0) { 3159 pde_store(pde, pa | PG_PS | PG_M | PG_A | 3160 PG_U | PG_RW | PG_V); 3161 pmap->pm_stats.resident_count += NBPDR / 3162 PAGE_SIZE; 3163 pmap_pde_mappings++; 3164 } 3165 /* Else continue on if the PDE is already valid. */ 3166 addr += NBPDR; 3167 } 3168 PMAP_UNLOCK(pmap); 3169 } 3170} 3171 3172/* 3173 * Routine: pmap_change_wiring 3174 * Function: Change the wiring attribute for a map/virtual-address 3175 * pair. 3176 * In/out conditions: 3177 * The mapping must already exist in the pmap. 3178 */ 3179void 3180pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 3181{ 3182 pt_entry_t *pte; 3183 3184 rw_wlock(&pvh_global_lock); 3185 PMAP_LOCK(pmap); 3186 pte = pmap_pte(pmap, va); 3187 3188 if (wired && !pmap_pte_w(pte)) { 3189 PT_SET_VA_MA((pte), *(pte) | PG_W, TRUE); 3190 pmap->pm_stats.wired_count++; 3191 } else if (!wired && pmap_pte_w(pte)) { 3192 PT_SET_VA_MA((pte), *(pte) & ~PG_W, TRUE); 3193 pmap->pm_stats.wired_count--; 3194 } 3195 3196 /* 3197 * Wiring is not a hardware characteristic so there is no need to 3198 * invalidate TLB. 3199 */ 3200 pmap_pte_release(pte); 3201 PMAP_UNLOCK(pmap); 3202 rw_wunlock(&pvh_global_lock); 3203} 3204 3205 3206 3207/* 3208 * Copy the range specified by src_addr/len 3209 * from the source map to the range dst_addr/len 3210 * in the destination map. 3211 * 3212 * This routine is only advisory and need not do anything. 3213 */ 3214 3215void 3216pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len, 3217 vm_offset_t src_addr) 3218{ 3219 vm_page_t free; 3220 vm_offset_t addr; 3221 vm_offset_t end_addr = src_addr + len; 3222 vm_offset_t pdnxt; 3223 3224 if (dst_addr != src_addr) 3225 return; 3226 3227 if (!pmap_is_current(src_pmap)) { 3228 CTR2(KTR_PMAP, 3229 "pmap_copy, skipping: pdir[PTDPTDI]=0x%jx PTDpde[0]=0x%jx", 3230 (src_pmap->pm_pdir[PTDPTDI] & PG_FRAME), (PTDpde[0] & PG_FRAME)); 3231 3232 return; 3233 } 3234 CTR5(KTR_PMAP, "pmap_copy: dst_pmap=%p src_pmap=%p dst_addr=0x%x len=%d src_addr=0x%x", 3235 dst_pmap, src_pmap, dst_addr, len, src_addr); 3236 3237#ifdef HAMFISTED_LOCKING 3238 mtx_lock(&createdelete_lock); 3239#endif 3240 3241 rw_wlock(&pvh_global_lock); 3242 if (dst_pmap < src_pmap) { 3243 PMAP_LOCK(dst_pmap); 3244 PMAP_LOCK(src_pmap); 3245 } else { 3246 PMAP_LOCK(src_pmap); 3247 PMAP_LOCK(dst_pmap); 3248 } 3249 sched_pin(); 3250 for (addr = src_addr; addr < end_addr; addr = pdnxt) { 3251 pt_entry_t *src_pte, *dst_pte; 3252 vm_page_t dstmpte, srcmpte; 3253 pd_entry_t srcptepaddr; 3254 u_int ptepindex; 3255 3256 KASSERT(addr < UPT_MIN_ADDRESS, 3257 ("pmap_copy: invalid to pmap_copy page tables")); 3258 3259 pdnxt = (addr + NBPDR) & ~PDRMASK; 3260 if (pdnxt < addr) 3261 pdnxt = end_addr; 3262 ptepindex = addr >> PDRSHIFT; 3263 3264 srcptepaddr = PT_GET(&src_pmap->pm_pdir[ptepindex]); 3265 if (srcptepaddr == 0) 3266 continue; 3267 3268 if (srcptepaddr & PG_PS) { 3269 if (dst_pmap->pm_pdir[ptepindex] == 0) { 3270 PD_SET_VA(dst_pmap, ptepindex, srcptepaddr & ~PG_W, TRUE); 3271 dst_pmap->pm_stats.resident_count += 3272 NBPDR / PAGE_SIZE; 3273 } 3274 continue; 3275 } 3276 3277 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME); 3278 KASSERT(srcmpte->wire_count > 0, 3279 ("pmap_copy: source page table page is unused")); 3280 3281 if (pdnxt > end_addr) 3282 pdnxt = end_addr; 3283 3284 src_pte = vtopte(addr); 3285 while (addr < pdnxt) { 3286 pt_entry_t ptetemp; 3287 ptetemp = *src_pte; 3288 /* 3289 * we only virtual copy managed pages 3290 */ 3291 if ((ptetemp & PG_MANAGED) != 0) { 3292 dstmpte = pmap_allocpte(dst_pmap, addr, 3293 PMAP_ENTER_NOSLEEP); 3294 if (dstmpte == NULL) 3295 goto out; 3296 dst_pte = pmap_pte_quick(dst_pmap, addr); 3297 if (*dst_pte == 0 && 3298 pmap_try_insert_pv_entry(dst_pmap, addr, 3299 PHYS_TO_VM_PAGE(xpmap_mtop(ptetemp) & PG_FRAME))) { 3300 /* 3301 * Clear the wired, modified, and 3302 * accessed (referenced) bits 3303 * during the copy. 3304 */ 3305 KASSERT(ptetemp != 0, ("src_pte not set")); 3306 PT_SET_VA_MA(dst_pte, ptetemp & ~(PG_W | PG_M | PG_A), TRUE /* XXX debug */); 3307 KASSERT(*dst_pte == (ptetemp & ~(PG_W | PG_M | PG_A)), 3308 ("no pmap copy expected: 0x%jx saw: 0x%jx", 3309 ptetemp & ~(PG_W | PG_M | PG_A), *dst_pte)); 3310 dst_pmap->pm_stats.resident_count++; 3311 } else { 3312 free = NULL; 3313 if (pmap_unwire_ptp(dst_pmap, dstmpte, 3314 &free)) { 3315 pmap_invalidate_page(dst_pmap, 3316 addr); 3317 pmap_free_zero_pages(free); 3318 } 3319 goto out; 3320 } 3321 if (dstmpte->wire_count >= srcmpte->wire_count) 3322 break; 3323 } 3324 addr += PAGE_SIZE; 3325 src_pte++; 3326 } 3327 } 3328out: 3329 PT_UPDATES_FLUSH(); 3330 sched_unpin(); 3331 rw_wunlock(&pvh_global_lock); 3332 PMAP_UNLOCK(src_pmap); 3333 PMAP_UNLOCK(dst_pmap); 3334 3335#ifdef HAMFISTED_LOCKING 3336 mtx_unlock(&createdelete_lock); 3337#endif 3338} 3339 3340static __inline void 3341pagezero(void *page) 3342{ 3343#if defined(I686_CPU) 3344 if (cpu_class == CPUCLASS_686) { 3345#if defined(CPU_ENABLE_SSE) 3346 if (cpu_feature & CPUID_SSE2) 3347 sse2_pagezero(page); 3348 else 3349#endif 3350 i686_pagezero(page); 3351 } else 3352#endif 3353 bzero(page, PAGE_SIZE); 3354} 3355 3356/* 3357 * pmap_zero_page zeros the specified hardware page by mapping 3358 * the page into KVM and using bzero to clear its contents. 3359 */ 3360void 3361pmap_zero_page(vm_page_t m) 3362{ 3363 struct sysmaps *sysmaps; 3364 3365 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3366 mtx_lock(&sysmaps->lock); 3367 if (*sysmaps->CMAP2) 3368 panic("pmap_zero_page: CMAP2 busy"); 3369 sched_pin(); 3370 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3371 pagezero(sysmaps->CADDR2); 3372 PT_SET_MA(sysmaps->CADDR2, 0); 3373 sched_unpin(); 3374 mtx_unlock(&sysmaps->lock); 3375} 3376 3377/* 3378 * pmap_zero_page_area zeros the specified hardware page by mapping 3379 * the page into KVM and using bzero to clear its contents. 3380 * 3381 * off and size may not cover an area beyond a single hardware page. 3382 */ 3383void 3384pmap_zero_page_area(vm_page_t m, int off, int size) 3385{ 3386 struct sysmaps *sysmaps; 3387 3388 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3389 mtx_lock(&sysmaps->lock); 3390 if (*sysmaps->CMAP2) 3391 panic("pmap_zero_page_area: CMAP2 busy"); 3392 sched_pin(); 3393 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3394 3395 if (off == 0 && size == PAGE_SIZE) 3396 pagezero(sysmaps->CADDR2); 3397 else 3398 bzero((char *)sysmaps->CADDR2 + off, size); 3399 PT_SET_MA(sysmaps->CADDR2, 0); 3400 sched_unpin(); 3401 mtx_unlock(&sysmaps->lock); 3402} 3403 3404/* 3405 * pmap_zero_page_idle zeros the specified hardware page by mapping 3406 * the page into KVM and using bzero to clear its contents. This 3407 * is intended to be called from the vm_pagezero process only and 3408 * outside of Giant. 3409 */ 3410void 3411pmap_zero_page_idle(vm_page_t m) 3412{ 3413 3414 if (*CMAP3) 3415 panic("pmap_zero_page_idle: CMAP3 busy"); 3416 sched_pin(); 3417 PT_SET_MA(CADDR3, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3418 pagezero(CADDR3); 3419 PT_SET_MA(CADDR3, 0); 3420 sched_unpin(); 3421} 3422 3423/* 3424 * pmap_copy_page copies the specified (machine independent) 3425 * page by mapping the page into virtual memory and using 3426 * bcopy to copy the page, one machine dependent page at a 3427 * time. 3428 */ 3429void 3430pmap_copy_page(vm_page_t src, vm_page_t dst) 3431{ 3432 struct sysmaps *sysmaps; 3433 3434 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3435 mtx_lock(&sysmaps->lock); 3436 if (*sysmaps->CMAP1) 3437 panic("pmap_copy_page: CMAP1 busy"); 3438 if (*sysmaps->CMAP2) 3439 panic("pmap_copy_page: CMAP2 busy"); 3440 sched_pin(); 3441 PT_SET_MA(sysmaps->CADDR1, PG_V | VM_PAGE_TO_MACH(src) | PG_A); 3442 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(dst) | PG_A | PG_M); 3443 bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE); 3444 PT_SET_MA(sysmaps->CADDR1, 0); 3445 PT_SET_MA(sysmaps->CADDR2, 0); 3446 sched_unpin(); 3447 mtx_unlock(&sysmaps->lock); 3448} 3449 3450int unmapped_buf_allowed = 1; 3451 3452void 3453pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[], 3454 vm_offset_t b_offset, int xfersize) 3455{ 3456 struct sysmaps *sysmaps; 3457 vm_page_t a_pg, b_pg; 3458 char *a_cp, *b_cp; 3459 vm_offset_t a_pg_offset, b_pg_offset; 3460 int cnt; 3461 3462 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3463 mtx_lock(&sysmaps->lock); 3464 if (*sysmaps->CMAP1 != 0) 3465 panic("pmap_copy_pages: CMAP1 busy"); 3466 if (*sysmaps->CMAP2 != 0) 3467 panic("pmap_copy_pages: CMAP2 busy"); 3468 sched_pin(); 3469 while (xfersize > 0) { 3470 a_pg = ma[a_offset >> PAGE_SHIFT]; 3471 a_pg_offset = a_offset & PAGE_MASK; 3472 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 3473 b_pg = mb[b_offset >> PAGE_SHIFT]; 3474 b_pg_offset = b_offset & PAGE_MASK; 3475 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 3476 PT_SET_MA(sysmaps->CADDR1, PG_V | VM_PAGE_TO_MACH(a_pg) | PG_A); 3477 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | 3478 VM_PAGE_TO_MACH(b_pg) | PG_A | PG_M); 3479 a_cp = sysmaps->CADDR1 + a_pg_offset; 3480 b_cp = sysmaps->CADDR2 + b_pg_offset; 3481 bcopy(a_cp, b_cp, cnt); 3482 a_offset += cnt; 3483 b_offset += cnt; 3484 xfersize -= cnt; 3485 } 3486 PT_SET_MA(sysmaps->CADDR1, 0); 3487 PT_SET_MA(sysmaps->CADDR2, 0); 3488 sched_unpin(); 3489 mtx_unlock(&sysmaps->lock); 3490} 3491 3492/* 3493 * Returns true if the pmap's pv is one of the first 3494 * 16 pvs linked to from this page. This count may 3495 * be changed upwards or downwards in the future; it 3496 * is only necessary that true be returned for a small 3497 * subset of pmaps for proper page aging. 3498 */ 3499boolean_t 3500pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 3501{ 3502 pv_entry_t pv; 3503 int loops = 0; 3504 boolean_t rv; 3505 3506 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3507 ("pmap_page_exists_quick: page %p is not managed", m)); 3508 rv = FALSE; 3509 rw_wlock(&pvh_global_lock); 3510 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 3511 if (PV_PMAP(pv) == pmap) { 3512 rv = TRUE; 3513 break; 3514 } 3515 loops++; 3516 if (loops >= 16) 3517 break; 3518 } 3519 rw_wunlock(&pvh_global_lock); 3520 return (rv); 3521} 3522 3523/* 3524 * pmap_page_wired_mappings: 3525 * 3526 * Return the number of managed mappings to the given physical page 3527 * that are wired. 3528 */ 3529int 3530pmap_page_wired_mappings(vm_page_t m) 3531{ 3532 pv_entry_t pv; 3533 pt_entry_t *pte; 3534 pmap_t pmap; 3535 int count; 3536 3537 count = 0; 3538 if ((m->oflags & VPO_UNMANAGED) != 0) 3539 return (count); 3540 rw_wlock(&pvh_global_lock); 3541 sched_pin(); 3542 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 3543 pmap = PV_PMAP(pv); 3544 PMAP_LOCK(pmap); 3545 pte = pmap_pte_quick(pmap, pv->pv_va); 3546 if ((*pte & PG_W) != 0) 3547 count++; 3548 PMAP_UNLOCK(pmap); 3549 } 3550 sched_unpin(); 3551 rw_wunlock(&pvh_global_lock); 3552 return (count); 3553} 3554 3555/* 3556 * Returns TRUE if the given page is mapped. Otherwise, returns FALSE. 3557 */ 3558boolean_t 3559pmap_page_is_mapped(vm_page_t m) 3560{ 3561 3562 if ((m->oflags & VPO_UNMANAGED) != 0) 3563 return (FALSE); 3564 return (!TAILQ_EMPTY(&m->md.pv_list)); 3565} 3566 3567/* 3568 * Remove all pages from specified address space 3569 * this aids process exit speeds. Also, this code 3570 * is special cased for current process only, but 3571 * can have the more generic (and slightly slower) 3572 * mode enabled. This is much faster than pmap_remove 3573 * in the case of running down an entire address space. 3574 */ 3575void 3576pmap_remove_pages(pmap_t pmap) 3577{ 3578 pt_entry_t *pte, tpte; 3579 vm_page_t m, free = NULL; 3580 pv_entry_t pv; 3581 struct pv_chunk *pc, *npc; 3582 int field, idx; 3583 int32_t bit; 3584 uint32_t inuse, bitmask; 3585 int allfree; 3586 3587 CTR1(KTR_PMAP, "pmap_remove_pages: pmap=%p", pmap); 3588 3589 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) { 3590 printf("warning: pmap_remove_pages called with non-current pmap\n"); 3591 return; 3592 } 3593 rw_wlock(&pvh_global_lock); 3594 KASSERT(pmap_is_current(pmap), ("removing pages from non-current pmap")); 3595 PMAP_LOCK(pmap); 3596 sched_pin(); 3597 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 3598 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap, 3599 pc->pc_pmap)); 3600 allfree = 1; 3601 for (field = 0; field < _NPCM; field++) { 3602 inuse = ~pc->pc_map[field] & pc_freemask[field]; 3603 while (inuse != 0) { 3604 bit = bsfl(inuse); 3605 bitmask = 1UL << bit; 3606 idx = field * 32 + bit; 3607 pv = &pc->pc_pventry[idx]; 3608 inuse &= ~bitmask; 3609 3610 pte = vtopte(pv->pv_va); 3611 tpte = *pte ? xpmap_mtop(*pte) : 0; 3612 3613 if (tpte == 0) { 3614 printf( 3615 "TPTE at %p IS ZERO @ VA %08x\n", 3616 pte, pv->pv_va); 3617 panic("bad pte"); 3618 } 3619 3620/* 3621 * We cannot remove wired pages from a process' mapping at this time 3622 */ 3623 if (tpte & PG_W) { 3624 allfree = 0; 3625 continue; 3626 } 3627 3628 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 3629 KASSERT(m->phys_addr == (tpte & PG_FRAME), 3630 ("vm_page_t %p phys_addr mismatch %016jx %016jx", 3631 m, (uintmax_t)m->phys_addr, 3632 (uintmax_t)tpte)); 3633 3634 KASSERT(m < &vm_page_array[vm_page_array_size], 3635 ("pmap_remove_pages: bad tpte %#jx", 3636 (uintmax_t)tpte)); 3637 3638 3639 PT_CLEAR_VA(pte, FALSE); 3640 3641 /* 3642 * Update the vm_page_t clean/reference bits. 3643 */ 3644 if (tpte & PG_M) 3645 vm_page_dirty(m); 3646 3647 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 3648 if (TAILQ_EMPTY(&m->md.pv_list)) 3649 vm_page_aflag_clear(m, PGA_WRITEABLE); 3650 3651 pmap_unuse_pt(pmap, pv->pv_va, &free); 3652 3653 /* Mark free */ 3654 PV_STAT(pv_entry_frees++); 3655 PV_STAT(pv_entry_spare++); 3656 pv_entry_count--; 3657 pc->pc_map[field] |= bitmask; 3658 pmap->pm_stats.resident_count--; 3659 } 3660 } 3661 PT_UPDATES_FLUSH(); 3662 if (allfree) { 3663 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 3664 free_pv_chunk(pc); 3665 } 3666 } 3667 PT_UPDATES_FLUSH(); 3668 if (*PMAP1) 3669 PT_SET_MA(PADDR1, 0); 3670 3671 sched_unpin(); 3672 pmap_invalidate_all(pmap); 3673 rw_wunlock(&pvh_global_lock); 3674 PMAP_UNLOCK(pmap); 3675 pmap_free_zero_pages(free); 3676} 3677 3678/* 3679 * pmap_is_modified: 3680 * 3681 * Return whether or not the specified physical page was modified 3682 * in any physical maps. 3683 */ 3684boolean_t 3685pmap_is_modified(vm_page_t m) 3686{ 3687 pv_entry_t pv; 3688 pt_entry_t *pte; 3689 pmap_t pmap; 3690 boolean_t rv; 3691 3692 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3693 ("pmap_is_modified: page %p is not managed", m)); 3694 rv = FALSE; 3695 3696 /* 3697 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 3698 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 3699 * is clear, no PTEs can have PG_M set. 3700 */ 3701 VM_OBJECT_ASSERT_WLOCKED(m->object); 3702 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 3703 return (rv); 3704 rw_wlock(&pvh_global_lock); 3705 sched_pin(); 3706 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 3707 pmap = PV_PMAP(pv); 3708 PMAP_LOCK(pmap); 3709 pte = pmap_pte_quick(pmap, pv->pv_va); 3710 rv = (*pte & PG_M) != 0; 3711 PMAP_UNLOCK(pmap); 3712 if (rv) 3713 break; 3714 } 3715 if (*PMAP1) 3716 PT_SET_MA(PADDR1, 0); 3717 sched_unpin(); 3718 rw_wunlock(&pvh_global_lock); 3719 return (rv); 3720} 3721 3722/* 3723 * pmap_is_prefaultable: 3724 * 3725 * Return whether or not the specified virtual address is elgible 3726 * for prefault. 3727 */ 3728static boolean_t 3729pmap_is_prefaultable_locked(pmap_t pmap, vm_offset_t addr) 3730{ 3731 pt_entry_t *pte; 3732 boolean_t rv = FALSE; 3733 3734 return (rv); 3735 3736 if (pmap_is_current(pmap) && *pmap_pde(pmap, addr)) { 3737 pte = vtopte(addr); 3738 rv = (*pte == 0); 3739 } 3740 return (rv); 3741} 3742 3743boolean_t 3744pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 3745{ 3746 boolean_t rv; 3747 3748 PMAP_LOCK(pmap); 3749 rv = pmap_is_prefaultable_locked(pmap, addr); 3750 PMAP_UNLOCK(pmap); 3751 return (rv); 3752} 3753 3754boolean_t 3755pmap_is_referenced(vm_page_t m) 3756{ 3757 pv_entry_t pv; 3758 pt_entry_t *pte; 3759 pmap_t pmap; 3760 boolean_t rv; 3761 3762 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3763 ("pmap_is_referenced: page %p is not managed", m)); 3764 rv = FALSE; 3765 rw_wlock(&pvh_global_lock); 3766 sched_pin(); 3767 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 3768 pmap = PV_PMAP(pv); 3769 PMAP_LOCK(pmap); 3770 pte = pmap_pte_quick(pmap, pv->pv_va); 3771 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V); 3772 PMAP_UNLOCK(pmap); 3773 if (rv) 3774 break; 3775 } 3776 if (*PMAP1) 3777 PT_SET_MA(PADDR1, 0); 3778 sched_unpin(); 3779 rw_wunlock(&pvh_global_lock); 3780 return (rv); 3781} 3782 3783void 3784pmap_map_readonly(pmap_t pmap, vm_offset_t va, int len) 3785{ 3786 int i, npages = round_page(len) >> PAGE_SHIFT; 3787 for (i = 0; i < npages; i++) { 3788 pt_entry_t *pte; 3789 pte = pmap_pte(pmap, (vm_offset_t)(va + i*PAGE_SIZE)); 3790 rw_wlock(&pvh_global_lock); 3791 pte_store(pte, xpmap_mtop(*pte & ~(PG_RW|PG_M))); 3792 rw_wunlock(&pvh_global_lock); 3793 PMAP_MARK_PRIV(xpmap_mtop(*pte)); 3794 pmap_pte_release(pte); 3795 } 3796} 3797 3798void 3799pmap_map_readwrite(pmap_t pmap, vm_offset_t va, int len) 3800{ 3801 int i, npages = round_page(len) >> PAGE_SHIFT; 3802 for (i = 0; i < npages; i++) { 3803 pt_entry_t *pte; 3804 pte = pmap_pte(pmap, (vm_offset_t)(va + i*PAGE_SIZE)); 3805 PMAP_MARK_UNPRIV(xpmap_mtop(*pte)); 3806 rw_wlock(&pvh_global_lock); 3807 pte_store(pte, xpmap_mtop(*pte) | (PG_RW|PG_M)); 3808 rw_wunlock(&pvh_global_lock); 3809 pmap_pte_release(pte); 3810 } 3811} 3812 3813/* 3814 * Clear the write and modified bits in each of the given page's mappings. 3815 */ 3816void 3817pmap_remove_write(vm_page_t m) 3818{ 3819 pv_entry_t pv; 3820 pmap_t pmap; 3821 pt_entry_t oldpte, *pte; 3822 3823 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3824 ("pmap_remove_write: page %p is not managed", m)); 3825 3826 /* 3827 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 3828 * set by another thread while the object is locked. Thus, 3829 * if PGA_WRITEABLE is clear, no page table entries need updating. 3830 */ 3831 VM_OBJECT_ASSERT_WLOCKED(m->object); 3832 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 3833 return; 3834 rw_wlock(&pvh_global_lock); 3835 sched_pin(); 3836 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 3837 pmap = PV_PMAP(pv); 3838 PMAP_LOCK(pmap); 3839 pte = pmap_pte_quick(pmap, pv->pv_va); 3840retry: 3841 oldpte = *pte; 3842 if ((oldpte & PG_RW) != 0) { 3843 vm_paddr_t newpte = oldpte & ~(PG_RW | PG_M); 3844 3845 /* 3846 * Regardless of whether a pte is 32 or 64 bits 3847 * in size, PG_RW and PG_M are among the least 3848 * significant 32 bits. 3849 */ 3850 PT_SET_VA_MA(pte, newpte, TRUE); 3851 if (*pte != newpte) 3852 goto retry; 3853 3854 if ((oldpte & PG_M) != 0) 3855 vm_page_dirty(m); 3856 pmap_invalidate_page(pmap, pv->pv_va); 3857 } 3858 PMAP_UNLOCK(pmap); 3859 } 3860 vm_page_aflag_clear(m, PGA_WRITEABLE); 3861 PT_UPDATES_FLUSH(); 3862 if (*PMAP1) 3863 PT_SET_MA(PADDR1, 0); 3864 sched_unpin(); 3865 rw_wunlock(&pvh_global_lock); 3866} 3867 3868/* 3869 * pmap_ts_referenced: 3870 * 3871 * Return a count of reference bits for a page, clearing those bits. 3872 * It is not necessary for every reference bit to be cleared, but it 3873 * is necessary that 0 only be returned when there are truly no 3874 * reference bits set. 3875 * 3876 * XXX: The exact number of bits to check and clear is a matter that 3877 * should be tested and standardized at some point in the future for 3878 * optimal aging of shared pages. 3879 */ 3880int 3881pmap_ts_referenced(vm_page_t m) 3882{ 3883 pv_entry_t pv, pvf, pvn; 3884 pmap_t pmap; 3885 pt_entry_t *pte; 3886 int rtval = 0; 3887 3888 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3889 ("pmap_ts_referenced: page %p is not managed", m)); 3890 rw_wlock(&pvh_global_lock); 3891 sched_pin(); 3892 if ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 3893 pvf = pv; 3894 do { 3895 pvn = TAILQ_NEXT(pv, pv_next); 3896 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 3897 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 3898 pmap = PV_PMAP(pv); 3899 PMAP_LOCK(pmap); 3900 pte = pmap_pte_quick(pmap, pv->pv_va); 3901 if ((*pte & PG_A) != 0) { 3902 PT_SET_VA_MA(pte, *pte & ~PG_A, FALSE); 3903 pmap_invalidate_page(pmap, pv->pv_va); 3904 rtval++; 3905 if (rtval > 4) 3906 pvn = NULL; 3907 } 3908 PMAP_UNLOCK(pmap); 3909 } while ((pv = pvn) != NULL && pv != pvf); 3910 } 3911 PT_UPDATES_FLUSH(); 3912 if (*PMAP1) 3913 PT_SET_MA(PADDR1, 0); 3914 sched_unpin(); 3915 rw_wunlock(&pvh_global_lock); 3916 return (rtval); 3917} 3918 3919/* 3920 * Apply the given advice to the specified range of addresses within the 3921 * given pmap. Depending on the advice, clear the referenced and/or 3922 * modified flags in each mapping and set the mapped page's dirty field. 3923 */ 3924void 3925pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice) 3926{ 3927 pd_entry_t oldpde; 3928 pt_entry_t *pte; 3929 vm_offset_t pdnxt; 3930 vm_page_t m; 3931 boolean_t anychanged; 3932 3933 if (advice != MADV_DONTNEED && advice != MADV_FREE) 3934 return; 3935 anychanged = FALSE; 3936 rw_wlock(&pvh_global_lock); 3937 sched_pin(); 3938 PMAP_LOCK(pmap); 3939 for (; sva < eva; sva = pdnxt) { 3940 pdnxt = (sva + NBPDR) & ~PDRMASK; 3941 if (pdnxt < sva) 3942 pdnxt = eva; 3943 oldpde = pmap->pm_pdir[sva >> PDRSHIFT]; 3944 if ((oldpde & (PG_PS | PG_V)) != PG_V) 3945 continue; 3946 if (pdnxt > eva) 3947 pdnxt = eva; 3948 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 3949 sva += PAGE_SIZE) { 3950 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | 3951 PG_V)) 3952 continue; 3953 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 3954 if (advice == MADV_DONTNEED) { 3955 /* 3956 * Future calls to pmap_is_modified() 3957 * can be avoided by making the page 3958 * dirty now. 3959 */ 3960 m = PHYS_TO_VM_PAGE(xpmap_mtop(*pte) & 3961 PG_FRAME); 3962 vm_page_dirty(m); 3963 } 3964 PT_SET_VA_MA(pte, *pte & ~(PG_M | PG_A), TRUE); 3965 } else if ((*pte & PG_A) != 0) 3966 PT_SET_VA_MA(pte, *pte & ~PG_A, TRUE); 3967 else 3968 continue; 3969 if ((*pte & PG_G) != 0) 3970 pmap_invalidate_page(pmap, sva); 3971 else 3972 anychanged = TRUE; 3973 } 3974 } 3975 PT_UPDATES_FLUSH(); 3976 if (*PMAP1) 3977 PT_SET_VA_MA(PMAP1, 0, TRUE); 3978 if (anychanged) 3979 pmap_invalidate_all(pmap); 3980 sched_unpin(); 3981 rw_wunlock(&pvh_global_lock); 3982 PMAP_UNLOCK(pmap); 3983} 3984 3985/* 3986 * Clear the modify bits on the specified physical page. 3987 */ 3988void 3989pmap_clear_modify(vm_page_t m) 3990{ 3991 pv_entry_t pv; 3992 pmap_t pmap; 3993 pt_entry_t *pte; 3994 3995 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3996 ("pmap_clear_modify: page %p is not managed", m)); 3997 VM_OBJECT_ASSERT_WLOCKED(m->object); 3998 KASSERT(!vm_page_xbusied(m), 3999 ("pmap_clear_modify: page %p is exclusive busied", m)); 4000 4001 /* 4002 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set. 4003 * If the object containing the page is locked and the page is not 4004 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 4005 */ 4006 if ((m->aflags & PGA_WRITEABLE) == 0) 4007 return; 4008 rw_wlock(&pvh_global_lock); 4009 sched_pin(); 4010 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 4011 pmap = PV_PMAP(pv); 4012 PMAP_LOCK(pmap); 4013 pte = pmap_pte_quick(pmap, pv->pv_va); 4014 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 4015 /* 4016 * Regardless of whether a pte is 32 or 64 bits 4017 * in size, PG_M is among the least significant 4018 * 32 bits. 4019 */ 4020 PT_SET_VA_MA(pte, *pte & ~PG_M, FALSE); 4021 pmap_invalidate_page(pmap, pv->pv_va); 4022 } 4023 PMAP_UNLOCK(pmap); 4024 } 4025 sched_unpin(); 4026 rw_wunlock(&pvh_global_lock); 4027} 4028 4029/* 4030 * Miscellaneous support routines follow 4031 */ 4032 4033/* 4034 * Map a set of physical memory pages into the kernel virtual 4035 * address space. Return a pointer to where it is mapped. This 4036 * routine is intended to be used for mapping device memory, 4037 * NOT real memory. 4038 */ 4039void * 4040pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode) 4041{ 4042 vm_offset_t va, offset; 4043 vm_size_t tmpsize; 4044 4045 offset = pa & PAGE_MASK; 4046 size = round_page(offset + size); 4047 pa = pa & PG_FRAME; 4048 4049 if (pa < KERNLOAD && pa + size <= KERNLOAD) 4050 va = KERNBASE + pa; 4051 else 4052 va = kva_alloc(size); 4053 if (!va) 4054 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 4055 4056 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE) 4057 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode); 4058 pmap_invalidate_range(kernel_pmap, va, va + tmpsize); 4059 pmap_invalidate_cache_range(va, va + size); 4060 return ((void *)(va + offset)); 4061} 4062 4063void * 4064pmap_mapdev(vm_paddr_t pa, vm_size_t size) 4065{ 4066 4067 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE)); 4068} 4069 4070void * 4071pmap_mapbios(vm_paddr_t pa, vm_size_t size) 4072{ 4073 4074 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK)); 4075} 4076 4077void 4078pmap_unmapdev(vm_offset_t va, vm_size_t size) 4079{ 4080 vm_offset_t base, offset; 4081 4082 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD) 4083 return; 4084 base = trunc_page(va); 4085 offset = va & PAGE_MASK; 4086 size = round_page(offset + size); 4087 kva_free(base, size); 4088} 4089 4090/* 4091 * Sets the memory attribute for the specified page. 4092 */ 4093void 4094pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma) 4095{ 4096 4097 m->md.pat_mode = ma; 4098 if ((m->flags & PG_FICTITIOUS) != 0) 4099 return; 4100 4101 /* 4102 * If "m" is a normal page, flush it from the cache. 4103 * See pmap_invalidate_cache_range(). 4104 * 4105 * First, try to find an existing mapping of the page by sf 4106 * buffer. sf_buf_invalidate_cache() modifies mapping and 4107 * flushes the cache. 4108 */ 4109 if (sf_buf_invalidate_cache(m)) 4110 return; 4111 4112 /* 4113 * If page is not mapped by sf buffer, but CPU does not 4114 * support self snoop, map the page transient and do 4115 * invalidation. In the worst case, whole cache is flushed by 4116 * pmap_invalidate_cache_range(). 4117 */ 4118 if ((cpu_feature & CPUID_SS) == 0) 4119 pmap_flush_page(m); 4120} 4121 4122static void 4123pmap_flush_page(vm_page_t m) 4124{ 4125 struct sysmaps *sysmaps; 4126 vm_offset_t sva, eva; 4127 4128 if ((cpu_feature & CPUID_CLFSH) != 0) { 4129 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 4130 mtx_lock(&sysmaps->lock); 4131 if (*sysmaps->CMAP2) 4132 panic("pmap_flush_page: CMAP2 busy"); 4133 sched_pin(); 4134 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | 4135 VM_PAGE_TO_MACH(m) | PG_A | PG_M | 4136 pmap_cache_bits(m->md.pat_mode, 0)); 4137 invlcaddr(sysmaps->CADDR2); 4138 sva = (vm_offset_t)sysmaps->CADDR2; 4139 eva = sva + PAGE_SIZE; 4140 4141 /* 4142 * Use mfence despite the ordering implied by 4143 * mtx_{un,}lock() because clflush is not guaranteed 4144 * to be ordered by any other instruction. 4145 */ 4146 mfence(); 4147 for (; sva < eva; sva += cpu_clflush_line_size) 4148 clflush(sva); 4149 mfence(); 4150 PT_SET_MA(sysmaps->CADDR2, 0); 4151 sched_unpin(); 4152 mtx_unlock(&sysmaps->lock); 4153 } else 4154 pmap_invalidate_cache(); 4155} 4156 4157/* 4158 * Changes the specified virtual address range's memory type to that given by 4159 * the parameter "mode". The specified virtual address range must be 4160 * completely contained within either the kernel map. 4161 * 4162 * Returns zero if the change completed successfully, and either EINVAL or 4163 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part 4164 * of the virtual address range was not mapped, and ENOMEM is returned if 4165 * there was insufficient memory available to complete the change. 4166 */ 4167int 4168pmap_change_attr(vm_offset_t va, vm_size_t size, int mode) 4169{ 4170 vm_offset_t base, offset, tmpva; 4171 pt_entry_t *pte; 4172 u_int opte, npte; 4173 pd_entry_t *pde; 4174 boolean_t changed; 4175 4176 base = trunc_page(va); 4177 offset = va & PAGE_MASK; 4178 size = round_page(offset + size); 4179 4180 /* Only supported on kernel virtual addresses. */ 4181 if (base <= VM_MAXUSER_ADDRESS) 4182 return (EINVAL); 4183 4184 /* 4MB pages and pages that aren't mapped aren't supported. */ 4185 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) { 4186 pde = pmap_pde(kernel_pmap, tmpva); 4187 if (*pde & PG_PS) 4188 return (EINVAL); 4189 if ((*pde & PG_V) == 0) 4190 return (EINVAL); 4191 pte = vtopte(va); 4192 if ((*pte & PG_V) == 0) 4193 return (EINVAL); 4194 } 4195 4196 changed = FALSE; 4197 4198 /* 4199 * Ok, all the pages exist and are 4k, so run through them updating 4200 * their cache mode. 4201 */ 4202 for (tmpva = base; size > 0; ) { 4203 pte = vtopte(tmpva); 4204 4205 /* 4206 * The cache mode bits are all in the low 32-bits of the 4207 * PTE, so we can just spin on updating the low 32-bits. 4208 */ 4209 do { 4210 opte = *(u_int *)pte; 4211 npte = opte & ~(PG_PTE_PAT | PG_NC_PCD | PG_NC_PWT); 4212 npte |= pmap_cache_bits(mode, 0); 4213 PT_SET_VA_MA(pte, npte, TRUE); 4214 } while (npte != opte && (*pte != npte)); 4215 if (npte != opte) 4216 changed = TRUE; 4217 tmpva += PAGE_SIZE; 4218 size -= PAGE_SIZE; 4219 } 4220 4221 /* 4222 * Flush CPU caches to make sure any data isn't cached that 4223 * shouldn't be, etc. 4224 */ 4225 if (changed) { 4226 pmap_invalidate_range(kernel_pmap, base, tmpva); 4227 pmap_invalidate_cache_range(base, tmpva); 4228 } 4229 return (0); 4230} 4231 4232/* 4233 * perform the pmap work for mincore 4234 */ 4235int 4236pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa) 4237{ 4238 pt_entry_t *ptep, pte; 4239 vm_paddr_t pa; 4240 int val; 4241 4242 PMAP_LOCK(pmap); 4243retry: 4244 ptep = pmap_pte(pmap, addr); 4245 pte = (ptep != NULL) ? PT_GET(ptep) : 0; 4246 pmap_pte_release(ptep); 4247 val = 0; 4248 if ((pte & PG_V) != 0) { 4249 val |= MINCORE_INCORE; 4250 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 4251 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 4252 if ((pte & PG_A) != 0) 4253 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 4254 } 4255 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 4256 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && 4257 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) { 4258 pa = pte & PG_FRAME; 4259 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */ 4260 if (vm_page_pa_tryrelock(pmap, pa, locked_pa)) 4261 goto retry; 4262 } else 4263 PA_UNLOCK_COND(*locked_pa); 4264 PMAP_UNLOCK(pmap); 4265 return (val); 4266} 4267 4268void 4269pmap_activate(struct thread *td) 4270{ 4271 pmap_t pmap, oldpmap; 4272 u_int cpuid; 4273 u_int32_t cr3; 4274 4275 critical_enter(); 4276 pmap = vmspace_pmap(td->td_proc->p_vmspace); 4277 oldpmap = PCPU_GET(curpmap); 4278 cpuid = PCPU_GET(cpuid); 4279#if defined(SMP) 4280 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active); 4281 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 4282#else 4283 CPU_CLR(cpuid, &oldpmap->pm_active); 4284 CPU_SET(cpuid, &pmap->pm_active); 4285#endif 4286#ifdef PAE 4287 cr3 = vtophys(pmap->pm_pdpt); 4288#else 4289 cr3 = vtophys(pmap->pm_pdir); 4290#endif 4291 /* 4292 * pmap_activate is for the current thread on the current cpu 4293 */ 4294 td->td_pcb->pcb_cr3 = cr3; 4295 PT_UPDATES_FLUSH(); 4296 load_cr3(cr3); 4297 PCPU_SET(curpmap, pmap); 4298 critical_exit(); 4299} 4300 4301void 4302pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 4303{ 4304} 4305 4306/* 4307 * Increase the starting virtual address of the given mapping if a 4308 * different alignment might result in more superpage mappings. 4309 */ 4310void 4311pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 4312 vm_offset_t *addr, vm_size_t size) 4313{ 4314 vm_offset_t superpage_offset; 4315 4316 if (size < NBPDR) 4317 return; 4318 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 4319 offset += ptoa(object->pg_color); 4320 superpage_offset = offset & PDRMASK; 4321 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR || 4322 (*addr & PDRMASK) == superpage_offset) 4323 return; 4324 if ((*addr & PDRMASK) < superpage_offset) 4325 *addr = (*addr & ~PDRMASK) + superpage_offset; 4326 else 4327 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset; 4328} 4329 4330void 4331pmap_suspend() 4332{ 4333 pmap_t pmap; 4334 int i, pdir, offset; 4335 vm_paddr_t pdirma; 4336 mmu_update_t mu[4]; 4337 4338 /* 4339 * We need to remove the recursive mapping structure from all 4340 * our pmaps so that Xen doesn't get confused when it restores 4341 * the page tables. The recursive map lives at page directory 4342 * index PTDPTDI. We assume that the suspend code has stopped 4343 * the other vcpus (if any). 4344 */ 4345 LIST_FOREACH(pmap, &allpmaps, pm_list) { 4346 for (i = 0; i < 4; i++) { 4347 /* 4348 * Figure out which page directory (L2) page 4349 * contains this bit of the recursive map and 4350 * the offset within that page of the map 4351 * entry 4352 */ 4353 pdir = (PTDPTDI + i) / NPDEPG; 4354 offset = (PTDPTDI + i) % NPDEPG; 4355 pdirma = pmap->pm_pdpt[pdir] & PG_FRAME; 4356 mu[i].ptr = pdirma + offset * sizeof(pd_entry_t); 4357 mu[i].val = 0; 4358 } 4359 HYPERVISOR_mmu_update(mu, 4, NULL, DOMID_SELF); 4360 } 4361} 4362 4363void 4364pmap_resume() 4365{ 4366 pmap_t pmap; 4367 int i, pdir, offset; 4368 vm_paddr_t pdirma; 4369 mmu_update_t mu[4]; 4370 4371 /* 4372 * Restore the recursive map that we removed on suspend. 4373 */ 4374 LIST_FOREACH(pmap, &allpmaps, pm_list) { 4375 for (i = 0; i < 4; i++) { 4376 /* 4377 * Figure out which page directory (L2) page 4378 * contains this bit of the recursive map and 4379 * the offset within that page of the map 4380 * entry 4381 */ 4382 pdir = (PTDPTDI + i) / NPDEPG; 4383 offset = (PTDPTDI + i) % NPDEPG; 4384 pdirma = pmap->pm_pdpt[pdir] & PG_FRAME; 4385 mu[i].ptr = pdirma + offset * sizeof(pd_entry_t); 4386 mu[i].val = (pmap->pm_pdpt[i] & PG_FRAME) | PG_V; 4387 } 4388 HYPERVISOR_mmu_update(mu, 4, NULL, DOMID_SELF); 4389 } 4390} 4391 4392#if defined(PMAP_DEBUG) 4393pmap_pid_dump(int pid) 4394{ 4395 pmap_t pmap; 4396 struct proc *p; 4397 int npte = 0; 4398 int index; 4399 4400 sx_slock(&allproc_lock); 4401 FOREACH_PROC_IN_SYSTEM(p) { 4402 if (p->p_pid != pid) 4403 continue; 4404 4405 if (p->p_vmspace) { 4406 int i,j; 4407 index = 0; 4408 pmap = vmspace_pmap(p->p_vmspace); 4409 for (i = 0; i < NPDEPTD; i++) { 4410 pd_entry_t *pde; 4411 pt_entry_t *pte; 4412 vm_offset_t base = i << PDRSHIFT; 4413 4414 pde = &pmap->pm_pdir[i]; 4415 if (pde && pmap_pde_v(pde)) { 4416 for (j = 0; j < NPTEPG; j++) { 4417 vm_offset_t va = base + (j << PAGE_SHIFT); 4418 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) { 4419 if (index) { 4420 index = 0; 4421 printf("\n"); 4422 } 4423 sx_sunlock(&allproc_lock); 4424 return (npte); 4425 } 4426 pte = pmap_pte(pmap, va); 4427 if (pte && pmap_pte_v(pte)) { 4428 pt_entry_t pa; 4429 vm_page_t m; 4430 pa = PT_GET(pte); 4431 m = PHYS_TO_VM_PAGE(pa & PG_FRAME); 4432 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x", 4433 va, pa, m->hold_count, m->wire_count, m->flags); 4434 npte++; 4435 index++; 4436 if (index >= 2) { 4437 index = 0; 4438 printf("\n"); 4439 } else { 4440 printf(" "); 4441 } 4442 } 4443 } 4444 } 4445 } 4446 } 4447 } 4448 sx_sunlock(&allproc_lock); 4449 return (npte); 4450} 4451#endif 4452 4453#if defined(DEBUG) 4454 4455static void pads(pmap_t pm); 4456void pmap_pvdump(vm_paddr_t pa); 4457 4458/* print address space of pmap*/ 4459static void 4460pads(pmap_t pm) 4461{ 4462 int i, j; 4463 vm_paddr_t va; 4464 pt_entry_t *ptep; 4465 4466 if (pm == kernel_pmap) 4467 return; 4468 for (i = 0; i < NPDEPTD; i++) 4469 if (pm->pm_pdir[i]) 4470 for (j = 0; j < NPTEPG; j++) { 4471 va = (i << PDRSHIFT) + (j << PAGE_SHIFT); 4472 if (pm == kernel_pmap && va < KERNBASE) 4473 continue; 4474 if (pm != kernel_pmap && va > UPT_MAX_ADDRESS) 4475 continue; 4476 ptep = pmap_pte(pm, va); 4477 if (pmap_pte_v(ptep)) 4478 printf("%x:%x ", va, *ptep); 4479 }; 4480 4481} 4482 4483void 4484pmap_pvdump(vm_paddr_t pa) 4485{ 4486 pv_entry_t pv; 4487 pmap_t pmap; 4488 vm_page_t m; 4489 4490 printf("pa %x", pa); 4491 m = PHYS_TO_VM_PAGE(pa); 4492 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 4493 pmap = PV_PMAP(pv); 4494 printf(" -> pmap %p, va %x", (void *)pmap, pv->pv_va); 4495 pads(pmap); 4496 } 4497 printf(" "); 4498} 4499#endif 4500