pmap.c revision 267964
1/*- 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * Copyright (c) 2005 Alan L. Cox <alc@cs.rice.edu> 9 * All rights reserved. 10 * 11 * This code is derived from software contributed to Berkeley by 12 * the Systems Programming Group of the University of Utah Computer 13 * Science Department and William Jolitz of UUNET Technologies Inc. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 3. All advertising materials mentioning features or use of this software 24 * must display the following acknowledgement: 25 * This product includes software developed by the University of 26 * California, Berkeley and its contributors. 27 * 4. Neither the name of the University nor the names of its contributors 28 * may be used to endorse or promote products derived from this software 29 * without specific prior written permission. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 41 * SUCH DAMAGE. 42 * 43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 44 */ 45/*- 46 * Copyright (c) 2003 Networks Associates Technology, Inc. 47 * All rights reserved. 48 * 49 * This software was developed for the FreeBSD Project by Jake Burkholder, 50 * Safeport Network Services, and Network Associates Laboratories, the 51 * Security Research Division of Network Associates, Inc. under 52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA 53 * CHATS research program. 54 * 55 * Redistribution and use in source and binary forms, with or without 56 * modification, are permitted provided that the following conditions 57 * are met: 58 * 1. Redistributions of source code must retain the above copyright 59 * notice, this list of conditions and the following disclaimer. 60 * 2. Redistributions in binary form must reproduce the above copyright 61 * notice, this list of conditions and the following disclaimer in the 62 * documentation and/or other materials provided with the distribution. 63 * 64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 74 * SUCH DAMAGE. 75 */ 76 77#include <sys/cdefs.h> 78__FBSDID("$FreeBSD: stable/10/sys/i386/xen/pmap.c 267964 2014-06-27 17:22:18Z jhb $"); 79 80/* 81 * Manages physical address maps. 82 * 83 * Since the information managed by this module is 84 * also stored by the logical address mapping module, 85 * this module may throw away valid virtual-to-physical 86 * mappings at almost any time. However, invalidations 87 * of virtual-to-physical mappings must be done as 88 * requested. 89 * 90 * In order to cope with hardware architectures which 91 * make virtual-to-physical map invalidates expensive, 92 * this module may delay invalidate or reduced protection 93 * operations until such time as they are actually 94 * necessary. This module is given full information as 95 * to which processors are currently using which maps, 96 * and to when physical maps must be made correct. 97 */ 98 99#include "opt_cpu.h" 100#include "opt_pmap.h" 101#include "opt_smp.h" 102#include "opt_xbox.h" 103 104#include <sys/param.h> 105#include <sys/systm.h> 106#include <sys/kernel.h> 107#include <sys/ktr.h> 108#include <sys/lock.h> 109#include <sys/malloc.h> 110#include <sys/mman.h> 111#include <sys/msgbuf.h> 112#include <sys/mutex.h> 113#include <sys/proc.h> 114#include <sys/rwlock.h> 115#include <sys/sf_buf.h> 116#include <sys/sx.h> 117#include <sys/vmmeter.h> 118#include <sys/sched.h> 119#include <sys/sysctl.h> 120#ifdef SMP 121#include <sys/smp.h> 122#else 123#include <sys/cpuset.h> 124#endif 125 126#include <vm/vm.h> 127#include <vm/vm_param.h> 128#include <vm/vm_kern.h> 129#include <vm/vm_page.h> 130#include <vm/vm_map.h> 131#include <vm/vm_object.h> 132#include <vm/vm_extern.h> 133#include <vm/vm_pageout.h> 134#include <vm/vm_pager.h> 135#include <vm/uma.h> 136 137#include <machine/cpu.h> 138#include <machine/cputypes.h> 139#include <machine/md_var.h> 140#include <machine/pcb.h> 141#include <machine/specialreg.h> 142#ifdef SMP 143#include <machine/smp.h> 144#endif 145 146#ifdef XBOX 147#include <machine/xbox.h> 148#endif 149 150#include <xen/interface/xen.h> 151#include <xen/hypervisor.h> 152#include <machine/xen/hypercall.h> 153#include <machine/xen/xenvar.h> 154#include <machine/xen/xenfunc.h> 155 156#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU) 157#define CPU_ENABLE_SSE 158#endif 159 160#ifndef PMAP_SHPGPERPROC 161#define PMAP_SHPGPERPROC 200 162#endif 163 164#define DIAGNOSTIC 165 166#if !defined(DIAGNOSTIC) 167#ifdef __GNUC_GNU_INLINE__ 168#define PMAP_INLINE __attribute__((__gnu_inline__)) inline 169#else 170#define PMAP_INLINE extern inline 171#endif 172#else 173#define PMAP_INLINE 174#endif 175 176#ifdef PV_STATS 177#define PV_STAT(x) do { x ; } while (0) 178#else 179#define PV_STAT(x) do { } while (0) 180#endif 181 182/* 183 * Get PDEs and PTEs for user/kernel address space 184 */ 185#define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT])) 186#define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT]) 187 188#define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0) 189#define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0) 190#define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0) 191#define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0) 192#define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0) 193 194#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v))) 195 196#define HAMFISTED_LOCKING 197#ifdef HAMFISTED_LOCKING 198static struct mtx createdelete_lock; 199#endif 200 201struct pmap kernel_pmap_store; 202LIST_HEAD(pmaplist, pmap); 203static struct pmaplist allpmaps; 204static struct mtx allpmaps_lock; 205 206vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 207vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 208int pgeflag = 0; /* PG_G or-in */ 209int pseflag = 0; /* PG_PS or-in */ 210 211int nkpt; 212vm_offset_t kernel_vm_end; 213extern u_int32_t KERNend; 214 215#ifdef PAE 216pt_entry_t pg_nx; 217#endif 218 219static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters"); 220 221static int pat_works; /* Is page attribute table sane? */ 222 223/* 224 * This lock is defined as static in other pmap implementations. It cannot, 225 * however, be defined as static here, because it is (ab)used to serialize 226 * queued page table changes in other sources files. 227 */ 228struct rwlock pvh_global_lock; 229 230/* 231 * Data for the pv entry allocation mechanism 232 */ 233static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks); 234static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 235static int shpgperproc = PMAP_SHPGPERPROC; 236 237struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */ 238int pv_maxchunks; /* How many chunks we have KVA for */ 239vm_offset_t pv_vafree; /* freelist stored in the PTE */ 240 241/* 242 * All those kernel PT submaps that BSD is so fond of 243 */ 244struct sysmaps { 245 struct mtx lock; 246 pt_entry_t *CMAP1; 247 pt_entry_t *CMAP2; 248 caddr_t CADDR1; 249 caddr_t CADDR2; 250}; 251static struct sysmaps sysmaps_pcpu[MAXCPU]; 252pt_entry_t *CMAP3; 253caddr_t ptvmmap = 0; 254caddr_t CADDR3; 255struct msgbuf *msgbufp = 0; 256 257/* 258 * Crashdump maps. 259 */ 260static caddr_t crashdumpmap; 261 262static pt_entry_t *PMAP1 = 0, *PMAP2; 263static pt_entry_t *PADDR1 = 0, *PADDR2; 264#ifdef SMP 265static int PMAP1cpu; 266static int PMAP1changedcpu; 267SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD, 268 &PMAP1changedcpu, 0, 269 "Number of times pmap_pte_quick changed CPU with same PMAP1"); 270#endif 271static int PMAP1changed; 272SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD, 273 &PMAP1changed, 0, 274 "Number of times pmap_pte_quick changed PMAP1"); 275static int PMAP1unchanged; 276SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD, 277 &PMAP1unchanged, 0, 278 "Number of times pmap_pte_quick didn't change PMAP1"); 279static struct mtx PMAP2mutex; 280 281static void free_pv_chunk(struct pv_chunk *pc); 282static void free_pv_entry(pmap_t pmap, pv_entry_t pv); 283static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try); 284static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va); 285static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, 286 vm_offset_t va); 287 288static vm_page_t pmap_enter_quick_locked(multicall_entry_t **mcl, int *count, pmap_t pmap, vm_offset_t va, 289 vm_page_t m, vm_prot_t prot, vm_page_t mpte); 290static void pmap_flush_page(vm_page_t m); 291static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode); 292static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva, 293 vm_page_t *free); 294static void pmap_remove_page(struct pmap *pmap, vm_offset_t va, 295 vm_page_t *free); 296static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, 297 vm_offset_t va); 298static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, 299 vm_page_t m); 300 301static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags); 302 303static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, int flags); 304static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, vm_page_t *free); 305static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va); 306static void pmap_pte_release(pt_entry_t *pte); 307static int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t *); 308static boolean_t pmap_is_prefaultable_locked(pmap_t pmap, vm_offset_t addr); 309 310static __inline void pagezero(void *page); 311 312CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t)); 313CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t)); 314 315/* 316 * If you get an error here, then you set KVA_PAGES wrong! See the 317 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be 318 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE. 319 */ 320CTASSERT(KERNBASE % (1 << 24) == 0); 321 322void 323pd_set(struct pmap *pmap, int ptepindex, vm_paddr_t val, int type) 324{ 325 vm_paddr_t pdir_ma = vtomach(&pmap->pm_pdir[ptepindex]); 326 327 switch (type) { 328 case SH_PD_SET_VA: 329#if 0 330 xen_queue_pt_update(shadow_pdir_ma, 331 xpmap_ptom(val & ~(PG_RW))); 332#endif 333 xen_queue_pt_update(pdir_ma, 334 xpmap_ptom(val)); 335 break; 336 case SH_PD_SET_VA_MA: 337#if 0 338 xen_queue_pt_update(shadow_pdir_ma, 339 val & ~(PG_RW)); 340#endif 341 xen_queue_pt_update(pdir_ma, val); 342 break; 343 case SH_PD_SET_VA_CLEAR: 344#if 0 345 xen_queue_pt_update(shadow_pdir_ma, 0); 346#endif 347 xen_queue_pt_update(pdir_ma, 0); 348 break; 349 } 350} 351 352/* 353 * Bootstrap the system enough to run with virtual memory. 354 * 355 * On the i386 this is called after mapping has already been enabled 356 * and just syncs the pmap module with what has already been done. 357 * [We can't call it easily with mapping off since the kernel is not 358 * mapped with PA == VA, hence we would have to relocate every address 359 * from the linked base (virtual) address "KERNBASE" to the actual 360 * (physical) address starting relative to 0] 361 */ 362void 363pmap_bootstrap(vm_paddr_t firstaddr) 364{ 365 vm_offset_t va; 366 pt_entry_t *pte, *unused; 367 struct sysmaps *sysmaps; 368 int i; 369 370 /* 371 * Initialize the first available kernel virtual address. However, 372 * using "firstaddr" may waste a few pages of the kernel virtual 373 * address space, because locore may not have mapped every physical 374 * page that it allocated. Preferably, locore would provide a first 375 * unused virtual address in addition to "firstaddr". 376 */ 377 virtual_avail = (vm_offset_t) KERNBASE + firstaddr; 378 379 virtual_end = VM_MAX_KERNEL_ADDRESS; 380 381 /* 382 * Initialize the kernel pmap (which is statically allocated). 383 */ 384 PMAP_LOCK_INIT(kernel_pmap); 385 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD); 386#ifdef PAE 387 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT); 388#endif 389 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */ 390 TAILQ_INIT(&kernel_pmap->pm_pvchunk); 391 392 /* 393 * Initialize the global pv list lock. 394 */ 395 rw_init_flags(&pvh_global_lock, "pmap pv global", RW_RECURSE); 396 397 LIST_INIT(&allpmaps); 398 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN); 399 mtx_lock_spin(&allpmaps_lock); 400 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list); 401 mtx_unlock_spin(&allpmaps_lock); 402 if (nkpt == 0) 403 nkpt = NKPT; 404 405 /* 406 * Reserve some special page table entries/VA space for temporary 407 * mapping of pages. 408 */ 409#define SYSMAP(c, p, v, n) \ 410 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 411 412 va = virtual_avail; 413 pte = vtopte(va); 414 415 /* 416 * CMAP1/CMAP2 are used for zeroing and copying pages. 417 * CMAP3 is used for the idle process page zeroing. 418 */ 419 for (i = 0; i < MAXCPU; i++) { 420 sysmaps = &sysmaps_pcpu[i]; 421 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF); 422 SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1) 423 SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1) 424 PT_SET_MA(sysmaps->CADDR1, 0); 425 PT_SET_MA(sysmaps->CADDR2, 0); 426 } 427 SYSMAP(caddr_t, CMAP3, CADDR3, 1) 428 PT_SET_MA(CADDR3, 0); 429 430 /* 431 * Crashdump maps. 432 */ 433 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS) 434 435 /* 436 * ptvmmap is used for reading arbitrary physical pages via /dev/mem. 437 */ 438 SYSMAP(caddr_t, unused, ptvmmap, 1) 439 440 /* 441 * msgbufp is used to map the system message buffer. 442 */ 443 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize))) 444 445 /* 446 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(), 447 * respectively. 448 */ 449 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1) 450 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1) 451 452 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF); 453 454 virtual_avail = va; 455 456 /* 457 * Leave in place an identity mapping (virt == phys) for the low 1 MB 458 * physical memory region that is used by the ACPI wakeup code. This 459 * mapping must not have PG_G set. 460 */ 461#ifndef XEN 462 /* 463 * leave here deliberately to show that this is not supported 464 */ 465#ifdef XBOX 466 /* FIXME: This is gross, but needed for the XBOX. Since we are in such 467 * an early stadium, we cannot yet neatly map video memory ... :-( 468 * Better fixes are very welcome! */ 469 if (!arch_i386_is_xbox) 470#endif 471 for (i = 1; i < NKPT; i++) 472 PTD[i] = 0; 473 474 /* Initialize the PAT MSR if present. */ 475 pmap_init_pat(); 476 477 /* Turn on PG_G on kernel page(s) */ 478 pmap_set_pg(); 479#endif 480 481#ifdef HAMFISTED_LOCKING 482 mtx_init(&createdelete_lock, "pmap create/delete", NULL, MTX_DEF); 483#endif 484} 485 486/* 487 * Setup the PAT MSR. 488 */ 489void 490pmap_init_pat(void) 491{ 492 uint64_t pat_msr; 493 494 /* Bail if this CPU doesn't implement PAT. */ 495 if (!(cpu_feature & CPUID_PAT)) 496 return; 497 498 if (cpu_vendor_id != CPU_VENDOR_INTEL || 499 (CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe)) { 500 /* 501 * Leave the indices 0-3 at the default of WB, WT, UC, and UC-. 502 * Program 4 and 5 as WP and WC. 503 * Leave 6 and 7 as UC and UC-. 504 */ 505 pat_msr = rdmsr(MSR_PAT); 506 pat_msr &= ~(PAT_MASK(4) | PAT_MASK(5)); 507 pat_msr |= PAT_VALUE(4, PAT_WRITE_PROTECTED) | 508 PAT_VALUE(5, PAT_WRITE_COMBINING); 509 pat_works = 1; 510 } else { 511 /* 512 * Due to some Intel errata, we can only safely use the lower 4 513 * PAT entries. Thus, just replace PAT Index 2 with WC instead 514 * of UC-. 515 * 516 * Intel Pentium III Processor Specification Update 517 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B 518 * or Mode C Paging) 519 * 520 * Intel Pentium IV Processor Specification Update 521 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly) 522 */ 523 pat_msr = rdmsr(MSR_PAT); 524 pat_msr &= ~PAT_MASK(2); 525 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING); 526 pat_works = 0; 527 } 528 wrmsr(MSR_PAT, pat_msr); 529} 530 531/* 532 * Initialize a vm_page's machine-dependent fields. 533 */ 534void 535pmap_page_init(vm_page_t m) 536{ 537 538 TAILQ_INIT(&m->md.pv_list); 539 m->md.pat_mode = PAT_WRITE_BACK; 540} 541 542/* 543 * ABuse the pte nodes for unmapped kva to thread a kva freelist through. 544 * Requirements: 545 * - Must deal with pages in order to ensure that none of the PG_* bits 546 * are ever set, PG_V in particular. 547 * - Assumes we can write to ptes without pte_store() atomic ops, even 548 * on PAE systems. This should be ok. 549 * - Assumes nothing will ever test these addresses for 0 to indicate 550 * no mapping instead of correctly checking PG_V. 551 * - Assumes a vm_offset_t will fit in a pte (true for i386). 552 * Because PG_V is never set, there can be no mappings to invalidate. 553 */ 554static int ptelist_count = 0; 555static vm_offset_t 556pmap_ptelist_alloc(vm_offset_t *head) 557{ 558 vm_offset_t va; 559 vm_offset_t *phead = (vm_offset_t *)*head; 560 561 if (ptelist_count == 0) { 562 printf("out of memory!!!!!!\n"); 563 return (0); /* Out of memory */ 564 } 565 ptelist_count--; 566 va = phead[ptelist_count]; 567 return (va); 568} 569 570static void 571pmap_ptelist_free(vm_offset_t *head, vm_offset_t va) 572{ 573 vm_offset_t *phead = (vm_offset_t *)*head; 574 575 phead[ptelist_count++] = va; 576} 577 578static void 579pmap_ptelist_init(vm_offset_t *head, void *base, int npages) 580{ 581 int i, nstackpages; 582 vm_offset_t va; 583 vm_page_t m; 584 585 nstackpages = (npages + PAGE_SIZE/sizeof(vm_offset_t) - 1)/ (PAGE_SIZE/sizeof(vm_offset_t)); 586 for (i = 0; i < nstackpages; i++) { 587 va = (vm_offset_t)base + i * PAGE_SIZE; 588 m = vm_page_alloc(NULL, i, 589 VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 590 VM_ALLOC_ZERO); 591 pmap_qenter(va, &m, 1); 592 } 593 594 *head = (vm_offset_t)base; 595 for (i = npages - 1; i >= nstackpages; i--) { 596 va = (vm_offset_t)base + i * PAGE_SIZE; 597 pmap_ptelist_free(head, va); 598 } 599} 600 601 602/* 603 * Initialize the pmap module. 604 * Called by vm_init, to initialize any structures that the pmap 605 * system needs to map virtual memory. 606 */ 607void 608pmap_init(void) 609{ 610 611 /* 612 * Initialize the address space (zone) for the pv entries. Set a 613 * high water mark so that the system can recover from excessive 614 * numbers of pv entries. 615 */ 616 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 617 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 618 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 619 pv_entry_max = roundup(pv_entry_max, _NPCPV); 620 pv_entry_high_water = 9 * (pv_entry_max / 10); 621 622 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc); 623 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks); 624 if (pv_chunkbase == NULL) 625 panic("pmap_init: not enough kvm for pv chunks"); 626 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks); 627} 628 629 630SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0, 631 "Max number of PV entries"); 632SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0, 633 "Page share factor per proc"); 634 635static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0, 636 "2/4MB page mapping counters"); 637 638static u_long pmap_pde_mappings; 639SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD, 640 &pmap_pde_mappings, 0, "2/4MB page mappings"); 641 642/*************************************************** 643 * Low level helper routines..... 644 ***************************************************/ 645 646/* 647 * Determine the appropriate bits to set in a PTE or PDE for a specified 648 * caching mode. 649 */ 650int 651pmap_cache_bits(int mode, boolean_t is_pde) 652{ 653 int pat_flag, pat_index, cache_bits; 654 655 /* The PAT bit is different for PTE's and PDE's. */ 656 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT; 657 658 /* If we don't support PAT, map extended modes to older ones. */ 659 if (!(cpu_feature & CPUID_PAT)) { 660 switch (mode) { 661 case PAT_UNCACHEABLE: 662 case PAT_WRITE_THROUGH: 663 case PAT_WRITE_BACK: 664 break; 665 case PAT_UNCACHED: 666 case PAT_WRITE_COMBINING: 667 case PAT_WRITE_PROTECTED: 668 mode = PAT_UNCACHEABLE; 669 break; 670 } 671 } 672 673 /* Map the caching mode to a PAT index. */ 674 if (pat_works) { 675 switch (mode) { 676 case PAT_UNCACHEABLE: 677 pat_index = 3; 678 break; 679 case PAT_WRITE_THROUGH: 680 pat_index = 1; 681 break; 682 case PAT_WRITE_BACK: 683 pat_index = 0; 684 break; 685 case PAT_UNCACHED: 686 pat_index = 2; 687 break; 688 case PAT_WRITE_COMBINING: 689 pat_index = 5; 690 break; 691 case PAT_WRITE_PROTECTED: 692 pat_index = 4; 693 break; 694 default: 695 panic("Unknown caching mode %d\n", mode); 696 } 697 } else { 698 switch (mode) { 699 case PAT_UNCACHED: 700 case PAT_UNCACHEABLE: 701 case PAT_WRITE_PROTECTED: 702 pat_index = 3; 703 break; 704 case PAT_WRITE_THROUGH: 705 pat_index = 1; 706 break; 707 case PAT_WRITE_BACK: 708 pat_index = 0; 709 break; 710 case PAT_WRITE_COMBINING: 711 pat_index = 2; 712 break; 713 default: 714 panic("Unknown caching mode %d\n", mode); 715 } 716 } 717 718 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */ 719 cache_bits = 0; 720 if (pat_index & 0x4) 721 cache_bits |= pat_flag; 722 if (pat_index & 0x2) 723 cache_bits |= PG_NC_PCD; 724 if (pat_index & 0x1) 725 cache_bits |= PG_NC_PWT; 726 return (cache_bits); 727} 728#ifdef SMP 729/* 730 * For SMP, these functions have to use the IPI mechanism for coherence. 731 * 732 * N.B.: Before calling any of the following TLB invalidation functions, 733 * the calling processor must ensure that all stores updating a non- 734 * kernel page table are globally performed. Otherwise, another 735 * processor could cache an old, pre-update entry without being 736 * invalidated. This can happen one of two ways: (1) The pmap becomes 737 * active on another processor after its pm_active field is checked by 738 * one of the following functions but before a store updating the page 739 * table is globally performed. (2) The pmap becomes active on another 740 * processor before its pm_active field is checked but due to 741 * speculative loads one of the following functions stills reads the 742 * pmap as inactive on the other processor. 743 * 744 * The kernel page table is exempt because its pm_active field is 745 * immutable. The kernel page table is always active on every 746 * processor. 747 */ 748void 749pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 750{ 751 cpuset_t other_cpus; 752 u_int cpuid; 753 754 CTR2(KTR_PMAP, "pmap_invalidate_page: pmap=%p va=0x%x", 755 pmap, va); 756 757 sched_pin(); 758 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 759 invlpg(va); 760 smp_invlpg(va); 761 } else { 762 cpuid = PCPU_GET(cpuid); 763 other_cpus = all_cpus; 764 CPU_CLR(cpuid, &other_cpus); 765 if (CPU_ISSET(cpuid, &pmap->pm_active)) 766 invlpg(va); 767 CPU_AND(&other_cpus, &pmap->pm_active); 768 if (!CPU_EMPTY(&other_cpus)) 769 smp_masked_invlpg(other_cpus, va); 770 } 771 sched_unpin(); 772 PT_UPDATES_FLUSH(); 773} 774 775void 776pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 777{ 778 cpuset_t other_cpus; 779 vm_offset_t addr; 780 u_int cpuid; 781 782 CTR3(KTR_PMAP, "pmap_invalidate_page: pmap=%p eva=0x%x sva=0x%x", 783 pmap, sva, eva); 784 785 sched_pin(); 786 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 787 for (addr = sva; addr < eva; addr += PAGE_SIZE) 788 invlpg(addr); 789 smp_invlpg_range(sva, eva); 790 } else { 791 cpuid = PCPU_GET(cpuid); 792 other_cpus = all_cpus; 793 CPU_CLR(cpuid, &other_cpus); 794 if (CPU_ISSET(cpuid, &pmap->pm_active)) 795 for (addr = sva; addr < eva; addr += PAGE_SIZE) 796 invlpg(addr); 797 CPU_AND(&other_cpus, &pmap->pm_active); 798 if (!CPU_EMPTY(&other_cpus)) 799 smp_masked_invlpg_range(other_cpus, sva, eva); 800 } 801 sched_unpin(); 802 PT_UPDATES_FLUSH(); 803} 804 805void 806pmap_invalidate_all(pmap_t pmap) 807{ 808 cpuset_t other_cpus; 809 u_int cpuid; 810 811 CTR1(KTR_PMAP, "pmap_invalidate_page: pmap=%p", pmap); 812 813 sched_pin(); 814 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 815 invltlb(); 816 smp_invltlb(); 817 } else { 818 cpuid = PCPU_GET(cpuid); 819 other_cpus = all_cpus; 820 CPU_CLR(cpuid, &other_cpus); 821 if (CPU_ISSET(cpuid, &pmap->pm_active)) 822 invltlb(); 823 CPU_AND(&other_cpus, &pmap->pm_active); 824 if (!CPU_EMPTY(&other_cpus)) 825 smp_masked_invltlb(other_cpus); 826 } 827 sched_unpin(); 828} 829 830void 831pmap_invalidate_cache(void) 832{ 833 834 sched_pin(); 835 wbinvd(); 836 smp_cache_flush(); 837 sched_unpin(); 838} 839#else /* !SMP */ 840/* 841 * Normal, non-SMP, 486+ invalidation functions. 842 * We inline these within pmap.c for speed. 843 */ 844PMAP_INLINE void 845pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 846{ 847 CTR2(KTR_PMAP, "pmap_invalidate_page: pmap=%p va=0x%x", 848 pmap, va); 849 850 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 851 invlpg(va); 852 PT_UPDATES_FLUSH(); 853} 854 855PMAP_INLINE void 856pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 857{ 858 vm_offset_t addr; 859 860 if (eva - sva > PAGE_SIZE) 861 CTR3(KTR_PMAP, "pmap_invalidate_range: pmap=%p sva=0x%x eva=0x%x", 862 pmap, sva, eva); 863 864 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 865 for (addr = sva; addr < eva; addr += PAGE_SIZE) 866 invlpg(addr); 867 PT_UPDATES_FLUSH(); 868} 869 870PMAP_INLINE void 871pmap_invalidate_all(pmap_t pmap) 872{ 873 874 CTR1(KTR_PMAP, "pmap_invalidate_all: pmap=%p", pmap); 875 876 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 877 invltlb(); 878} 879 880PMAP_INLINE void 881pmap_invalidate_cache(void) 882{ 883 884 wbinvd(); 885} 886#endif /* !SMP */ 887 888#define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024) 889 890void 891pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva) 892{ 893 894 KASSERT((sva & PAGE_MASK) == 0, 895 ("pmap_invalidate_cache_range: sva not page-aligned")); 896 KASSERT((eva & PAGE_MASK) == 0, 897 ("pmap_invalidate_cache_range: eva not page-aligned")); 898 899 if (cpu_feature & CPUID_SS) 900 ; /* If "Self Snoop" is supported, do nothing. */ 901 else if ((cpu_feature & CPUID_CLFSH) != 0 && 902 eva - sva < PMAP_CLFLUSH_THRESHOLD) { 903 904 /* 905 * Otherwise, do per-cache line flush. Use the mfence 906 * instruction to insure that previous stores are 907 * included in the write-back. The processor 908 * propagates flush to other processors in the cache 909 * coherence domain. 910 */ 911 mfence(); 912 for (; sva < eva; sva += cpu_clflush_line_size) 913 clflush(sva); 914 mfence(); 915 } else { 916 917 /* 918 * No targeted cache flush methods are supported by CPU, 919 * or the supplied range is bigger than 2MB. 920 * Globally invalidate cache. 921 */ 922 pmap_invalidate_cache(); 923 } 924} 925 926void 927pmap_invalidate_cache_pages(vm_page_t *pages, int count) 928{ 929 int i; 930 931 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE || 932 (cpu_feature & CPUID_CLFSH) == 0) { 933 pmap_invalidate_cache(); 934 } else { 935 for (i = 0; i < count; i++) 936 pmap_flush_page(pages[i]); 937 } 938} 939 940/* 941 * Are we current address space or kernel? N.B. We return FALSE when 942 * a pmap's page table is in use because a kernel thread is borrowing 943 * it. The borrowed page table can change spontaneously, making any 944 * dependence on its continued use subject to a race condition. 945 */ 946static __inline int 947pmap_is_current(pmap_t pmap) 948{ 949 950 return (pmap == kernel_pmap || 951 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace) && 952 (pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & PG_FRAME))); 953} 954 955/* 956 * If the given pmap is not the current or kernel pmap, the returned pte must 957 * be released by passing it to pmap_pte_release(). 958 */ 959pt_entry_t * 960pmap_pte(pmap_t pmap, vm_offset_t va) 961{ 962 pd_entry_t newpf; 963 pd_entry_t *pde; 964 965 pde = pmap_pde(pmap, va); 966 if (*pde & PG_PS) 967 return (pde); 968 if (*pde != 0) { 969 /* are we current address space or kernel? */ 970 if (pmap_is_current(pmap)) 971 return (vtopte(va)); 972 mtx_lock(&PMAP2mutex); 973 newpf = *pde & PG_FRAME; 974 if ((*PMAP2 & PG_FRAME) != newpf) { 975 PT_SET_MA(PADDR2, newpf | PG_V | PG_A | PG_M); 976 CTR3(KTR_PMAP, "pmap_pte: pmap=%p va=0x%x newpte=0x%08x", 977 pmap, va, (*PMAP2 & 0xffffffff)); 978 } 979 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1))); 980 } 981 return (NULL); 982} 983 984/* 985 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte 986 * being NULL. 987 */ 988static __inline void 989pmap_pte_release(pt_entry_t *pte) 990{ 991 992 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2) { 993 CTR1(KTR_PMAP, "pmap_pte_release: pte=0x%jx", 994 *PMAP2); 995 rw_wlock(&pvh_global_lock); 996 PT_SET_VA(PMAP2, 0, TRUE); 997 rw_wunlock(&pvh_global_lock); 998 mtx_unlock(&PMAP2mutex); 999 } 1000} 1001 1002static __inline void 1003invlcaddr(void *caddr) 1004{ 1005 1006 invlpg((u_int)caddr); 1007 PT_UPDATES_FLUSH(); 1008} 1009 1010/* 1011 * Super fast pmap_pte routine best used when scanning 1012 * the pv lists. This eliminates many coarse-grained 1013 * invltlb calls. Note that many of the pv list 1014 * scans are across different pmaps. It is very wasteful 1015 * to do an entire invltlb for checking a single mapping. 1016 * 1017 * If the given pmap is not the current pmap, pvh_global_lock 1018 * must be held and curthread pinned to a CPU. 1019 */ 1020static pt_entry_t * 1021pmap_pte_quick(pmap_t pmap, vm_offset_t va) 1022{ 1023 pd_entry_t newpf; 1024 pd_entry_t *pde; 1025 1026 pde = pmap_pde(pmap, va); 1027 if (*pde & PG_PS) 1028 return (pde); 1029 if (*pde != 0) { 1030 /* are we current address space or kernel? */ 1031 if (pmap_is_current(pmap)) 1032 return (vtopte(va)); 1033 rw_assert(&pvh_global_lock, RA_WLOCKED); 1034 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 1035 newpf = *pde & PG_FRAME; 1036 if ((*PMAP1 & PG_FRAME) != newpf) { 1037 PT_SET_MA(PADDR1, newpf | PG_V | PG_A | PG_M); 1038 CTR3(KTR_PMAP, "pmap_pte_quick: pmap=%p va=0x%x newpte=0x%08x", 1039 pmap, va, (u_long)*PMAP1); 1040 1041#ifdef SMP 1042 PMAP1cpu = PCPU_GET(cpuid); 1043#endif 1044 PMAP1changed++; 1045 } else 1046#ifdef SMP 1047 if (PMAP1cpu != PCPU_GET(cpuid)) { 1048 PMAP1cpu = PCPU_GET(cpuid); 1049 invlcaddr(PADDR1); 1050 PMAP1changedcpu++; 1051 } else 1052#endif 1053 PMAP1unchanged++; 1054 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1))); 1055 } 1056 return (0); 1057} 1058 1059/* 1060 * Routine: pmap_extract 1061 * Function: 1062 * Extract the physical page address associated 1063 * with the given map/virtual_address pair. 1064 */ 1065vm_paddr_t 1066pmap_extract(pmap_t pmap, vm_offset_t va) 1067{ 1068 vm_paddr_t rtval; 1069 pt_entry_t *pte; 1070 pd_entry_t pde; 1071 pt_entry_t pteval; 1072 1073 rtval = 0; 1074 PMAP_LOCK(pmap); 1075 pde = pmap->pm_pdir[va >> PDRSHIFT]; 1076 if (pde != 0) { 1077 if ((pde & PG_PS) != 0) { 1078 rtval = xpmap_mtop(pde & PG_PS_FRAME) | (va & PDRMASK); 1079 PMAP_UNLOCK(pmap); 1080 return rtval; 1081 } 1082 pte = pmap_pte(pmap, va); 1083 pteval = *pte ? xpmap_mtop(*pte) : 0; 1084 rtval = (pteval & PG_FRAME) | (va & PAGE_MASK); 1085 pmap_pte_release(pte); 1086 } 1087 PMAP_UNLOCK(pmap); 1088 return (rtval); 1089} 1090 1091/* 1092 * Routine: pmap_extract_ma 1093 * Function: 1094 * Like pmap_extract, but returns machine address 1095 */ 1096vm_paddr_t 1097pmap_extract_ma(pmap_t pmap, vm_offset_t va) 1098{ 1099 vm_paddr_t rtval; 1100 pt_entry_t *pte; 1101 pd_entry_t pde; 1102 1103 rtval = 0; 1104 PMAP_LOCK(pmap); 1105 pde = pmap->pm_pdir[va >> PDRSHIFT]; 1106 if (pde != 0) { 1107 if ((pde & PG_PS) != 0) { 1108 rtval = (pde & ~PDRMASK) | (va & PDRMASK); 1109 PMAP_UNLOCK(pmap); 1110 return rtval; 1111 } 1112 pte = pmap_pte(pmap, va); 1113 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK); 1114 pmap_pte_release(pte); 1115 } 1116 PMAP_UNLOCK(pmap); 1117 return (rtval); 1118} 1119 1120/* 1121 * Routine: pmap_extract_and_hold 1122 * Function: 1123 * Atomically extract and hold the physical page 1124 * with the given pmap and virtual address pair 1125 * if that mapping permits the given protection. 1126 */ 1127vm_page_t 1128pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1129{ 1130 pd_entry_t pde; 1131 pt_entry_t pte, *ptep; 1132 vm_page_t m; 1133 vm_paddr_t pa; 1134 1135 pa = 0; 1136 m = NULL; 1137 PMAP_LOCK(pmap); 1138retry: 1139 pde = PT_GET(pmap_pde(pmap, va)); 1140 if (pde != 0) { 1141 if (pde & PG_PS) { 1142 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) { 1143 if (vm_page_pa_tryrelock(pmap, (pde & 1144 PG_PS_FRAME) | (va & PDRMASK), &pa)) 1145 goto retry; 1146 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) | 1147 (va & PDRMASK)); 1148 vm_page_hold(m); 1149 } 1150 } else { 1151 ptep = pmap_pte(pmap, va); 1152 pte = PT_GET(ptep); 1153 pmap_pte_release(ptep); 1154 if (pte != 0 && 1155 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) { 1156 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME, 1157 &pa)) 1158 goto retry; 1159 m = PHYS_TO_VM_PAGE(pte & PG_FRAME); 1160 vm_page_hold(m); 1161 } 1162 } 1163 } 1164 PA_UNLOCK_COND(pa); 1165 PMAP_UNLOCK(pmap); 1166 return (m); 1167} 1168 1169/*************************************************** 1170 * Low level mapping routines..... 1171 ***************************************************/ 1172 1173/* 1174 * Add a wired page to the kva. 1175 * Note: not SMP coherent. 1176 * 1177 * This function may be used before pmap_bootstrap() is called. 1178 */ 1179void 1180pmap_kenter(vm_offset_t va, vm_paddr_t pa) 1181{ 1182 1183 PT_SET_MA(va, xpmap_ptom(pa)| PG_RW | PG_V | pgeflag); 1184} 1185 1186void 1187pmap_kenter_ma(vm_offset_t va, vm_paddr_t ma) 1188{ 1189 pt_entry_t *pte; 1190 1191 pte = vtopte(va); 1192 pte_store_ma(pte, ma | PG_RW | PG_V | pgeflag); 1193} 1194 1195static __inline void 1196pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode) 1197{ 1198 1199 PT_SET_MA(va, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0)); 1200} 1201 1202/* 1203 * Remove a page from the kernel pagetables. 1204 * Note: not SMP coherent. 1205 * 1206 * This function may be used before pmap_bootstrap() is called. 1207 */ 1208PMAP_INLINE void 1209pmap_kremove(vm_offset_t va) 1210{ 1211 pt_entry_t *pte; 1212 1213 pte = vtopte(va); 1214 PT_CLEAR_VA(pte, FALSE); 1215} 1216 1217/* 1218 * Used to map a range of physical addresses into kernel 1219 * virtual address space. 1220 * 1221 * The value passed in '*virt' is a suggested virtual address for 1222 * the mapping. Architectures which can support a direct-mapped 1223 * physical to virtual region can return the appropriate address 1224 * within that region, leaving '*virt' unchanged. Other 1225 * architectures should map the pages starting at '*virt' and 1226 * update '*virt' with the first usable address after the mapped 1227 * region. 1228 */ 1229vm_offset_t 1230pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) 1231{ 1232 vm_offset_t va, sva; 1233 1234 va = sva = *virt; 1235 CTR4(KTR_PMAP, "pmap_map: va=0x%x start=0x%jx end=0x%jx prot=0x%x", 1236 va, start, end, prot); 1237 while (start < end) { 1238 pmap_kenter(va, start); 1239 va += PAGE_SIZE; 1240 start += PAGE_SIZE; 1241 } 1242 pmap_invalidate_range(kernel_pmap, sva, va); 1243 *virt = va; 1244 return (sva); 1245} 1246 1247 1248/* 1249 * Add a list of wired pages to the kva 1250 * this routine is only used for temporary 1251 * kernel mappings that do not need to have 1252 * page modification or references recorded. 1253 * Note that old mappings are simply written 1254 * over. The page *must* be wired. 1255 * Note: SMP coherent. Uses a ranged shootdown IPI. 1256 */ 1257void 1258pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count) 1259{ 1260 pt_entry_t *endpte, *pte; 1261 vm_paddr_t pa; 1262 vm_offset_t va = sva; 1263 int mclcount = 0; 1264 multicall_entry_t mcl[16]; 1265 multicall_entry_t *mclp = mcl; 1266 int error; 1267 1268 CTR2(KTR_PMAP, "pmap_qenter:sva=0x%x count=%d", va, count); 1269 pte = vtopte(sva); 1270 endpte = pte + count; 1271 while (pte < endpte) { 1272 pa = VM_PAGE_TO_MACH(*ma) | pgeflag | PG_RW | PG_V | PG_M | PG_A; 1273 1274 mclp->op = __HYPERVISOR_update_va_mapping; 1275 mclp->args[0] = va; 1276 mclp->args[1] = (uint32_t)(pa & 0xffffffff); 1277 mclp->args[2] = (uint32_t)(pa >> 32); 1278 mclp->args[3] = (*pte & PG_V) ? UVMF_INVLPG|UVMF_ALL : 0; 1279 1280 va += PAGE_SIZE; 1281 pte++; 1282 ma++; 1283 mclp++; 1284 mclcount++; 1285 if (mclcount == 16) { 1286 error = HYPERVISOR_multicall(mcl, mclcount); 1287 mclp = mcl; 1288 mclcount = 0; 1289 KASSERT(error == 0, ("bad multicall %d", error)); 1290 } 1291 } 1292 if (mclcount) { 1293 error = HYPERVISOR_multicall(mcl, mclcount); 1294 KASSERT(error == 0, ("bad multicall %d", error)); 1295 } 1296 1297#ifdef INVARIANTS 1298 for (pte = vtopte(sva), mclcount = 0; mclcount < count; mclcount++, pte++) 1299 KASSERT(*pte, ("pte not set for va=0x%x", sva + mclcount*PAGE_SIZE)); 1300#endif 1301} 1302 1303/* 1304 * This routine tears out page mappings from the 1305 * kernel -- it is meant only for temporary mappings. 1306 * Note: SMP coherent. Uses a ranged shootdown IPI. 1307 */ 1308void 1309pmap_qremove(vm_offset_t sva, int count) 1310{ 1311 vm_offset_t va; 1312 1313 CTR2(KTR_PMAP, "pmap_qremove: sva=0x%x count=%d", sva, count); 1314 va = sva; 1315 rw_wlock(&pvh_global_lock); 1316 critical_enter(); 1317 while (count-- > 0) { 1318 pmap_kremove(va); 1319 va += PAGE_SIZE; 1320 } 1321 PT_UPDATES_FLUSH(); 1322 pmap_invalidate_range(kernel_pmap, sva, va); 1323 critical_exit(); 1324 rw_wunlock(&pvh_global_lock); 1325} 1326 1327/*************************************************** 1328 * Page table page management routines..... 1329 ***************************************************/ 1330static __inline void 1331pmap_free_zero_pages(vm_page_t free) 1332{ 1333 vm_page_t m; 1334 1335 while (free != NULL) { 1336 m = free; 1337 free = (void *)m->object; 1338 m->object = NULL; 1339 vm_page_free_zero(m); 1340 } 1341} 1342 1343/* 1344 * Decrements a page table page's wire count, which is used to record the 1345 * number of valid page table entries within the page. If the wire count 1346 * drops to zero, then the page table page is unmapped. Returns TRUE if the 1347 * page table page was unmapped and FALSE otherwise. 1348 */ 1349static inline boolean_t 1350pmap_unwire_ptp(pmap_t pmap, vm_page_t m, vm_page_t *free) 1351{ 1352 1353 --m->wire_count; 1354 if (m->wire_count == 0) { 1355 _pmap_unwire_ptp(pmap, m, free); 1356 return (TRUE); 1357 } else 1358 return (FALSE); 1359} 1360 1361static void 1362_pmap_unwire_ptp(pmap_t pmap, vm_page_t m, vm_page_t *free) 1363{ 1364 vm_offset_t pteva; 1365 1366 PT_UPDATES_FLUSH(); 1367 /* 1368 * unmap the page table page 1369 */ 1370 xen_pt_unpin(pmap->pm_pdir[m->pindex]); 1371 /* 1372 * page *might* contain residual mapping :-/ 1373 */ 1374 PD_CLEAR_VA(pmap, m->pindex, TRUE); 1375 pmap_zero_page(m); 1376 --pmap->pm_stats.resident_count; 1377 1378 /* 1379 * This is a release store so that the ordinary store unmapping 1380 * the page table page is globally performed before TLB shoot- 1381 * down is begun. 1382 */ 1383 atomic_subtract_rel_int(&cnt.v_wire_count, 1); 1384 1385 /* 1386 * Do an invltlb to make the invalidated mapping 1387 * take effect immediately. 1388 */ 1389 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex); 1390 pmap_invalidate_page(pmap, pteva); 1391 1392 /* 1393 * Put page on a list so that it is released after 1394 * *ALL* TLB shootdown is done 1395 */ 1396 m->object = (void *)*free; 1397 *free = m; 1398} 1399 1400/* 1401 * After removing a page table entry, this routine is used to 1402 * conditionally free the page, and manage the hold/wire counts. 1403 */ 1404static int 1405pmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t *free) 1406{ 1407 pd_entry_t ptepde; 1408 vm_page_t mpte; 1409 1410 if (va >= VM_MAXUSER_ADDRESS) 1411 return (0); 1412 ptepde = PT_GET(pmap_pde(pmap, va)); 1413 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME); 1414 return (pmap_unwire_ptp(pmap, mpte, free)); 1415} 1416 1417/* 1418 * Initialize the pmap for the swapper process. 1419 */ 1420void 1421pmap_pinit0(pmap_t pmap) 1422{ 1423 1424 PMAP_LOCK_INIT(pmap); 1425 /* 1426 * Since the page table directory is shared with the kernel pmap, 1427 * which is already included in the list "allpmaps", this pmap does 1428 * not need to be inserted into that list. 1429 */ 1430 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD); 1431#ifdef PAE 1432 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT); 1433#endif 1434 CPU_ZERO(&pmap->pm_active); 1435 PCPU_SET(curpmap, pmap); 1436 TAILQ_INIT(&pmap->pm_pvchunk); 1437 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1438} 1439 1440/* 1441 * Initialize a preallocated and zeroed pmap structure, 1442 * such as one in a vmspace structure. 1443 */ 1444int 1445pmap_pinit(pmap_t pmap) 1446{ 1447 vm_page_t m, ptdpg[NPGPTD + 1]; 1448 int npgptd = NPGPTD + 1; 1449 int i; 1450 1451#ifdef HAMFISTED_LOCKING 1452 mtx_lock(&createdelete_lock); 1453#endif 1454 1455 /* 1456 * No need to allocate page table space yet but we do need a valid 1457 * page directory table. 1458 */ 1459 if (pmap->pm_pdir == NULL) { 1460 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD); 1461 if (pmap->pm_pdir == NULL) { 1462 PMAP_LOCK_DESTROY(pmap); 1463#ifdef HAMFISTED_LOCKING 1464 mtx_unlock(&createdelete_lock); 1465#endif 1466 return (0); 1467 } 1468#ifdef PAE 1469 pmap->pm_pdpt = (pd_entry_t *)kva_alloc(1); 1470#endif 1471 } 1472 1473 /* 1474 * allocate the page directory page(s) 1475 */ 1476 for (i = 0; i < npgptd;) { 1477 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | 1478 VM_ALLOC_WIRED | VM_ALLOC_ZERO); 1479 if (m == NULL) 1480 VM_WAIT; 1481 else { 1482 ptdpg[i++] = m; 1483 } 1484 } 1485 1486 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD); 1487 1488 for (i = 0; i < NPGPTD; i++) 1489 if ((ptdpg[i]->flags & PG_ZERO) == 0) 1490 pagezero(pmap->pm_pdir + (i * NPDEPG)); 1491 1492 mtx_lock_spin(&allpmaps_lock); 1493 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1494 /* Copy the kernel page table directory entries. */ 1495 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t)); 1496 mtx_unlock_spin(&allpmaps_lock); 1497 1498#ifdef PAE 1499 pmap_qenter((vm_offset_t)pmap->pm_pdpt, &ptdpg[NPGPTD], 1); 1500 if ((ptdpg[NPGPTD]->flags & PG_ZERO) == 0) 1501 bzero(pmap->pm_pdpt, PAGE_SIZE); 1502 for (i = 0; i < NPGPTD; i++) { 1503 vm_paddr_t ma; 1504 1505 ma = VM_PAGE_TO_MACH(ptdpg[i]); 1506 pmap->pm_pdpt[i] = ma | PG_V; 1507 1508 } 1509#endif 1510 for (i = 0; i < NPGPTD; i++) { 1511 pt_entry_t *pd; 1512 vm_paddr_t ma; 1513 1514 ma = VM_PAGE_TO_MACH(ptdpg[i]); 1515 pd = pmap->pm_pdir + (i * NPDEPG); 1516 PT_SET_MA(pd, *vtopte((vm_offset_t)pd) & ~(PG_M|PG_A|PG_U|PG_RW)); 1517#if 0 1518 xen_pgd_pin(ma); 1519#endif 1520 } 1521 1522#ifdef PAE 1523 PT_SET_MA(pmap->pm_pdpt, *vtopte((vm_offset_t)pmap->pm_pdpt) & ~PG_RW); 1524#endif 1525 rw_wlock(&pvh_global_lock); 1526 xen_flush_queue(); 1527 xen_pgdpt_pin(VM_PAGE_TO_MACH(ptdpg[NPGPTD])); 1528 for (i = 0; i < NPGPTD; i++) { 1529 vm_paddr_t ma = VM_PAGE_TO_MACH(ptdpg[i]); 1530 PT_SET_VA_MA(&pmap->pm_pdir[PTDPTDI + i], ma | PG_V | PG_A, FALSE); 1531 } 1532 xen_flush_queue(); 1533 rw_wunlock(&pvh_global_lock); 1534 CPU_ZERO(&pmap->pm_active); 1535 TAILQ_INIT(&pmap->pm_pvchunk); 1536 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1537 1538#ifdef HAMFISTED_LOCKING 1539 mtx_unlock(&createdelete_lock); 1540#endif 1541 return (1); 1542} 1543 1544/* 1545 * this routine is called if the page table page is not 1546 * mapped correctly. 1547 */ 1548static vm_page_t 1549_pmap_allocpte(pmap_t pmap, u_int ptepindex, int flags) 1550{ 1551 vm_paddr_t ptema; 1552 vm_page_t m; 1553 1554 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1555 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1556 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1557 1558 /* 1559 * Allocate a page table page. 1560 */ 1561 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ | 1562 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) { 1563 if (flags & M_WAITOK) { 1564 PMAP_UNLOCK(pmap); 1565 rw_wunlock(&pvh_global_lock); 1566 VM_WAIT; 1567 rw_wlock(&pvh_global_lock); 1568 PMAP_LOCK(pmap); 1569 } 1570 1571 /* 1572 * Indicate the need to retry. While waiting, the page table 1573 * page may have been allocated. 1574 */ 1575 return (NULL); 1576 } 1577 if ((m->flags & PG_ZERO) == 0) 1578 pmap_zero_page(m); 1579 1580 /* 1581 * Map the pagetable page into the process address space, if 1582 * it isn't already there. 1583 */ 1584 1585 pmap->pm_stats.resident_count++; 1586 1587 ptema = VM_PAGE_TO_MACH(m); 1588 xen_pt_pin(ptema); 1589 PT_SET_VA_MA(&pmap->pm_pdir[ptepindex], 1590 (ptema | PG_U | PG_RW | PG_V | PG_A | PG_M), TRUE); 1591 1592 KASSERT(pmap->pm_pdir[ptepindex], 1593 ("_pmap_allocpte: ptepindex=%d did not get mapped", ptepindex)); 1594 return (m); 1595} 1596 1597static vm_page_t 1598pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags) 1599{ 1600 u_int ptepindex; 1601 pd_entry_t ptema; 1602 vm_page_t m; 1603 1604 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1605 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1606 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1607 1608 /* 1609 * Calculate pagetable page index 1610 */ 1611 ptepindex = va >> PDRSHIFT; 1612retry: 1613 /* 1614 * Get the page directory entry 1615 */ 1616 ptema = pmap->pm_pdir[ptepindex]; 1617 1618 /* 1619 * This supports switching from a 4MB page to a 1620 * normal 4K page. 1621 */ 1622 if (ptema & PG_PS) { 1623 /* 1624 * XXX 1625 */ 1626 pmap->pm_pdir[ptepindex] = 0; 1627 ptema = 0; 1628 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 1629 pmap_invalidate_all(kernel_pmap); 1630 } 1631 1632 /* 1633 * If the page table page is mapped, we just increment the 1634 * hold count, and activate it. 1635 */ 1636 if (ptema & PG_V) { 1637 m = PHYS_TO_VM_PAGE(xpmap_mtop(ptema) & PG_FRAME); 1638 m->wire_count++; 1639 } else { 1640 /* 1641 * Here if the pte page isn't mapped, or if it has 1642 * been deallocated. 1643 */ 1644 CTR3(KTR_PMAP, "pmap_allocpte: pmap=%p va=0x%08x flags=0x%x", 1645 pmap, va, flags); 1646 m = _pmap_allocpte(pmap, ptepindex, flags); 1647 if (m == NULL && (flags & M_WAITOK)) 1648 goto retry; 1649 1650 KASSERT(pmap->pm_pdir[ptepindex], ("ptepindex=%d did not get mapped", ptepindex)); 1651 } 1652 return (m); 1653} 1654 1655 1656/*************************************************** 1657* Pmap allocation/deallocation routines. 1658 ***************************************************/ 1659 1660#ifdef SMP 1661/* 1662 * Deal with a SMP shootdown of other users of the pmap that we are 1663 * trying to dispose of. This can be a bit hairy. 1664 */ 1665static cpuset_t *lazymask; 1666static u_int lazyptd; 1667static volatile u_int lazywait; 1668 1669void pmap_lazyfix_action(void); 1670 1671void 1672pmap_lazyfix_action(void) 1673{ 1674 1675#ifdef COUNT_IPIS 1676 (*ipi_lazypmap_counts[PCPU_GET(cpuid)])++; 1677#endif 1678 if (rcr3() == lazyptd) 1679 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1680 CPU_CLR_ATOMIC(PCPU_GET(cpuid), lazymask); 1681 atomic_store_rel_int(&lazywait, 1); 1682} 1683 1684static void 1685pmap_lazyfix_self(u_int cpuid) 1686{ 1687 1688 if (rcr3() == lazyptd) 1689 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1690 CPU_CLR_ATOMIC(cpuid, lazymask); 1691} 1692 1693 1694static void 1695pmap_lazyfix(pmap_t pmap) 1696{ 1697 cpuset_t mymask, mask; 1698 u_int cpuid, spins; 1699 int lsb; 1700 1701 mask = pmap->pm_active; 1702 while (!CPU_EMPTY(&mask)) { 1703 spins = 50000000; 1704 1705 /* Find least significant set bit. */ 1706 lsb = CPU_FFS(&mask); 1707 MPASS(lsb != 0); 1708 lsb--; 1709 CPU_SETOF(lsb, &mask); 1710 mtx_lock_spin(&smp_ipi_mtx); 1711#ifdef PAE 1712 lazyptd = vtophys(pmap->pm_pdpt); 1713#else 1714 lazyptd = vtophys(pmap->pm_pdir); 1715#endif 1716 cpuid = PCPU_GET(cpuid); 1717 1718 /* Use a cpuset just for having an easy check. */ 1719 CPU_SETOF(cpuid, &mymask); 1720 if (!CPU_CMP(&mask, &mymask)) { 1721 lazymask = &pmap->pm_active; 1722 pmap_lazyfix_self(cpuid); 1723 } else { 1724 atomic_store_rel_int((u_int *)&lazymask, 1725 (u_int)&pmap->pm_active); 1726 atomic_store_rel_int(&lazywait, 0); 1727 ipi_selected(mask, IPI_LAZYPMAP); 1728 while (lazywait == 0) { 1729 ia32_pause(); 1730 if (--spins == 0) 1731 break; 1732 } 1733 } 1734 mtx_unlock_spin(&smp_ipi_mtx); 1735 if (spins == 0) 1736 printf("pmap_lazyfix: spun for 50000000\n"); 1737 mask = pmap->pm_active; 1738 } 1739} 1740 1741#else /* SMP */ 1742 1743/* 1744 * Cleaning up on uniprocessor is easy. For various reasons, we're 1745 * unlikely to have to even execute this code, including the fact 1746 * that the cleanup is deferred until the parent does a wait(2), which 1747 * means that another userland process has run. 1748 */ 1749static void 1750pmap_lazyfix(pmap_t pmap) 1751{ 1752 u_int cr3; 1753 1754 cr3 = vtophys(pmap->pm_pdir); 1755 if (cr3 == rcr3()) { 1756 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1757 CPU_CLR(PCPU_GET(cpuid), &pmap->pm_active); 1758 } 1759} 1760#endif /* SMP */ 1761 1762/* 1763 * Release any resources held by the given physical map. 1764 * Called when a pmap initialized by pmap_pinit is being released. 1765 * Should only be called if the map contains no valid mappings. 1766 */ 1767void 1768pmap_release(pmap_t pmap) 1769{ 1770 vm_page_t m, ptdpg[2*NPGPTD+1]; 1771 vm_paddr_t ma; 1772 int i; 1773#ifdef PAE 1774 int npgptd = NPGPTD + 1; 1775#else 1776 int npgptd = NPGPTD; 1777#endif 1778 1779 KASSERT(pmap->pm_stats.resident_count == 0, 1780 ("pmap_release: pmap resident count %ld != 0", 1781 pmap->pm_stats.resident_count)); 1782 PT_UPDATES_FLUSH(); 1783 1784#ifdef HAMFISTED_LOCKING 1785 mtx_lock(&createdelete_lock); 1786#endif 1787 1788 pmap_lazyfix(pmap); 1789 mtx_lock_spin(&allpmaps_lock); 1790 LIST_REMOVE(pmap, pm_list); 1791 mtx_unlock_spin(&allpmaps_lock); 1792 1793 for (i = 0; i < NPGPTD; i++) 1794 ptdpg[i] = PHYS_TO_VM_PAGE(vtophys(pmap->pm_pdir + (i*NPDEPG)) & PG_FRAME); 1795 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD); 1796#ifdef PAE 1797 ptdpg[NPGPTD] = PHYS_TO_VM_PAGE(vtophys(pmap->pm_pdpt)); 1798#endif 1799 1800 for (i = 0; i < npgptd; i++) { 1801 m = ptdpg[i]; 1802 ma = VM_PAGE_TO_MACH(m); 1803 /* unpinning L1 and L2 treated the same */ 1804#if 0 1805 xen_pgd_unpin(ma); 1806#else 1807 if (i == NPGPTD) 1808 xen_pgd_unpin(ma); 1809#endif 1810#ifdef PAE 1811 if (i < NPGPTD) 1812 KASSERT(VM_PAGE_TO_MACH(m) == (pmap->pm_pdpt[i] & PG_FRAME), 1813 ("pmap_release: got wrong ptd page")); 1814#endif 1815 m->wire_count--; 1816 atomic_subtract_int(&cnt.v_wire_count, 1); 1817 vm_page_free(m); 1818 } 1819#ifdef PAE 1820 pmap_qremove((vm_offset_t)pmap->pm_pdpt, 1); 1821#endif 1822 1823#ifdef HAMFISTED_LOCKING 1824 mtx_unlock(&createdelete_lock); 1825#endif 1826} 1827 1828static int 1829kvm_size(SYSCTL_HANDLER_ARGS) 1830{ 1831 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE; 1832 1833 return (sysctl_handle_long(oidp, &ksize, 0, req)); 1834} 1835SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD, 1836 0, 0, kvm_size, "IU", "Size of KVM"); 1837 1838static int 1839kvm_free(SYSCTL_HANDLER_ARGS) 1840{ 1841 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end; 1842 1843 return (sysctl_handle_long(oidp, &kfree, 0, req)); 1844} 1845SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD, 1846 0, 0, kvm_free, "IU", "Amount of KVM free"); 1847 1848/* 1849 * grow the number of kernel page table entries, if needed 1850 */ 1851void 1852pmap_growkernel(vm_offset_t addr) 1853{ 1854 struct pmap *pmap; 1855 vm_paddr_t ptppaddr; 1856 vm_page_t nkpg; 1857 pd_entry_t newpdir; 1858 1859 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 1860 if (kernel_vm_end == 0) { 1861 kernel_vm_end = KERNBASE; 1862 nkpt = 0; 1863 while (pdir_pde(PTD, kernel_vm_end)) { 1864 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1865 nkpt++; 1866 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1867 kernel_vm_end = kernel_map->max_offset; 1868 break; 1869 } 1870 } 1871 } 1872 addr = roundup2(addr, NBPDR); 1873 if (addr - 1 >= kernel_map->max_offset) 1874 addr = kernel_map->max_offset; 1875 while (kernel_vm_end < addr) { 1876 if (pdir_pde(PTD, kernel_vm_end)) { 1877 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 1878 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1879 kernel_vm_end = kernel_map->max_offset; 1880 break; 1881 } 1882 continue; 1883 } 1884 1885 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT, 1886 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 1887 VM_ALLOC_ZERO); 1888 if (nkpg == NULL) 1889 panic("pmap_growkernel: no memory to grow kernel"); 1890 1891 nkpt++; 1892 1893 if ((nkpg->flags & PG_ZERO) == 0) 1894 pmap_zero_page(nkpg); 1895 ptppaddr = VM_PAGE_TO_PHYS(nkpg); 1896 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M); 1897 rw_wlock(&pvh_global_lock); 1898 PD_SET_VA(kernel_pmap, (kernel_vm_end >> PDRSHIFT), newpdir, TRUE); 1899 mtx_lock_spin(&allpmaps_lock); 1900 LIST_FOREACH(pmap, &allpmaps, pm_list) 1901 PD_SET_VA(pmap, (kernel_vm_end >> PDRSHIFT), newpdir, TRUE); 1902 1903 mtx_unlock_spin(&allpmaps_lock); 1904 rw_wunlock(&pvh_global_lock); 1905 1906 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 1907 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1908 kernel_vm_end = kernel_map->max_offset; 1909 break; 1910 } 1911 } 1912} 1913 1914 1915/*************************************************** 1916 * page management routines. 1917 ***************************************************/ 1918 1919CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE); 1920CTASSERT(_NPCM == 11); 1921CTASSERT(_NPCPV == 336); 1922 1923static __inline struct pv_chunk * 1924pv_to_chunk(pv_entry_t pv) 1925{ 1926 1927 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK)); 1928} 1929 1930#define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap) 1931 1932#define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */ 1933#define PC_FREE10 0x0000fffful /* Free values for index 10 */ 1934 1935static const uint32_t pc_freemask[_NPCM] = { 1936 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1937 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1938 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1939 PC_FREE0_9, PC_FREE10 1940}; 1941 1942SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0, 1943 "Current number of pv entries"); 1944 1945#ifdef PV_STATS 1946static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail; 1947 1948SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0, 1949 "Current number of pv entry chunks"); 1950SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0, 1951 "Current number of pv entry chunks allocated"); 1952SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0, 1953 "Current number of pv entry chunks frees"); 1954SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0, 1955 "Number of times tried to get a chunk page but failed."); 1956 1957static long pv_entry_frees, pv_entry_allocs; 1958static int pv_entry_spare; 1959 1960SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0, 1961 "Current number of pv entry frees"); 1962SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0, 1963 "Current number of pv entry allocs"); 1964SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0, 1965 "Current number of spare pv entries"); 1966#endif 1967 1968/* 1969 * We are in a serious low memory condition. Resort to 1970 * drastic measures to free some pages so we can allocate 1971 * another pv entry chunk. 1972 */ 1973static vm_page_t 1974pmap_pv_reclaim(pmap_t locked_pmap) 1975{ 1976 struct pch newtail; 1977 struct pv_chunk *pc; 1978 pmap_t pmap; 1979 pt_entry_t *pte, tpte; 1980 pv_entry_t pv; 1981 vm_offset_t va; 1982 vm_page_t free, m, m_pc; 1983 uint32_t inuse; 1984 int bit, field, freed; 1985 1986 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED); 1987 pmap = NULL; 1988 free = m_pc = NULL; 1989 TAILQ_INIT(&newtail); 1990 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 || 1991 free == NULL)) { 1992 TAILQ_REMOVE(&pv_chunks, pc, pc_lru); 1993 if (pmap != pc->pc_pmap) { 1994 if (pmap != NULL) { 1995 pmap_invalidate_all(pmap); 1996 if (pmap != locked_pmap) 1997 PMAP_UNLOCK(pmap); 1998 } 1999 pmap = pc->pc_pmap; 2000 /* Avoid deadlock and lock recursion. */ 2001 if (pmap > locked_pmap) 2002 PMAP_LOCK(pmap); 2003 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) { 2004 pmap = NULL; 2005 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 2006 continue; 2007 } 2008 } 2009 2010 /* 2011 * Destroy every non-wired, 4 KB page mapping in the chunk. 2012 */ 2013 freed = 0; 2014 for (field = 0; field < _NPCM; field++) { 2015 for (inuse = ~pc->pc_map[field] & pc_freemask[field]; 2016 inuse != 0; inuse &= ~(1UL << bit)) { 2017 bit = bsfl(inuse); 2018 pv = &pc->pc_pventry[field * 32 + bit]; 2019 va = pv->pv_va; 2020 pte = pmap_pte(pmap, va); 2021 tpte = *pte; 2022 if ((tpte & PG_W) == 0) 2023 tpte = pte_load_clear(pte); 2024 pmap_pte_release(pte); 2025 if ((tpte & PG_W) != 0) 2026 continue; 2027 KASSERT(tpte != 0, 2028 ("pmap_pv_reclaim: pmap %p va %x zero pte", 2029 pmap, va)); 2030 if ((tpte & PG_G) != 0) 2031 pmap_invalidate_page(pmap, va); 2032 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 2033 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2034 vm_page_dirty(m); 2035 if ((tpte & PG_A) != 0) 2036 vm_page_aflag_set(m, PGA_REFERENCED); 2037 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 2038 if (TAILQ_EMPTY(&m->md.pv_list)) 2039 vm_page_aflag_clear(m, PGA_WRITEABLE); 2040 pc->pc_map[field] |= 1UL << bit; 2041 pmap_unuse_pt(pmap, va, &free); 2042 freed++; 2043 } 2044 } 2045 if (freed == 0) { 2046 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 2047 continue; 2048 } 2049 /* Every freed mapping is for a 4 KB page. */ 2050 pmap->pm_stats.resident_count -= freed; 2051 PV_STAT(pv_entry_frees += freed); 2052 PV_STAT(pv_entry_spare += freed); 2053 pv_entry_count -= freed; 2054 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2055 for (field = 0; field < _NPCM; field++) 2056 if (pc->pc_map[field] != pc_freemask[field]) { 2057 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, 2058 pc_list); 2059 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 2060 2061 /* 2062 * One freed pv entry in locked_pmap is 2063 * sufficient. 2064 */ 2065 if (pmap == locked_pmap) 2066 goto out; 2067 break; 2068 } 2069 if (field == _NPCM) { 2070 PV_STAT(pv_entry_spare -= _NPCPV); 2071 PV_STAT(pc_chunk_count--); 2072 PV_STAT(pc_chunk_frees++); 2073 /* Entire chunk is free; return it. */ 2074 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 2075 pmap_qremove((vm_offset_t)pc, 1); 2076 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 2077 break; 2078 } 2079 } 2080out: 2081 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru); 2082 if (pmap != NULL) { 2083 pmap_invalidate_all(pmap); 2084 if (pmap != locked_pmap) 2085 PMAP_UNLOCK(pmap); 2086 } 2087 if (m_pc == NULL && pv_vafree != 0 && free != NULL) { 2088 m_pc = free; 2089 free = (void *)m_pc->object; 2090 /* Recycle a freed page table page. */ 2091 m_pc->wire_count = 1; 2092 atomic_add_int(&cnt.v_wire_count, 1); 2093 } 2094 pmap_free_zero_pages(free); 2095 return (m_pc); 2096} 2097 2098/* 2099 * free the pv_entry back to the free list 2100 */ 2101static void 2102free_pv_entry(pmap_t pmap, pv_entry_t pv) 2103{ 2104 struct pv_chunk *pc; 2105 int idx, field, bit; 2106 2107 rw_assert(&pvh_global_lock, RA_WLOCKED); 2108 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2109 PV_STAT(pv_entry_frees++); 2110 PV_STAT(pv_entry_spare++); 2111 pv_entry_count--; 2112 pc = pv_to_chunk(pv); 2113 idx = pv - &pc->pc_pventry[0]; 2114 field = idx / 32; 2115 bit = idx % 32; 2116 pc->pc_map[field] |= 1ul << bit; 2117 for (idx = 0; idx < _NPCM; idx++) 2118 if (pc->pc_map[idx] != pc_freemask[idx]) { 2119 /* 2120 * 98% of the time, pc is already at the head of the 2121 * list. If it isn't already, move it to the head. 2122 */ 2123 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) != 2124 pc)) { 2125 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2126 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, 2127 pc_list); 2128 } 2129 return; 2130 } 2131 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2132 free_pv_chunk(pc); 2133} 2134 2135static void 2136free_pv_chunk(struct pv_chunk *pc) 2137{ 2138 vm_page_t m; 2139 2140 TAILQ_REMOVE(&pv_chunks, pc, pc_lru); 2141 PV_STAT(pv_entry_spare -= _NPCPV); 2142 PV_STAT(pc_chunk_count--); 2143 PV_STAT(pc_chunk_frees++); 2144 /* entire chunk is free, return it */ 2145 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 2146 pmap_qremove((vm_offset_t)pc, 1); 2147 vm_page_unwire(m, 0); 2148 vm_page_free(m); 2149 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 2150} 2151 2152/* 2153 * get a new pv_entry, allocating a block from the system 2154 * when needed. 2155 */ 2156static pv_entry_t 2157get_pv_entry(pmap_t pmap, boolean_t try) 2158{ 2159 static const struct timeval printinterval = { 60, 0 }; 2160 static struct timeval lastprint; 2161 int bit, field; 2162 pv_entry_t pv; 2163 struct pv_chunk *pc; 2164 vm_page_t m; 2165 2166 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2167 rw_assert(&pvh_global_lock, RA_WLOCKED); 2168 PV_STAT(pv_entry_allocs++); 2169 pv_entry_count++; 2170 if (pv_entry_count > pv_entry_high_water) 2171 if (ratecheck(&lastprint, &printinterval)) 2172 printf("Approaching the limit on PV entries, consider " 2173 "increasing either the vm.pmap.shpgperproc or the " 2174 "vm.pmap.pv_entry_max tunable.\n"); 2175retry: 2176 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 2177 if (pc != NULL) { 2178 for (field = 0; field < _NPCM; field++) { 2179 if (pc->pc_map[field]) { 2180 bit = bsfl(pc->pc_map[field]); 2181 break; 2182 } 2183 } 2184 if (field < _NPCM) { 2185 pv = &pc->pc_pventry[field * 32 + bit]; 2186 pc->pc_map[field] &= ~(1ul << bit); 2187 /* If this was the last item, move it to tail */ 2188 for (field = 0; field < _NPCM; field++) 2189 if (pc->pc_map[field] != 0) { 2190 PV_STAT(pv_entry_spare--); 2191 return (pv); /* not full, return */ 2192 } 2193 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2194 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 2195 PV_STAT(pv_entry_spare--); 2196 return (pv); 2197 } 2198 } 2199 /* 2200 * Access to the ptelist "pv_vafree" is synchronized by the page 2201 * queues lock. If "pv_vafree" is currently non-empty, it will 2202 * remain non-empty until pmap_ptelist_alloc() completes. 2203 */ 2204 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | 2205 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 2206 if (try) { 2207 pv_entry_count--; 2208 PV_STAT(pc_chunk_tryfail++); 2209 return (NULL); 2210 } 2211 m = pmap_pv_reclaim(pmap); 2212 if (m == NULL) 2213 goto retry; 2214 } 2215 PV_STAT(pc_chunk_count++); 2216 PV_STAT(pc_chunk_allocs++); 2217 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree); 2218 pmap_qenter((vm_offset_t)pc, &m, 1); 2219 if ((m->flags & PG_ZERO) == 0) 2220 pagezero(pc); 2221 pc->pc_pmap = pmap; 2222 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */ 2223 for (field = 1; field < _NPCM; field++) 2224 pc->pc_map[field] = pc_freemask[field]; 2225 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru); 2226 pv = &pc->pc_pventry[0]; 2227 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2228 PV_STAT(pv_entry_spare += _NPCPV - 1); 2229 return (pv); 2230} 2231 2232static __inline pv_entry_t 2233pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2234{ 2235 pv_entry_t pv; 2236 2237 rw_assert(&pvh_global_lock, RA_WLOCKED); 2238 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 2239 if (pmap == PV_PMAP(pv) && va == pv->pv_va) { 2240 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next); 2241 break; 2242 } 2243 } 2244 return (pv); 2245} 2246 2247static void 2248pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2249{ 2250 pv_entry_t pv; 2251 2252 pv = pmap_pvh_remove(pvh, pmap, va); 2253 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found")); 2254 free_pv_entry(pmap, pv); 2255} 2256 2257static void 2258pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va) 2259{ 2260 2261 rw_assert(&pvh_global_lock, RA_WLOCKED); 2262 pmap_pvh_free(&m->md, pmap, va); 2263 if (TAILQ_EMPTY(&m->md.pv_list)) 2264 vm_page_aflag_clear(m, PGA_WRITEABLE); 2265} 2266 2267/* 2268 * Conditionally create a pv entry. 2269 */ 2270static boolean_t 2271pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2272{ 2273 pv_entry_t pv; 2274 2275 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2276 rw_assert(&pvh_global_lock, RA_WLOCKED); 2277 if (pv_entry_count < pv_entry_high_water && 2278 (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2279 pv->pv_va = va; 2280 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 2281 return (TRUE); 2282 } else 2283 return (FALSE); 2284} 2285 2286/* 2287 * pmap_remove_pte: do the things to unmap a page in a process 2288 */ 2289static int 2290pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va, vm_page_t *free) 2291{ 2292 pt_entry_t oldpte; 2293 vm_page_t m; 2294 2295 CTR3(KTR_PMAP, "pmap_remove_pte: pmap=%p *ptq=0x%x va=0x%x", 2296 pmap, (u_long)*ptq, va); 2297 2298 rw_assert(&pvh_global_lock, RA_WLOCKED); 2299 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2300 oldpte = *ptq; 2301 PT_SET_VA_MA(ptq, 0, TRUE); 2302 KASSERT(oldpte != 0, 2303 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va)); 2304 if (oldpte & PG_W) 2305 pmap->pm_stats.wired_count -= 1; 2306 /* 2307 * Machines that don't support invlpg, also don't support 2308 * PG_G. 2309 */ 2310 if (oldpte & PG_G) 2311 pmap_invalidate_page(kernel_pmap, va); 2312 pmap->pm_stats.resident_count -= 1; 2313 if (oldpte & PG_MANAGED) { 2314 m = PHYS_TO_VM_PAGE(xpmap_mtop(oldpte) & PG_FRAME); 2315 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2316 vm_page_dirty(m); 2317 if (oldpte & PG_A) 2318 vm_page_aflag_set(m, PGA_REFERENCED); 2319 pmap_remove_entry(pmap, m, va); 2320 } 2321 return (pmap_unuse_pt(pmap, va, free)); 2322} 2323 2324/* 2325 * Remove a single page from a process address space 2326 */ 2327static void 2328pmap_remove_page(pmap_t pmap, vm_offset_t va, vm_page_t *free) 2329{ 2330 pt_entry_t *pte; 2331 2332 CTR2(KTR_PMAP, "pmap_remove_page: pmap=%p va=0x%x", 2333 pmap, va); 2334 2335 rw_assert(&pvh_global_lock, RA_WLOCKED); 2336 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 2337 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2338 if ((pte = pmap_pte_quick(pmap, va)) == NULL || (*pte & PG_V) == 0) 2339 return; 2340 pmap_remove_pte(pmap, pte, va, free); 2341 pmap_invalidate_page(pmap, va); 2342 if (*PMAP1) 2343 PT_SET_MA(PADDR1, 0); 2344 2345} 2346 2347/* 2348 * Remove the given range of addresses from the specified map. 2349 * 2350 * It is assumed that the start and end are properly 2351 * rounded to the page size. 2352 */ 2353void 2354pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2355{ 2356 vm_offset_t pdnxt; 2357 pd_entry_t ptpaddr; 2358 pt_entry_t *pte; 2359 vm_page_t free = NULL; 2360 int anyvalid; 2361 2362 CTR3(KTR_PMAP, "pmap_remove: pmap=%p sva=0x%x eva=0x%x", 2363 pmap, sva, eva); 2364 2365 /* 2366 * Perform an unsynchronized read. This is, however, safe. 2367 */ 2368 if (pmap->pm_stats.resident_count == 0) 2369 return; 2370 2371 anyvalid = 0; 2372 2373 rw_wlock(&pvh_global_lock); 2374 sched_pin(); 2375 PMAP_LOCK(pmap); 2376 2377 /* 2378 * special handling of removing one page. a very 2379 * common operation and easy to short circuit some 2380 * code. 2381 */ 2382 if ((sva + PAGE_SIZE == eva) && 2383 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) { 2384 pmap_remove_page(pmap, sva, &free); 2385 goto out; 2386 } 2387 2388 for (; sva < eva; sva = pdnxt) { 2389 u_int pdirindex; 2390 2391 /* 2392 * Calculate index for next page table. 2393 */ 2394 pdnxt = (sva + NBPDR) & ~PDRMASK; 2395 if (pdnxt < sva) 2396 pdnxt = eva; 2397 if (pmap->pm_stats.resident_count == 0) 2398 break; 2399 2400 pdirindex = sva >> PDRSHIFT; 2401 ptpaddr = pmap->pm_pdir[pdirindex]; 2402 2403 /* 2404 * Weed out invalid mappings. Note: we assume that the page 2405 * directory table is always allocated, and in kernel virtual. 2406 */ 2407 if (ptpaddr == 0) 2408 continue; 2409 2410 /* 2411 * Check for large page. 2412 */ 2413 if ((ptpaddr & PG_PS) != 0) { 2414 PD_CLEAR_VA(pmap, pdirindex, TRUE); 2415 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 2416 anyvalid = 1; 2417 continue; 2418 } 2419 2420 /* 2421 * Limit our scan to either the end of the va represented 2422 * by the current page table page, or to the end of the 2423 * range being removed. 2424 */ 2425 if (pdnxt > eva) 2426 pdnxt = eva; 2427 2428 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2429 sva += PAGE_SIZE) { 2430 if ((*pte & PG_V) == 0) 2431 continue; 2432 2433 /* 2434 * The TLB entry for a PG_G mapping is invalidated 2435 * by pmap_remove_pte(). 2436 */ 2437 if ((*pte & PG_G) == 0) 2438 anyvalid = 1; 2439 if (pmap_remove_pte(pmap, pte, sva, &free)) 2440 break; 2441 } 2442 } 2443 PT_UPDATES_FLUSH(); 2444 if (*PMAP1) 2445 PT_SET_VA_MA(PMAP1, 0, TRUE); 2446out: 2447 if (anyvalid) 2448 pmap_invalidate_all(pmap); 2449 sched_unpin(); 2450 rw_wunlock(&pvh_global_lock); 2451 PMAP_UNLOCK(pmap); 2452 pmap_free_zero_pages(free); 2453} 2454 2455/* 2456 * Routine: pmap_remove_all 2457 * Function: 2458 * Removes this physical page from 2459 * all physical maps in which it resides. 2460 * Reflects back modify bits to the pager. 2461 * 2462 * Notes: 2463 * Original versions of this routine were very 2464 * inefficient because they iteratively called 2465 * pmap_remove (slow...) 2466 */ 2467 2468void 2469pmap_remove_all(vm_page_t m) 2470{ 2471 pv_entry_t pv; 2472 pmap_t pmap; 2473 pt_entry_t *pte, tpte; 2474 vm_page_t free; 2475 2476 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2477 ("pmap_remove_all: page %p is not managed", m)); 2478 free = NULL; 2479 rw_wlock(&pvh_global_lock); 2480 sched_pin(); 2481 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 2482 pmap = PV_PMAP(pv); 2483 PMAP_LOCK(pmap); 2484 pmap->pm_stats.resident_count--; 2485 pte = pmap_pte_quick(pmap, pv->pv_va); 2486 tpte = *pte; 2487 PT_SET_VA_MA(pte, 0, TRUE); 2488 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte", 2489 pmap, pv->pv_va)); 2490 if (tpte & PG_W) 2491 pmap->pm_stats.wired_count--; 2492 if (tpte & PG_A) 2493 vm_page_aflag_set(m, PGA_REFERENCED); 2494 2495 /* 2496 * Update the vm_page_t clean and reference bits. 2497 */ 2498 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2499 vm_page_dirty(m); 2500 pmap_unuse_pt(pmap, pv->pv_va, &free); 2501 pmap_invalidate_page(pmap, pv->pv_va); 2502 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 2503 free_pv_entry(pmap, pv); 2504 PMAP_UNLOCK(pmap); 2505 } 2506 vm_page_aflag_clear(m, PGA_WRITEABLE); 2507 PT_UPDATES_FLUSH(); 2508 if (*PMAP1) 2509 PT_SET_MA(PADDR1, 0); 2510 sched_unpin(); 2511 rw_wunlock(&pvh_global_lock); 2512 pmap_free_zero_pages(free); 2513} 2514 2515/* 2516 * Set the physical protection on the 2517 * specified range of this map as requested. 2518 */ 2519void 2520pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 2521{ 2522 vm_offset_t pdnxt; 2523 pd_entry_t ptpaddr; 2524 pt_entry_t *pte; 2525 int anychanged; 2526 2527 CTR4(KTR_PMAP, "pmap_protect: pmap=%p sva=0x%x eva=0x%x prot=0x%x", 2528 pmap, sva, eva, prot); 2529 2530 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2531 pmap_remove(pmap, sva, eva); 2532 return; 2533 } 2534 2535#ifdef PAE 2536 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) == 2537 (VM_PROT_WRITE|VM_PROT_EXECUTE)) 2538 return; 2539#else 2540 if (prot & VM_PROT_WRITE) 2541 return; 2542#endif 2543 2544 anychanged = 0; 2545 2546 rw_wlock(&pvh_global_lock); 2547 sched_pin(); 2548 PMAP_LOCK(pmap); 2549 for (; sva < eva; sva = pdnxt) { 2550 pt_entry_t obits, pbits; 2551 u_int pdirindex; 2552 2553 pdnxt = (sva + NBPDR) & ~PDRMASK; 2554 if (pdnxt < sva) 2555 pdnxt = eva; 2556 2557 pdirindex = sva >> PDRSHIFT; 2558 ptpaddr = pmap->pm_pdir[pdirindex]; 2559 2560 /* 2561 * Weed out invalid mappings. Note: we assume that the page 2562 * directory table is always allocated, and in kernel virtual. 2563 */ 2564 if (ptpaddr == 0) 2565 continue; 2566 2567 /* 2568 * Check for large page. 2569 */ 2570 if ((ptpaddr & PG_PS) != 0) { 2571 if ((prot & VM_PROT_WRITE) == 0) 2572 pmap->pm_pdir[pdirindex] &= ~(PG_M|PG_RW); 2573#ifdef PAE 2574 if ((prot & VM_PROT_EXECUTE) == 0) 2575 pmap->pm_pdir[pdirindex] |= pg_nx; 2576#endif 2577 anychanged = 1; 2578 continue; 2579 } 2580 2581 if (pdnxt > eva) 2582 pdnxt = eva; 2583 2584 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2585 sva += PAGE_SIZE) { 2586 vm_page_t m; 2587 2588retry: 2589 /* 2590 * Regardless of whether a pte is 32 or 64 bits in 2591 * size, PG_RW, PG_A, and PG_M are among the least 2592 * significant 32 bits. 2593 */ 2594 obits = pbits = *pte; 2595 if ((pbits & PG_V) == 0) 2596 continue; 2597 2598 if ((prot & VM_PROT_WRITE) == 0) { 2599 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) == 2600 (PG_MANAGED | PG_M | PG_RW)) { 2601 m = PHYS_TO_VM_PAGE(xpmap_mtop(pbits) & 2602 PG_FRAME); 2603 vm_page_dirty(m); 2604 } 2605 pbits &= ~(PG_RW | PG_M); 2606 } 2607#ifdef PAE 2608 if ((prot & VM_PROT_EXECUTE) == 0) 2609 pbits |= pg_nx; 2610#endif 2611 2612 if (pbits != obits) { 2613 obits = *pte; 2614 PT_SET_VA_MA(pte, pbits, TRUE); 2615 if (*pte != pbits) 2616 goto retry; 2617 if (obits & PG_G) 2618 pmap_invalidate_page(pmap, sva); 2619 else 2620 anychanged = 1; 2621 } 2622 } 2623 } 2624 PT_UPDATES_FLUSH(); 2625 if (*PMAP1) 2626 PT_SET_VA_MA(PMAP1, 0, TRUE); 2627 if (anychanged) 2628 pmap_invalidate_all(pmap); 2629 sched_unpin(); 2630 rw_wunlock(&pvh_global_lock); 2631 PMAP_UNLOCK(pmap); 2632} 2633 2634/* 2635 * Insert the given physical page (p) at 2636 * the specified virtual address (v) in the 2637 * target physical map with the protection requested. 2638 * 2639 * If specified, the page will be wired down, meaning 2640 * that the related pte can not be reclaimed. 2641 * 2642 * NB: This is the only routine which MAY NOT lazy-evaluate 2643 * or lose information. That is, this routine must actually 2644 * insert this page into the given map NOW. 2645 */ 2646void 2647pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 2648 vm_prot_t prot, boolean_t wired) 2649{ 2650 pd_entry_t *pde; 2651 pt_entry_t *pte; 2652 pt_entry_t newpte, origpte; 2653 pv_entry_t pv; 2654 vm_paddr_t opa, pa; 2655 vm_page_t mpte, om; 2656 boolean_t invlva; 2657 2658 CTR6(KTR_PMAP, "pmap_enter: pmap=%08p va=0x%08x access=0x%x ma=0x%08x prot=0x%x wired=%d", 2659 pmap, va, access, VM_PAGE_TO_MACH(m), prot, wired); 2660 va = trunc_page(va); 2661 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig")); 2662 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS, 2663 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)", 2664 va)); 2665 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 2666 VM_OBJECT_ASSERT_WLOCKED(m->object); 2667 2668 mpte = NULL; 2669 2670 rw_wlock(&pvh_global_lock); 2671 PMAP_LOCK(pmap); 2672 sched_pin(); 2673 2674 /* 2675 * In the case that a page table page is not 2676 * resident, we are creating it here. 2677 */ 2678 if (va < VM_MAXUSER_ADDRESS) { 2679 mpte = pmap_allocpte(pmap, va, M_WAITOK); 2680 } 2681 2682 pde = pmap_pde(pmap, va); 2683 if ((*pde & PG_PS) != 0) 2684 panic("pmap_enter: attempted pmap_enter on 4MB page"); 2685 pte = pmap_pte_quick(pmap, va); 2686 2687 /* 2688 * Page Directory table entry not valid, we need a new PT page 2689 */ 2690 if (pte == NULL) { 2691 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x", 2692 (uintmax_t)pmap->pm_pdir[va >> PDRSHIFT], va); 2693 } 2694 2695 pa = VM_PAGE_TO_PHYS(m); 2696 om = NULL; 2697 opa = origpte = 0; 2698 2699#if 0 2700 KASSERT((*pte & PG_V) || (*pte == 0), ("address set but not valid pte=%p *pte=0x%016jx", 2701 pte, *pte)); 2702#endif 2703 origpte = *pte; 2704 if (origpte) 2705 origpte = xpmap_mtop(origpte); 2706 opa = origpte & PG_FRAME; 2707 2708 /* 2709 * Mapping has not changed, must be protection or wiring change. 2710 */ 2711 if (origpte && (opa == pa)) { 2712 /* 2713 * Wiring change, just update stats. We don't worry about 2714 * wiring PT pages as they remain resident as long as there 2715 * are valid mappings in them. Hence, if a user page is wired, 2716 * the PT page will be also. 2717 */ 2718 if (wired && ((origpte & PG_W) == 0)) 2719 pmap->pm_stats.wired_count++; 2720 else if (!wired && (origpte & PG_W)) 2721 pmap->pm_stats.wired_count--; 2722 2723 /* 2724 * Remove extra pte reference 2725 */ 2726 if (mpte) 2727 mpte->wire_count--; 2728 2729 if (origpte & PG_MANAGED) { 2730 om = m; 2731 pa |= PG_MANAGED; 2732 } 2733 goto validate; 2734 } 2735 2736 pv = NULL; 2737 2738 /* 2739 * Mapping has changed, invalidate old range and fall through to 2740 * handle validating new mapping. 2741 */ 2742 if (opa) { 2743 if (origpte & PG_W) 2744 pmap->pm_stats.wired_count--; 2745 if (origpte & PG_MANAGED) { 2746 om = PHYS_TO_VM_PAGE(opa); 2747 pv = pmap_pvh_remove(&om->md, pmap, va); 2748 } else if (va < VM_MAXUSER_ADDRESS) 2749 printf("va=0x%x is unmanaged :-( \n", va); 2750 2751 if (mpte != NULL) { 2752 mpte->wire_count--; 2753 KASSERT(mpte->wire_count > 0, 2754 ("pmap_enter: missing reference to page table page," 2755 " va: 0x%x", va)); 2756 } 2757 } else 2758 pmap->pm_stats.resident_count++; 2759 2760 /* 2761 * Enter on the PV list if part of our managed memory. 2762 */ 2763 if ((m->oflags & VPO_UNMANAGED) == 0) { 2764 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 2765 ("pmap_enter: managed mapping within the clean submap")); 2766 if (pv == NULL) 2767 pv = get_pv_entry(pmap, FALSE); 2768 pv->pv_va = va; 2769 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 2770 pa |= PG_MANAGED; 2771 } else if (pv != NULL) 2772 free_pv_entry(pmap, pv); 2773 2774 /* 2775 * Increment counters 2776 */ 2777 if (wired) 2778 pmap->pm_stats.wired_count++; 2779 2780validate: 2781 /* 2782 * Now validate mapping with desired protection/wiring. 2783 */ 2784 newpte = (pt_entry_t)(pa | PG_V); 2785 if ((prot & VM_PROT_WRITE) != 0) { 2786 newpte |= PG_RW; 2787 if ((newpte & PG_MANAGED) != 0) 2788 vm_page_aflag_set(m, PGA_WRITEABLE); 2789 } 2790#ifdef PAE 2791 if ((prot & VM_PROT_EXECUTE) == 0) 2792 newpte |= pg_nx; 2793#endif 2794 if (wired) 2795 newpte |= PG_W; 2796 if (va < VM_MAXUSER_ADDRESS) 2797 newpte |= PG_U; 2798 if (pmap == kernel_pmap) 2799 newpte |= pgeflag; 2800 2801 critical_enter(); 2802 /* 2803 * if the mapping or permission bits are different, we need 2804 * to update the pte. 2805 */ 2806 if ((origpte & ~(PG_M|PG_A)) != newpte) { 2807 if (origpte) { 2808 invlva = FALSE; 2809 origpte = *pte; 2810 PT_SET_VA(pte, newpte | PG_A, FALSE); 2811 if (origpte & PG_A) { 2812 if (origpte & PG_MANAGED) 2813 vm_page_aflag_set(om, PGA_REFERENCED); 2814 if (opa != VM_PAGE_TO_PHYS(m)) 2815 invlva = TRUE; 2816#ifdef PAE 2817 if ((origpte & PG_NX) == 0 && 2818 (newpte & PG_NX) != 0) 2819 invlva = TRUE; 2820#endif 2821 } 2822 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 2823 if ((origpte & PG_MANAGED) != 0) 2824 vm_page_dirty(om); 2825 if ((prot & VM_PROT_WRITE) == 0) 2826 invlva = TRUE; 2827 } 2828 if ((origpte & PG_MANAGED) != 0 && 2829 TAILQ_EMPTY(&om->md.pv_list)) 2830 vm_page_aflag_clear(om, PGA_WRITEABLE); 2831 if (invlva) 2832 pmap_invalidate_page(pmap, va); 2833 } else{ 2834 PT_SET_VA(pte, newpte | PG_A, FALSE); 2835 } 2836 2837 } 2838 PT_UPDATES_FLUSH(); 2839 critical_exit(); 2840 if (*PMAP1) 2841 PT_SET_VA_MA(PMAP1, 0, TRUE); 2842 sched_unpin(); 2843 rw_wunlock(&pvh_global_lock); 2844 PMAP_UNLOCK(pmap); 2845} 2846 2847/* 2848 * Maps a sequence of resident pages belonging to the same object. 2849 * The sequence begins with the given page m_start. This page is 2850 * mapped at the given virtual address start. Each subsequent page is 2851 * mapped at a virtual address that is offset from start by the same 2852 * amount as the page is offset from m_start within the object. The 2853 * last page in the sequence is the page with the largest offset from 2854 * m_start that can be mapped at a virtual address less than the given 2855 * virtual address end. Not every virtual page between start and end 2856 * is mapped; only those for which a resident page exists with the 2857 * corresponding offset from m_start are mapped. 2858 */ 2859void 2860pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 2861 vm_page_t m_start, vm_prot_t prot) 2862{ 2863 vm_page_t m, mpte; 2864 vm_pindex_t diff, psize; 2865 multicall_entry_t mcl[16]; 2866 multicall_entry_t *mclp = mcl; 2867 int error, count = 0; 2868 2869 VM_OBJECT_ASSERT_LOCKED(m_start->object); 2870 2871 psize = atop(end - start); 2872 mpte = NULL; 2873 m = m_start; 2874 rw_wlock(&pvh_global_lock); 2875 PMAP_LOCK(pmap); 2876 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 2877 mpte = pmap_enter_quick_locked(&mclp, &count, pmap, start + ptoa(diff), m, 2878 prot, mpte); 2879 m = TAILQ_NEXT(m, listq); 2880 if (count == 16) { 2881 error = HYPERVISOR_multicall(mcl, count); 2882 KASSERT(error == 0, ("bad multicall %d", error)); 2883 mclp = mcl; 2884 count = 0; 2885 } 2886 } 2887 if (count) { 2888 error = HYPERVISOR_multicall(mcl, count); 2889 KASSERT(error == 0, ("bad multicall %d", error)); 2890 } 2891 rw_wunlock(&pvh_global_lock); 2892 PMAP_UNLOCK(pmap); 2893} 2894 2895/* 2896 * this code makes some *MAJOR* assumptions: 2897 * 1. Current pmap & pmap exists. 2898 * 2. Not wired. 2899 * 3. Read access. 2900 * 4. No page table pages. 2901 * but is *MUCH* faster than pmap_enter... 2902 */ 2903 2904void 2905pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 2906{ 2907 multicall_entry_t mcl, *mclp; 2908 int count = 0; 2909 mclp = &mcl; 2910 2911 CTR4(KTR_PMAP, "pmap_enter_quick: pmap=%p va=0x%x m=%p prot=0x%x", 2912 pmap, va, m, prot); 2913 2914 rw_wlock(&pvh_global_lock); 2915 PMAP_LOCK(pmap); 2916 (void)pmap_enter_quick_locked(&mclp, &count, pmap, va, m, prot, NULL); 2917 if (count) 2918 HYPERVISOR_multicall(&mcl, count); 2919 rw_wunlock(&pvh_global_lock); 2920 PMAP_UNLOCK(pmap); 2921} 2922 2923#ifdef notyet 2924void 2925pmap_enter_quick_range(pmap_t pmap, vm_offset_t *addrs, vm_page_t *pages, vm_prot_t *prots, int count) 2926{ 2927 int i, error, index = 0; 2928 multicall_entry_t mcl[16]; 2929 multicall_entry_t *mclp = mcl; 2930 2931 PMAP_LOCK(pmap); 2932 for (i = 0; i < count; i++, addrs++, pages++, prots++) { 2933 if (!pmap_is_prefaultable_locked(pmap, *addrs)) 2934 continue; 2935 2936 (void) pmap_enter_quick_locked(&mclp, &index, pmap, *addrs, *pages, *prots, NULL); 2937 if (index == 16) { 2938 error = HYPERVISOR_multicall(mcl, index); 2939 mclp = mcl; 2940 index = 0; 2941 KASSERT(error == 0, ("bad multicall %d", error)); 2942 } 2943 } 2944 if (index) { 2945 error = HYPERVISOR_multicall(mcl, index); 2946 KASSERT(error == 0, ("bad multicall %d", error)); 2947 } 2948 2949 PMAP_UNLOCK(pmap); 2950} 2951#endif 2952 2953static vm_page_t 2954pmap_enter_quick_locked(multicall_entry_t **mclpp, int *count, pmap_t pmap, vm_offset_t va, vm_page_t m, 2955 vm_prot_t prot, vm_page_t mpte) 2956{ 2957 pt_entry_t *pte; 2958 vm_paddr_t pa; 2959 vm_page_t free; 2960 multicall_entry_t *mcl = *mclpp; 2961 2962 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 2963 (m->oflags & VPO_UNMANAGED) != 0, 2964 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 2965 rw_assert(&pvh_global_lock, RA_WLOCKED); 2966 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2967 2968 /* 2969 * In the case that a page table page is not 2970 * resident, we are creating it here. 2971 */ 2972 if (va < VM_MAXUSER_ADDRESS) { 2973 u_int ptepindex; 2974 pd_entry_t ptema; 2975 2976 /* 2977 * Calculate pagetable page index 2978 */ 2979 ptepindex = va >> PDRSHIFT; 2980 if (mpte && (mpte->pindex == ptepindex)) { 2981 mpte->wire_count++; 2982 } else { 2983 /* 2984 * Get the page directory entry 2985 */ 2986 ptema = pmap->pm_pdir[ptepindex]; 2987 2988 /* 2989 * If the page table page is mapped, we just increment 2990 * the hold count, and activate it. 2991 */ 2992 if (ptema & PG_V) { 2993 if (ptema & PG_PS) 2994 panic("pmap_enter_quick: unexpected mapping into 4MB page"); 2995 mpte = PHYS_TO_VM_PAGE(xpmap_mtop(ptema) & PG_FRAME); 2996 mpte->wire_count++; 2997 } else { 2998 mpte = _pmap_allocpte(pmap, ptepindex, 2999 M_NOWAIT); 3000 if (mpte == NULL) 3001 return (mpte); 3002 } 3003 } 3004 } else { 3005 mpte = NULL; 3006 } 3007 3008 /* 3009 * This call to vtopte makes the assumption that we are 3010 * entering the page into the current pmap. In order to support 3011 * quick entry into any pmap, one would likely use pmap_pte_quick. 3012 * But that isn't as quick as vtopte. 3013 */ 3014 KASSERT(pmap_is_current(pmap), ("entering pages in non-current pmap")); 3015 pte = vtopte(va); 3016 if (*pte & PG_V) { 3017 if (mpte != NULL) { 3018 mpte->wire_count--; 3019 mpte = NULL; 3020 } 3021 return (mpte); 3022 } 3023 3024 /* 3025 * Enter on the PV list if part of our managed memory. 3026 */ 3027 if ((m->oflags & VPO_UNMANAGED) == 0 && 3028 !pmap_try_insert_pv_entry(pmap, va, m)) { 3029 if (mpte != NULL) { 3030 free = NULL; 3031 if (pmap_unwire_ptp(pmap, mpte, &free)) { 3032 pmap_invalidate_page(pmap, va); 3033 pmap_free_zero_pages(free); 3034 } 3035 3036 mpte = NULL; 3037 } 3038 return (mpte); 3039 } 3040 3041 /* 3042 * Increment counters 3043 */ 3044 pmap->pm_stats.resident_count++; 3045 3046 pa = VM_PAGE_TO_PHYS(m); 3047#ifdef PAE 3048 if ((prot & VM_PROT_EXECUTE) == 0) 3049 pa |= pg_nx; 3050#endif 3051 3052#if 0 3053 /* 3054 * Now validate mapping with RO protection 3055 */ 3056 if ((m->oflags & VPO_UNMANAGED) != 0) 3057 pte_store(pte, pa | PG_V | PG_U); 3058 else 3059 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED); 3060#else 3061 /* 3062 * Now validate mapping with RO protection 3063 */ 3064 if ((m->oflags & VPO_UNMANAGED) != 0) 3065 pa = xpmap_ptom(pa | PG_V | PG_U); 3066 else 3067 pa = xpmap_ptom(pa | PG_V | PG_U | PG_MANAGED); 3068 3069 mcl->op = __HYPERVISOR_update_va_mapping; 3070 mcl->args[0] = va; 3071 mcl->args[1] = (uint32_t)(pa & 0xffffffff); 3072 mcl->args[2] = (uint32_t)(pa >> 32); 3073 mcl->args[3] = 0; 3074 *mclpp = mcl + 1; 3075 *count = *count + 1; 3076#endif 3077 return (mpte); 3078} 3079 3080/* 3081 * Make a temporary mapping for a physical address. This is only intended 3082 * to be used for panic dumps. 3083 */ 3084void * 3085pmap_kenter_temporary(vm_paddr_t pa, int i) 3086{ 3087 vm_offset_t va; 3088 vm_paddr_t ma = xpmap_ptom(pa); 3089 3090 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE); 3091 PT_SET_MA(va, (ma & ~PAGE_MASK) | PG_V | pgeflag); 3092 invlpg(va); 3093 return ((void *)crashdumpmap); 3094} 3095 3096/* 3097 * This code maps large physical mmap regions into the 3098 * processor address space. Note that some shortcuts 3099 * are taken, but the code works. 3100 */ 3101void 3102pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object, 3103 vm_pindex_t pindex, vm_size_t size) 3104{ 3105 pd_entry_t *pde; 3106 vm_paddr_t pa, ptepa; 3107 vm_page_t p; 3108 int pat_mode; 3109 3110 VM_OBJECT_ASSERT_WLOCKED(object); 3111 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 3112 ("pmap_object_init_pt: non-device object")); 3113 if (pseflag && 3114 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) { 3115 if (!vm_object_populate(object, pindex, pindex + atop(size))) 3116 return; 3117 p = vm_page_lookup(object, pindex); 3118 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3119 ("pmap_object_init_pt: invalid page %p", p)); 3120 pat_mode = p->md.pat_mode; 3121 3122 /* 3123 * Abort the mapping if the first page is not physically 3124 * aligned to a 2/4MB page boundary. 3125 */ 3126 ptepa = VM_PAGE_TO_PHYS(p); 3127 if (ptepa & (NBPDR - 1)) 3128 return; 3129 3130 /* 3131 * Skip the first page. Abort the mapping if the rest of 3132 * the pages are not physically contiguous or have differing 3133 * memory attributes. 3134 */ 3135 p = TAILQ_NEXT(p, listq); 3136 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size; 3137 pa += PAGE_SIZE) { 3138 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3139 ("pmap_object_init_pt: invalid page %p", p)); 3140 if (pa != VM_PAGE_TO_PHYS(p) || 3141 pat_mode != p->md.pat_mode) 3142 return; 3143 p = TAILQ_NEXT(p, listq); 3144 } 3145 3146 /* 3147 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and 3148 * "size" is a multiple of 2/4M, adding the PAT setting to 3149 * "pa" will not affect the termination of this loop. 3150 */ 3151 PMAP_LOCK(pmap); 3152 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa + 3153 size; pa += NBPDR) { 3154 pde = pmap_pde(pmap, addr); 3155 if (*pde == 0) { 3156 pde_store(pde, pa | PG_PS | PG_M | PG_A | 3157 PG_U | PG_RW | PG_V); 3158 pmap->pm_stats.resident_count += NBPDR / 3159 PAGE_SIZE; 3160 pmap_pde_mappings++; 3161 } 3162 /* Else continue on if the PDE is already valid. */ 3163 addr += NBPDR; 3164 } 3165 PMAP_UNLOCK(pmap); 3166 } 3167} 3168 3169/* 3170 * Routine: pmap_change_wiring 3171 * Function: Change the wiring attribute for a map/virtual-address 3172 * pair. 3173 * In/out conditions: 3174 * The mapping must already exist in the pmap. 3175 */ 3176void 3177pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 3178{ 3179 pt_entry_t *pte; 3180 3181 rw_wlock(&pvh_global_lock); 3182 PMAP_LOCK(pmap); 3183 pte = pmap_pte(pmap, va); 3184 3185 if (wired && !pmap_pte_w(pte)) { 3186 PT_SET_VA_MA((pte), *(pte) | PG_W, TRUE); 3187 pmap->pm_stats.wired_count++; 3188 } else if (!wired && pmap_pte_w(pte)) { 3189 PT_SET_VA_MA((pte), *(pte) & ~PG_W, TRUE); 3190 pmap->pm_stats.wired_count--; 3191 } 3192 3193 /* 3194 * Wiring is not a hardware characteristic so there is no need to 3195 * invalidate TLB. 3196 */ 3197 pmap_pte_release(pte); 3198 PMAP_UNLOCK(pmap); 3199 rw_wunlock(&pvh_global_lock); 3200} 3201 3202 3203 3204/* 3205 * Copy the range specified by src_addr/len 3206 * from the source map to the range dst_addr/len 3207 * in the destination map. 3208 * 3209 * This routine is only advisory and need not do anything. 3210 */ 3211 3212void 3213pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len, 3214 vm_offset_t src_addr) 3215{ 3216 vm_page_t free; 3217 vm_offset_t addr; 3218 vm_offset_t end_addr = src_addr + len; 3219 vm_offset_t pdnxt; 3220 3221 if (dst_addr != src_addr) 3222 return; 3223 3224 if (!pmap_is_current(src_pmap)) { 3225 CTR2(KTR_PMAP, 3226 "pmap_copy, skipping: pdir[PTDPTDI]=0x%jx PTDpde[0]=0x%jx", 3227 (src_pmap->pm_pdir[PTDPTDI] & PG_FRAME), (PTDpde[0] & PG_FRAME)); 3228 3229 return; 3230 } 3231 CTR5(KTR_PMAP, "pmap_copy: dst_pmap=%p src_pmap=%p dst_addr=0x%x len=%d src_addr=0x%x", 3232 dst_pmap, src_pmap, dst_addr, len, src_addr); 3233 3234#ifdef HAMFISTED_LOCKING 3235 mtx_lock(&createdelete_lock); 3236#endif 3237 3238 rw_wlock(&pvh_global_lock); 3239 if (dst_pmap < src_pmap) { 3240 PMAP_LOCK(dst_pmap); 3241 PMAP_LOCK(src_pmap); 3242 } else { 3243 PMAP_LOCK(src_pmap); 3244 PMAP_LOCK(dst_pmap); 3245 } 3246 sched_pin(); 3247 for (addr = src_addr; addr < end_addr; addr = pdnxt) { 3248 pt_entry_t *src_pte, *dst_pte; 3249 vm_page_t dstmpte, srcmpte; 3250 pd_entry_t srcptepaddr; 3251 u_int ptepindex; 3252 3253 KASSERT(addr < UPT_MIN_ADDRESS, 3254 ("pmap_copy: invalid to pmap_copy page tables")); 3255 3256 pdnxt = (addr + NBPDR) & ~PDRMASK; 3257 if (pdnxt < addr) 3258 pdnxt = end_addr; 3259 ptepindex = addr >> PDRSHIFT; 3260 3261 srcptepaddr = PT_GET(&src_pmap->pm_pdir[ptepindex]); 3262 if (srcptepaddr == 0) 3263 continue; 3264 3265 if (srcptepaddr & PG_PS) { 3266 if (dst_pmap->pm_pdir[ptepindex] == 0) { 3267 PD_SET_VA(dst_pmap, ptepindex, srcptepaddr & ~PG_W, TRUE); 3268 dst_pmap->pm_stats.resident_count += 3269 NBPDR / PAGE_SIZE; 3270 } 3271 continue; 3272 } 3273 3274 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME); 3275 KASSERT(srcmpte->wire_count > 0, 3276 ("pmap_copy: source page table page is unused")); 3277 3278 if (pdnxt > end_addr) 3279 pdnxt = end_addr; 3280 3281 src_pte = vtopte(addr); 3282 while (addr < pdnxt) { 3283 pt_entry_t ptetemp; 3284 ptetemp = *src_pte; 3285 /* 3286 * we only virtual copy managed pages 3287 */ 3288 if ((ptetemp & PG_MANAGED) != 0) { 3289 dstmpte = pmap_allocpte(dst_pmap, addr, 3290 M_NOWAIT); 3291 if (dstmpte == NULL) 3292 goto out; 3293 dst_pte = pmap_pte_quick(dst_pmap, addr); 3294 if (*dst_pte == 0 && 3295 pmap_try_insert_pv_entry(dst_pmap, addr, 3296 PHYS_TO_VM_PAGE(xpmap_mtop(ptetemp) & PG_FRAME))) { 3297 /* 3298 * Clear the wired, modified, and 3299 * accessed (referenced) bits 3300 * during the copy. 3301 */ 3302 KASSERT(ptetemp != 0, ("src_pte not set")); 3303 PT_SET_VA_MA(dst_pte, ptetemp & ~(PG_W | PG_M | PG_A), TRUE /* XXX debug */); 3304 KASSERT(*dst_pte == (ptetemp & ~(PG_W | PG_M | PG_A)), 3305 ("no pmap copy expected: 0x%jx saw: 0x%jx", 3306 ptetemp & ~(PG_W | PG_M | PG_A), *dst_pte)); 3307 dst_pmap->pm_stats.resident_count++; 3308 } else { 3309 free = NULL; 3310 if (pmap_unwire_ptp(dst_pmap, dstmpte, 3311 &free)) { 3312 pmap_invalidate_page(dst_pmap, 3313 addr); 3314 pmap_free_zero_pages(free); 3315 } 3316 goto out; 3317 } 3318 if (dstmpte->wire_count >= srcmpte->wire_count) 3319 break; 3320 } 3321 addr += PAGE_SIZE; 3322 src_pte++; 3323 } 3324 } 3325out: 3326 PT_UPDATES_FLUSH(); 3327 sched_unpin(); 3328 rw_wunlock(&pvh_global_lock); 3329 PMAP_UNLOCK(src_pmap); 3330 PMAP_UNLOCK(dst_pmap); 3331 3332#ifdef HAMFISTED_LOCKING 3333 mtx_unlock(&createdelete_lock); 3334#endif 3335} 3336 3337static __inline void 3338pagezero(void *page) 3339{ 3340#if defined(I686_CPU) 3341 if (cpu_class == CPUCLASS_686) { 3342#if defined(CPU_ENABLE_SSE) 3343 if (cpu_feature & CPUID_SSE2) 3344 sse2_pagezero(page); 3345 else 3346#endif 3347 i686_pagezero(page); 3348 } else 3349#endif 3350 bzero(page, PAGE_SIZE); 3351} 3352 3353/* 3354 * pmap_zero_page zeros the specified hardware page by mapping 3355 * the page into KVM and using bzero to clear its contents. 3356 */ 3357void 3358pmap_zero_page(vm_page_t m) 3359{ 3360 struct sysmaps *sysmaps; 3361 3362 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3363 mtx_lock(&sysmaps->lock); 3364 if (*sysmaps->CMAP2) 3365 panic("pmap_zero_page: CMAP2 busy"); 3366 sched_pin(); 3367 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3368 pagezero(sysmaps->CADDR2); 3369 PT_SET_MA(sysmaps->CADDR2, 0); 3370 sched_unpin(); 3371 mtx_unlock(&sysmaps->lock); 3372} 3373 3374/* 3375 * pmap_zero_page_area zeros the specified hardware page by mapping 3376 * the page into KVM and using bzero to clear its contents. 3377 * 3378 * off and size may not cover an area beyond a single hardware page. 3379 */ 3380void 3381pmap_zero_page_area(vm_page_t m, int off, int size) 3382{ 3383 struct sysmaps *sysmaps; 3384 3385 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3386 mtx_lock(&sysmaps->lock); 3387 if (*sysmaps->CMAP2) 3388 panic("pmap_zero_page_area: CMAP2 busy"); 3389 sched_pin(); 3390 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3391 3392 if (off == 0 && size == PAGE_SIZE) 3393 pagezero(sysmaps->CADDR2); 3394 else 3395 bzero((char *)sysmaps->CADDR2 + off, size); 3396 PT_SET_MA(sysmaps->CADDR2, 0); 3397 sched_unpin(); 3398 mtx_unlock(&sysmaps->lock); 3399} 3400 3401/* 3402 * pmap_zero_page_idle zeros the specified hardware page by mapping 3403 * the page into KVM and using bzero to clear its contents. This 3404 * is intended to be called from the vm_pagezero process only and 3405 * outside of Giant. 3406 */ 3407void 3408pmap_zero_page_idle(vm_page_t m) 3409{ 3410 3411 if (*CMAP3) 3412 panic("pmap_zero_page_idle: CMAP3 busy"); 3413 sched_pin(); 3414 PT_SET_MA(CADDR3, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3415 pagezero(CADDR3); 3416 PT_SET_MA(CADDR3, 0); 3417 sched_unpin(); 3418} 3419 3420/* 3421 * pmap_copy_page copies the specified (machine independent) 3422 * page by mapping the page into virtual memory and using 3423 * bcopy to copy the page, one machine dependent page at a 3424 * time. 3425 */ 3426void 3427pmap_copy_page(vm_page_t src, vm_page_t dst) 3428{ 3429 struct sysmaps *sysmaps; 3430 3431 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3432 mtx_lock(&sysmaps->lock); 3433 if (*sysmaps->CMAP1) 3434 panic("pmap_copy_page: CMAP1 busy"); 3435 if (*sysmaps->CMAP2) 3436 panic("pmap_copy_page: CMAP2 busy"); 3437 sched_pin(); 3438 PT_SET_MA(sysmaps->CADDR1, PG_V | VM_PAGE_TO_MACH(src) | PG_A); 3439 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(dst) | PG_A | PG_M); 3440 bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE); 3441 PT_SET_MA(sysmaps->CADDR1, 0); 3442 PT_SET_MA(sysmaps->CADDR2, 0); 3443 sched_unpin(); 3444 mtx_unlock(&sysmaps->lock); 3445} 3446 3447int unmapped_buf_allowed = 1; 3448 3449void 3450pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[], 3451 vm_offset_t b_offset, int xfersize) 3452{ 3453 struct sysmaps *sysmaps; 3454 vm_page_t a_pg, b_pg; 3455 char *a_cp, *b_cp; 3456 vm_offset_t a_pg_offset, b_pg_offset; 3457 int cnt; 3458 3459 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3460 mtx_lock(&sysmaps->lock); 3461 if (*sysmaps->CMAP1 != 0) 3462 panic("pmap_copy_pages: CMAP1 busy"); 3463 if (*sysmaps->CMAP2 != 0) 3464 panic("pmap_copy_pages: CMAP2 busy"); 3465 sched_pin(); 3466 while (xfersize > 0) { 3467 a_pg = ma[a_offset >> PAGE_SHIFT]; 3468 a_pg_offset = a_offset & PAGE_MASK; 3469 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 3470 b_pg = mb[b_offset >> PAGE_SHIFT]; 3471 b_pg_offset = b_offset & PAGE_MASK; 3472 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 3473 PT_SET_MA(sysmaps->CADDR1, PG_V | VM_PAGE_TO_MACH(a_pg) | PG_A); 3474 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | 3475 VM_PAGE_TO_MACH(b_pg) | PG_A | PG_M); 3476 a_cp = sysmaps->CADDR1 + a_pg_offset; 3477 b_cp = sysmaps->CADDR2 + b_pg_offset; 3478 bcopy(a_cp, b_cp, cnt); 3479 a_offset += cnt; 3480 b_offset += cnt; 3481 xfersize -= cnt; 3482 } 3483 PT_SET_MA(sysmaps->CADDR1, 0); 3484 PT_SET_MA(sysmaps->CADDR2, 0); 3485 sched_unpin(); 3486 mtx_unlock(&sysmaps->lock); 3487} 3488 3489/* 3490 * Returns true if the pmap's pv is one of the first 3491 * 16 pvs linked to from this page. This count may 3492 * be changed upwards or downwards in the future; it 3493 * is only necessary that true be returned for a small 3494 * subset of pmaps for proper page aging. 3495 */ 3496boolean_t 3497pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 3498{ 3499 pv_entry_t pv; 3500 int loops = 0; 3501 boolean_t rv; 3502 3503 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3504 ("pmap_page_exists_quick: page %p is not managed", m)); 3505 rv = FALSE; 3506 rw_wlock(&pvh_global_lock); 3507 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 3508 if (PV_PMAP(pv) == pmap) { 3509 rv = TRUE; 3510 break; 3511 } 3512 loops++; 3513 if (loops >= 16) 3514 break; 3515 } 3516 rw_wunlock(&pvh_global_lock); 3517 return (rv); 3518} 3519 3520/* 3521 * pmap_page_wired_mappings: 3522 * 3523 * Return the number of managed mappings to the given physical page 3524 * that are wired. 3525 */ 3526int 3527pmap_page_wired_mappings(vm_page_t m) 3528{ 3529 pv_entry_t pv; 3530 pt_entry_t *pte; 3531 pmap_t pmap; 3532 int count; 3533 3534 count = 0; 3535 if ((m->oflags & VPO_UNMANAGED) != 0) 3536 return (count); 3537 rw_wlock(&pvh_global_lock); 3538 sched_pin(); 3539 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 3540 pmap = PV_PMAP(pv); 3541 PMAP_LOCK(pmap); 3542 pte = pmap_pte_quick(pmap, pv->pv_va); 3543 if ((*pte & PG_W) != 0) 3544 count++; 3545 PMAP_UNLOCK(pmap); 3546 } 3547 sched_unpin(); 3548 rw_wunlock(&pvh_global_lock); 3549 return (count); 3550} 3551 3552/* 3553 * Returns TRUE if the given page is mapped. Otherwise, returns FALSE. 3554 */ 3555boolean_t 3556pmap_page_is_mapped(vm_page_t m) 3557{ 3558 3559 if ((m->oflags & VPO_UNMANAGED) != 0) 3560 return (FALSE); 3561 return (!TAILQ_EMPTY(&m->md.pv_list)); 3562} 3563 3564/* 3565 * Remove all pages from specified address space 3566 * this aids process exit speeds. Also, this code 3567 * is special cased for current process only, but 3568 * can have the more generic (and slightly slower) 3569 * mode enabled. This is much faster than pmap_remove 3570 * in the case of running down an entire address space. 3571 */ 3572void 3573pmap_remove_pages(pmap_t pmap) 3574{ 3575 pt_entry_t *pte, tpte; 3576 vm_page_t m, free = NULL; 3577 pv_entry_t pv; 3578 struct pv_chunk *pc, *npc; 3579 int field, idx; 3580 int32_t bit; 3581 uint32_t inuse, bitmask; 3582 int allfree; 3583 3584 CTR1(KTR_PMAP, "pmap_remove_pages: pmap=%p", pmap); 3585 3586 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) { 3587 printf("warning: pmap_remove_pages called with non-current pmap\n"); 3588 return; 3589 } 3590 rw_wlock(&pvh_global_lock); 3591 KASSERT(pmap_is_current(pmap), ("removing pages from non-current pmap")); 3592 PMAP_LOCK(pmap); 3593 sched_pin(); 3594 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 3595 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap, 3596 pc->pc_pmap)); 3597 allfree = 1; 3598 for (field = 0; field < _NPCM; field++) { 3599 inuse = ~pc->pc_map[field] & pc_freemask[field]; 3600 while (inuse != 0) { 3601 bit = bsfl(inuse); 3602 bitmask = 1UL << bit; 3603 idx = field * 32 + bit; 3604 pv = &pc->pc_pventry[idx]; 3605 inuse &= ~bitmask; 3606 3607 pte = vtopte(pv->pv_va); 3608 tpte = *pte ? xpmap_mtop(*pte) : 0; 3609 3610 if (tpte == 0) { 3611 printf( 3612 "TPTE at %p IS ZERO @ VA %08x\n", 3613 pte, pv->pv_va); 3614 panic("bad pte"); 3615 } 3616 3617/* 3618 * We cannot remove wired pages from a process' mapping at this time 3619 */ 3620 if (tpte & PG_W) { 3621 allfree = 0; 3622 continue; 3623 } 3624 3625 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 3626 KASSERT(m->phys_addr == (tpte & PG_FRAME), 3627 ("vm_page_t %p phys_addr mismatch %016jx %016jx", 3628 m, (uintmax_t)m->phys_addr, 3629 (uintmax_t)tpte)); 3630 3631 KASSERT(m < &vm_page_array[vm_page_array_size], 3632 ("pmap_remove_pages: bad tpte %#jx", 3633 (uintmax_t)tpte)); 3634 3635 3636 PT_CLEAR_VA(pte, FALSE); 3637 3638 /* 3639 * Update the vm_page_t clean/reference bits. 3640 */ 3641 if (tpte & PG_M) 3642 vm_page_dirty(m); 3643 3644 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 3645 if (TAILQ_EMPTY(&m->md.pv_list)) 3646 vm_page_aflag_clear(m, PGA_WRITEABLE); 3647 3648 pmap_unuse_pt(pmap, pv->pv_va, &free); 3649 3650 /* Mark free */ 3651 PV_STAT(pv_entry_frees++); 3652 PV_STAT(pv_entry_spare++); 3653 pv_entry_count--; 3654 pc->pc_map[field] |= bitmask; 3655 pmap->pm_stats.resident_count--; 3656 } 3657 } 3658 PT_UPDATES_FLUSH(); 3659 if (allfree) { 3660 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 3661 free_pv_chunk(pc); 3662 } 3663 } 3664 PT_UPDATES_FLUSH(); 3665 if (*PMAP1) 3666 PT_SET_MA(PADDR1, 0); 3667 3668 sched_unpin(); 3669 pmap_invalidate_all(pmap); 3670 rw_wunlock(&pvh_global_lock); 3671 PMAP_UNLOCK(pmap); 3672 pmap_free_zero_pages(free); 3673} 3674 3675/* 3676 * pmap_is_modified: 3677 * 3678 * Return whether or not the specified physical page was modified 3679 * in any physical maps. 3680 */ 3681boolean_t 3682pmap_is_modified(vm_page_t m) 3683{ 3684 pv_entry_t pv; 3685 pt_entry_t *pte; 3686 pmap_t pmap; 3687 boolean_t rv; 3688 3689 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3690 ("pmap_is_modified: page %p is not managed", m)); 3691 rv = FALSE; 3692 3693 /* 3694 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 3695 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 3696 * is clear, no PTEs can have PG_M set. 3697 */ 3698 VM_OBJECT_ASSERT_WLOCKED(m->object); 3699 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 3700 return (rv); 3701 rw_wlock(&pvh_global_lock); 3702 sched_pin(); 3703 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 3704 pmap = PV_PMAP(pv); 3705 PMAP_LOCK(pmap); 3706 pte = pmap_pte_quick(pmap, pv->pv_va); 3707 rv = (*pte & PG_M) != 0; 3708 PMAP_UNLOCK(pmap); 3709 if (rv) 3710 break; 3711 } 3712 if (*PMAP1) 3713 PT_SET_MA(PADDR1, 0); 3714 sched_unpin(); 3715 rw_wunlock(&pvh_global_lock); 3716 return (rv); 3717} 3718 3719/* 3720 * pmap_is_prefaultable: 3721 * 3722 * Return whether or not the specified virtual address is elgible 3723 * for prefault. 3724 */ 3725static boolean_t 3726pmap_is_prefaultable_locked(pmap_t pmap, vm_offset_t addr) 3727{ 3728 pt_entry_t *pte; 3729 boolean_t rv = FALSE; 3730 3731 return (rv); 3732 3733 if (pmap_is_current(pmap) && *pmap_pde(pmap, addr)) { 3734 pte = vtopte(addr); 3735 rv = (*pte == 0); 3736 } 3737 return (rv); 3738} 3739 3740boolean_t 3741pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 3742{ 3743 boolean_t rv; 3744 3745 PMAP_LOCK(pmap); 3746 rv = pmap_is_prefaultable_locked(pmap, addr); 3747 PMAP_UNLOCK(pmap); 3748 return (rv); 3749} 3750 3751boolean_t 3752pmap_is_referenced(vm_page_t m) 3753{ 3754 pv_entry_t pv; 3755 pt_entry_t *pte; 3756 pmap_t pmap; 3757 boolean_t rv; 3758 3759 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3760 ("pmap_is_referenced: page %p is not managed", m)); 3761 rv = FALSE; 3762 rw_wlock(&pvh_global_lock); 3763 sched_pin(); 3764 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 3765 pmap = PV_PMAP(pv); 3766 PMAP_LOCK(pmap); 3767 pte = pmap_pte_quick(pmap, pv->pv_va); 3768 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V); 3769 PMAP_UNLOCK(pmap); 3770 if (rv) 3771 break; 3772 } 3773 if (*PMAP1) 3774 PT_SET_MA(PADDR1, 0); 3775 sched_unpin(); 3776 rw_wunlock(&pvh_global_lock); 3777 return (rv); 3778} 3779 3780void 3781pmap_map_readonly(pmap_t pmap, vm_offset_t va, int len) 3782{ 3783 int i, npages = round_page(len) >> PAGE_SHIFT; 3784 for (i = 0; i < npages; i++) { 3785 pt_entry_t *pte; 3786 pte = pmap_pte(pmap, (vm_offset_t)(va + i*PAGE_SIZE)); 3787 rw_wlock(&pvh_global_lock); 3788 pte_store(pte, xpmap_mtop(*pte & ~(PG_RW|PG_M))); 3789 rw_wunlock(&pvh_global_lock); 3790 PMAP_MARK_PRIV(xpmap_mtop(*pte)); 3791 pmap_pte_release(pte); 3792 } 3793} 3794 3795void 3796pmap_map_readwrite(pmap_t pmap, vm_offset_t va, int len) 3797{ 3798 int i, npages = round_page(len) >> PAGE_SHIFT; 3799 for (i = 0; i < npages; i++) { 3800 pt_entry_t *pte; 3801 pte = pmap_pte(pmap, (vm_offset_t)(va + i*PAGE_SIZE)); 3802 PMAP_MARK_UNPRIV(xpmap_mtop(*pte)); 3803 rw_wlock(&pvh_global_lock); 3804 pte_store(pte, xpmap_mtop(*pte) | (PG_RW|PG_M)); 3805 rw_wunlock(&pvh_global_lock); 3806 pmap_pte_release(pte); 3807 } 3808} 3809 3810/* 3811 * Clear the write and modified bits in each of the given page's mappings. 3812 */ 3813void 3814pmap_remove_write(vm_page_t m) 3815{ 3816 pv_entry_t pv; 3817 pmap_t pmap; 3818 pt_entry_t oldpte, *pte; 3819 3820 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3821 ("pmap_remove_write: page %p is not managed", m)); 3822 3823 /* 3824 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 3825 * set by another thread while the object is locked. Thus, 3826 * if PGA_WRITEABLE is clear, no page table entries need updating. 3827 */ 3828 VM_OBJECT_ASSERT_WLOCKED(m->object); 3829 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 3830 return; 3831 rw_wlock(&pvh_global_lock); 3832 sched_pin(); 3833 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 3834 pmap = PV_PMAP(pv); 3835 PMAP_LOCK(pmap); 3836 pte = pmap_pte_quick(pmap, pv->pv_va); 3837retry: 3838 oldpte = *pte; 3839 if ((oldpte & PG_RW) != 0) { 3840 vm_paddr_t newpte = oldpte & ~(PG_RW | PG_M); 3841 3842 /* 3843 * Regardless of whether a pte is 32 or 64 bits 3844 * in size, PG_RW and PG_M are among the least 3845 * significant 32 bits. 3846 */ 3847 PT_SET_VA_MA(pte, newpte, TRUE); 3848 if (*pte != newpte) 3849 goto retry; 3850 3851 if ((oldpte & PG_M) != 0) 3852 vm_page_dirty(m); 3853 pmap_invalidate_page(pmap, pv->pv_va); 3854 } 3855 PMAP_UNLOCK(pmap); 3856 } 3857 vm_page_aflag_clear(m, PGA_WRITEABLE); 3858 PT_UPDATES_FLUSH(); 3859 if (*PMAP1) 3860 PT_SET_MA(PADDR1, 0); 3861 sched_unpin(); 3862 rw_wunlock(&pvh_global_lock); 3863} 3864 3865/* 3866 * pmap_ts_referenced: 3867 * 3868 * Return a count of reference bits for a page, clearing those bits. 3869 * It is not necessary for every reference bit to be cleared, but it 3870 * is necessary that 0 only be returned when there are truly no 3871 * reference bits set. 3872 * 3873 * XXX: The exact number of bits to check and clear is a matter that 3874 * should be tested and standardized at some point in the future for 3875 * optimal aging of shared pages. 3876 */ 3877int 3878pmap_ts_referenced(vm_page_t m) 3879{ 3880 pv_entry_t pv, pvf, pvn; 3881 pmap_t pmap; 3882 pt_entry_t *pte; 3883 int rtval = 0; 3884 3885 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3886 ("pmap_ts_referenced: page %p is not managed", m)); 3887 rw_wlock(&pvh_global_lock); 3888 sched_pin(); 3889 if ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 3890 pvf = pv; 3891 do { 3892 pvn = TAILQ_NEXT(pv, pv_next); 3893 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 3894 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 3895 pmap = PV_PMAP(pv); 3896 PMAP_LOCK(pmap); 3897 pte = pmap_pte_quick(pmap, pv->pv_va); 3898 if ((*pte & PG_A) != 0) { 3899 PT_SET_VA_MA(pte, *pte & ~PG_A, FALSE); 3900 pmap_invalidate_page(pmap, pv->pv_va); 3901 rtval++; 3902 if (rtval > 4) 3903 pvn = NULL; 3904 } 3905 PMAP_UNLOCK(pmap); 3906 } while ((pv = pvn) != NULL && pv != pvf); 3907 } 3908 PT_UPDATES_FLUSH(); 3909 if (*PMAP1) 3910 PT_SET_MA(PADDR1, 0); 3911 sched_unpin(); 3912 rw_wunlock(&pvh_global_lock); 3913 return (rtval); 3914} 3915 3916/* 3917 * Apply the given advice to the specified range of addresses within the 3918 * given pmap. Depending on the advice, clear the referenced and/or 3919 * modified flags in each mapping and set the mapped page's dirty field. 3920 */ 3921void 3922pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice) 3923{ 3924 pd_entry_t oldpde; 3925 pt_entry_t *pte; 3926 vm_offset_t pdnxt; 3927 vm_page_t m; 3928 boolean_t anychanged; 3929 3930 if (advice != MADV_DONTNEED && advice != MADV_FREE) 3931 return; 3932 anychanged = FALSE; 3933 rw_wlock(&pvh_global_lock); 3934 sched_pin(); 3935 PMAP_LOCK(pmap); 3936 for (; sva < eva; sva = pdnxt) { 3937 pdnxt = (sva + NBPDR) & ~PDRMASK; 3938 if (pdnxt < sva) 3939 pdnxt = eva; 3940 oldpde = pmap->pm_pdir[sva >> PDRSHIFT]; 3941 if ((oldpde & (PG_PS | PG_V)) != PG_V) 3942 continue; 3943 if (pdnxt > eva) 3944 pdnxt = eva; 3945 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 3946 sva += PAGE_SIZE) { 3947 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | 3948 PG_V)) 3949 continue; 3950 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 3951 if (advice == MADV_DONTNEED) { 3952 /* 3953 * Future calls to pmap_is_modified() 3954 * can be avoided by making the page 3955 * dirty now. 3956 */ 3957 m = PHYS_TO_VM_PAGE(xpmap_mtop(*pte) & 3958 PG_FRAME); 3959 vm_page_dirty(m); 3960 } 3961 PT_SET_VA_MA(pte, *pte & ~(PG_M | PG_A), TRUE); 3962 } else if ((*pte & PG_A) != 0) 3963 PT_SET_VA_MA(pte, *pte & ~PG_A, TRUE); 3964 else 3965 continue; 3966 if ((*pte & PG_G) != 0) 3967 pmap_invalidate_page(pmap, sva); 3968 else 3969 anychanged = TRUE; 3970 } 3971 } 3972 PT_UPDATES_FLUSH(); 3973 if (*PMAP1) 3974 PT_SET_VA_MA(PMAP1, 0, TRUE); 3975 if (anychanged) 3976 pmap_invalidate_all(pmap); 3977 sched_unpin(); 3978 rw_wunlock(&pvh_global_lock); 3979 PMAP_UNLOCK(pmap); 3980} 3981 3982/* 3983 * Clear the modify bits on the specified physical page. 3984 */ 3985void 3986pmap_clear_modify(vm_page_t m) 3987{ 3988 pv_entry_t pv; 3989 pmap_t pmap; 3990 pt_entry_t *pte; 3991 3992 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3993 ("pmap_clear_modify: page %p is not managed", m)); 3994 VM_OBJECT_ASSERT_WLOCKED(m->object); 3995 KASSERT(!vm_page_xbusied(m), 3996 ("pmap_clear_modify: page %p is exclusive busied", m)); 3997 3998 /* 3999 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set. 4000 * If the object containing the page is locked and the page is not 4001 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 4002 */ 4003 if ((m->aflags & PGA_WRITEABLE) == 0) 4004 return; 4005 rw_wlock(&pvh_global_lock); 4006 sched_pin(); 4007 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 4008 pmap = PV_PMAP(pv); 4009 PMAP_LOCK(pmap); 4010 pte = pmap_pte_quick(pmap, pv->pv_va); 4011 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 4012 /* 4013 * Regardless of whether a pte is 32 or 64 bits 4014 * in size, PG_M is among the least significant 4015 * 32 bits. 4016 */ 4017 PT_SET_VA_MA(pte, *pte & ~PG_M, FALSE); 4018 pmap_invalidate_page(pmap, pv->pv_va); 4019 } 4020 PMAP_UNLOCK(pmap); 4021 } 4022 sched_unpin(); 4023 rw_wunlock(&pvh_global_lock); 4024} 4025 4026/* 4027 * Miscellaneous support routines follow 4028 */ 4029 4030/* 4031 * Map a set of physical memory pages into the kernel virtual 4032 * address space. Return a pointer to where it is mapped. This 4033 * routine is intended to be used for mapping device memory, 4034 * NOT real memory. 4035 */ 4036void * 4037pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode) 4038{ 4039 vm_offset_t va, offset; 4040 vm_size_t tmpsize; 4041 4042 offset = pa & PAGE_MASK; 4043 size = round_page(offset + size); 4044 pa = pa & PG_FRAME; 4045 4046 if (pa < KERNLOAD && pa + size <= KERNLOAD) 4047 va = KERNBASE + pa; 4048 else 4049 va = kva_alloc(size); 4050 if (!va) 4051 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 4052 4053 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE) 4054 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode); 4055 pmap_invalidate_range(kernel_pmap, va, va + tmpsize); 4056 pmap_invalidate_cache_range(va, va + size); 4057 return ((void *)(va + offset)); 4058} 4059 4060void * 4061pmap_mapdev(vm_paddr_t pa, vm_size_t size) 4062{ 4063 4064 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE)); 4065} 4066 4067void * 4068pmap_mapbios(vm_paddr_t pa, vm_size_t size) 4069{ 4070 4071 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK)); 4072} 4073 4074void 4075pmap_unmapdev(vm_offset_t va, vm_size_t size) 4076{ 4077 vm_offset_t base, offset; 4078 4079 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD) 4080 return; 4081 base = trunc_page(va); 4082 offset = va & PAGE_MASK; 4083 size = round_page(offset + size); 4084 kva_free(base, size); 4085} 4086 4087/* 4088 * Sets the memory attribute for the specified page. 4089 */ 4090void 4091pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma) 4092{ 4093 4094 m->md.pat_mode = ma; 4095 if ((m->flags & PG_FICTITIOUS) != 0) 4096 return; 4097 4098 /* 4099 * If "m" is a normal page, flush it from the cache. 4100 * See pmap_invalidate_cache_range(). 4101 * 4102 * First, try to find an existing mapping of the page by sf 4103 * buffer. sf_buf_invalidate_cache() modifies mapping and 4104 * flushes the cache. 4105 */ 4106 if (sf_buf_invalidate_cache(m)) 4107 return; 4108 4109 /* 4110 * If page is not mapped by sf buffer, but CPU does not 4111 * support self snoop, map the page transient and do 4112 * invalidation. In the worst case, whole cache is flushed by 4113 * pmap_invalidate_cache_range(). 4114 */ 4115 if ((cpu_feature & CPUID_SS) == 0) 4116 pmap_flush_page(m); 4117} 4118 4119static void 4120pmap_flush_page(vm_page_t m) 4121{ 4122 struct sysmaps *sysmaps; 4123 vm_offset_t sva, eva; 4124 4125 if ((cpu_feature & CPUID_CLFSH) != 0) { 4126 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 4127 mtx_lock(&sysmaps->lock); 4128 if (*sysmaps->CMAP2) 4129 panic("pmap_flush_page: CMAP2 busy"); 4130 sched_pin(); 4131 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | 4132 VM_PAGE_TO_MACH(m) | PG_A | PG_M | 4133 pmap_cache_bits(m->md.pat_mode, 0)); 4134 invlcaddr(sysmaps->CADDR2); 4135 sva = (vm_offset_t)sysmaps->CADDR2; 4136 eva = sva + PAGE_SIZE; 4137 4138 /* 4139 * Use mfence despite the ordering implied by 4140 * mtx_{un,}lock() because clflush is not guaranteed 4141 * to be ordered by any other instruction. 4142 */ 4143 mfence(); 4144 for (; sva < eva; sva += cpu_clflush_line_size) 4145 clflush(sva); 4146 mfence(); 4147 PT_SET_MA(sysmaps->CADDR2, 0); 4148 sched_unpin(); 4149 mtx_unlock(&sysmaps->lock); 4150 } else 4151 pmap_invalidate_cache(); 4152} 4153 4154/* 4155 * Changes the specified virtual address range's memory type to that given by 4156 * the parameter "mode". The specified virtual address range must be 4157 * completely contained within either the kernel map. 4158 * 4159 * Returns zero if the change completed successfully, and either EINVAL or 4160 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part 4161 * of the virtual address range was not mapped, and ENOMEM is returned if 4162 * there was insufficient memory available to complete the change. 4163 */ 4164int 4165pmap_change_attr(vm_offset_t va, vm_size_t size, int mode) 4166{ 4167 vm_offset_t base, offset, tmpva; 4168 pt_entry_t *pte; 4169 u_int opte, npte; 4170 pd_entry_t *pde; 4171 boolean_t changed; 4172 4173 base = trunc_page(va); 4174 offset = va & PAGE_MASK; 4175 size = round_page(offset + size); 4176 4177 /* Only supported on kernel virtual addresses. */ 4178 if (base <= VM_MAXUSER_ADDRESS) 4179 return (EINVAL); 4180 4181 /* 4MB pages and pages that aren't mapped aren't supported. */ 4182 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) { 4183 pde = pmap_pde(kernel_pmap, tmpva); 4184 if (*pde & PG_PS) 4185 return (EINVAL); 4186 if ((*pde & PG_V) == 0) 4187 return (EINVAL); 4188 pte = vtopte(va); 4189 if ((*pte & PG_V) == 0) 4190 return (EINVAL); 4191 } 4192 4193 changed = FALSE; 4194 4195 /* 4196 * Ok, all the pages exist and are 4k, so run through them updating 4197 * their cache mode. 4198 */ 4199 for (tmpva = base; size > 0; ) { 4200 pte = vtopte(tmpva); 4201 4202 /* 4203 * The cache mode bits are all in the low 32-bits of the 4204 * PTE, so we can just spin on updating the low 32-bits. 4205 */ 4206 do { 4207 opte = *(u_int *)pte; 4208 npte = opte & ~(PG_PTE_PAT | PG_NC_PCD | PG_NC_PWT); 4209 npte |= pmap_cache_bits(mode, 0); 4210 PT_SET_VA_MA(pte, npte, TRUE); 4211 } while (npte != opte && (*pte != npte)); 4212 if (npte != opte) 4213 changed = TRUE; 4214 tmpva += PAGE_SIZE; 4215 size -= PAGE_SIZE; 4216 } 4217 4218 /* 4219 * Flush CPU caches to make sure any data isn't cached that 4220 * shouldn't be, etc. 4221 */ 4222 if (changed) { 4223 pmap_invalidate_range(kernel_pmap, base, tmpva); 4224 pmap_invalidate_cache_range(base, tmpva); 4225 } 4226 return (0); 4227} 4228 4229/* 4230 * perform the pmap work for mincore 4231 */ 4232int 4233pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa) 4234{ 4235 pt_entry_t *ptep, pte; 4236 vm_paddr_t pa; 4237 int val; 4238 4239 PMAP_LOCK(pmap); 4240retry: 4241 ptep = pmap_pte(pmap, addr); 4242 pte = (ptep != NULL) ? PT_GET(ptep) : 0; 4243 pmap_pte_release(ptep); 4244 val = 0; 4245 if ((pte & PG_V) != 0) { 4246 val |= MINCORE_INCORE; 4247 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 4248 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 4249 if ((pte & PG_A) != 0) 4250 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 4251 } 4252 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 4253 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && 4254 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) { 4255 pa = pte & PG_FRAME; 4256 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */ 4257 if (vm_page_pa_tryrelock(pmap, pa, locked_pa)) 4258 goto retry; 4259 } else 4260 PA_UNLOCK_COND(*locked_pa); 4261 PMAP_UNLOCK(pmap); 4262 return (val); 4263} 4264 4265void 4266pmap_activate(struct thread *td) 4267{ 4268 pmap_t pmap, oldpmap; 4269 u_int cpuid; 4270 u_int32_t cr3; 4271 4272 critical_enter(); 4273 pmap = vmspace_pmap(td->td_proc->p_vmspace); 4274 oldpmap = PCPU_GET(curpmap); 4275 cpuid = PCPU_GET(cpuid); 4276#if defined(SMP) 4277 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active); 4278 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 4279#else 4280 CPU_CLR(cpuid, &oldpmap->pm_active); 4281 CPU_SET(cpuid, &pmap->pm_active); 4282#endif 4283#ifdef PAE 4284 cr3 = vtophys(pmap->pm_pdpt); 4285#else 4286 cr3 = vtophys(pmap->pm_pdir); 4287#endif 4288 /* 4289 * pmap_activate is for the current thread on the current cpu 4290 */ 4291 td->td_pcb->pcb_cr3 = cr3; 4292 PT_UPDATES_FLUSH(); 4293 load_cr3(cr3); 4294 PCPU_SET(curpmap, pmap); 4295 critical_exit(); 4296} 4297 4298void 4299pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 4300{ 4301} 4302 4303/* 4304 * Increase the starting virtual address of the given mapping if a 4305 * different alignment might result in more superpage mappings. 4306 */ 4307void 4308pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 4309 vm_offset_t *addr, vm_size_t size) 4310{ 4311 vm_offset_t superpage_offset; 4312 4313 if (size < NBPDR) 4314 return; 4315 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 4316 offset += ptoa(object->pg_color); 4317 superpage_offset = offset & PDRMASK; 4318 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR || 4319 (*addr & PDRMASK) == superpage_offset) 4320 return; 4321 if ((*addr & PDRMASK) < superpage_offset) 4322 *addr = (*addr & ~PDRMASK) + superpage_offset; 4323 else 4324 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset; 4325} 4326 4327void 4328pmap_suspend() 4329{ 4330 pmap_t pmap; 4331 int i, pdir, offset; 4332 vm_paddr_t pdirma; 4333 mmu_update_t mu[4]; 4334 4335 /* 4336 * We need to remove the recursive mapping structure from all 4337 * our pmaps so that Xen doesn't get confused when it restores 4338 * the page tables. The recursive map lives at page directory 4339 * index PTDPTDI. We assume that the suspend code has stopped 4340 * the other vcpus (if any). 4341 */ 4342 LIST_FOREACH(pmap, &allpmaps, pm_list) { 4343 for (i = 0; i < 4; i++) { 4344 /* 4345 * Figure out which page directory (L2) page 4346 * contains this bit of the recursive map and 4347 * the offset within that page of the map 4348 * entry 4349 */ 4350 pdir = (PTDPTDI + i) / NPDEPG; 4351 offset = (PTDPTDI + i) % NPDEPG; 4352 pdirma = pmap->pm_pdpt[pdir] & PG_FRAME; 4353 mu[i].ptr = pdirma + offset * sizeof(pd_entry_t); 4354 mu[i].val = 0; 4355 } 4356 HYPERVISOR_mmu_update(mu, 4, NULL, DOMID_SELF); 4357 } 4358} 4359 4360void 4361pmap_resume() 4362{ 4363 pmap_t pmap; 4364 int i, pdir, offset; 4365 vm_paddr_t pdirma; 4366 mmu_update_t mu[4]; 4367 4368 /* 4369 * Restore the recursive map that we removed on suspend. 4370 */ 4371 LIST_FOREACH(pmap, &allpmaps, pm_list) { 4372 for (i = 0; i < 4; i++) { 4373 /* 4374 * Figure out which page directory (L2) page 4375 * contains this bit of the recursive map and 4376 * the offset within that page of the map 4377 * entry 4378 */ 4379 pdir = (PTDPTDI + i) / NPDEPG; 4380 offset = (PTDPTDI + i) % NPDEPG; 4381 pdirma = pmap->pm_pdpt[pdir] & PG_FRAME; 4382 mu[i].ptr = pdirma + offset * sizeof(pd_entry_t); 4383 mu[i].val = (pmap->pm_pdpt[i] & PG_FRAME) | PG_V; 4384 } 4385 HYPERVISOR_mmu_update(mu, 4, NULL, DOMID_SELF); 4386 } 4387} 4388 4389#if defined(PMAP_DEBUG) 4390pmap_pid_dump(int pid) 4391{ 4392 pmap_t pmap; 4393 struct proc *p; 4394 int npte = 0; 4395 int index; 4396 4397 sx_slock(&allproc_lock); 4398 FOREACH_PROC_IN_SYSTEM(p) { 4399 if (p->p_pid != pid) 4400 continue; 4401 4402 if (p->p_vmspace) { 4403 int i,j; 4404 index = 0; 4405 pmap = vmspace_pmap(p->p_vmspace); 4406 for (i = 0; i < NPDEPTD; i++) { 4407 pd_entry_t *pde; 4408 pt_entry_t *pte; 4409 vm_offset_t base = i << PDRSHIFT; 4410 4411 pde = &pmap->pm_pdir[i]; 4412 if (pde && pmap_pde_v(pde)) { 4413 for (j = 0; j < NPTEPG; j++) { 4414 vm_offset_t va = base + (j << PAGE_SHIFT); 4415 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) { 4416 if (index) { 4417 index = 0; 4418 printf("\n"); 4419 } 4420 sx_sunlock(&allproc_lock); 4421 return (npte); 4422 } 4423 pte = pmap_pte(pmap, va); 4424 if (pte && pmap_pte_v(pte)) { 4425 pt_entry_t pa; 4426 vm_page_t m; 4427 pa = PT_GET(pte); 4428 m = PHYS_TO_VM_PAGE(pa & PG_FRAME); 4429 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x", 4430 va, pa, m->hold_count, m->wire_count, m->flags); 4431 npte++; 4432 index++; 4433 if (index >= 2) { 4434 index = 0; 4435 printf("\n"); 4436 } else { 4437 printf(" "); 4438 } 4439 } 4440 } 4441 } 4442 } 4443 } 4444 } 4445 sx_sunlock(&allproc_lock); 4446 return (npte); 4447} 4448#endif 4449 4450#if defined(DEBUG) 4451 4452static void pads(pmap_t pm); 4453void pmap_pvdump(vm_paddr_t pa); 4454 4455/* print address space of pmap*/ 4456static void 4457pads(pmap_t pm) 4458{ 4459 int i, j; 4460 vm_paddr_t va; 4461 pt_entry_t *ptep; 4462 4463 if (pm == kernel_pmap) 4464 return; 4465 for (i = 0; i < NPDEPTD; i++) 4466 if (pm->pm_pdir[i]) 4467 for (j = 0; j < NPTEPG; j++) { 4468 va = (i << PDRSHIFT) + (j << PAGE_SHIFT); 4469 if (pm == kernel_pmap && va < KERNBASE) 4470 continue; 4471 if (pm != kernel_pmap && va > UPT_MAX_ADDRESS) 4472 continue; 4473 ptep = pmap_pte(pm, va); 4474 if (pmap_pte_v(ptep)) 4475 printf("%x:%x ", va, *ptep); 4476 }; 4477 4478} 4479 4480void 4481pmap_pvdump(vm_paddr_t pa) 4482{ 4483 pv_entry_t pv; 4484 pmap_t pmap; 4485 vm_page_t m; 4486 4487 printf("pa %x", pa); 4488 m = PHYS_TO_VM_PAGE(pa); 4489 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 4490 pmap = PV_PMAP(pv); 4491 printf(" -> pmap %p, va %x", (void *)pmap, pv->pv_va); 4492 pads(pmap); 4493 } 4494 printf(" "); 4495} 4496#endif 4497