npx.c revision 276084
1/*- 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 4. Neither the name of the University nor the names of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: stable/10/sys/i386/isa/npx.c 276084 2014-12-22 21:32:39Z jhb $"); 35 36#include "opt_cpu.h" 37#include "opt_isa.h" 38#include "opt_npx.h" 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/bus.h> 43#include <sys/kernel.h> 44#include <sys/lock.h> 45#include <sys/malloc.h> 46#include <sys/module.h> 47#include <sys/mutex.h> 48#include <sys/mutex.h> 49#include <sys/proc.h> 50#include <sys/smp.h> 51#include <sys/sysctl.h> 52#include <machine/bus.h> 53#include <sys/rman.h> 54#ifdef NPX_DEBUG 55#include <sys/syslog.h> 56#endif 57#include <sys/signalvar.h> 58#include <vm/uma.h> 59 60#include <machine/asmacros.h> 61#include <machine/cputypes.h> 62#include <machine/frame.h> 63#include <machine/md_var.h> 64#include <machine/pcb.h> 65#include <machine/psl.h> 66#include <machine/resource.h> 67#include <machine/specialreg.h> 68#include <machine/segments.h> 69#include <machine/ucontext.h> 70 71#include <machine/intr_machdep.h> 72#ifdef XEN 73#include <xen/xen-os.h> 74#include <xen/hypervisor.h> 75#endif 76 77#ifdef DEV_ISA 78#include <isa/isavar.h> 79#endif 80 81#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU) 82#define CPU_ENABLE_SSE 83#endif 84 85/* 86 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver. 87 */ 88 89#if defined(__GNUCLIKE_ASM) && !defined(lint) 90 91#define fldcw(cw) __asm __volatile("fldcw %0" : : "m" (cw)) 92#define fnclex() __asm __volatile("fnclex") 93#define fninit() __asm __volatile("fninit") 94#define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 95#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 96#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=am" (*(addr))) 97#define fp_divide_by_0() __asm __volatile( \ 98 "fldz; fld1; fdiv %st,%st(1); fnop") 99#define frstor(addr) __asm __volatile("frstor %0" : : "m" (*(addr))) 100#ifdef CPU_ENABLE_SSE 101#define fxrstor(addr) __asm __volatile("fxrstor %0" : : "m" (*(addr))) 102#define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 103#define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr)) 104#define stmxcsr(addr) __asm __volatile("stmxcsr %0" : : "m" (*(addr))) 105 106static __inline void 107xrstor(char *addr, uint64_t mask) 108{ 109 uint32_t low, hi; 110 111 low = mask; 112 hi = mask >> 32; 113 __asm __volatile("xrstor %0" : : "m" (*addr), "a" (low), "d" (hi)); 114} 115 116static __inline void 117xsave(char *addr, uint64_t mask) 118{ 119 uint32_t low, hi; 120 121 low = mask; 122 hi = mask >> 32; 123 __asm __volatile("xsave %0" : "=m" (*addr) : "a" (low), "d" (hi) : 124 "memory"); 125} 126 127static __inline void 128xsaveopt(char *addr, uint64_t mask) 129{ 130 uint32_t low, hi; 131 132 low = mask; 133 hi = mask >> 32; 134 __asm __volatile("xsaveopt %0" : "=m" (*addr) : "a" (low), "d" (hi) : 135 "memory"); 136} 137#endif 138#else /* !(__GNUCLIKE_ASM && !lint) */ 139 140void fldcw(u_short cw); 141void fnclex(void); 142void fninit(void); 143void fnsave(caddr_t addr); 144void fnstcw(caddr_t addr); 145void fnstsw(caddr_t addr); 146void fp_divide_by_0(void); 147void frstor(caddr_t addr); 148#ifdef CPU_ENABLE_SSE 149void fxsave(caddr_t addr); 150void fxrstor(caddr_t addr); 151void ldmxcsr(u_int csr); 152void stmxcsr(u_int *csr); 153void xrstor(char *addr, uint64_t mask); 154void xsave(char *addr, uint64_t mask); 155void xsaveopt(char *addr, uint64_t mask); 156#endif 157 158#endif /* __GNUCLIKE_ASM && !lint */ 159 160#ifdef XEN 161#define start_emulating() (HYPERVISOR_fpu_taskswitch(1)) 162#define stop_emulating() (HYPERVISOR_fpu_taskswitch(0)) 163#else 164#define start_emulating() load_cr0(rcr0() | CR0_TS) 165#define stop_emulating() clts() 166#endif 167 168#ifdef CPU_ENABLE_SSE 169#define GET_FPU_CW(thread) \ 170 (cpu_fxsr ? \ 171 (thread)->td_pcb->pcb_save->sv_xmm.sv_env.en_cw : \ 172 (thread)->td_pcb->pcb_save->sv_87.sv_env.en_cw) 173#define GET_FPU_SW(thread) \ 174 (cpu_fxsr ? \ 175 (thread)->td_pcb->pcb_save->sv_xmm.sv_env.en_sw : \ 176 (thread)->td_pcb->pcb_save->sv_87.sv_env.en_sw) 177#define SET_FPU_CW(savefpu, value) do { \ 178 if (cpu_fxsr) \ 179 (savefpu)->sv_xmm.sv_env.en_cw = (value); \ 180 else \ 181 (savefpu)->sv_87.sv_env.en_cw = (value); \ 182} while (0) 183#else /* CPU_ENABLE_SSE */ 184#define GET_FPU_CW(thread) \ 185 (thread->td_pcb->pcb_save->sv_87.sv_env.en_cw) 186#define GET_FPU_SW(thread) \ 187 (thread->td_pcb->pcb_save->sv_87.sv_env.en_sw) 188#define SET_FPU_CW(savefpu, value) \ 189 (savefpu)->sv_87.sv_env.en_cw = (value) 190#endif /* CPU_ENABLE_SSE */ 191 192#ifdef CPU_ENABLE_SSE 193CTASSERT(sizeof(union savefpu) == 512); 194CTASSERT(sizeof(struct xstate_hdr) == 64); 195CTASSERT(sizeof(struct savefpu_ymm) == 832); 196 197/* 198 * This requirement is to make it easier for asm code to calculate 199 * offset of the fpu save area from the pcb address. FPU save area 200 * must be 64-byte aligned. 201 */ 202CTASSERT(sizeof(struct pcb) % XSAVE_AREA_ALIGN == 0); 203 204static void fpu_clean_state(void); 205#endif 206 207static void fpusave(union savefpu *); 208static void fpurstor(union savefpu *); 209 210int hw_float; 211 212SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD, 213 &hw_float, 0, "Floating point instructions executed in hardware"); 214 215#ifdef CPU_ENABLE_SSE 216int use_xsave; 217uint64_t xsave_mask; 218#endif 219static uma_zone_t fpu_save_area_zone; 220static union savefpu *npx_initialstate; 221 222#ifdef CPU_ENABLE_SSE 223struct xsave_area_elm_descr { 224 u_int offset; 225 u_int size; 226} *xsave_area_desc; 227 228static int use_xsaveopt; 229#endif 230 231static volatile u_int npx_traps_while_probing; 232 233alias_for_inthand_t probetrap; 234__asm(" \n\ 235 .text \n\ 236 .p2align 2,0x90 \n\ 237 .type " __XSTRING(CNAME(probetrap)) ",@function \n\ 238" __XSTRING(CNAME(probetrap)) ": \n\ 239 ss \n\ 240 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\ 241 fnclex \n\ 242 iret \n\ 243"); 244 245/* 246 * Determine if an FPU is present and how to use it. 247 */ 248static int 249npx_probe(void) 250{ 251 struct gate_descriptor save_idt_npxtrap; 252 u_short control, status; 253 254 /* 255 * Modern CPUs all have an FPU that uses the INT16 interface 256 * and provide a simple way to verify that, so handle the 257 * common case right away. 258 */ 259 if (cpu_feature & CPUID_FPU) { 260 hw_float = 1; 261 return (1); 262 } 263 264 save_idt_npxtrap = idt[IDT_MF]; 265 setidt(IDT_MF, probetrap, SDT_SYS386TGT, SEL_KPL, 266 GSEL(GCODE_SEL, SEL_KPL)); 267 268 /* 269 * Don't trap while we're probing. 270 */ 271 stop_emulating(); 272 273 /* 274 * Finish resetting the coprocessor, if any. If there is an error 275 * pending, then we may get a bogus IRQ13, but npx_intr() will handle 276 * it OK. Bogus halts have never been observed, but we enabled 277 * IRQ13 and cleared the BUSY# latch early to handle them anyway. 278 */ 279 fninit(); 280 281 /* 282 * Don't use fwait here because it might hang. 283 * Don't use fnop here because it usually hangs if there is no FPU. 284 */ 285 DELAY(1000); /* wait for any IRQ13 */ 286#ifdef DIAGNOSTIC 287 if (npx_traps_while_probing != 0) 288 printf("fninit caused %u bogus npx trap(s)\n", 289 npx_traps_while_probing); 290#endif 291 /* 292 * Check for a status of mostly zero. 293 */ 294 status = 0x5a5a; 295 fnstsw(&status); 296 if ((status & 0xb8ff) == 0) { 297 /* 298 * Good, now check for a proper control word. 299 */ 300 control = 0x5a5a; 301 fnstcw(&control); 302 if ((control & 0x1f3f) == 0x033f) { 303 /* 304 * We have an npx, now divide by 0 to see if exception 305 * 16 works. 306 */ 307 control &= ~(1 << 2); /* enable divide by 0 trap */ 308 fldcw(control); 309#ifdef FPU_ERROR_BROKEN 310 /* 311 * FPU error signal doesn't work on some CPU 312 * accelerator board. 313 */ 314 hw_float = 1; 315 return (1); 316#endif 317 npx_traps_while_probing = 0; 318 fp_divide_by_0(); 319 if (npx_traps_while_probing != 0) { 320 /* 321 * Good, exception 16 works. 322 */ 323 hw_float = 1; 324 goto cleanup; 325 } 326 printf( 327 "FPU does not use exception 16 for error reporting\n"); 328 goto cleanup; 329 } 330 } 331 332 /* 333 * Probe failed. Floating point simply won't work. 334 * Notify user and disable FPU/MMX/SSE instruction execution. 335 */ 336 printf("WARNING: no FPU!\n"); 337 __asm __volatile("smsw %%ax; orb %0,%%al; lmsw %%ax" : : 338 "n" (CR0_EM | CR0_MP) : "ax"); 339 340cleanup: 341 idt[IDT_MF] = save_idt_npxtrap; 342 return (hw_float); 343} 344 345#ifdef CPU_ENABLE_SSE 346/* 347 * Enable XSAVE if supported and allowed by user. 348 * Calculate the xsave_mask. 349 */ 350static void 351npxinit_bsp1(void) 352{ 353 u_int cp[4]; 354 uint64_t xsave_mask_user; 355 356 if (cpu_fxsr && (cpu_feature2 & CPUID2_XSAVE) != 0) { 357 use_xsave = 1; 358 TUNABLE_INT_FETCH("hw.use_xsave", &use_xsave); 359 } 360 if (!use_xsave) 361 return; 362 363 cpuid_count(0xd, 0x0, cp); 364 xsave_mask = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 365 if ((cp[0] & xsave_mask) != xsave_mask) 366 panic("CPU0 does not support X87 or SSE: %x", cp[0]); 367 xsave_mask = ((uint64_t)cp[3] << 32) | cp[0]; 368 xsave_mask_user = xsave_mask; 369 TUNABLE_QUAD_FETCH("hw.xsave_mask", &xsave_mask_user); 370 xsave_mask_user |= XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 371 xsave_mask &= xsave_mask_user; 372 if ((xsave_mask & XFEATURE_AVX512) != XFEATURE_AVX512) 373 xsave_mask &= ~XFEATURE_AVX512; 374 if ((xsave_mask & XFEATURE_MPX) != XFEATURE_MPX) 375 xsave_mask &= ~XFEATURE_MPX; 376 377 cpuid_count(0xd, 0x1, cp); 378 if ((cp[0] & CPUID_EXTSTATE_XSAVEOPT) != 0) 379 use_xsaveopt = 1; 380} 381#endif 382/* 383 384 * Calculate the fpu save area size. 385 */ 386static void 387npxinit_bsp2(void) 388{ 389#ifdef CPU_ENABLE_SSE 390 u_int cp[4]; 391 392 if (use_xsave) { 393 cpuid_count(0xd, 0x0, cp); 394 cpu_max_ext_state_size = cp[1]; 395 396 /* 397 * Reload the cpu_feature2, since we enabled OSXSAVE. 398 */ 399 do_cpuid(1, cp); 400 cpu_feature2 = cp[2]; 401 } else 402#endif 403 cpu_max_ext_state_size = sizeof(union savefpu); 404} 405 406/* 407 * Initialize floating point unit. 408 */ 409void 410npxinit(bool bsp) 411{ 412 static union savefpu dummy; 413 register_t saveintr; 414#ifdef CPU_ENABLE_SSE 415 u_int mxcsr; 416#endif 417 u_short control; 418 419 if (bsp) { 420 if (!npx_probe()) 421 return; 422#ifdef CPU_ENABLE_SSE 423 npxinit_bsp1(); 424#endif 425 } 426 427#ifdef CPU_ENABLE_SSE 428 if (use_xsave) { 429 load_cr4(rcr4() | CR4_XSAVE); 430 load_xcr(XCR0, xsave_mask); 431 } 432#endif 433 434 /* 435 * XCR0 shall be set up before CPU can report the save area size. 436 */ 437 if (bsp) 438 npxinit_bsp2(); 439 440 /* 441 * fninit has the same h/w bugs as fnsave. Use the detoxified 442 * fnsave to throw away any junk in the fpu. fpusave() initializes 443 * the fpu. 444 * 445 * It is too early for critical_enter() to work on AP. 446 */ 447 saveintr = intr_disable(); 448 stop_emulating(); 449#ifdef CPU_ENABLE_SSE 450 if (cpu_fxsr) 451 fninit(); 452 else 453#endif 454 fnsave(&dummy); 455 control = __INITIAL_NPXCW__; 456 fldcw(control); 457#ifdef CPU_ENABLE_SSE 458 if (cpu_fxsr) { 459 mxcsr = __INITIAL_MXCSR__; 460 ldmxcsr(mxcsr); 461 } 462#endif 463 start_emulating(); 464 intr_restore(saveintr); 465} 466 467/* 468 * On the boot CPU we generate a clean state that is used to 469 * initialize the floating point unit when it is first used by a 470 * process. 471 */ 472static void 473npxinitstate(void *arg __unused) 474{ 475 register_t saveintr; 476#ifdef CPU_ENABLE_SSE 477 int cp[4], i, max_ext_n; 478#endif 479 480 if (!hw_float) 481 return; 482 483 npx_initialstate = malloc(cpu_max_ext_state_size, M_DEVBUF, 484 M_WAITOK | M_ZERO); 485 saveintr = intr_disable(); 486 stop_emulating(); 487 488 fpusave(npx_initialstate); 489#ifdef CPU_ENABLE_SSE 490 if (cpu_fxsr) { 491 if (npx_initialstate->sv_xmm.sv_env.en_mxcsr_mask) 492 cpu_mxcsr_mask = 493 npx_initialstate->sv_xmm.sv_env.en_mxcsr_mask; 494 else 495 cpu_mxcsr_mask = 0xFFBF; 496 497 /* 498 * The fninit instruction does not modify XMM 499 * registers. The fpusave call dumped the garbage 500 * contained in the registers after reset to the 501 * initial state saved. Clear XMM registers file 502 * image to make the startup program state and signal 503 * handler XMM register content predictable. 504 */ 505 bzero(npx_initialstate->sv_xmm.sv_fp, 506 sizeof(npx_initialstate->sv_xmm.sv_fp)); 507 bzero(npx_initialstate->sv_xmm.sv_xmm, 508 sizeof(npx_initialstate->sv_xmm.sv_xmm)); 509 } else 510#endif 511 bzero(npx_initialstate->sv_87.sv_ac, 512 sizeof(npx_initialstate->sv_87.sv_ac)); 513 514#ifdef CPU_ENABLE_SSE 515 /* 516 * Create a table describing the layout of the CPU Extended 517 * Save Area. 518 */ 519 if (use_xsave) { 520 if (xsave_mask >> 32 != 0) 521 max_ext_n = fls(xsave_mask >> 32) + 32; 522 else 523 max_ext_n = fls(xsave_mask); 524 xsave_area_desc = malloc(max_ext_n * sizeof(struct 525 xsave_area_elm_descr), M_DEVBUF, M_WAITOK | M_ZERO); 526 /* x87 state */ 527 xsave_area_desc[0].offset = 0; 528 xsave_area_desc[0].size = 160; 529 /* XMM */ 530 xsave_area_desc[1].offset = 160; 531 xsave_area_desc[1].size = 288 - 160; 532 533 for (i = 2; i < max_ext_n; i++) { 534 cpuid_count(0xd, i, cp); 535 xsave_area_desc[i].offset = cp[1]; 536 xsave_area_desc[i].size = cp[0]; 537 } 538 } 539#endif 540 541 fpu_save_area_zone = uma_zcreate("FPU_save_area", 542 cpu_max_ext_state_size, NULL, NULL, NULL, NULL, 543 XSAVE_AREA_ALIGN - 1, 0); 544 545 start_emulating(); 546 intr_restore(saveintr); 547} 548SYSINIT(npxinitstate, SI_SUB_DRIVERS, SI_ORDER_ANY, npxinitstate, NULL); 549 550/* 551 * Free coprocessor (if we have it). 552 */ 553void 554npxexit(td) 555 struct thread *td; 556{ 557 558 critical_enter(); 559 if (curthread == PCPU_GET(fpcurthread)) { 560 stop_emulating(); 561 fpusave(curpcb->pcb_save); 562 start_emulating(); 563 PCPU_SET(fpcurthread, NULL); 564 } 565 critical_exit(); 566#ifdef NPX_DEBUG 567 if (hw_float) { 568 u_int masked_exceptions; 569 570 masked_exceptions = GET_FPU_CW(td) & GET_FPU_SW(td) & 0x7f; 571 /* 572 * Log exceptions that would have trapped with the old 573 * control word (overflow, divide by 0, and invalid operand). 574 */ 575 if (masked_exceptions & 0x0d) 576 log(LOG_ERR, 577 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n", 578 td->td_proc->p_pid, td->td_proc->p_comm, 579 masked_exceptions); 580 } 581#endif 582} 583 584int 585npxformat() 586{ 587 588 if (!hw_float) 589 return (_MC_FPFMT_NODEV); 590#ifdef CPU_ENABLE_SSE 591 if (cpu_fxsr) 592 return (_MC_FPFMT_XMM); 593#endif 594 return (_MC_FPFMT_387); 595} 596 597/* 598 * The following mechanism is used to ensure that the FPE_... value 599 * that is passed as a trapcode to the signal handler of the user 600 * process does not have more than one bit set. 601 * 602 * Multiple bits may be set if the user process modifies the control 603 * word while a status word bit is already set. While this is a sign 604 * of bad coding, we have no choise than to narrow them down to one 605 * bit, since we must not send a trapcode that is not exactly one of 606 * the FPE_ macros. 607 * 608 * The mechanism has a static table with 127 entries. Each combination 609 * of the 7 FPU status word exception bits directly translates to a 610 * position in this table, where a single FPE_... value is stored. 611 * This FPE_... value stored there is considered the "most important" 612 * of the exception bits and will be sent as the signal code. The 613 * precedence of the bits is based upon Intel Document "Numerical 614 * Applications", Chapter "Special Computational Situations". 615 * 616 * The macro to choose one of these values does these steps: 1) Throw 617 * away status word bits that cannot be masked. 2) Throw away the bits 618 * currently masked in the control word, assuming the user isn't 619 * interested in them anymore. 3) Reinsert status word bit 7 (stack 620 * fault) if it is set, which cannot be masked but must be presered. 621 * 4) Use the remaining bits to point into the trapcode table. 622 * 623 * The 6 maskable bits in order of their preference, as stated in the 624 * above referenced Intel manual: 625 * 1 Invalid operation (FP_X_INV) 626 * 1a Stack underflow 627 * 1b Stack overflow 628 * 1c Operand of unsupported format 629 * 1d SNaN operand. 630 * 2 QNaN operand (not an exception, irrelavant here) 631 * 3 Any other invalid-operation not mentioned above or zero divide 632 * (FP_X_INV, FP_X_DZ) 633 * 4 Denormal operand (FP_X_DNML) 634 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 635 * 6 Inexact result (FP_X_IMP) 636 */ 637static char fpetable[128] = { 638 0, 639 FPE_FLTINV, /* 1 - INV */ 640 FPE_FLTUND, /* 2 - DNML */ 641 FPE_FLTINV, /* 3 - INV | DNML */ 642 FPE_FLTDIV, /* 4 - DZ */ 643 FPE_FLTINV, /* 5 - INV | DZ */ 644 FPE_FLTDIV, /* 6 - DNML | DZ */ 645 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 646 FPE_FLTOVF, /* 8 - OFL */ 647 FPE_FLTINV, /* 9 - INV | OFL */ 648 FPE_FLTUND, /* A - DNML | OFL */ 649 FPE_FLTINV, /* B - INV | DNML | OFL */ 650 FPE_FLTDIV, /* C - DZ | OFL */ 651 FPE_FLTINV, /* D - INV | DZ | OFL */ 652 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 653 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 654 FPE_FLTUND, /* 10 - UFL */ 655 FPE_FLTINV, /* 11 - INV | UFL */ 656 FPE_FLTUND, /* 12 - DNML | UFL */ 657 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 658 FPE_FLTDIV, /* 14 - DZ | UFL */ 659 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 660 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 661 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 662 FPE_FLTOVF, /* 18 - OFL | UFL */ 663 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 664 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 665 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 666 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 667 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 668 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 669 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 670 FPE_FLTRES, /* 20 - IMP */ 671 FPE_FLTINV, /* 21 - INV | IMP */ 672 FPE_FLTUND, /* 22 - DNML | IMP */ 673 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 674 FPE_FLTDIV, /* 24 - DZ | IMP */ 675 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 676 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 677 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 678 FPE_FLTOVF, /* 28 - OFL | IMP */ 679 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 680 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 681 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 682 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 683 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 684 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 685 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 686 FPE_FLTUND, /* 30 - UFL | IMP */ 687 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 688 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 689 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 690 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 691 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 692 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 693 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 694 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 695 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 696 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 697 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 698 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 699 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 700 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 701 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 702 FPE_FLTSUB, /* 40 - STK */ 703 FPE_FLTSUB, /* 41 - INV | STK */ 704 FPE_FLTUND, /* 42 - DNML | STK */ 705 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 706 FPE_FLTDIV, /* 44 - DZ | STK */ 707 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 708 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 709 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 710 FPE_FLTOVF, /* 48 - OFL | STK */ 711 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 712 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 713 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 714 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 715 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 716 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 717 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 718 FPE_FLTUND, /* 50 - UFL | STK */ 719 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 720 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 721 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 722 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 723 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 724 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 725 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 726 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 727 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 728 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 729 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 730 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 731 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 732 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 733 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 734 FPE_FLTRES, /* 60 - IMP | STK */ 735 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 736 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 737 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 738 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 739 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 740 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 741 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 742 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 743 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 744 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 745 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 746 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 747 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 748 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 749 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 750 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 751 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 752 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 753 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 754 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 755 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 756 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 757 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 758 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 759 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 760 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 761 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 762 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 763 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 764 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 765 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 766}; 767 768/* 769 * Read the FP status and control words, then generate si_code value 770 * for SIGFPE. The error code chosen will be one of the 771 * FPE_... macros. It will be sent as the second argument to old 772 * BSD-style signal handlers and as "siginfo_t->si_code" (second 773 * argument) to SA_SIGINFO signal handlers. 774 * 775 * Some time ago, we cleared the x87 exceptions with FNCLEX there. 776 * Clearing exceptions was necessary mainly to avoid IRQ13 bugs. The 777 * usermode code which understands the FPU hardware enough to enable 778 * the exceptions, can also handle clearing the exception state in the 779 * handler. The only consequence of not clearing the exception is the 780 * rethrow of the SIGFPE on return from the signal handler and 781 * reexecution of the corresponding instruction. 782 * 783 * For XMM traps, the exceptions were never cleared. 784 */ 785int 786npxtrap_x87(void) 787{ 788 u_short control, status; 789 790 if (!hw_float) { 791 printf( 792 "npxtrap_x87: fpcurthread = %p, curthread = %p, hw_float = %d\n", 793 PCPU_GET(fpcurthread), curthread, hw_float); 794 panic("npxtrap from nowhere"); 795 } 796 critical_enter(); 797 798 /* 799 * Interrupt handling (for another interrupt) may have pushed the 800 * state to memory. Fetch the relevant parts of the state from 801 * wherever they are. 802 */ 803 if (PCPU_GET(fpcurthread) != curthread) { 804 control = GET_FPU_CW(curthread); 805 status = GET_FPU_SW(curthread); 806 } else { 807 fnstcw(&control); 808 fnstsw(&status); 809 } 810 critical_exit(); 811 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 812} 813 814#ifdef CPU_ENABLE_SSE 815int 816npxtrap_sse(void) 817{ 818 u_int mxcsr; 819 820 if (!hw_float) { 821 printf( 822 "npxtrap_sse: fpcurthread = %p, curthread = %p, hw_float = %d\n", 823 PCPU_GET(fpcurthread), curthread, hw_float); 824 panic("npxtrap from nowhere"); 825 } 826 critical_enter(); 827 if (PCPU_GET(fpcurthread) != curthread) 828 mxcsr = curthread->td_pcb->pcb_save->sv_xmm.sv_env.en_mxcsr; 829 else 830 stmxcsr(&mxcsr); 831 critical_exit(); 832 return (fpetable[(mxcsr & (~mxcsr >> 7)) & 0x3f]); 833} 834#endif 835 836/* 837 * Implement device not available (DNA) exception 838 * 839 * It would be better to switch FP context here (if curthread != fpcurthread) 840 * and not necessarily for every context switch, but it is too hard to 841 * access foreign pcb's. 842 */ 843 844static int err_count = 0; 845 846int 847npxdna(void) 848{ 849 850 if (!hw_float) 851 return (0); 852 critical_enter(); 853 if (PCPU_GET(fpcurthread) == curthread) { 854 printf("npxdna: fpcurthread == curthread %d times\n", 855 ++err_count); 856 stop_emulating(); 857 critical_exit(); 858 return (1); 859 } 860 if (PCPU_GET(fpcurthread) != NULL) { 861 printf("npxdna: fpcurthread = %p (%d), curthread = %p (%d)\n", 862 PCPU_GET(fpcurthread), 863 PCPU_GET(fpcurthread)->td_proc->p_pid, 864 curthread, curthread->td_proc->p_pid); 865 panic("npxdna"); 866 } 867 stop_emulating(); 868 /* 869 * Record new context early in case frstor causes a trap. 870 */ 871 PCPU_SET(fpcurthread, curthread); 872 873#ifdef CPU_ENABLE_SSE 874 if (cpu_fxsr) 875 fpu_clean_state(); 876#endif 877 878 if ((curpcb->pcb_flags & PCB_NPXINITDONE) == 0) { 879 /* 880 * This is the first time this thread has used the FPU or 881 * the PCB doesn't contain a clean FPU state. Explicitly 882 * load an initial state. 883 * 884 * We prefer to restore the state from the actual save 885 * area in PCB instead of directly loading from 886 * npx_initialstate, to ignite the XSAVEOPT 887 * tracking engine. 888 */ 889 bcopy(npx_initialstate, curpcb->pcb_save, cpu_max_ext_state_size); 890 fpurstor(curpcb->pcb_save); 891 if (curpcb->pcb_initial_npxcw != __INITIAL_NPXCW__) 892 fldcw(curpcb->pcb_initial_npxcw); 893 curpcb->pcb_flags |= PCB_NPXINITDONE; 894 if (PCB_USER_FPU(curpcb)) 895 curpcb->pcb_flags |= PCB_NPXUSERINITDONE; 896 } else { 897 fpurstor(curpcb->pcb_save); 898 } 899 critical_exit(); 900 901 return (1); 902} 903 904/* 905 * Wrapper for fpusave() called from context switch routines. 906 * 907 * npxsave() must be called with interrupts disabled, so that it clears 908 * fpcurthread atomically with saving the state. We require callers to do the 909 * disabling, since most callers need to disable interrupts anyway to call 910 * npxsave() atomically with checking fpcurthread. 911 */ 912void 913npxsave(addr) 914 union savefpu *addr; 915{ 916 917 stop_emulating(); 918#ifdef CPU_ENABLE_SSE 919 if (use_xsaveopt) 920 xsaveopt((char *)addr, xsave_mask); 921 else 922#endif 923 fpusave(addr); 924 start_emulating(); 925 PCPU_SET(fpcurthread, NULL); 926} 927 928/* 929 * Unconditionally save the current co-processor state across suspend and 930 * resume. 931 */ 932void 933npxsuspend(union savefpu *addr) 934{ 935 register_t cr0; 936 937 if (!hw_float) 938 return; 939 if (PCPU_GET(fpcurthread) == NULL) { 940 bcopy(npx_initialstate, addr, cpu_max_ext_state_size); 941 return; 942 } 943 cr0 = rcr0(); 944 stop_emulating(); 945 fpusave(addr); 946 load_cr0(cr0); 947} 948 949void 950npxresume(union savefpu *addr) 951{ 952 register_t cr0; 953 954 if (!hw_float) 955 return; 956 957 cr0 = rcr0(); 958 npxinit(false); 959 stop_emulating(); 960 fpurstor(addr); 961 load_cr0(cr0); 962} 963 964void 965npxdrop() 966{ 967 struct thread *td; 968 969 /* 970 * Discard pending exceptions in the !cpu_fxsr case so that unmasked 971 * ones don't cause a panic on the next frstor. 972 */ 973#ifdef CPU_ENABLE_SSE 974 if (!cpu_fxsr) 975#endif 976 fnclex(); 977 978 td = PCPU_GET(fpcurthread); 979 KASSERT(td == curthread, ("fpudrop: fpcurthread != curthread")); 980 CRITICAL_ASSERT(td); 981 PCPU_SET(fpcurthread, NULL); 982 td->td_pcb->pcb_flags &= ~PCB_NPXINITDONE; 983 start_emulating(); 984} 985 986/* 987 * Get the user state of the FPU into pcb->pcb_user_save without 988 * dropping ownership (if possible). It returns the FPU ownership 989 * status. 990 */ 991int 992npxgetregs(struct thread *td) 993{ 994 struct pcb *pcb; 995#ifdef CPU_ENABLE_SSE 996 uint64_t *xstate_bv, bit; 997 char *sa; 998 int max_ext_n, i; 999#endif 1000 int owned; 1001 1002 if (!hw_float) 1003 return (_MC_FPOWNED_NONE); 1004 1005 pcb = td->td_pcb; 1006 if ((pcb->pcb_flags & PCB_NPXINITDONE) == 0) { 1007 bcopy(npx_initialstate, get_pcb_user_save_pcb(pcb), 1008 cpu_max_ext_state_size); 1009 SET_FPU_CW(get_pcb_user_save_pcb(pcb), pcb->pcb_initial_npxcw); 1010 npxuserinited(td); 1011 return (_MC_FPOWNED_PCB); 1012 } 1013 critical_enter(); 1014 if (td == PCPU_GET(fpcurthread)) { 1015 fpusave(get_pcb_user_save_pcb(pcb)); 1016#ifdef CPU_ENABLE_SSE 1017 if (!cpu_fxsr) 1018#endif 1019 /* 1020 * fnsave initializes the FPU and destroys whatever 1021 * context it contains. Make sure the FPU owner 1022 * starts with a clean state next time. 1023 */ 1024 npxdrop(); 1025 owned = _MC_FPOWNED_FPU; 1026 } else { 1027 owned = _MC_FPOWNED_PCB; 1028 } 1029 critical_exit(); 1030#ifdef CPU_ENABLE_SSE 1031 if (use_xsave) { 1032 /* 1033 * Handle partially saved state. 1034 */ 1035 sa = (char *)get_pcb_user_save_pcb(pcb); 1036 xstate_bv = (uint64_t *)(sa + sizeof(union savefpu) + 1037 offsetof(struct xstate_hdr, xstate_bv)); 1038 if (xsave_mask >> 32 != 0) 1039 max_ext_n = fls(xsave_mask >> 32) + 32; 1040 else 1041 max_ext_n = fls(xsave_mask); 1042 for (i = 0; i < max_ext_n; i++) { 1043 bit = 1ULL << i; 1044 if ((xsave_mask & bit) == 0 || (*xstate_bv & bit) != 0) 1045 continue; 1046 bcopy((char *)npx_initialstate + 1047 xsave_area_desc[i].offset, 1048 sa + xsave_area_desc[i].offset, 1049 xsave_area_desc[i].size); 1050 *xstate_bv |= bit; 1051 } 1052 } 1053#endif 1054 return (owned); 1055} 1056 1057void 1058npxuserinited(struct thread *td) 1059{ 1060 struct pcb *pcb; 1061 1062 pcb = td->td_pcb; 1063 if (PCB_USER_FPU(pcb)) 1064 pcb->pcb_flags |= PCB_NPXINITDONE; 1065 pcb->pcb_flags |= PCB_NPXUSERINITDONE; 1066} 1067 1068#ifdef CPU_ENABLE_SSE 1069int 1070npxsetxstate(struct thread *td, char *xfpustate, size_t xfpustate_size) 1071{ 1072 struct xstate_hdr *hdr, *ehdr; 1073 size_t len, max_len; 1074 uint64_t bv; 1075 1076 /* XXXKIB should we clear all extended state in xstate_bv instead ? */ 1077 if (xfpustate == NULL) 1078 return (0); 1079 if (!use_xsave) 1080 return (EOPNOTSUPP); 1081 1082 len = xfpustate_size; 1083 if (len < sizeof(struct xstate_hdr)) 1084 return (EINVAL); 1085 max_len = cpu_max_ext_state_size - sizeof(union savefpu); 1086 if (len > max_len) 1087 return (EINVAL); 1088 1089 ehdr = (struct xstate_hdr *)xfpustate; 1090 bv = ehdr->xstate_bv; 1091 1092 /* 1093 * Avoid #gp. 1094 */ 1095 if (bv & ~xsave_mask) 1096 return (EINVAL); 1097 1098 hdr = (struct xstate_hdr *)(get_pcb_user_save_td(td) + 1); 1099 1100 hdr->xstate_bv = bv; 1101 bcopy(xfpustate + sizeof(struct xstate_hdr), 1102 (char *)(hdr + 1), len - sizeof(struct xstate_hdr)); 1103 1104 return (0); 1105} 1106#endif 1107 1108int 1109npxsetregs(struct thread *td, union savefpu *addr, char *xfpustate, 1110 size_t xfpustate_size) 1111{ 1112 struct pcb *pcb; 1113#ifdef CPU_ENABLE_SSE 1114 int error; 1115#endif 1116 1117 if (!hw_float) 1118 return (ENXIO); 1119 1120 pcb = td->td_pcb; 1121 critical_enter(); 1122 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) { 1123#ifdef CPU_ENABLE_SSE 1124 error = npxsetxstate(td, xfpustate, xfpustate_size); 1125 if (error != 0) { 1126 critical_exit(); 1127 return (error); 1128 } 1129 if (!cpu_fxsr) 1130#endif 1131 fnclex(); /* As in npxdrop(). */ 1132 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr)); 1133 fpurstor(get_pcb_user_save_td(td)); 1134 critical_exit(); 1135 pcb->pcb_flags |= PCB_NPXUSERINITDONE | PCB_NPXINITDONE; 1136 } else { 1137 critical_exit(); 1138#ifdef CPU_ENABLE_SSE 1139 error = npxsetxstate(td, xfpustate, xfpustate_size); 1140 if (error != 0) 1141 return (error); 1142#endif 1143 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr)); 1144 npxuserinited(td); 1145 } 1146 return (0); 1147} 1148 1149static void 1150fpusave(addr) 1151 union savefpu *addr; 1152{ 1153 1154#ifdef CPU_ENABLE_SSE 1155 if (use_xsave) 1156 xsave((char *)addr, xsave_mask); 1157 else if (cpu_fxsr) 1158 fxsave(addr); 1159 else 1160#endif 1161 fnsave(addr); 1162} 1163 1164#ifdef CPU_ENABLE_SSE 1165/* 1166 * On AuthenticAMD processors, the fxrstor instruction does not restore 1167 * the x87's stored last instruction pointer, last data pointer, and last 1168 * opcode values, except in the rare case in which the exception summary 1169 * (ES) bit in the x87 status word is set to 1. 1170 * 1171 * In order to avoid leaking this information across processes, we clean 1172 * these values by performing a dummy load before executing fxrstor(). 1173 */ 1174static void 1175fpu_clean_state(void) 1176{ 1177 static float dummy_variable = 0.0; 1178 u_short status; 1179 1180 /* 1181 * Clear the ES bit in the x87 status word if it is currently 1182 * set, in order to avoid causing a fault in the upcoming load. 1183 */ 1184 fnstsw(&status); 1185 if (status & 0x80) 1186 fnclex(); 1187 1188 /* 1189 * Load the dummy variable into the x87 stack. This mangles 1190 * the x87 stack, but we don't care since we're about to call 1191 * fxrstor() anyway. 1192 */ 1193 __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable)); 1194} 1195#endif /* CPU_ENABLE_SSE */ 1196 1197static void 1198fpurstor(addr) 1199 union savefpu *addr; 1200{ 1201 1202#ifdef CPU_ENABLE_SSE 1203 if (use_xsave) 1204 xrstor((char *)addr, xsave_mask); 1205 else if (cpu_fxsr) 1206 fxrstor(addr); 1207 else 1208#endif 1209 frstor(addr); 1210} 1211 1212#ifdef DEV_ISA 1213/* 1214 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI. 1215 */ 1216static struct isa_pnp_id npxisa_ids[] = { 1217 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 1218 { 0 } 1219}; 1220 1221static int 1222npxisa_probe(device_t dev) 1223{ 1224 int result; 1225 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) { 1226 device_quiet(dev); 1227 } 1228 return(result); 1229} 1230 1231static int 1232npxisa_attach(device_t dev) 1233{ 1234 return (0); 1235} 1236 1237static device_method_t npxisa_methods[] = { 1238 /* Device interface */ 1239 DEVMETHOD(device_probe, npxisa_probe), 1240 DEVMETHOD(device_attach, npxisa_attach), 1241 DEVMETHOD(device_detach, bus_generic_detach), 1242 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1243 DEVMETHOD(device_suspend, bus_generic_suspend), 1244 DEVMETHOD(device_resume, bus_generic_resume), 1245 1246 { 0, 0 } 1247}; 1248 1249static driver_t npxisa_driver = { 1250 "npxisa", 1251 npxisa_methods, 1252 1, /* no softc */ 1253}; 1254 1255static devclass_t npxisa_devclass; 1256 1257DRIVER_MODULE(npxisa, isa, npxisa_driver, npxisa_devclass, 0, 0); 1258#ifndef PC98 1259DRIVER_MODULE(npxisa, acpi, npxisa_driver, npxisa_devclass, 0, 0); 1260#endif 1261#endif /* DEV_ISA */ 1262 1263static MALLOC_DEFINE(M_FPUKERN_CTX, "fpukern_ctx", 1264 "Kernel contexts for FPU state"); 1265 1266#define FPU_KERN_CTX_NPXINITDONE 0x01 1267#define FPU_KERN_CTX_DUMMY 0x02 1268 1269struct fpu_kern_ctx { 1270 union savefpu *prev; 1271 uint32_t flags; 1272 char hwstate1[]; 1273}; 1274 1275struct fpu_kern_ctx * 1276fpu_kern_alloc_ctx(u_int flags) 1277{ 1278 struct fpu_kern_ctx *res; 1279 size_t sz; 1280 1281 sz = sizeof(struct fpu_kern_ctx) + XSAVE_AREA_ALIGN + 1282 cpu_max_ext_state_size; 1283 res = malloc(sz, M_FPUKERN_CTX, ((flags & FPU_KERN_NOWAIT) ? 1284 M_NOWAIT : M_WAITOK) | M_ZERO); 1285 return (res); 1286} 1287 1288void 1289fpu_kern_free_ctx(struct fpu_kern_ctx *ctx) 1290{ 1291 1292 /* XXXKIB clear the memory ? */ 1293 free(ctx, M_FPUKERN_CTX); 1294} 1295 1296static union savefpu * 1297fpu_kern_ctx_savefpu(struct fpu_kern_ctx *ctx) 1298{ 1299 vm_offset_t p; 1300 1301 p = (vm_offset_t)&ctx->hwstate1; 1302 p = roundup2(p, XSAVE_AREA_ALIGN); 1303 return ((union savefpu *)p); 1304} 1305 1306int 1307fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, u_int flags) 1308{ 1309 struct pcb *pcb; 1310 1311 if ((flags & FPU_KERN_KTHR) != 0 && is_fpu_kern_thread(0)) { 1312 ctx->flags = FPU_KERN_CTX_DUMMY; 1313 return (0); 1314 } 1315 pcb = td->td_pcb; 1316 KASSERT(!PCB_USER_FPU(pcb) || pcb->pcb_save == 1317 get_pcb_user_save_pcb(pcb), ("mangled pcb_save")); 1318 ctx->flags = 0; 1319 if ((pcb->pcb_flags & PCB_NPXINITDONE) != 0) 1320 ctx->flags |= FPU_KERN_CTX_NPXINITDONE; 1321 npxexit(td); 1322 ctx->prev = pcb->pcb_save; 1323 pcb->pcb_save = fpu_kern_ctx_savefpu(ctx); 1324 pcb->pcb_flags |= PCB_KERNNPX; 1325 pcb->pcb_flags &= ~PCB_NPXINITDONE; 1326 return (0); 1327} 1328 1329int 1330fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx) 1331{ 1332 struct pcb *pcb; 1333 1334 if (is_fpu_kern_thread(0) && (ctx->flags & FPU_KERN_CTX_DUMMY) != 0) 1335 return (0); 1336 pcb = td->td_pcb; 1337 critical_enter(); 1338 if (curthread == PCPU_GET(fpcurthread)) 1339 npxdrop(); 1340 critical_exit(); 1341 pcb->pcb_save = ctx->prev; 1342 if (pcb->pcb_save == get_pcb_user_save_pcb(pcb)) { 1343 if ((pcb->pcb_flags & PCB_NPXUSERINITDONE) != 0) 1344 pcb->pcb_flags |= PCB_NPXINITDONE; 1345 else 1346 pcb->pcb_flags &= ~PCB_NPXINITDONE; 1347 pcb->pcb_flags &= ~PCB_KERNNPX; 1348 } else { 1349 if ((ctx->flags & FPU_KERN_CTX_NPXINITDONE) != 0) 1350 pcb->pcb_flags |= PCB_NPXINITDONE; 1351 else 1352 pcb->pcb_flags &= ~PCB_NPXINITDONE; 1353 KASSERT(!PCB_USER_FPU(pcb), ("unpaired fpu_kern_leave")); 1354 } 1355 return (0); 1356} 1357 1358int 1359fpu_kern_thread(u_int flags) 1360{ 1361 struct pcb *pcb; 1362 1363 pcb = curpcb; 1364 KASSERT((curthread->td_pflags & TDP_KTHREAD) != 0, 1365 ("Only kthread may use fpu_kern_thread")); 1366 KASSERT(curpcb->pcb_save == get_pcb_user_save_pcb(curpcb), 1367 ("mangled pcb_save")); 1368 KASSERT(PCB_USER_FPU(curpcb), ("recursive call")); 1369 1370 curpcb->pcb_flags |= PCB_KERNNPX; 1371 return (0); 1372} 1373 1374int 1375is_fpu_kern_thread(u_int flags) 1376{ 1377 1378 if ((curthread->td_pflags & TDP_KTHREAD) == 0) 1379 return (0); 1380 return ((curpcb->pcb_flags & PCB_KERNNPX) != 0); 1381} 1382 1383/* 1384 * FPU save area alloc/free/init utility routines 1385 */ 1386union savefpu * 1387fpu_save_area_alloc(void) 1388{ 1389 1390 return (uma_zalloc(fpu_save_area_zone, 0)); 1391} 1392 1393void 1394fpu_save_area_free(union savefpu *fsa) 1395{ 1396 1397 uma_zfree(fpu_save_area_zone, fsa); 1398} 1399 1400void 1401fpu_save_area_reset(union savefpu *fsa) 1402{ 1403 1404 bcopy(npx_initialstate, fsa, cpu_max_ext_state_size); 1405} 1406