pmap.c revision 270439
150477Speter/*- 216186Salex * Copyright (c) 1991 Regents of the University of California. 316186Salex * All rights reserved. 488064Sru * Copyright (c) 1994 John S. Dyson 588064Sru * All rights reserved. 616186Salex * Copyright (c) 1994 David Greenman 716186Salex * All rights reserved. 8 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu> 9 * All rights reserved. 10 * 11 * This code is derived from software contributed to Berkeley by 12 * the Systems Programming Group of the University of Utah Computer 13 * Science Department and William Jolitz of UUNET Technologies Inc. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 3. All advertising materials mentioning features or use of this software 24 * must display the following acknowledgement: 25 * This product includes software developed by the University of 26 * California, Berkeley and its contributors. 27 * 4. Neither the name of the University nor the names of its contributors 28 * may be used to endorse or promote products derived from this software 29 * without specific prior written permission. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 41 * SUCH DAMAGE. 42 * 43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 44 */ 45/*- 46 * Copyright (c) 2003 Networks Associates Technology, Inc. 47 * All rights reserved. 48 * 49 * This software was developed for the FreeBSD Project by Jake Burkholder, 50 * Safeport Network Services, and Network Associates Laboratories, the 51 * Security Research Division of Network Associates, Inc. under 52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA 53 * CHATS research program. 54 * 55 * Redistribution and use in source and binary forms, with or without 56 * modification, are permitted provided that the following conditions 57 * are met: 58 * 1. Redistributions of source code must retain the above copyright 59 * notice, this list of conditions and the following disclaimer. 60 * 2. Redistributions in binary form must reproduce the above copyright 61 * notice, this list of conditions and the following disclaimer in the 62 * documentation and/or other materials provided with the distribution. 63 * 64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 74 * SUCH DAMAGE. 75 */ 76 77#include <sys/cdefs.h> 78__FBSDID("$FreeBSD: stable/10/sys/i386/i386/pmap.c 270439 2014-08-24 07:53:15Z kib $"); 79 80/* 81 * Manages physical address maps. 82 * 83 * Since the information managed by this module is 84 * also stored by the logical address mapping module, 85 * this module may throw away valid virtual-to-physical 86 * mappings at almost any time. However, invalidations 87 * of virtual-to-physical mappings must be done as 88 * requested. 89 * 90 * In order to cope with hardware architectures which 91 * make virtual-to-physical map invalidates expensive, 92 * this module may delay invalidate or reduced protection 93 * operations until such time as they are actually 94 * necessary. This module is given full information as 95 * to which processors are currently using which maps, 96 * and to when physical maps must be made correct. 97 */ 98 99#include "opt_apic.h" 100#include "opt_cpu.h" 101#include "opt_pmap.h" 102#include "opt_smp.h" 103#include "opt_xbox.h" 104 105#include <sys/param.h> 106#include <sys/systm.h> 107#include <sys/kernel.h> 108#include <sys/ktr.h> 109#include <sys/lock.h> 110#include <sys/malloc.h> 111#include <sys/mman.h> 112#include <sys/msgbuf.h> 113#include <sys/mutex.h> 114#include <sys/proc.h> 115#include <sys/rwlock.h> 116#include <sys/sf_buf.h> 117#include <sys/sx.h> 118#include <sys/vmmeter.h> 119#include <sys/sched.h> 120#include <sys/sysctl.h> 121#ifdef SMP 122#include <sys/smp.h> 123#else 124#include <sys/cpuset.h> 125#endif 126 127#include <vm/vm.h> 128#include <vm/vm_param.h> 129#include <vm/vm_kern.h> 130#include <vm/vm_page.h> 131#include <vm/vm_map.h> 132#include <vm/vm_object.h> 133#include <vm/vm_extern.h> 134#include <vm/vm_pageout.h> 135#include <vm/vm_pager.h> 136#include <vm/vm_radix.h> 137#include <vm/vm_reserv.h> 138#include <vm/uma.h> 139 140#ifdef DEV_APIC 141#include <sys/bus.h> 142#include <machine/intr_machdep.h> 143#include <machine/apicvar.h> 144#endif 145#include <machine/cpu.h> 146#include <machine/cputypes.h> 147#include <machine/md_var.h> 148#include <machine/pcb.h> 149#include <machine/specialreg.h> 150#ifdef SMP 151#include <machine/smp.h> 152#endif 153 154#ifdef XBOX 155#include <machine/xbox.h> 156#endif 157 158#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU) 159#define CPU_ENABLE_SSE 160#endif 161 162#ifndef PMAP_SHPGPERPROC 163#define PMAP_SHPGPERPROC 200 164#endif 165 166#if !defined(DIAGNOSTIC) 167#ifdef __GNUC_GNU_INLINE__ 168#define PMAP_INLINE __attribute__((__gnu_inline__)) inline 169#else 170#define PMAP_INLINE extern inline 171#endif 172#else 173#define PMAP_INLINE 174#endif 175 176#ifdef PV_STATS 177#define PV_STAT(x) do { x ; } while (0) 178#else 179#define PV_STAT(x) do { } while (0) 180#endif 181 182#define pa_index(pa) ((pa) >> PDRSHIFT) 183#define pa_to_pvh(pa) (&pv_table[pa_index(pa)]) 184 185/* 186 * Get PDEs and PTEs for user/kernel address space 187 */ 188#define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT])) 189#define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT]) 190 191#define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0) 192#define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0) 193#define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0) 194#define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0) 195#define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0) 196 197#define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \ 198 atomic_clear_int((u_int *)(pte), PG_W)) 199#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v))) 200 201struct pmap kernel_pmap_store; 202LIST_HEAD(pmaplist, pmap); 203static struct pmaplist allpmaps; 204static struct mtx allpmaps_lock; 205 206vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 207vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 208int pgeflag = 0; /* PG_G or-in */ 209int pseflag = 0; /* PG_PS or-in */ 210 211static int nkpt = NKPT; 212vm_offset_t kernel_vm_end = KERNBASE + NKPT * NBPDR; 213extern u_int32_t KERNend; 214extern u_int32_t KPTphys; 215 216#ifdef PAE 217pt_entry_t pg_nx; 218static uma_zone_t pdptzone; 219#endif 220 221static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters"); 222 223static int pat_works = 1; 224SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1, 225 "Is page attribute table fully functional?"); 226 227static int pg_ps_enabled = 1; 228SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN, &pg_ps_enabled, 0, 229 "Are large page mappings enabled?"); 230 231#define PAT_INDEX_SIZE 8 232static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */ 233 234static struct rwlock_padalign pvh_global_lock; 235 236/* 237 * Data for the pv entry allocation mechanism 238 */ 239static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks); 240static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 241static struct md_page *pv_table; 242static int shpgperproc = PMAP_SHPGPERPROC; 243 244struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */ 245int pv_maxchunks; /* How many chunks we have KVA for */ 246vm_offset_t pv_vafree; /* freelist stored in the PTE */ 247 248/* 249 * All those kernel PT submaps that BSD is so fond of 250 */ 251struct sysmaps { 252 struct mtx lock; 253 pt_entry_t *CMAP1; 254 pt_entry_t *CMAP2; 255 caddr_t CADDR1; 256 caddr_t CADDR2; 257}; 258static struct sysmaps sysmaps_pcpu[MAXCPU]; 259pt_entry_t *CMAP3; 260static pd_entry_t *KPTD; 261caddr_t ptvmmap = 0; 262caddr_t CADDR3; 263struct msgbuf *msgbufp = 0; 264 265/* 266 * Crashdump maps. 267 */ 268static caddr_t crashdumpmap; 269 270static pt_entry_t *PMAP1 = 0, *PMAP2; 271static pt_entry_t *PADDR1 = 0, *PADDR2; 272#ifdef SMP 273static int PMAP1cpu; 274static int PMAP1changedcpu; 275SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD, 276 &PMAP1changedcpu, 0, 277 "Number of times pmap_pte_quick changed CPU with same PMAP1"); 278#endif 279static int PMAP1changed; 280SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD, 281 &PMAP1changed, 0, 282 "Number of times pmap_pte_quick changed PMAP1"); 283static int PMAP1unchanged; 284SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD, 285 &PMAP1unchanged, 0, 286 "Number of times pmap_pte_quick didn't change PMAP1"); 287static struct mtx PMAP2mutex; 288 289static void free_pv_chunk(struct pv_chunk *pc); 290static void free_pv_entry(pmap_t pmap, pv_entry_t pv); 291static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try); 292static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa); 293static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa); 294static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa); 295static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va); 296static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, 297 vm_offset_t va); 298static int pmap_pvh_wired_mappings(struct md_page *pvh, int count); 299 300static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va); 301static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, 302 vm_prot_t prot); 303static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, 304 vm_page_t m, vm_prot_t prot, vm_page_t mpte); 305static void pmap_flush_page(vm_page_t m); 306static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte); 307static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte); 308static boolean_t pmap_is_modified_pvh(struct md_page *pvh); 309static boolean_t pmap_is_referenced_pvh(struct md_page *pvh); 310static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode); 311static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde); 312static vm_page_t pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va); 313static void pmap_pde_attr(pd_entry_t *pde, int cache_bits); 314static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va); 315static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, 316 vm_prot_t prot); 317static void pmap_pte_attr(pt_entry_t *pte, int cache_bits); 318static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva, 319 struct spglist *free); 320static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva, 321 struct spglist *free); 322static void pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte); 323static void pmap_remove_page(struct pmap *pmap, vm_offset_t va, 324 struct spglist *free); 325static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, 326 vm_offset_t va); 327static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m); 328static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, 329 vm_page_t m); 330static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, 331 pd_entry_t newpde); 332static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde); 333 334static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags); 335 336static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags); 337static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free); 338static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va); 339static void pmap_pte_release(pt_entry_t *pte); 340static int pmap_unuse_pt(pmap_t, vm_offset_t, struct spglist *); 341#ifdef PAE 342static void *pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait); 343#endif 344static void pmap_set_pg(void); 345 346static __inline void pagezero(void *page); 347 348CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t)); 349CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t)); 350 351/* 352 * If you get an error here, then you set KVA_PAGES wrong! See the 353 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be 354 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE. 355 */ 356CTASSERT(KERNBASE % (1 << 24) == 0); 357 358/* 359 * Bootstrap the system enough to run with virtual memory. 360 * 361 * On the i386 this is called after mapping has already been enabled 362 * and just syncs the pmap module with what has already been done. 363 * [We can't call it easily with mapping off since the kernel is not 364 * mapped with PA == VA, hence we would have to relocate every address 365 * from the linked base (virtual) address "KERNBASE" to the actual 366 * (physical) address starting relative to 0] 367 */ 368void 369pmap_bootstrap(vm_paddr_t firstaddr) 370{ 371 vm_offset_t va; 372 pt_entry_t *pte, *unused; 373 struct sysmaps *sysmaps; 374 int i; 375 376 /* 377 * Initialize the first available kernel virtual address. However, 378 * using "firstaddr" may waste a few pages of the kernel virtual 379 * address space, because locore may not have mapped every physical 380 * page that it allocated. Preferably, locore would provide a first 381 * unused virtual address in addition to "firstaddr". 382 */ 383 virtual_avail = (vm_offset_t) KERNBASE + firstaddr; 384 385 virtual_end = VM_MAX_KERNEL_ADDRESS; 386 387 /* 388 * Initialize the kernel pmap (which is statically allocated). 389 */ 390 PMAP_LOCK_INIT(kernel_pmap); 391 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD); 392#ifdef PAE 393 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT); 394#endif 395 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */ 396 TAILQ_INIT(&kernel_pmap->pm_pvchunk); 397 398 /* 399 * Initialize the global pv list lock. 400 */ 401 rw_init(&pvh_global_lock, "pmap pv global"); 402 403 LIST_INIT(&allpmaps); 404 405 /* 406 * Request a spin mutex so that changes to allpmaps cannot be 407 * preempted by smp_rendezvous_cpus(). Otherwise, 408 * pmap_update_pde_kernel() could access allpmaps while it is 409 * being changed. 410 */ 411 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN); 412 mtx_lock_spin(&allpmaps_lock); 413 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list); 414 mtx_unlock_spin(&allpmaps_lock); 415 416 /* 417 * Reserve some special page table entries/VA space for temporary 418 * mapping of pages. 419 */ 420#define SYSMAP(c, p, v, n) \ 421 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 422 423 va = virtual_avail; 424 pte = vtopte(va); 425 426 /* 427 * CMAP1/CMAP2 are used for zeroing and copying pages. 428 * CMAP3 is used for the idle process page zeroing. 429 */ 430 for (i = 0; i < MAXCPU; i++) { 431 sysmaps = &sysmaps_pcpu[i]; 432 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF); 433 SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1) 434 SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1) 435 } 436 SYSMAP(caddr_t, CMAP3, CADDR3, 1) 437 438 /* 439 * Crashdump maps. 440 */ 441 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS) 442 443 /* 444 * ptvmmap is used for reading arbitrary physical pages via /dev/mem. 445 */ 446 SYSMAP(caddr_t, unused, ptvmmap, 1) 447 448 /* 449 * msgbufp is used to map the system message buffer. 450 */ 451 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize))) 452 453 /* 454 * KPTmap is used by pmap_kextract(). 455 * 456 * KPTmap is first initialized by locore. However, that initial 457 * KPTmap can only support NKPT page table pages. Here, a larger 458 * KPTmap is created that can support KVA_PAGES page table pages. 459 */ 460 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES) 461 462 for (i = 0; i < NKPT; i++) 463 KPTD[i] = (KPTphys + (i << PAGE_SHIFT)) | pgeflag | PG_RW | PG_V; 464 465 /* 466 * Adjust the start of the KPTD and KPTmap so that the implementation 467 * of pmap_kextract() and pmap_growkernel() can be made simpler. 468 */ 469 KPTD -= KPTDI; 470 KPTmap -= i386_btop(KPTDI << PDRSHIFT); 471 472 /* 473 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(), 474 * respectively. 475 */ 476 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1) 477 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1) 478 479 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF); 480 481 virtual_avail = va; 482 483 /* 484 * Leave in place an identity mapping (virt == phys) for the low 1 MB 485 * physical memory region that is used by the ACPI wakeup code. This 486 * mapping must not have PG_G set. 487 */ 488#ifdef XBOX 489 /* FIXME: This is gross, but needed for the XBOX. Since we are in such 490 * an early stadium, we cannot yet neatly map video memory ... :-( 491 * Better fixes are very welcome! */ 492 if (!arch_i386_is_xbox) 493#endif 494 for (i = 1; i < NKPT; i++) 495 PTD[i] = 0; 496 497 /* Initialize the PAT MSR if present. */ 498 pmap_init_pat(); 499 500 /* Turn on PG_G on kernel page(s) */ 501 pmap_set_pg(); 502} 503 504/* 505 * Setup the PAT MSR. 506 */ 507void 508pmap_init_pat(void) 509{ 510 int pat_table[PAT_INDEX_SIZE]; 511 uint64_t pat_msr; 512 u_long cr0, cr4; 513 int i; 514 515 /* Set default PAT index table. */ 516 for (i = 0; i < PAT_INDEX_SIZE; i++) 517 pat_table[i] = -1; 518 pat_table[PAT_WRITE_BACK] = 0; 519 pat_table[PAT_WRITE_THROUGH] = 1; 520 pat_table[PAT_UNCACHEABLE] = 3; 521 pat_table[PAT_WRITE_COMBINING] = 3; 522 pat_table[PAT_WRITE_PROTECTED] = 3; 523 pat_table[PAT_UNCACHED] = 3; 524 525 /* Bail if this CPU doesn't implement PAT. */ 526 if ((cpu_feature & CPUID_PAT) == 0) { 527 for (i = 0; i < PAT_INDEX_SIZE; i++) 528 pat_index[i] = pat_table[i]; 529 pat_works = 0; 530 return; 531 } 532 533 /* 534 * Due to some Intel errata, we can only safely use the lower 4 535 * PAT entries. 536 * 537 * Intel Pentium III Processor Specification Update 538 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B 539 * or Mode C Paging) 540 * 541 * Intel Pentium IV Processor Specification Update 542 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly) 543 */ 544 if (cpu_vendor_id == CPU_VENDOR_INTEL && 545 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe)) 546 pat_works = 0; 547 548 /* Initialize default PAT entries. */ 549 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) | 550 PAT_VALUE(1, PAT_WRITE_THROUGH) | 551 PAT_VALUE(2, PAT_UNCACHED) | 552 PAT_VALUE(3, PAT_UNCACHEABLE) | 553 PAT_VALUE(4, PAT_WRITE_BACK) | 554 PAT_VALUE(5, PAT_WRITE_THROUGH) | 555 PAT_VALUE(6, PAT_UNCACHED) | 556 PAT_VALUE(7, PAT_UNCACHEABLE); 557 558 if (pat_works) { 559 /* 560 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC. 561 * Program 5 and 6 as WP and WC. 562 * Leave 4 and 7 as WB and UC. 563 */ 564 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6)); 565 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) | 566 PAT_VALUE(6, PAT_WRITE_COMBINING); 567 pat_table[PAT_UNCACHED] = 2; 568 pat_table[PAT_WRITE_PROTECTED] = 5; 569 pat_table[PAT_WRITE_COMBINING] = 6; 570 } else { 571 /* 572 * Just replace PAT Index 2 with WC instead of UC-. 573 */ 574 pat_msr &= ~PAT_MASK(2); 575 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING); 576 pat_table[PAT_WRITE_COMBINING] = 2; 577 } 578 579 /* Disable PGE. */ 580 cr4 = rcr4(); 581 load_cr4(cr4 & ~CR4_PGE); 582 583 /* Disable caches (CD = 1, NW = 0). */ 584 cr0 = rcr0(); 585 load_cr0((cr0 & ~CR0_NW) | CR0_CD); 586 587 /* Flushes caches and TLBs. */ 588 wbinvd(); 589 invltlb(); 590 591 /* Update PAT and index table. */ 592 wrmsr(MSR_PAT, pat_msr); 593 for (i = 0; i < PAT_INDEX_SIZE; i++) 594 pat_index[i] = pat_table[i]; 595 596 /* Flush caches and TLBs again. */ 597 wbinvd(); 598 invltlb(); 599 600 /* Restore caches and PGE. */ 601 load_cr0(cr0); 602 load_cr4(cr4); 603} 604 605/* 606 * Set PG_G on kernel pages. Only the BSP calls this when SMP is turned on. 607 */ 608static void 609pmap_set_pg(void) 610{ 611 pt_entry_t *pte; 612 vm_offset_t va, endva; 613 614 if (pgeflag == 0) 615 return; 616 617 endva = KERNBASE + KERNend; 618 619 if (pseflag) { 620 va = KERNBASE + KERNLOAD; 621 while (va < endva) { 622 pdir_pde(PTD, va) |= pgeflag; 623 invltlb(); /* Play it safe, invltlb() every time */ 624 va += NBPDR; 625 } 626 } else { 627 va = (vm_offset_t)btext; 628 while (va < endva) { 629 pte = vtopte(va); 630 if (*pte) 631 *pte |= pgeflag; 632 invltlb(); /* Play it safe, invltlb() every time */ 633 va += PAGE_SIZE; 634 } 635 } 636} 637 638/* 639 * Initialize a vm_page's machine-dependent fields. 640 */ 641void 642pmap_page_init(vm_page_t m) 643{ 644 645 TAILQ_INIT(&m->md.pv_list); 646 m->md.pat_mode = PAT_WRITE_BACK; 647} 648 649#ifdef PAE 650static void * 651pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 652{ 653 654 /* Inform UMA that this allocator uses kernel_map/object. */ 655 *flags = UMA_SLAB_KERNEL; 656 return ((void *)kmem_alloc_contig(kernel_arena, bytes, wait, 0x0ULL, 657 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT)); 658} 659#endif 660 661/* 662 * ABuse the pte nodes for unmapped kva to thread a kva freelist through. 663 * Requirements: 664 * - Must deal with pages in order to ensure that none of the PG_* bits 665 * are ever set, PG_V in particular. 666 * - Assumes we can write to ptes without pte_store() atomic ops, even 667 * on PAE systems. This should be ok. 668 * - Assumes nothing will ever test these addresses for 0 to indicate 669 * no mapping instead of correctly checking PG_V. 670 * - Assumes a vm_offset_t will fit in a pte (true for i386). 671 * Because PG_V is never set, there can be no mappings to invalidate. 672 */ 673static vm_offset_t 674pmap_ptelist_alloc(vm_offset_t *head) 675{ 676 pt_entry_t *pte; 677 vm_offset_t va; 678 679 va = *head; 680 if (va == 0) 681 panic("pmap_ptelist_alloc: exhausted ptelist KVA"); 682 pte = vtopte(va); 683 *head = *pte; 684 if (*head & PG_V) 685 panic("pmap_ptelist_alloc: va with PG_V set!"); 686 *pte = 0; 687 return (va); 688} 689 690static void 691pmap_ptelist_free(vm_offset_t *head, vm_offset_t va) 692{ 693 pt_entry_t *pte; 694 695 if (va & PG_V) 696 panic("pmap_ptelist_free: freeing va with PG_V set!"); 697 pte = vtopte(va); 698 *pte = *head; /* virtual! PG_V is 0 though */ 699 *head = va; 700} 701 702static void 703pmap_ptelist_init(vm_offset_t *head, void *base, int npages) 704{ 705 int i; 706 vm_offset_t va; 707 708 *head = 0; 709 for (i = npages - 1; i >= 0; i--) { 710 va = (vm_offset_t)base + i * PAGE_SIZE; 711 pmap_ptelist_free(head, va); 712 } 713} 714 715 716/* 717 * Initialize the pmap module. 718 * Called by vm_init, to initialize any structures that the pmap 719 * system needs to map virtual memory. 720 */ 721void 722pmap_init(void) 723{ 724 vm_page_t mpte; 725 vm_size_t s; 726 int i, pv_npg; 727 728 /* 729 * Initialize the vm page array entries for the kernel pmap's 730 * page table pages. 731 */ 732 for (i = 0; i < NKPT; i++) { 733 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT)); 734 KASSERT(mpte >= vm_page_array && 735 mpte < &vm_page_array[vm_page_array_size], 736 ("pmap_init: page table page is out of range")); 737 mpte->pindex = i + KPTDI; 738 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT); 739 } 740 741 /* 742 * Initialize the address space (zone) for the pv entries. Set a 743 * high water mark so that the system can recover from excessive 744 * numbers of pv entries. 745 */ 746 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 747 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 748 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 749 pv_entry_max = roundup(pv_entry_max, _NPCPV); 750 pv_entry_high_water = 9 * (pv_entry_max / 10); 751 752 /* 753 * If the kernel is running on a virtual machine, then it must assume 754 * that MCA is enabled by the hypervisor. Moreover, the kernel must 755 * be prepared for the hypervisor changing the vendor and family that 756 * are reported by CPUID. Consequently, the workaround for AMD Family 757 * 10h Erratum 383 is enabled if the processor's feature set does not 758 * include at least one feature that is only supported by older Intel 759 * or newer AMD processors. 760 */ 761 if (vm_guest == VM_GUEST_VM && (cpu_feature & CPUID_SS) == 0 && 762 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI | 763 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP | 764 AMDID2_FMA4)) == 0) 765 workaround_erratum383 = 1; 766 767 /* 768 * Are large page mappings supported and enabled? 769 */ 770 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled); 771 if (pseflag == 0) 772 pg_ps_enabled = 0; 773 else if (pg_ps_enabled) { 774 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0, 775 ("pmap_init: can't assign to pagesizes[1]")); 776 pagesizes[1] = NBPDR; 777 } 778 779 /* 780 * Calculate the size of the pv head table for superpages. 781 */ 782 for (i = 0; phys_avail[i + 1]; i += 2); 783 pv_npg = round_4mpage(phys_avail[(i - 2) + 1]) / NBPDR; 784 785 /* 786 * Allocate memory for the pv head table for superpages. 787 */ 788 s = (vm_size_t)(pv_npg * sizeof(struct md_page)); 789 s = round_page(s); 790 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s, 791 M_WAITOK | M_ZERO); 792 for (i = 0; i < pv_npg; i++) 793 TAILQ_INIT(&pv_table[i].pv_list); 794 795 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc); 796 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks); 797 if (pv_chunkbase == NULL) 798 panic("pmap_init: not enough kvm for pv chunks"); 799 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks); 800#ifdef PAE 801 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL, 802 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1, 803 UMA_ZONE_VM | UMA_ZONE_NOFREE); 804 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf); 805#endif 806} 807 808 809SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0, 810 "Max number of PV entries"); 811SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0, 812 "Page share factor per proc"); 813 814static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0, 815 "2/4MB page mapping counters"); 816 817static u_long pmap_pde_demotions; 818SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD, 819 &pmap_pde_demotions, 0, "2/4MB page demotions"); 820 821static u_long pmap_pde_mappings; 822SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD, 823 &pmap_pde_mappings, 0, "2/4MB page mappings"); 824 825static u_long pmap_pde_p_failures; 826SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD, 827 &pmap_pde_p_failures, 0, "2/4MB page promotion failures"); 828 829static u_long pmap_pde_promotions; 830SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD, 831 &pmap_pde_promotions, 0, "2/4MB page promotions"); 832 833/*************************************************** 834 * Low level helper routines..... 835 ***************************************************/ 836 837/* 838 * Determine the appropriate bits to set in a PTE or PDE for a specified 839 * caching mode. 840 */ 841int 842pmap_cache_bits(int mode, boolean_t is_pde) 843{ 844 int cache_bits, pat_flag, pat_idx; 845 846 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0) 847 panic("Unknown caching mode %d\n", mode); 848 849 /* The PAT bit is different for PTE's and PDE's. */ 850 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT; 851 852 /* Map the caching mode to a PAT index. */ 853 pat_idx = pat_index[mode]; 854 855 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */ 856 cache_bits = 0; 857 if (pat_idx & 0x4) 858 cache_bits |= pat_flag; 859 if (pat_idx & 0x2) 860 cache_bits |= PG_NC_PCD; 861 if (pat_idx & 0x1) 862 cache_bits |= PG_NC_PWT; 863 return (cache_bits); 864} 865 866/* 867 * The caller is responsible for maintaining TLB consistency. 868 */ 869static void 870pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde) 871{ 872 pd_entry_t *pde; 873 pmap_t pmap; 874 boolean_t PTD_updated; 875 876 PTD_updated = FALSE; 877 mtx_lock_spin(&allpmaps_lock); 878 LIST_FOREACH(pmap, &allpmaps, pm_list) { 879 if ((pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & 880 PG_FRAME)) 881 PTD_updated = TRUE; 882 pde = pmap_pde(pmap, va); 883 pde_store(pde, newpde); 884 } 885 mtx_unlock_spin(&allpmaps_lock); 886 KASSERT(PTD_updated, 887 ("pmap_kenter_pde: current page table is not in allpmaps")); 888} 889 890/* 891 * After changing the page size for the specified virtual address in the page 892 * table, flush the corresponding entries from the processor's TLB. Only the 893 * calling processor's TLB is affected. 894 * 895 * The calling thread must be pinned to a processor. 896 */ 897static void 898pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde) 899{ 900 u_long cr4; 901 902 if ((newpde & PG_PS) == 0) 903 /* Demotion: flush a specific 2MB page mapping. */ 904 invlpg(va); 905 else if ((newpde & PG_G) == 0) 906 /* 907 * Promotion: flush every 4KB page mapping from the TLB 908 * because there are too many to flush individually. 909 */ 910 invltlb(); 911 else { 912 /* 913 * Promotion: flush every 4KB page mapping from the TLB, 914 * including any global (PG_G) mappings. 915 */ 916 cr4 = rcr4(); 917 load_cr4(cr4 & ~CR4_PGE); 918 /* 919 * Although preemption at this point could be detrimental to 920 * performance, it would not lead to an error. PG_G is simply 921 * ignored if CR4.PGE is clear. Moreover, in case this block 922 * is re-entered, the load_cr4() either above or below will 923 * modify CR4.PGE flushing the TLB. 924 */ 925 load_cr4(cr4 | CR4_PGE); 926 } 927} 928#ifdef SMP 929/* 930 * For SMP, these functions have to use the IPI mechanism for coherence. 931 * 932 * N.B.: Before calling any of the following TLB invalidation functions, 933 * the calling processor must ensure that all stores updating a non- 934 * kernel page table are globally performed. Otherwise, another 935 * processor could cache an old, pre-update entry without being 936 * invalidated. This can happen one of two ways: (1) The pmap becomes 937 * active on another processor after its pm_active field is checked by 938 * one of the following functions but before a store updating the page 939 * table is globally performed. (2) The pmap becomes active on another 940 * processor before its pm_active field is checked but due to 941 * speculative loads one of the following functions stills reads the 942 * pmap as inactive on the other processor. 943 * 944 * The kernel page table is exempt because its pm_active field is 945 * immutable. The kernel page table is always active on every 946 * processor. 947 */ 948void 949pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 950{ 951 cpuset_t other_cpus; 952 u_int cpuid; 953 954 sched_pin(); 955 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 956 invlpg(va); 957 smp_invlpg(va); 958 } else { 959 cpuid = PCPU_GET(cpuid); 960 other_cpus = all_cpus; 961 CPU_CLR(cpuid, &other_cpus); 962 if (CPU_ISSET(cpuid, &pmap->pm_active)) 963 invlpg(va); 964 CPU_AND(&other_cpus, &pmap->pm_active); 965 if (!CPU_EMPTY(&other_cpus)) 966 smp_masked_invlpg(other_cpus, va); 967 } 968 sched_unpin(); 969} 970 971void 972pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 973{ 974 cpuset_t other_cpus; 975 vm_offset_t addr; 976 u_int cpuid; 977 978 sched_pin(); 979 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 980 for (addr = sva; addr < eva; addr += PAGE_SIZE) 981 invlpg(addr); 982 smp_invlpg_range(sva, eva); 983 } else { 984 cpuid = PCPU_GET(cpuid); 985 other_cpus = all_cpus; 986 CPU_CLR(cpuid, &other_cpus); 987 if (CPU_ISSET(cpuid, &pmap->pm_active)) 988 for (addr = sva; addr < eva; addr += PAGE_SIZE) 989 invlpg(addr); 990 CPU_AND(&other_cpus, &pmap->pm_active); 991 if (!CPU_EMPTY(&other_cpus)) 992 smp_masked_invlpg_range(other_cpus, sva, eva); 993 } 994 sched_unpin(); 995} 996 997void 998pmap_invalidate_all(pmap_t pmap) 999{ 1000 cpuset_t other_cpus; 1001 u_int cpuid; 1002 1003 sched_pin(); 1004 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 1005 invltlb(); 1006 smp_invltlb(); 1007 } else { 1008 cpuid = PCPU_GET(cpuid); 1009 other_cpus = all_cpus; 1010 CPU_CLR(cpuid, &other_cpus); 1011 if (CPU_ISSET(cpuid, &pmap->pm_active)) 1012 invltlb(); 1013 CPU_AND(&other_cpus, &pmap->pm_active); 1014 if (!CPU_EMPTY(&other_cpus)) 1015 smp_masked_invltlb(other_cpus); 1016 } 1017 sched_unpin(); 1018} 1019 1020void 1021pmap_invalidate_cache(void) 1022{ 1023 1024 sched_pin(); 1025 wbinvd(); 1026 smp_cache_flush(); 1027 sched_unpin(); 1028} 1029 1030struct pde_action { 1031 cpuset_t invalidate; /* processors that invalidate their TLB */ 1032 vm_offset_t va; 1033 pd_entry_t *pde; 1034 pd_entry_t newpde; 1035 u_int store; /* processor that updates the PDE */ 1036}; 1037 1038static void 1039pmap_update_pde_kernel(void *arg) 1040{ 1041 struct pde_action *act = arg; 1042 pd_entry_t *pde; 1043 pmap_t pmap; 1044 1045 if (act->store == PCPU_GET(cpuid)) { 1046 1047 /* 1048 * Elsewhere, this operation requires allpmaps_lock for 1049 * synchronization. Here, it does not because it is being 1050 * performed in the context of an all_cpus rendezvous. 1051 */ 1052 LIST_FOREACH(pmap, &allpmaps, pm_list) { 1053 pde = pmap_pde(pmap, act->va); 1054 pde_store(pde, act->newpde); 1055 } 1056 } 1057} 1058 1059static void 1060pmap_update_pde_user(void *arg) 1061{ 1062 struct pde_action *act = arg; 1063 1064 if (act->store == PCPU_GET(cpuid)) 1065 pde_store(act->pde, act->newpde); 1066} 1067 1068static void 1069pmap_update_pde_teardown(void *arg) 1070{ 1071 struct pde_action *act = arg; 1072 1073 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate)) 1074 pmap_update_pde_invalidate(act->va, act->newpde); 1075} 1076 1077/* 1078 * Change the page size for the specified virtual address in a way that 1079 * prevents any possibility of the TLB ever having two entries that map the 1080 * same virtual address using different page sizes. This is the recommended 1081 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a 1082 * machine check exception for a TLB state that is improperly diagnosed as a 1083 * hardware error. 1084 */ 1085static void 1086pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde) 1087{ 1088 struct pde_action act; 1089 cpuset_t active, other_cpus; 1090 u_int cpuid; 1091 1092 sched_pin(); 1093 cpuid = PCPU_GET(cpuid); 1094 other_cpus = all_cpus; 1095 CPU_CLR(cpuid, &other_cpus); 1096 if (pmap == kernel_pmap) 1097 active = all_cpus; 1098 else 1099 active = pmap->pm_active; 1100 if (CPU_OVERLAP(&active, &other_cpus)) { 1101 act.store = cpuid; 1102 act.invalidate = active; 1103 act.va = va; 1104 act.pde = pde; 1105 act.newpde = newpde; 1106 CPU_SET(cpuid, &active); 1107 smp_rendezvous_cpus(active, 1108 smp_no_rendevous_barrier, pmap == kernel_pmap ? 1109 pmap_update_pde_kernel : pmap_update_pde_user, 1110 pmap_update_pde_teardown, &act); 1111 } else { 1112 if (pmap == kernel_pmap) 1113 pmap_kenter_pde(va, newpde); 1114 else 1115 pde_store(pde, newpde); 1116 if (CPU_ISSET(cpuid, &active)) 1117 pmap_update_pde_invalidate(va, newpde); 1118 } 1119 sched_unpin(); 1120} 1121#else /* !SMP */ 1122/* 1123 * Normal, non-SMP, 486+ invalidation functions. 1124 * We inline these within pmap.c for speed. 1125 */ 1126PMAP_INLINE void 1127pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 1128{ 1129 1130 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 1131 invlpg(va); 1132} 1133 1134PMAP_INLINE void 1135pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 1136{ 1137 vm_offset_t addr; 1138 1139 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 1140 for (addr = sva; addr < eva; addr += PAGE_SIZE) 1141 invlpg(addr); 1142} 1143 1144PMAP_INLINE void 1145pmap_invalidate_all(pmap_t pmap) 1146{ 1147 1148 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 1149 invltlb(); 1150} 1151 1152PMAP_INLINE void 1153pmap_invalidate_cache(void) 1154{ 1155 1156 wbinvd(); 1157} 1158 1159static void 1160pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde) 1161{ 1162 1163 if (pmap == kernel_pmap) 1164 pmap_kenter_pde(va, newpde); 1165 else 1166 pde_store(pde, newpde); 1167 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 1168 pmap_update_pde_invalidate(va, newpde); 1169} 1170#endif /* !SMP */ 1171 1172#define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024) 1173 1174void 1175pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva) 1176{ 1177 1178 KASSERT((sva & PAGE_MASK) == 0, 1179 ("pmap_invalidate_cache_range: sva not page-aligned")); 1180 KASSERT((eva & PAGE_MASK) == 0, 1181 ("pmap_invalidate_cache_range: eva not page-aligned")); 1182 1183 if (cpu_feature & CPUID_SS) 1184 ; /* If "Self Snoop" is supported, do nothing. */ 1185 else if ((cpu_feature & CPUID_CLFSH) != 0 && 1186 eva - sva < PMAP_CLFLUSH_THRESHOLD) { 1187 1188#ifdef DEV_APIC 1189 /* 1190 * XXX: Some CPUs fault, hang, or trash the local APIC 1191 * registers if we use CLFLUSH on the local APIC 1192 * range. The local APIC is always uncached, so we 1193 * don't need to flush for that range anyway. 1194 */ 1195 if (pmap_kextract(sva) == lapic_paddr) 1196 return; 1197#endif 1198 /* 1199 * Otherwise, do per-cache line flush. Use the mfence 1200 * instruction to insure that previous stores are 1201 * included in the write-back. The processor 1202 * propagates flush to other processors in the cache 1203 * coherence domain. 1204 */ 1205 mfence(); 1206 for (; sva < eva; sva += cpu_clflush_line_size) 1207 clflush(sva); 1208 mfence(); 1209 } else { 1210 1211 /* 1212 * No targeted cache flush methods are supported by CPU, 1213 * or the supplied range is bigger than 2MB. 1214 * Globally invalidate cache. 1215 */ 1216 pmap_invalidate_cache(); 1217 } 1218} 1219 1220void 1221pmap_invalidate_cache_pages(vm_page_t *pages, int count) 1222{ 1223 int i; 1224 1225 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE || 1226 (cpu_feature & CPUID_CLFSH) == 0) { 1227 pmap_invalidate_cache(); 1228 } else { 1229 for (i = 0; i < count; i++) 1230 pmap_flush_page(pages[i]); 1231 } 1232} 1233 1234/* 1235 * Are we current address space or kernel? N.B. We return FALSE when 1236 * a pmap's page table is in use because a kernel thread is borrowing 1237 * it. The borrowed page table can change spontaneously, making any 1238 * dependence on its continued use subject to a race condition. 1239 */ 1240static __inline int 1241pmap_is_current(pmap_t pmap) 1242{ 1243 1244 return (pmap == kernel_pmap || 1245 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace) && 1246 (pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & PG_FRAME))); 1247} 1248 1249/* 1250 * If the given pmap is not the current or kernel pmap, the returned pte must 1251 * be released by passing it to pmap_pte_release(). 1252 */ 1253pt_entry_t * 1254pmap_pte(pmap_t pmap, vm_offset_t va) 1255{ 1256 pd_entry_t newpf; 1257 pd_entry_t *pde; 1258 1259 pde = pmap_pde(pmap, va); 1260 if (*pde & PG_PS) 1261 return (pde); 1262 if (*pde != 0) { 1263 /* are we current address space or kernel? */ 1264 if (pmap_is_current(pmap)) 1265 return (vtopte(va)); 1266 mtx_lock(&PMAP2mutex); 1267 newpf = *pde & PG_FRAME; 1268 if ((*PMAP2 & PG_FRAME) != newpf) { 1269 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M; 1270 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2); 1271 } 1272 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1))); 1273 } 1274 return (NULL); 1275} 1276 1277/* 1278 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte 1279 * being NULL. 1280 */ 1281static __inline void 1282pmap_pte_release(pt_entry_t *pte) 1283{ 1284 1285 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2) 1286 mtx_unlock(&PMAP2mutex); 1287} 1288 1289/* 1290 * NB: The sequence of updating a page table followed by accesses to the 1291 * corresponding pages is subject to the situation described in the "AMD64 1292 * Architecture Programmer's Manual Volume 2: System Programming" rev. 3.23, 1293 * "7.3.1 Special Coherency Considerations". Therefore, issuing the INVLPG 1294 * right after modifying the PTE bits is crucial. 1295 */ 1296static __inline void 1297invlcaddr(void *caddr) 1298{ 1299 1300 invlpg((u_int)caddr); 1301} 1302 1303/* 1304 * Super fast pmap_pte routine best used when scanning 1305 * the pv lists. This eliminates many coarse-grained 1306 * invltlb calls. Note that many of the pv list 1307 * scans are across different pmaps. It is very wasteful 1308 * to do an entire invltlb for checking a single mapping. 1309 * 1310 * If the given pmap is not the current pmap, pvh_global_lock 1311 * must be held and curthread pinned to a CPU. 1312 */ 1313static pt_entry_t * 1314pmap_pte_quick(pmap_t pmap, vm_offset_t va) 1315{ 1316 pd_entry_t newpf; 1317 pd_entry_t *pde; 1318 1319 pde = pmap_pde(pmap, va); 1320 if (*pde & PG_PS) 1321 return (pde); 1322 if (*pde != 0) { 1323 /* are we current address space or kernel? */ 1324 if (pmap_is_current(pmap)) 1325 return (vtopte(va)); 1326 rw_assert(&pvh_global_lock, RA_WLOCKED); 1327 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 1328 newpf = *pde & PG_FRAME; 1329 if ((*PMAP1 & PG_FRAME) != newpf) { 1330 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M; 1331#ifdef SMP 1332 PMAP1cpu = PCPU_GET(cpuid); 1333#endif 1334 invlcaddr(PADDR1); 1335 PMAP1changed++; 1336 } else 1337#ifdef SMP 1338 if (PMAP1cpu != PCPU_GET(cpuid)) { 1339 PMAP1cpu = PCPU_GET(cpuid); 1340 invlcaddr(PADDR1); 1341 PMAP1changedcpu++; 1342 } else 1343#endif 1344 PMAP1unchanged++; 1345 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1))); 1346 } 1347 return (0); 1348} 1349 1350/* 1351 * Routine: pmap_extract 1352 * Function: 1353 * Extract the physical page address associated 1354 * with the given map/virtual_address pair. 1355 */ 1356vm_paddr_t 1357pmap_extract(pmap_t pmap, vm_offset_t va) 1358{ 1359 vm_paddr_t rtval; 1360 pt_entry_t *pte; 1361 pd_entry_t pde; 1362 1363 rtval = 0; 1364 PMAP_LOCK(pmap); 1365 pde = pmap->pm_pdir[va >> PDRSHIFT]; 1366 if (pde != 0) { 1367 if ((pde & PG_PS) != 0) 1368 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK); 1369 else { 1370 pte = pmap_pte(pmap, va); 1371 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK); 1372 pmap_pte_release(pte); 1373 } 1374 } 1375 PMAP_UNLOCK(pmap); 1376 return (rtval); 1377} 1378 1379/* 1380 * Routine: pmap_extract_and_hold 1381 * Function: 1382 * Atomically extract and hold the physical page 1383 * with the given pmap and virtual address pair 1384 * if that mapping permits the given protection. 1385 */ 1386vm_page_t 1387pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1388{ 1389 pd_entry_t pde; 1390 pt_entry_t pte, *ptep; 1391 vm_page_t m; 1392 vm_paddr_t pa; 1393 1394 pa = 0; 1395 m = NULL; 1396 PMAP_LOCK(pmap); 1397retry: 1398 pde = *pmap_pde(pmap, va); 1399 if (pde != 0) { 1400 if (pde & PG_PS) { 1401 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) { 1402 if (vm_page_pa_tryrelock(pmap, (pde & 1403 PG_PS_FRAME) | (va & PDRMASK), &pa)) 1404 goto retry; 1405 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) | 1406 (va & PDRMASK)); 1407 vm_page_hold(m); 1408 } 1409 } else { 1410 ptep = pmap_pte(pmap, va); 1411 pte = *ptep; 1412 pmap_pte_release(ptep); 1413 if (pte != 0 && 1414 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) { 1415 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME, 1416 &pa)) 1417 goto retry; 1418 m = PHYS_TO_VM_PAGE(pte & PG_FRAME); 1419 vm_page_hold(m); 1420 } 1421 } 1422 } 1423 PA_UNLOCK_COND(pa); 1424 PMAP_UNLOCK(pmap); 1425 return (m); 1426} 1427 1428/*************************************************** 1429 * Low level mapping routines..... 1430 ***************************************************/ 1431 1432/* 1433 * Add a wired page to the kva. 1434 * Note: not SMP coherent. 1435 * 1436 * This function may be used before pmap_bootstrap() is called. 1437 */ 1438PMAP_INLINE void 1439pmap_kenter(vm_offset_t va, vm_paddr_t pa) 1440{ 1441 pt_entry_t *pte; 1442 1443 pte = vtopte(va); 1444 pte_store(pte, pa | PG_RW | PG_V | pgeflag); 1445} 1446 1447static __inline void 1448pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode) 1449{ 1450 pt_entry_t *pte; 1451 1452 pte = vtopte(va); 1453 pte_store(pte, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0)); 1454} 1455 1456/* 1457 * Remove a page from the kernel pagetables. 1458 * Note: not SMP coherent. 1459 * 1460 * This function may be used before pmap_bootstrap() is called. 1461 */ 1462PMAP_INLINE void 1463pmap_kremove(vm_offset_t va) 1464{ 1465 pt_entry_t *pte; 1466 1467 pte = vtopte(va); 1468 pte_clear(pte); 1469} 1470 1471/* 1472 * Used to map a range of physical addresses into kernel 1473 * virtual address space. 1474 * 1475 * The value passed in '*virt' is a suggested virtual address for 1476 * the mapping. Architectures which can support a direct-mapped 1477 * physical to virtual region can return the appropriate address 1478 * within that region, leaving '*virt' unchanged. Other 1479 * architectures should map the pages starting at '*virt' and 1480 * update '*virt' with the first usable address after the mapped 1481 * region. 1482 */ 1483vm_offset_t 1484pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) 1485{ 1486 vm_offset_t va, sva; 1487 vm_paddr_t superpage_offset; 1488 pd_entry_t newpde; 1489 1490 va = *virt; 1491 /* 1492 * Does the physical address range's size and alignment permit at 1493 * least one superpage mapping to be created? 1494 */ 1495 superpage_offset = start & PDRMASK; 1496 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) { 1497 /* 1498 * Increase the starting virtual address so that its alignment 1499 * does not preclude the use of superpage mappings. 1500 */ 1501 if ((va & PDRMASK) < superpage_offset) 1502 va = (va & ~PDRMASK) + superpage_offset; 1503 else if ((va & PDRMASK) > superpage_offset) 1504 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset; 1505 } 1506 sva = va; 1507 while (start < end) { 1508 if ((start & PDRMASK) == 0 && end - start >= NBPDR && 1509 pseflag) { 1510 KASSERT((va & PDRMASK) == 0, 1511 ("pmap_map: misaligned va %#x", va)); 1512 newpde = start | PG_PS | pgeflag | PG_RW | PG_V; 1513 pmap_kenter_pde(va, newpde); 1514 va += NBPDR; 1515 start += NBPDR; 1516 } else { 1517 pmap_kenter(va, start); 1518 va += PAGE_SIZE; 1519 start += PAGE_SIZE; 1520 } 1521 } 1522 pmap_invalidate_range(kernel_pmap, sva, va); 1523 *virt = va; 1524 return (sva); 1525} 1526 1527 1528/* 1529 * Add a list of wired pages to the kva 1530 * this routine is only used for temporary 1531 * kernel mappings that do not need to have 1532 * page modification or references recorded. 1533 * Note that old mappings are simply written 1534 * over. The page *must* be wired. 1535 * Note: SMP coherent. Uses a ranged shootdown IPI. 1536 */ 1537void 1538pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count) 1539{ 1540 pt_entry_t *endpte, oldpte, pa, *pte; 1541 vm_page_t m; 1542 1543 oldpte = 0; 1544 pte = vtopte(sva); 1545 endpte = pte + count; 1546 while (pte < endpte) { 1547 m = *ma++; 1548 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0); 1549 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) { 1550 oldpte |= *pte; 1551 pte_store(pte, pa | pgeflag | PG_RW | PG_V); 1552 } 1553 pte++; 1554 } 1555 if (__predict_false((oldpte & PG_V) != 0)) 1556 pmap_invalidate_range(kernel_pmap, sva, sva + count * 1557 PAGE_SIZE); 1558} 1559 1560/* 1561 * This routine tears out page mappings from the 1562 * kernel -- it is meant only for temporary mappings. 1563 * Note: SMP coherent. Uses a ranged shootdown IPI. 1564 */ 1565void 1566pmap_qremove(vm_offset_t sva, int count) 1567{ 1568 vm_offset_t va; 1569 1570 va = sva; 1571 while (count-- > 0) { 1572 pmap_kremove(va); 1573 va += PAGE_SIZE; 1574 } 1575 pmap_invalidate_range(kernel_pmap, sva, va); 1576} 1577 1578/*************************************************** 1579 * Page table page management routines..... 1580 ***************************************************/ 1581static __inline void 1582pmap_free_zero_pages(struct spglist *free) 1583{ 1584 vm_page_t m; 1585 1586 while ((m = SLIST_FIRST(free)) != NULL) { 1587 SLIST_REMOVE_HEAD(free, plinks.s.ss); 1588 /* Preserve the page's PG_ZERO setting. */ 1589 vm_page_free_toq(m); 1590 } 1591} 1592 1593/* 1594 * Schedule the specified unused page table page to be freed. Specifically, 1595 * add the page to the specified list of pages that will be released to the 1596 * physical memory manager after the TLB has been updated. 1597 */ 1598static __inline void 1599pmap_add_delayed_free_list(vm_page_t m, struct spglist *free, 1600 boolean_t set_PG_ZERO) 1601{ 1602 1603 if (set_PG_ZERO) 1604 m->flags |= PG_ZERO; 1605 else 1606 m->flags &= ~PG_ZERO; 1607 SLIST_INSERT_HEAD(free, m, plinks.s.ss); 1608} 1609 1610/* 1611 * Inserts the specified page table page into the specified pmap's collection 1612 * of idle page table pages. Each of a pmap's page table pages is responsible 1613 * for mapping a distinct range of virtual addresses. The pmap's collection is 1614 * ordered by this virtual address range. 1615 */ 1616static __inline int 1617pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte) 1618{ 1619 1620 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1621 return (vm_radix_insert(&pmap->pm_root, mpte)); 1622} 1623 1624/* 1625 * Looks for a page table page mapping the specified virtual address in the 1626 * specified pmap's collection of idle page table pages. Returns NULL if there 1627 * is no page table page corresponding to the specified virtual address. 1628 */ 1629static __inline vm_page_t 1630pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va) 1631{ 1632 1633 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1634 return (vm_radix_lookup(&pmap->pm_root, va >> PDRSHIFT)); 1635} 1636 1637/* 1638 * Removes the specified page table page from the specified pmap's collection 1639 * of idle page table pages. The specified page table page must be a member of 1640 * the pmap's collection. 1641 */ 1642static __inline void 1643pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte) 1644{ 1645 1646 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1647 vm_radix_remove(&pmap->pm_root, mpte->pindex); 1648} 1649 1650/* 1651 * Decrements a page table page's wire count, which is used to record the 1652 * number of valid page table entries within the page. If the wire count 1653 * drops to zero, then the page table page is unmapped. Returns TRUE if the 1654 * page table page was unmapped and FALSE otherwise. 1655 */ 1656static inline boolean_t 1657pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free) 1658{ 1659 1660 --m->wire_count; 1661 if (m->wire_count == 0) { 1662 _pmap_unwire_ptp(pmap, m, free); 1663 return (TRUE); 1664 } else 1665 return (FALSE); 1666} 1667 1668static void 1669_pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free) 1670{ 1671 vm_offset_t pteva; 1672 1673 /* 1674 * unmap the page table page 1675 */ 1676 pmap->pm_pdir[m->pindex] = 0; 1677 --pmap->pm_stats.resident_count; 1678 1679 /* 1680 * This is a release store so that the ordinary store unmapping 1681 * the page table page is globally performed before TLB shoot- 1682 * down is begun. 1683 */ 1684 atomic_subtract_rel_int(&cnt.v_wire_count, 1); 1685 1686 /* 1687 * Do an invltlb to make the invalidated mapping 1688 * take effect immediately. 1689 */ 1690 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex); 1691 pmap_invalidate_page(pmap, pteva); 1692 1693 /* 1694 * Put page on a list so that it is released after 1695 * *ALL* TLB shootdown is done 1696 */ 1697 pmap_add_delayed_free_list(m, free, TRUE); 1698} 1699 1700/* 1701 * After removing a page table entry, this routine is used to 1702 * conditionally free the page, and manage the hold/wire counts. 1703 */ 1704static int 1705pmap_unuse_pt(pmap_t pmap, vm_offset_t va, struct spglist *free) 1706{ 1707 pd_entry_t ptepde; 1708 vm_page_t mpte; 1709 1710 if (va >= VM_MAXUSER_ADDRESS) 1711 return (0); 1712 ptepde = *pmap_pde(pmap, va); 1713 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME); 1714 return (pmap_unwire_ptp(pmap, mpte, free)); 1715} 1716 1717/* 1718 * Initialize the pmap for the swapper process. 1719 */ 1720void 1721pmap_pinit0(pmap_t pmap) 1722{ 1723 1724 PMAP_LOCK_INIT(pmap); 1725 /* 1726 * Since the page table directory is shared with the kernel pmap, 1727 * which is already included in the list "allpmaps", this pmap does 1728 * not need to be inserted into that list. 1729 */ 1730 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD); 1731#ifdef PAE 1732 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT); 1733#endif 1734 pmap->pm_root.rt_root = 0; 1735 CPU_ZERO(&pmap->pm_active); 1736 PCPU_SET(curpmap, pmap); 1737 TAILQ_INIT(&pmap->pm_pvchunk); 1738 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1739} 1740 1741/* 1742 * Initialize a preallocated and zeroed pmap structure, 1743 * such as one in a vmspace structure. 1744 */ 1745int 1746pmap_pinit(pmap_t pmap) 1747{ 1748 vm_page_t m, ptdpg[NPGPTD]; 1749 vm_paddr_t pa; 1750 int i; 1751 1752 /* 1753 * No need to allocate page table space yet but we do need a valid 1754 * page directory table. 1755 */ 1756 if (pmap->pm_pdir == NULL) { 1757 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD); 1758 if (pmap->pm_pdir == NULL) { 1759 PMAP_LOCK_DESTROY(pmap); 1760 return (0); 1761 } 1762#ifdef PAE 1763 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO); 1764 KASSERT(((vm_offset_t)pmap->pm_pdpt & 1765 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0, 1766 ("pmap_pinit: pdpt misaligned")); 1767 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30), 1768 ("pmap_pinit: pdpt above 4g")); 1769#endif 1770 pmap->pm_root.rt_root = 0; 1771 } 1772 KASSERT(vm_radix_is_empty(&pmap->pm_root), 1773 ("pmap_pinit: pmap has reserved page table page(s)")); 1774 1775 /* 1776 * allocate the page directory page(s) 1777 */ 1778 for (i = 0; i < NPGPTD;) { 1779 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | 1780 VM_ALLOC_WIRED | VM_ALLOC_ZERO); 1781 if (m == NULL) 1782 VM_WAIT; 1783 else { 1784 ptdpg[i++] = m; 1785 } 1786 } 1787 1788 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD); 1789 1790 for (i = 0; i < NPGPTD; i++) 1791 if ((ptdpg[i]->flags & PG_ZERO) == 0) 1792 pagezero(pmap->pm_pdir + (i * NPDEPG)); 1793 1794 mtx_lock_spin(&allpmaps_lock); 1795 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1796 /* Copy the kernel page table directory entries. */ 1797 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t)); 1798 mtx_unlock_spin(&allpmaps_lock); 1799 1800 /* install self-referential address mapping entry(s) */ 1801 for (i = 0; i < NPGPTD; i++) { 1802 pa = VM_PAGE_TO_PHYS(ptdpg[i]); 1803 pmap->pm_pdir[PTDPTDI + i] = pa | PG_V | PG_RW | PG_A | PG_M; 1804#ifdef PAE 1805 pmap->pm_pdpt[i] = pa | PG_V; 1806#endif 1807 } 1808 1809 CPU_ZERO(&pmap->pm_active); 1810 TAILQ_INIT(&pmap->pm_pvchunk); 1811 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1812 1813 return (1); 1814} 1815 1816/* 1817 * this routine is called if the page table page is not 1818 * mapped correctly. 1819 */ 1820static vm_page_t 1821_pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags) 1822{ 1823 vm_paddr_t ptepa; 1824 vm_page_t m; 1825 1826 /* 1827 * Allocate a page table page. 1828 */ 1829 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ | 1830 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) { 1831 if ((flags & PMAP_ENTER_NOSLEEP) == 0) { 1832 PMAP_UNLOCK(pmap); 1833 rw_wunlock(&pvh_global_lock); 1834 VM_WAIT; 1835 rw_wlock(&pvh_global_lock); 1836 PMAP_LOCK(pmap); 1837 } 1838 1839 /* 1840 * Indicate the need to retry. While waiting, the page table 1841 * page may have been allocated. 1842 */ 1843 return (NULL); 1844 } 1845 if ((m->flags & PG_ZERO) == 0) 1846 pmap_zero_page(m); 1847 1848 /* 1849 * Map the pagetable page into the process address space, if 1850 * it isn't already there. 1851 */ 1852 1853 pmap->pm_stats.resident_count++; 1854 1855 ptepa = VM_PAGE_TO_PHYS(m); 1856 pmap->pm_pdir[ptepindex] = 1857 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M); 1858 1859 return (m); 1860} 1861 1862static vm_page_t 1863pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags) 1864{ 1865 u_int ptepindex; 1866 pd_entry_t ptepa; 1867 vm_page_t m; 1868 1869 /* 1870 * Calculate pagetable page index 1871 */ 1872 ptepindex = va >> PDRSHIFT; 1873retry: 1874 /* 1875 * Get the page directory entry 1876 */ 1877 ptepa = pmap->pm_pdir[ptepindex]; 1878 1879 /* 1880 * This supports switching from a 4MB page to a 1881 * normal 4K page. 1882 */ 1883 if (ptepa & PG_PS) { 1884 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va); 1885 ptepa = pmap->pm_pdir[ptepindex]; 1886 } 1887 1888 /* 1889 * If the page table page is mapped, we just increment the 1890 * hold count, and activate it. 1891 */ 1892 if (ptepa) { 1893 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME); 1894 m->wire_count++; 1895 } else { 1896 /* 1897 * Here if the pte page isn't mapped, or if it has 1898 * been deallocated. 1899 */ 1900 m = _pmap_allocpte(pmap, ptepindex, flags); 1901 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0) 1902 goto retry; 1903 } 1904 return (m); 1905} 1906 1907 1908/*************************************************** 1909* Pmap allocation/deallocation routines. 1910 ***************************************************/ 1911 1912#ifdef SMP 1913/* 1914 * Deal with a SMP shootdown of other users of the pmap that we are 1915 * trying to dispose of. This can be a bit hairy. 1916 */ 1917static cpuset_t *lazymask; 1918static u_int lazyptd; 1919static volatile u_int lazywait; 1920 1921void pmap_lazyfix_action(void); 1922 1923void 1924pmap_lazyfix_action(void) 1925{ 1926 1927#ifdef COUNT_IPIS 1928 (*ipi_lazypmap_counts[PCPU_GET(cpuid)])++; 1929#endif 1930 if (rcr3() == lazyptd) 1931 load_cr3(curpcb->pcb_cr3); 1932 CPU_CLR_ATOMIC(PCPU_GET(cpuid), lazymask); 1933 atomic_store_rel_int(&lazywait, 1); 1934} 1935 1936static void 1937pmap_lazyfix_self(u_int cpuid) 1938{ 1939 1940 if (rcr3() == lazyptd) 1941 load_cr3(curpcb->pcb_cr3); 1942 CPU_CLR_ATOMIC(cpuid, lazymask); 1943} 1944 1945 1946static void 1947pmap_lazyfix(pmap_t pmap) 1948{ 1949 cpuset_t mymask, mask; 1950 u_int cpuid, spins; 1951 int lsb; 1952 1953 mask = pmap->pm_active; 1954 while (!CPU_EMPTY(&mask)) { 1955 spins = 50000000; 1956 1957 /* Find least significant set bit. */ 1958 lsb = CPU_FFS(&mask); 1959 MPASS(lsb != 0); 1960 lsb--; 1961 CPU_SETOF(lsb, &mask); 1962 mtx_lock_spin(&smp_ipi_mtx); 1963#ifdef PAE 1964 lazyptd = vtophys(pmap->pm_pdpt); 1965#else 1966 lazyptd = vtophys(pmap->pm_pdir); 1967#endif 1968 cpuid = PCPU_GET(cpuid); 1969 1970 /* Use a cpuset just for having an easy check. */ 1971 CPU_SETOF(cpuid, &mymask); 1972 if (!CPU_CMP(&mask, &mymask)) { 1973 lazymask = &pmap->pm_active; 1974 pmap_lazyfix_self(cpuid); 1975 } else { 1976 atomic_store_rel_int((u_int *)&lazymask, 1977 (u_int)&pmap->pm_active); 1978 atomic_store_rel_int(&lazywait, 0); 1979 ipi_selected(mask, IPI_LAZYPMAP); 1980 while (lazywait == 0) { 1981 ia32_pause(); 1982 if (--spins == 0) 1983 break; 1984 } 1985 } 1986 mtx_unlock_spin(&smp_ipi_mtx); 1987 if (spins == 0) 1988 printf("pmap_lazyfix: spun for 50000000\n"); 1989 mask = pmap->pm_active; 1990 } 1991} 1992 1993#else /* SMP */ 1994 1995/* 1996 * Cleaning up on uniprocessor is easy. For various reasons, we're 1997 * unlikely to have to even execute this code, including the fact 1998 * that the cleanup is deferred until the parent does a wait(2), which 1999 * means that another userland process has run. 2000 */ 2001static void 2002pmap_lazyfix(pmap_t pmap) 2003{ 2004 u_int cr3; 2005 2006 cr3 = vtophys(pmap->pm_pdir); 2007 if (cr3 == rcr3()) { 2008 load_cr3(curpcb->pcb_cr3); 2009 CPU_CLR(PCPU_GET(cpuid), &pmap->pm_active); 2010 } 2011} 2012#endif /* SMP */ 2013 2014/* 2015 * Release any resources held by the given physical map. 2016 * Called when a pmap initialized by pmap_pinit is being released. 2017 * Should only be called if the map contains no valid mappings. 2018 */ 2019void 2020pmap_release(pmap_t pmap) 2021{ 2022 vm_page_t m, ptdpg[NPGPTD]; 2023 int i; 2024 2025 KASSERT(pmap->pm_stats.resident_count == 0, 2026 ("pmap_release: pmap resident count %ld != 0", 2027 pmap->pm_stats.resident_count)); 2028 KASSERT(vm_radix_is_empty(&pmap->pm_root), 2029 ("pmap_release: pmap has reserved page table page(s)")); 2030 2031 pmap_lazyfix(pmap); 2032 mtx_lock_spin(&allpmaps_lock); 2033 LIST_REMOVE(pmap, pm_list); 2034 mtx_unlock_spin(&allpmaps_lock); 2035 2036 for (i = 0; i < NPGPTD; i++) 2037 ptdpg[i] = PHYS_TO_VM_PAGE(pmap->pm_pdir[PTDPTDI + i] & 2038 PG_FRAME); 2039 2040 bzero(pmap->pm_pdir + PTDPTDI, (nkpt + NPGPTD) * 2041 sizeof(*pmap->pm_pdir)); 2042 2043 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD); 2044 2045 for (i = 0; i < NPGPTD; i++) { 2046 m = ptdpg[i]; 2047#ifdef PAE 2048 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME), 2049 ("pmap_release: got wrong ptd page")); 2050#endif 2051 m->wire_count--; 2052 atomic_subtract_int(&cnt.v_wire_count, 1); 2053 vm_page_free_zero(m); 2054 } 2055} 2056 2057static int 2058kvm_size(SYSCTL_HANDLER_ARGS) 2059{ 2060 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE; 2061 2062 return (sysctl_handle_long(oidp, &ksize, 0, req)); 2063} 2064SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD, 2065 0, 0, kvm_size, "IU", "Size of KVM"); 2066 2067static int 2068kvm_free(SYSCTL_HANDLER_ARGS) 2069{ 2070 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end; 2071 2072 return (sysctl_handle_long(oidp, &kfree, 0, req)); 2073} 2074SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD, 2075 0, 0, kvm_free, "IU", "Amount of KVM free"); 2076 2077/* 2078 * grow the number of kernel page table entries, if needed 2079 */ 2080void 2081pmap_growkernel(vm_offset_t addr) 2082{ 2083 vm_paddr_t ptppaddr; 2084 vm_page_t nkpg; 2085 pd_entry_t newpdir; 2086 2087 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 2088 addr = roundup2(addr, NBPDR); 2089 if (addr - 1 >= kernel_map->max_offset) 2090 addr = kernel_map->max_offset; 2091 while (kernel_vm_end < addr) { 2092 if (pdir_pde(PTD, kernel_vm_end)) { 2093 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 2094 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 2095 kernel_vm_end = kernel_map->max_offset; 2096 break; 2097 } 2098 continue; 2099 } 2100 2101 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT, 2102 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 2103 VM_ALLOC_ZERO); 2104 if (nkpg == NULL) 2105 panic("pmap_growkernel: no memory to grow kernel"); 2106 2107 nkpt++; 2108 2109 if ((nkpg->flags & PG_ZERO) == 0) 2110 pmap_zero_page(nkpg); 2111 ptppaddr = VM_PAGE_TO_PHYS(nkpg); 2112 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M); 2113 pdir_pde(KPTD, kernel_vm_end) = pgeflag | newpdir; 2114 2115 pmap_kenter_pde(kernel_vm_end, newpdir); 2116 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 2117 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 2118 kernel_vm_end = kernel_map->max_offset; 2119 break; 2120 } 2121 } 2122} 2123 2124 2125/*************************************************** 2126 * page management routines. 2127 ***************************************************/ 2128 2129CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE); 2130CTASSERT(_NPCM == 11); 2131CTASSERT(_NPCPV == 336); 2132 2133static __inline struct pv_chunk * 2134pv_to_chunk(pv_entry_t pv) 2135{ 2136 2137 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK)); 2138} 2139 2140#define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap) 2141 2142#define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */ 2143#define PC_FREE10 0x0000fffful /* Free values for index 10 */ 2144 2145static const uint32_t pc_freemask[_NPCM] = { 2146 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 2147 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 2148 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 2149 PC_FREE0_9, PC_FREE10 2150}; 2151 2152SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0, 2153 "Current number of pv entries"); 2154 2155#ifdef PV_STATS 2156static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail; 2157 2158SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0, 2159 "Current number of pv entry chunks"); 2160SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0, 2161 "Current number of pv entry chunks allocated"); 2162SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0, 2163 "Current number of pv entry chunks frees"); 2164SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0, 2165 "Number of times tried to get a chunk page but failed."); 2166 2167static long pv_entry_frees, pv_entry_allocs; 2168static int pv_entry_spare; 2169 2170SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0, 2171 "Current number of pv entry frees"); 2172SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0, 2173 "Current number of pv entry allocs"); 2174SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0, 2175 "Current number of spare pv entries"); 2176#endif 2177 2178/* 2179 * We are in a serious low memory condition. Resort to 2180 * drastic measures to free some pages so we can allocate 2181 * another pv entry chunk. 2182 */ 2183static vm_page_t 2184pmap_pv_reclaim(pmap_t locked_pmap) 2185{ 2186 struct pch newtail; 2187 struct pv_chunk *pc; 2188 struct md_page *pvh; 2189 pd_entry_t *pde; 2190 pmap_t pmap; 2191 pt_entry_t *pte, tpte; 2192 pv_entry_t pv; 2193 vm_offset_t va; 2194 vm_page_t m, m_pc; 2195 struct spglist free; 2196 uint32_t inuse; 2197 int bit, field, freed; 2198 2199 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED); 2200 pmap = NULL; 2201 m_pc = NULL; 2202 SLIST_INIT(&free); 2203 TAILQ_INIT(&newtail); 2204 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 || 2205 SLIST_EMPTY(&free))) { 2206 TAILQ_REMOVE(&pv_chunks, pc, pc_lru); 2207 if (pmap != pc->pc_pmap) { 2208 if (pmap != NULL) { 2209 pmap_invalidate_all(pmap); 2210 if (pmap != locked_pmap) 2211 PMAP_UNLOCK(pmap); 2212 } 2213 pmap = pc->pc_pmap; 2214 /* Avoid deadlock and lock recursion. */ 2215 if (pmap > locked_pmap) 2216 PMAP_LOCK(pmap); 2217 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) { 2218 pmap = NULL; 2219 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 2220 continue; 2221 } 2222 } 2223 2224 /* 2225 * Destroy every non-wired, 4 KB page mapping in the chunk. 2226 */ 2227 freed = 0; 2228 for (field = 0; field < _NPCM; field++) { 2229 for (inuse = ~pc->pc_map[field] & pc_freemask[field]; 2230 inuse != 0; inuse &= ~(1UL << bit)) { 2231 bit = bsfl(inuse); 2232 pv = &pc->pc_pventry[field * 32 + bit]; 2233 va = pv->pv_va; 2234 pde = pmap_pde(pmap, va); 2235 if ((*pde & PG_PS) != 0) 2236 continue; 2237 pte = pmap_pte(pmap, va); 2238 tpte = *pte; 2239 if ((tpte & PG_W) == 0) 2240 tpte = pte_load_clear(pte); 2241 pmap_pte_release(pte); 2242 if ((tpte & PG_W) != 0) 2243 continue; 2244 KASSERT(tpte != 0, 2245 ("pmap_pv_reclaim: pmap %p va %x zero pte", 2246 pmap, va)); 2247 if ((tpte & PG_G) != 0) 2248 pmap_invalidate_page(pmap, va); 2249 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 2250 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2251 vm_page_dirty(m); 2252 if ((tpte & PG_A) != 0) 2253 vm_page_aflag_set(m, PGA_REFERENCED); 2254 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 2255 if (TAILQ_EMPTY(&m->md.pv_list) && 2256 (m->flags & PG_FICTITIOUS) == 0) { 2257 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 2258 if (TAILQ_EMPTY(&pvh->pv_list)) { 2259 vm_page_aflag_clear(m, 2260 PGA_WRITEABLE); 2261 } 2262 } 2263 pc->pc_map[field] |= 1UL << bit; 2264 pmap_unuse_pt(pmap, va, &free); 2265 freed++; 2266 } 2267 } 2268 if (freed == 0) { 2269 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 2270 continue; 2271 } 2272 /* Every freed mapping is for a 4 KB page. */ 2273 pmap->pm_stats.resident_count -= freed; 2274 PV_STAT(pv_entry_frees += freed); 2275 PV_STAT(pv_entry_spare += freed); 2276 pv_entry_count -= freed; 2277 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2278 for (field = 0; field < _NPCM; field++) 2279 if (pc->pc_map[field] != pc_freemask[field]) { 2280 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, 2281 pc_list); 2282 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 2283 2284 /* 2285 * One freed pv entry in locked_pmap is 2286 * sufficient. 2287 */ 2288 if (pmap == locked_pmap) 2289 goto out; 2290 break; 2291 } 2292 if (field == _NPCM) { 2293 PV_STAT(pv_entry_spare -= _NPCPV); 2294 PV_STAT(pc_chunk_count--); 2295 PV_STAT(pc_chunk_frees++); 2296 /* Entire chunk is free; return it. */ 2297 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 2298 pmap_qremove((vm_offset_t)pc, 1); 2299 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 2300 break; 2301 } 2302 } 2303out: 2304 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru); 2305 if (pmap != NULL) { 2306 pmap_invalidate_all(pmap); 2307 if (pmap != locked_pmap) 2308 PMAP_UNLOCK(pmap); 2309 } 2310 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) { 2311 m_pc = SLIST_FIRST(&free); 2312 SLIST_REMOVE_HEAD(&free, plinks.s.ss); 2313 /* Recycle a freed page table page. */ 2314 m_pc->wire_count = 1; 2315 atomic_add_int(&cnt.v_wire_count, 1); 2316 } 2317 pmap_free_zero_pages(&free); 2318 return (m_pc); 2319} 2320 2321/* 2322 * free the pv_entry back to the free list 2323 */ 2324static void 2325free_pv_entry(pmap_t pmap, pv_entry_t pv) 2326{ 2327 struct pv_chunk *pc; 2328 int idx, field, bit; 2329 2330 rw_assert(&pvh_global_lock, RA_WLOCKED); 2331 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2332 PV_STAT(pv_entry_frees++); 2333 PV_STAT(pv_entry_spare++); 2334 pv_entry_count--; 2335 pc = pv_to_chunk(pv); 2336 idx = pv - &pc->pc_pventry[0]; 2337 field = idx / 32; 2338 bit = idx % 32; 2339 pc->pc_map[field] |= 1ul << bit; 2340 for (idx = 0; idx < _NPCM; idx++) 2341 if (pc->pc_map[idx] != pc_freemask[idx]) { 2342 /* 2343 * 98% of the time, pc is already at the head of the 2344 * list. If it isn't already, move it to the head. 2345 */ 2346 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) != 2347 pc)) { 2348 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2349 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, 2350 pc_list); 2351 } 2352 return; 2353 } 2354 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2355 free_pv_chunk(pc); 2356} 2357 2358static void 2359free_pv_chunk(struct pv_chunk *pc) 2360{ 2361 vm_page_t m; 2362 2363 TAILQ_REMOVE(&pv_chunks, pc, pc_lru); 2364 PV_STAT(pv_entry_spare -= _NPCPV); 2365 PV_STAT(pc_chunk_count--); 2366 PV_STAT(pc_chunk_frees++); 2367 /* entire chunk is free, return it */ 2368 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 2369 pmap_qremove((vm_offset_t)pc, 1); 2370 vm_page_unwire(m, 0); 2371 vm_page_free(m); 2372 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 2373} 2374 2375/* 2376 * get a new pv_entry, allocating a block from the system 2377 * when needed. 2378 */ 2379static pv_entry_t 2380get_pv_entry(pmap_t pmap, boolean_t try) 2381{ 2382 static const struct timeval printinterval = { 60, 0 }; 2383 static struct timeval lastprint; 2384 int bit, field; 2385 pv_entry_t pv; 2386 struct pv_chunk *pc; 2387 vm_page_t m; 2388 2389 rw_assert(&pvh_global_lock, RA_WLOCKED); 2390 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2391 PV_STAT(pv_entry_allocs++); 2392 pv_entry_count++; 2393 if (pv_entry_count > pv_entry_high_water) 2394 if (ratecheck(&lastprint, &printinterval)) 2395 printf("Approaching the limit on PV entries, consider " 2396 "increasing either the vm.pmap.shpgperproc or the " 2397 "vm.pmap.pv_entry_max tunable.\n"); 2398retry: 2399 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 2400 if (pc != NULL) { 2401 for (field = 0; field < _NPCM; field++) { 2402 if (pc->pc_map[field]) { 2403 bit = bsfl(pc->pc_map[field]); 2404 break; 2405 } 2406 } 2407 if (field < _NPCM) { 2408 pv = &pc->pc_pventry[field * 32 + bit]; 2409 pc->pc_map[field] &= ~(1ul << bit); 2410 /* If this was the last item, move it to tail */ 2411 for (field = 0; field < _NPCM; field++) 2412 if (pc->pc_map[field] != 0) { 2413 PV_STAT(pv_entry_spare--); 2414 return (pv); /* not full, return */ 2415 } 2416 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2417 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 2418 PV_STAT(pv_entry_spare--); 2419 return (pv); 2420 } 2421 } 2422 /* 2423 * Access to the ptelist "pv_vafree" is synchronized by the pvh 2424 * global lock. If "pv_vafree" is currently non-empty, it will 2425 * remain non-empty until pmap_ptelist_alloc() completes. 2426 */ 2427 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | 2428 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 2429 if (try) { 2430 pv_entry_count--; 2431 PV_STAT(pc_chunk_tryfail++); 2432 return (NULL); 2433 } 2434 m = pmap_pv_reclaim(pmap); 2435 if (m == NULL) 2436 goto retry; 2437 } 2438 PV_STAT(pc_chunk_count++); 2439 PV_STAT(pc_chunk_allocs++); 2440 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree); 2441 pmap_qenter((vm_offset_t)pc, &m, 1); 2442 pc->pc_pmap = pmap; 2443 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */ 2444 for (field = 1; field < _NPCM; field++) 2445 pc->pc_map[field] = pc_freemask[field]; 2446 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru); 2447 pv = &pc->pc_pventry[0]; 2448 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2449 PV_STAT(pv_entry_spare += _NPCPV - 1); 2450 return (pv); 2451} 2452 2453static __inline pv_entry_t 2454pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2455{ 2456 pv_entry_t pv; 2457 2458 rw_assert(&pvh_global_lock, RA_WLOCKED); 2459 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 2460 if (pmap == PV_PMAP(pv) && va == pv->pv_va) { 2461 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next); 2462 break; 2463 } 2464 } 2465 return (pv); 2466} 2467 2468static void 2469pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 2470{ 2471 struct md_page *pvh; 2472 pv_entry_t pv; 2473 vm_offset_t va_last; 2474 vm_page_t m; 2475 2476 rw_assert(&pvh_global_lock, RA_WLOCKED); 2477 KASSERT((pa & PDRMASK) == 0, 2478 ("pmap_pv_demote_pde: pa is not 4mpage aligned")); 2479 2480 /* 2481 * Transfer the 4mpage's pv entry for this mapping to the first 2482 * page's pv list. 2483 */ 2484 pvh = pa_to_pvh(pa); 2485 va = trunc_4mpage(va); 2486 pv = pmap_pvh_remove(pvh, pmap, va); 2487 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found")); 2488 m = PHYS_TO_VM_PAGE(pa); 2489 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 2490 /* Instantiate the remaining NPTEPG - 1 pv entries. */ 2491 va_last = va + NBPDR - PAGE_SIZE; 2492 do { 2493 m++; 2494 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2495 ("pmap_pv_demote_pde: page %p is not managed", m)); 2496 va += PAGE_SIZE; 2497 pmap_insert_entry(pmap, va, m); 2498 } while (va < va_last); 2499} 2500 2501static void 2502pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 2503{ 2504 struct md_page *pvh; 2505 pv_entry_t pv; 2506 vm_offset_t va_last; 2507 vm_page_t m; 2508 2509 rw_assert(&pvh_global_lock, RA_WLOCKED); 2510 KASSERT((pa & PDRMASK) == 0, 2511 ("pmap_pv_promote_pde: pa is not 4mpage aligned")); 2512 2513 /* 2514 * Transfer the first page's pv entry for this mapping to the 2515 * 4mpage's pv list. Aside from avoiding the cost of a call 2516 * to get_pv_entry(), a transfer avoids the possibility that 2517 * get_pv_entry() calls pmap_collect() and that pmap_collect() 2518 * removes one of the mappings that is being promoted. 2519 */ 2520 m = PHYS_TO_VM_PAGE(pa); 2521 va = trunc_4mpage(va); 2522 pv = pmap_pvh_remove(&m->md, pmap, va); 2523 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found")); 2524 pvh = pa_to_pvh(pa); 2525 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next); 2526 /* Free the remaining NPTEPG - 1 pv entries. */ 2527 va_last = va + NBPDR - PAGE_SIZE; 2528 do { 2529 m++; 2530 va += PAGE_SIZE; 2531 pmap_pvh_free(&m->md, pmap, va); 2532 } while (va < va_last); 2533} 2534 2535static void 2536pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2537{ 2538 pv_entry_t pv; 2539 2540 pv = pmap_pvh_remove(pvh, pmap, va); 2541 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found")); 2542 free_pv_entry(pmap, pv); 2543} 2544 2545static void 2546pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va) 2547{ 2548 struct md_page *pvh; 2549 2550 rw_assert(&pvh_global_lock, RA_WLOCKED); 2551 pmap_pvh_free(&m->md, pmap, va); 2552 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) { 2553 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 2554 if (TAILQ_EMPTY(&pvh->pv_list)) 2555 vm_page_aflag_clear(m, PGA_WRITEABLE); 2556 } 2557} 2558 2559/* 2560 * Create a pv entry for page at pa for 2561 * (pmap, va). 2562 */ 2563static void 2564pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2565{ 2566 pv_entry_t pv; 2567 2568 rw_assert(&pvh_global_lock, RA_WLOCKED); 2569 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2570 pv = get_pv_entry(pmap, FALSE); 2571 pv->pv_va = va; 2572 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 2573} 2574 2575/* 2576 * Conditionally create a pv entry. 2577 */ 2578static boolean_t 2579pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2580{ 2581 pv_entry_t pv; 2582 2583 rw_assert(&pvh_global_lock, RA_WLOCKED); 2584 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2585 if (pv_entry_count < pv_entry_high_water && 2586 (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2587 pv->pv_va = va; 2588 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 2589 return (TRUE); 2590 } else 2591 return (FALSE); 2592} 2593 2594/* 2595 * Create the pv entries for each of the pages within a superpage. 2596 */ 2597static boolean_t 2598pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 2599{ 2600 struct md_page *pvh; 2601 pv_entry_t pv; 2602 2603 rw_assert(&pvh_global_lock, RA_WLOCKED); 2604 if (pv_entry_count < pv_entry_high_water && 2605 (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2606 pv->pv_va = va; 2607 pvh = pa_to_pvh(pa); 2608 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next); 2609 return (TRUE); 2610 } else 2611 return (FALSE); 2612} 2613 2614/* 2615 * Fills a page table page with mappings to consecutive physical pages. 2616 */ 2617static void 2618pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte) 2619{ 2620 pt_entry_t *pte; 2621 2622 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) { 2623 *pte = newpte; 2624 newpte += PAGE_SIZE; 2625 } 2626} 2627 2628/* 2629 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the 2630 * 2- or 4MB page mapping is invalidated. 2631 */ 2632static boolean_t 2633pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va) 2634{ 2635 pd_entry_t newpde, oldpde; 2636 pt_entry_t *firstpte, newpte; 2637 vm_paddr_t mptepa; 2638 vm_page_t mpte; 2639 struct spglist free; 2640 2641 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2642 oldpde = *pde; 2643 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V), 2644 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V")); 2645 if ((oldpde & PG_A) != 0 && (mpte = pmap_lookup_pt_page(pmap, va)) != 2646 NULL) 2647 pmap_remove_pt_page(pmap, mpte); 2648 else { 2649 KASSERT((oldpde & PG_W) == 0, 2650 ("pmap_demote_pde: page table page for a wired mapping" 2651 " is missing")); 2652 2653 /* 2654 * Invalidate the 2- or 4MB page mapping and return 2655 * "failure" if the mapping was never accessed or the 2656 * allocation of the new page table page fails. 2657 */ 2658 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL, 2659 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL | 2660 VM_ALLOC_WIRED)) == NULL) { 2661 SLIST_INIT(&free); 2662 pmap_remove_pde(pmap, pde, trunc_4mpage(va), &free); 2663 pmap_invalidate_page(pmap, trunc_4mpage(va)); 2664 pmap_free_zero_pages(&free); 2665 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x" 2666 " in pmap %p", va, pmap); 2667 return (FALSE); 2668 } 2669 if (va < VM_MAXUSER_ADDRESS) 2670 pmap->pm_stats.resident_count++; 2671 } 2672 mptepa = VM_PAGE_TO_PHYS(mpte); 2673 2674 /* 2675 * If the page mapping is in the kernel's address space, then the 2676 * KPTmap can provide access to the page table page. Otherwise, 2677 * temporarily map the page table page (mpte) into the kernel's 2678 * address space at either PADDR1 or PADDR2. 2679 */ 2680 if (va >= KERNBASE) 2681 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))]; 2682 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) { 2683 if ((*PMAP1 & PG_FRAME) != mptepa) { 2684 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M; 2685#ifdef SMP 2686 PMAP1cpu = PCPU_GET(cpuid); 2687#endif 2688 invlcaddr(PADDR1); 2689 PMAP1changed++; 2690 } else 2691#ifdef SMP 2692 if (PMAP1cpu != PCPU_GET(cpuid)) { 2693 PMAP1cpu = PCPU_GET(cpuid); 2694 invlcaddr(PADDR1); 2695 PMAP1changedcpu++; 2696 } else 2697#endif 2698 PMAP1unchanged++; 2699 firstpte = PADDR1; 2700 } else { 2701 mtx_lock(&PMAP2mutex); 2702 if ((*PMAP2 & PG_FRAME) != mptepa) { 2703 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M; 2704 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2); 2705 } 2706 firstpte = PADDR2; 2707 } 2708 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V; 2709 KASSERT((oldpde & PG_A) != 0, 2710 ("pmap_demote_pde: oldpde is missing PG_A")); 2711 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW, 2712 ("pmap_demote_pde: oldpde is missing PG_M")); 2713 newpte = oldpde & ~PG_PS; 2714 if ((newpte & PG_PDE_PAT) != 0) 2715 newpte ^= PG_PDE_PAT | PG_PTE_PAT; 2716 2717 /* 2718 * If the page table page is new, initialize it. 2719 */ 2720 if (mpte->wire_count == 1) { 2721 mpte->wire_count = NPTEPG; 2722 pmap_fill_ptp(firstpte, newpte); 2723 } 2724 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME), 2725 ("pmap_demote_pde: firstpte and newpte map different physical" 2726 " addresses")); 2727 2728 /* 2729 * If the mapping has changed attributes, update the page table 2730 * entries. 2731 */ 2732 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE)) 2733 pmap_fill_ptp(firstpte, newpte); 2734 2735 /* 2736 * Demote the mapping. This pmap is locked. The old PDE has 2737 * PG_A set. If the old PDE has PG_RW set, it also has PG_M 2738 * set. Thus, there is no danger of a race with another 2739 * processor changing the setting of PG_A and/or PG_M between 2740 * the read above and the store below. 2741 */ 2742 if (workaround_erratum383) 2743 pmap_update_pde(pmap, va, pde, newpde); 2744 else if (pmap == kernel_pmap) 2745 pmap_kenter_pde(va, newpde); 2746 else 2747 pde_store(pde, newpde); 2748 if (firstpte == PADDR2) 2749 mtx_unlock(&PMAP2mutex); 2750 2751 /* 2752 * Invalidate the recursive mapping of the page table page. 2753 */ 2754 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va)); 2755 2756 /* 2757 * Demote the pv entry. This depends on the earlier demotion 2758 * of the mapping. Specifically, the (re)creation of a per- 2759 * page pv entry might trigger the execution of pmap_collect(), 2760 * which might reclaim a newly (re)created per-page pv entry 2761 * and destroy the associated mapping. In order to destroy 2762 * the mapping, the PDE must have already changed from mapping 2763 * the 2mpage to referencing the page table page. 2764 */ 2765 if ((oldpde & PG_MANAGED) != 0) 2766 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME); 2767 2768 pmap_pde_demotions++; 2769 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x" 2770 " in pmap %p", va, pmap); 2771 return (TRUE); 2772} 2773 2774/* 2775 * Removes a 2- or 4MB page mapping from the kernel pmap. 2776 */ 2777static void 2778pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va) 2779{ 2780 pd_entry_t newpde; 2781 vm_paddr_t mptepa; 2782 vm_page_t mpte; 2783 2784 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2785 mpte = pmap_lookup_pt_page(pmap, va); 2786 if (mpte == NULL) 2787 panic("pmap_remove_kernel_pde: Missing pt page."); 2788 2789 pmap_remove_pt_page(pmap, mpte); 2790 mptepa = VM_PAGE_TO_PHYS(mpte); 2791 newpde = mptepa | PG_M | PG_A | PG_RW | PG_V; 2792 2793 /* 2794 * Initialize the page table page. 2795 */ 2796 pagezero((void *)&KPTmap[i386_btop(trunc_4mpage(va))]); 2797 2798 /* 2799 * Remove the mapping. 2800 */ 2801 if (workaround_erratum383) 2802 pmap_update_pde(pmap, va, pde, newpde); 2803 else 2804 pmap_kenter_pde(va, newpde); 2805 2806 /* 2807 * Invalidate the recursive mapping of the page table page. 2808 */ 2809 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va)); 2810} 2811 2812/* 2813 * pmap_remove_pde: do the things to unmap a superpage in a process 2814 */ 2815static void 2816pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva, 2817 struct spglist *free) 2818{ 2819 struct md_page *pvh; 2820 pd_entry_t oldpde; 2821 vm_offset_t eva, va; 2822 vm_page_t m, mpte; 2823 2824 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2825 KASSERT((sva & PDRMASK) == 0, 2826 ("pmap_remove_pde: sva is not 4mpage aligned")); 2827 oldpde = pte_load_clear(pdq); 2828 if (oldpde & PG_W) 2829 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE; 2830 2831 /* 2832 * Machines that don't support invlpg, also don't support 2833 * PG_G. 2834 */ 2835 if (oldpde & PG_G) 2836 pmap_invalidate_page(kernel_pmap, sva); 2837 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 2838 if (oldpde & PG_MANAGED) { 2839 pvh = pa_to_pvh(oldpde & PG_PS_FRAME); 2840 pmap_pvh_free(pvh, pmap, sva); 2841 eva = sva + NBPDR; 2842 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME); 2843 va < eva; va += PAGE_SIZE, m++) { 2844 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2845 vm_page_dirty(m); 2846 if (oldpde & PG_A) 2847 vm_page_aflag_set(m, PGA_REFERENCED); 2848 if (TAILQ_EMPTY(&m->md.pv_list) && 2849 TAILQ_EMPTY(&pvh->pv_list)) 2850 vm_page_aflag_clear(m, PGA_WRITEABLE); 2851 } 2852 } 2853 if (pmap == kernel_pmap) { 2854 pmap_remove_kernel_pde(pmap, pdq, sva); 2855 } else { 2856 mpte = pmap_lookup_pt_page(pmap, sva); 2857 if (mpte != NULL) { 2858 pmap_remove_pt_page(pmap, mpte); 2859 pmap->pm_stats.resident_count--; 2860 KASSERT(mpte->wire_count == NPTEPG, 2861 ("pmap_remove_pde: pte page wire count error")); 2862 mpte->wire_count = 0; 2863 pmap_add_delayed_free_list(mpte, free, FALSE); 2864 atomic_subtract_int(&cnt.v_wire_count, 1); 2865 } 2866 } 2867} 2868 2869/* 2870 * pmap_remove_pte: do the things to unmap a page in a process 2871 */ 2872static int 2873pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va, 2874 struct spglist *free) 2875{ 2876 pt_entry_t oldpte; 2877 vm_page_t m; 2878 2879 rw_assert(&pvh_global_lock, RA_WLOCKED); 2880 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2881 oldpte = pte_load_clear(ptq); 2882 KASSERT(oldpte != 0, 2883 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va)); 2884 if (oldpte & PG_W) 2885 pmap->pm_stats.wired_count -= 1; 2886 /* 2887 * Machines that don't support invlpg, also don't support 2888 * PG_G. 2889 */ 2890 if (oldpte & PG_G) 2891 pmap_invalidate_page(kernel_pmap, va); 2892 pmap->pm_stats.resident_count -= 1; 2893 if (oldpte & PG_MANAGED) { 2894 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME); 2895 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2896 vm_page_dirty(m); 2897 if (oldpte & PG_A) 2898 vm_page_aflag_set(m, PGA_REFERENCED); 2899 pmap_remove_entry(pmap, m, va); 2900 } 2901 return (pmap_unuse_pt(pmap, va, free)); 2902} 2903 2904/* 2905 * Remove a single page from a process address space 2906 */ 2907static void 2908pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free) 2909{ 2910 pt_entry_t *pte; 2911 2912 rw_assert(&pvh_global_lock, RA_WLOCKED); 2913 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 2914 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2915 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0) 2916 return; 2917 pmap_remove_pte(pmap, pte, va, free); 2918 pmap_invalidate_page(pmap, va); 2919} 2920 2921/* 2922 * Remove the given range of addresses from the specified map. 2923 * 2924 * It is assumed that the start and end are properly 2925 * rounded to the page size. 2926 */ 2927void 2928pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2929{ 2930 vm_offset_t pdnxt; 2931 pd_entry_t ptpaddr; 2932 pt_entry_t *pte; 2933 struct spglist free; 2934 int anyvalid; 2935 2936 /* 2937 * Perform an unsynchronized read. This is, however, safe. 2938 */ 2939 if (pmap->pm_stats.resident_count == 0) 2940 return; 2941 2942 anyvalid = 0; 2943 SLIST_INIT(&free); 2944 2945 rw_wlock(&pvh_global_lock); 2946 sched_pin(); 2947 PMAP_LOCK(pmap); 2948 2949 /* 2950 * special handling of removing one page. a very 2951 * common operation and easy to short circuit some 2952 * code. 2953 */ 2954 if ((sva + PAGE_SIZE == eva) && 2955 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) { 2956 pmap_remove_page(pmap, sva, &free); 2957 goto out; 2958 } 2959 2960 for (; sva < eva; sva = pdnxt) { 2961 u_int pdirindex; 2962 2963 /* 2964 * Calculate index for next page table. 2965 */ 2966 pdnxt = (sva + NBPDR) & ~PDRMASK; 2967 if (pdnxt < sva) 2968 pdnxt = eva; 2969 if (pmap->pm_stats.resident_count == 0) 2970 break; 2971 2972 pdirindex = sva >> PDRSHIFT; 2973 ptpaddr = pmap->pm_pdir[pdirindex]; 2974 2975 /* 2976 * Weed out invalid mappings. Note: we assume that the page 2977 * directory table is always allocated, and in kernel virtual. 2978 */ 2979 if (ptpaddr == 0) 2980 continue; 2981 2982 /* 2983 * Check for large page. 2984 */ 2985 if ((ptpaddr & PG_PS) != 0) { 2986 /* 2987 * Are we removing the entire large page? If not, 2988 * demote the mapping and fall through. 2989 */ 2990 if (sva + NBPDR == pdnxt && eva >= pdnxt) { 2991 /* 2992 * The TLB entry for a PG_G mapping is 2993 * invalidated by pmap_remove_pde(). 2994 */ 2995 if ((ptpaddr & PG_G) == 0) 2996 anyvalid = 1; 2997 pmap_remove_pde(pmap, 2998 &pmap->pm_pdir[pdirindex], sva, &free); 2999 continue; 3000 } else if (!pmap_demote_pde(pmap, 3001 &pmap->pm_pdir[pdirindex], sva)) { 3002 /* The large page mapping was destroyed. */ 3003 continue; 3004 } 3005 } 3006 3007 /* 3008 * Limit our scan to either the end of the va represented 3009 * by the current page table page, or to the end of the 3010 * range being removed. 3011 */ 3012 if (pdnxt > eva) 3013 pdnxt = eva; 3014 3015 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 3016 sva += PAGE_SIZE) { 3017 if (*pte == 0) 3018 continue; 3019 3020 /* 3021 * The TLB entry for a PG_G mapping is invalidated 3022 * by pmap_remove_pte(). 3023 */ 3024 if ((*pte & PG_G) == 0) 3025 anyvalid = 1; 3026 if (pmap_remove_pte(pmap, pte, sva, &free)) 3027 break; 3028 } 3029 } 3030out: 3031 sched_unpin(); 3032 if (anyvalid) 3033 pmap_invalidate_all(pmap); 3034 rw_wunlock(&pvh_global_lock); 3035 PMAP_UNLOCK(pmap); 3036 pmap_free_zero_pages(&free); 3037} 3038 3039/* 3040 * Routine: pmap_remove_all 3041 * Function: 3042 * Removes this physical page from 3043 * all physical maps in which it resides. 3044 * Reflects back modify bits to the pager. 3045 * 3046 * Notes: 3047 * Original versions of this routine were very 3048 * inefficient because they iteratively called 3049 * pmap_remove (slow...) 3050 */ 3051 3052void 3053pmap_remove_all(vm_page_t m) 3054{ 3055 struct md_page *pvh; 3056 pv_entry_t pv; 3057 pmap_t pmap; 3058 pt_entry_t *pte, tpte; 3059 pd_entry_t *pde; 3060 vm_offset_t va; 3061 struct spglist free; 3062 3063 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3064 ("pmap_remove_all: page %p is not managed", m)); 3065 SLIST_INIT(&free); 3066 rw_wlock(&pvh_global_lock); 3067 sched_pin(); 3068 if ((m->flags & PG_FICTITIOUS) != 0) 3069 goto small_mappings; 3070 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 3071 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) { 3072 va = pv->pv_va; 3073 pmap = PV_PMAP(pv); 3074 PMAP_LOCK(pmap); 3075 pde = pmap_pde(pmap, va); 3076 (void)pmap_demote_pde(pmap, pde, va); 3077 PMAP_UNLOCK(pmap); 3078 } 3079small_mappings: 3080 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 3081 pmap = PV_PMAP(pv); 3082 PMAP_LOCK(pmap); 3083 pmap->pm_stats.resident_count--; 3084 pde = pmap_pde(pmap, pv->pv_va); 3085 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found" 3086 " a 4mpage in page %p's pv list", m)); 3087 pte = pmap_pte_quick(pmap, pv->pv_va); 3088 tpte = pte_load_clear(pte); 3089 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte", 3090 pmap, pv->pv_va)); 3091 if (tpte & PG_W) 3092 pmap->pm_stats.wired_count--; 3093 if (tpte & PG_A) 3094 vm_page_aflag_set(m, PGA_REFERENCED); 3095 3096 /* 3097 * Update the vm_page_t clean and reference bits. 3098 */ 3099 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 3100 vm_page_dirty(m); 3101 pmap_unuse_pt(pmap, pv->pv_va, &free); 3102 pmap_invalidate_page(pmap, pv->pv_va); 3103 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 3104 free_pv_entry(pmap, pv); 3105 PMAP_UNLOCK(pmap); 3106 } 3107 vm_page_aflag_clear(m, PGA_WRITEABLE); 3108 sched_unpin(); 3109 rw_wunlock(&pvh_global_lock); 3110 pmap_free_zero_pages(&free); 3111} 3112 3113/* 3114 * pmap_protect_pde: do the things to protect a 4mpage in a process 3115 */ 3116static boolean_t 3117pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot) 3118{ 3119 pd_entry_t newpde, oldpde; 3120 vm_offset_t eva, va; 3121 vm_page_t m; 3122 boolean_t anychanged; 3123 3124 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3125 KASSERT((sva & PDRMASK) == 0, 3126 ("pmap_protect_pde: sva is not 4mpage aligned")); 3127 anychanged = FALSE; 3128retry: 3129 oldpde = newpde = *pde; 3130 if (oldpde & PG_MANAGED) { 3131 eva = sva + NBPDR; 3132 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME); 3133 va < eva; va += PAGE_SIZE, m++) 3134 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) 3135 vm_page_dirty(m); 3136 } 3137 if ((prot & VM_PROT_WRITE) == 0) 3138 newpde &= ~(PG_RW | PG_M); 3139#ifdef PAE 3140 if ((prot & VM_PROT_EXECUTE) == 0) 3141 newpde |= pg_nx; 3142#endif 3143 if (newpde != oldpde) { 3144 if (!pde_cmpset(pde, oldpde, newpde)) 3145 goto retry; 3146 if (oldpde & PG_G) 3147 pmap_invalidate_page(pmap, sva); 3148 else 3149 anychanged = TRUE; 3150 } 3151 return (anychanged); 3152} 3153 3154/* 3155 * Set the physical protection on the 3156 * specified range of this map as requested. 3157 */ 3158void 3159pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 3160{ 3161 vm_offset_t pdnxt; 3162 pd_entry_t ptpaddr; 3163 pt_entry_t *pte; 3164 boolean_t anychanged, pv_lists_locked; 3165 3166 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 3167 pmap_remove(pmap, sva, eva); 3168 return; 3169 } 3170 3171#ifdef PAE 3172 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) == 3173 (VM_PROT_WRITE|VM_PROT_EXECUTE)) 3174 return; 3175#else 3176 if (prot & VM_PROT_WRITE) 3177 return; 3178#endif 3179 3180 if (pmap_is_current(pmap)) 3181 pv_lists_locked = FALSE; 3182 else { 3183 pv_lists_locked = TRUE; 3184resume: 3185 rw_wlock(&pvh_global_lock); 3186 sched_pin(); 3187 } 3188 anychanged = FALSE; 3189 3190 PMAP_LOCK(pmap); 3191 for (; sva < eva; sva = pdnxt) { 3192 pt_entry_t obits, pbits; 3193 u_int pdirindex; 3194 3195 pdnxt = (sva + NBPDR) & ~PDRMASK; 3196 if (pdnxt < sva) 3197 pdnxt = eva; 3198 3199 pdirindex = sva >> PDRSHIFT; 3200 ptpaddr = pmap->pm_pdir[pdirindex]; 3201 3202 /* 3203 * Weed out invalid mappings. Note: we assume that the page 3204 * directory table is always allocated, and in kernel virtual. 3205 */ 3206 if (ptpaddr == 0) 3207 continue; 3208 3209 /* 3210 * Check for large page. 3211 */ 3212 if ((ptpaddr & PG_PS) != 0) { 3213 /* 3214 * Are we protecting the entire large page? If not, 3215 * demote the mapping and fall through. 3216 */ 3217 if (sva + NBPDR == pdnxt && eva >= pdnxt) { 3218 /* 3219 * The TLB entry for a PG_G mapping is 3220 * invalidated by pmap_protect_pde(). 3221 */ 3222 if (pmap_protect_pde(pmap, 3223 &pmap->pm_pdir[pdirindex], sva, prot)) 3224 anychanged = TRUE; 3225 continue; 3226 } else { 3227 if (!pv_lists_locked) { 3228 pv_lists_locked = TRUE; 3229 if (!rw_try_wlock(&pvh_global_lock)) { 3230 if (anychanged) 3231 pmap_invalidate_all( 3232 pmap); 3233 PMAP_UNLOCK(pmap); 3234 goto resume; 3235 } 3236 sched_pin(); 3237 } 3238 if (!pmap_demote_pde(pmap, 3239 &pmap->pm_pdir[pdirindex], sva)) { 3240 /* 3241 * The large page mapping was 3242 * destroyed. 3243 */ 3244 continue; 3245 } 3246 } 3247 } 3248 3249 if (pdnxt > eva) 3250 pdnxt = eva; 3251 3252 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 3253 sva += PAGE_SIZE) { 3254 vm_page_t m; 3255 3256retry: 3257 /* 3258 * Regardless of whether a pte is 32 or 64 bits in 3259 * size, PG_RW, PG_A, and PG_M are among the least 3260 * significant 32 bits. 3261 */ 3262 obits = pbits = *pte; 3263 if ((pbits & PG_V) == 0) 3264 continue; 3265 3266 if ((prot & VM_PROT_WRITE) == 0) { 3267 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) == 3268 (PG_MANAGED | PG_M | PG_RW)) { 3269 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME); 3270 vm_page_dirty(m); 3271 } 3272 pbits &= ~(PG_RW | PG_M); 3273 } 3274#ifdef PAE 3275 if ((prot & VM_PROT_EXECUTE) == 0) 3276 pbits |= pg_nx; 3277#endif 3278 3279 if (pbits != obits) { 3280#ifdef PAE 3281 if (!atomic_cmpset_64(pte, obits, pbits)) 3282 goto retry; 3283#else 3284 if (!atomic_cmpset_int((u_int *)pte, obits, 3285 pbits)) 3286 goto retry; 3287#endif 3288 if (obits & PG_G) 3289 pmap_invalidate_page(pmap, sva); 3290 else 3291 anychanged = TRUE; 3292 } 3293 } 3294 } 3295 if (anychanged) 3296 pmap_invalidate_all(pmap); 3297 if (pv_lists_locked) { 3298 sched_unpin(); 3299 rw_wunlock(&pvh_global_lock); 3300 } 3301 PMAP_UNLOCK(pmap); 3302} 3303 3304/* 3305 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are 3306 * within a single page table page (PTP) to a single 2- or 4MB page mapping. 3307 * For promotion to occur, two conditions must be met: (1) the 4KB page 3308 * mappings must map aligned, contiguous physical memory and (2) the 4KB page 3309 * mappings must have identical characteristics. 3310 * 3311 * Managed (PG_MANAGED) mappings within the kernel address space are not 3312 * promoted. The reason is that kernel PDEs are replicated in each pmap but 3313 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel 3314 * pmap. 3315 */ 3316static void 3317pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va) 3318{ 3319 pd_entry_t newpde; 3320 pt_entry_t *firstpte, oldpte, pa, *pte; 3321 vm_offset_t oldpteva; 3322 vm_page_t mpte; 3323 3324 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3325 3326 /* 3327 * Examine the first PTE in the specified PTP. Abort if this PTE is 3328 * either invalid, unused, or does not map the first 4KB physical page 3329 * within a 2- or 4MB page. 3330 */ 3331 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va)); 3332setpde: 3333 newpde = *firstpte; 3334 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) { 3335 pmap_pde_p_failures++; 3336 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3337 " in pmap %p", va, pmap); 3338 return; 3339 } 3340 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) { 3341 pmap_pde_p_failures++; 3342 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3343 " in pmap %p", va, pmap); 3344 return; 3345 } 3346 if ((newpde & (PG_M | PG_RW)) == PG_RW) { 3347 /* 3348 * When PG_M is already clear, PG_RW can be cleared without 3349 * a TLB invalidation. 3350 */ 3351 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde & 3352 ~PG_RW)) 3353 goto setpde; 3354 newpde &= ~PG_RW; 3355 } 3356 3357 /* 3358 * Examine each of the other PTEs in the specified PTP. Abort if this 3359 * PTE maps an unexpected 4KB physical page or does not have identical 3360 * characteristics to the first PTE. 3361 */ 3362 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE; 3363 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) { 3364setpte: 3365 oldpte = *pte; 3366 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) { 3367 pmap_pde_p_failures++; 3368 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3369 " in pmap %p", va, pmap); 3370 return; 3371 } 3372 if ((oldpte & (PG_M | PG_RW)) == PG_RW) { 3373 /* 3374 * When PG_M is already clear, PG_RW can be cleared 3375 * without a TLB invalidation. 3376 */ 3377 if (!atomic_cmpset_int((u_int *)pte, oldpte, 3378 oldpte & ~PG_RW)) 3379 goto setpte; 3380 oldpte &= ~PG_RW; 3381 oldpteva = (oldpte & PG_FRAME & PDRMASK) | 3382 (va & ~PDRMASK); 3383 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x" 3384 " in pmap %p", oldpteva, pmap); 3385 } 3386 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) { 3387 pmap_pde_p_failures++; 3388 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3389 " in pmap %p", va, pmap); 3390 return; 3391 } 3392 pa -= PAGE_SIZE; 3393 } 3394 3395 /* 3396 * Save the page table page in its current state until the PDE 3397 * mapping the superpage is demoted by pmap_demote_pde() or 3398 * destroyed by pmap_remove_pde(). 3399 */ 3400 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME); 3401 KASSERT(mpte >= vm_page_array && 3402 mpte < &vm_page_array[vm_page_array_size], 3403 ("pmap_promote_pde: page table page is out of range")); 3404 KASSERT(mpte->pindex == va >> PDRSHIFT, 3405 ("pmap_promote_pde: page table page's pindex is wrong")); 3406 if (pmap_insert_pt_page(pmap, mpte)) { 3407 pmap_pde_p_failures++; 3408 CTR2(KTR_PMAP, 3409 "pmap_promote_pde: failure for va %#x in pmap %p", va, 3410 pmap); 3411 return; 3412 } 3413 3414 /* 3415 * Promote the pv entries. 3416 */ 3417 if ((newpde & PG_MANAGED) != 0) 3418 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME); 3419 3420 /* 3421 * Propagate the PAT index to its proper position. 3422 */ 3423 if ((newpde & PG_PTE_PAT) != 0) 3424 newpde ^= PG_PDE_PAT | PG_PTE_PAT; 3425 3426 /* 3427 * Map the superpage. 3428 */ 3429 if (workaround_erratum383) 3430 pmap_update_pde(pmap, va, pde, PG_PS | newpde); 3431 else if (pmap == kernel_pmap) 3432 pmap_kenter_pde(va, PG_PS | newpde); 3433 else 3434 pde_store(pde, PG_PS | newpde); 3435 3436 pmap_pde_promotions++; 3437 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x" 3438 " in pmap %p", va, pmap); 3439} 3440 3441/* 3442 * Insert the given physical page (p) at 3443 * the specified virtual address (v) in the 3444 * target physical map with the protection requested. 3445 * 3446 * If specified, the page will be wired down, meaning 3447 * that the related pte can not be reclaimed. 3448 * 3449 * NB: This is the only routine which MAY NOT lazy-evaluate 3450 * or lose information. That is, this routine must actually 3451 * insert this page into the given map NOW. 3452 */ 3453int 3454pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 3455 u_int flags, int8_t psind) 3456{ 3457 pd_entry_t *pde; 3458 pt_entry_t *pte; 3459 pt_entry_t newpte, origpte; 3460 pv_entry_t pv; 3461 vm_paddr_t opa, pa; 3462 vm_page_t mpte, om; 3463 boolean_t invlva, wired; 3464 3465 va = trunc_page(va); 3466 mpte = NULL; 3467 wired = (flags & PMAP_ENTER_WIRED) != 0; 3468 3469 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig")); 3470 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS, 3471 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)", 3472 va)); 3473 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 3474 VM_OBJECT_ASSERT_LOCKED(m->object); 3475 3476 rw_wlock(&pvh_global_lock); 3477 PMAP_LOCK(pmap); 3478 sched_pin(); 3479 3480 /* 3481 * In the case that a page table page is not 3482 * resident, we are creating it here. 3483 */ 3484 if (va < VM_MAXUSER_ADDRESS) { 3485 mpte = pmap_allocpte(pmap, va, flags); 3486 if (mpte == NULL) { 3487 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0, 3488 ("pmap_allocpte failed with sleep allowed")); 3489 sched_unpin(); 3490 rw_wunlock(&pvh_global_lock); 3491 PMAP_UNLOCK(pmap); 3492 return (KERN_RESOURCE_SHORTAGE); 3493 } 3494 } 3495 3496 pde = pmap_pde(pmap, va); 3497 if ((*pde & PG_PS) != 0) 3498 panic("pmap_enter: attempted pmap_enter on 4MB page"); 3499 pte = pmap_pte_quick(pmap, va); 3500 3501 /* 3502 * Page Directory table entry not valid, we need a new PT page 3503 */ 3504 if (pte == NULL) { 3505 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x", 3506 (uintmax_t)pmap->pm_pdir[PTDPTDI], va); 3507 } 3508 3509 pa = VM_PAGE_TO_PHYS(m); 3510 om = NULL; 3511 origpte = *pte; 3512 opa = origpte & PG_FRAME; 3513 3514 /* 3515 * Mapping has not changed, must be protection or wiring change. 3516 */ 3517 if (origpte && (opa == pa)) { 3518 /* 3519 * Wiring change, just update stats. We don't worry about 3520 * wiring PT pages as they remain resident as long as there 3521 * are valid mappings in them. Hence, if a user page is wired, 3522 * the PT page will be also. 3523 */ 3524 if (wired && ((origpte & PG_W) == 0)) 3525 pmap->pm_stats.wired_count++; 3526 else if (!wired && (origpte & PG_W)) 3527 pmap->pm_stats.wired_count--; 3528 3529 /* 3530 * Remove extra pte reference 3531 */ 3532 if (mpte) 3533 mpte->wire_count--; 3534 3535 if (origpte & PG_MANAGED) { 3536 om = m; 3537 pa |= PG_MANAGED; 3538 } 3539 goto validate; 3540 } 3541 3542 pv = NULL; 3543 3544 /* 3545 * Mapping has changed, invalidate old range and fall through to 3546 * handle validating new mapping. 3547 */ 3548 if (opa) { 3549 if (origpte & PG_W) 3550 pmap->pm_stats.wired_count--; 3551 if (origpte & PG_MANAGED) { 3552 om = PHYS_TO_VM_PAGE(opa); 3553 pv = pmap_pvh_remove(&om->md, pmap, va); 3554 } 3555 if (mpte != NULL) { 3556 mpte->wire_count--; 3557 KASSERT(mpte->wire_count > 0, 3558 ("pmap_enter: missing reference to page table page," 3559 " va: 0x%x", va)); 3560 } 3561 } else 3562 pmap->pm_stats.resident_count++; 3563 3564 /* 3565 * Enter on the PV list if part of our managed memory. 3566 */ 3567 if ((m->oflags & VPO_UNMANAGED) == 0) { 3568 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 3569 ("pmap_enter: managed mapping within the clean submap")); 3570 if (pv == NULL) 3571 pv = get_pv_entry(pmap, FALSE); 3572 pv->pv_va = va; 3573 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 3574 pa |= PG_MANAGED; 3575 } else if (pv != NULL) 3576 free_pv_entry(pmap, pv); 3577 3578 /* 3579 * Increment counters 3580 */ 3581 if (wired) 3582 pmap->pm_stats.wired_count++; 3583 3584validate: 3585 /* 3586 * Now validate mapping with desired protection/wiring. 3587 */ 3588 newpte = (pt_entry_t)(pa | pmap_cache_bits(m->md.pat_mode, 0) | PG_V); 3589 if ((prot & VM_PROT_WRITE) != 0) { 3590 newpte |= PG_RW; 3591 if ((newpte & PG_MANAGED) != 0) 3592 vm_page_aflag_set(m, PGA_WRITEABLE); 3593 } 3594#ifdef PAE 3595 if ((prot & VM_PROT_EXECUTE) == 0) 3596 newpte |= pg_nx; 3597#endif 3598 if (wired) 3599 newpte |= PG_W; 3600 if (va < VM_MAXUSER_ADDRESS) 3601 newpte |= PG_U; 3602 if (pmap == kernel_pmap) 3603 newpte |= pgeflag; 3604 3605 /* 3606 * if the mapping or permission bits are different, we need 3607 * to update the pte. 3608 */ 3609 if ((origpte & ~(PG_M|PG_A)) != newpte) { 3610 newpte |= PG_A; 3611 if ((flags & VM_PROT_WRITE) != 0) 3612 newpte |= PG_M; 3613 if (origpte & PG_V) { 3614 invlva = FALSE; 3615 origpte = pte_load_store(pte, newpte); 3616 if (origpte & PG_A) { 3617 if (origpte & PG_MANAGED) 3618 vm_page_aflag_set(om, PGA_REFERENCED); 3619 if (opa != VM_PAGE_TO_PHYS(m)) 3620 invlva = TRUE; 3621#ifdef PAE 3622 if ((origpte & PG_NX) == 0 && 3623 (newpte & PG_NX) != 0) 3624 invlva = TRUE; 3625#endif 3626 } 3627 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 3628 if ((origpte & PG_MANAGED) != 0) 3629 vm_page_dirty(om); 3630 if ((prot & VM_PROT_WRITE) == 0) 3631 invlva = TRUE; 3632 } 3633 if ((origpte & PG_MANAGED) != 0 && 3634 TAILQ_EMPTY(&om->md.pv_list) && 3635 ((om->flags & PG_FICTITIOUS) != 0 || 3636 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list))) 3637 vm_page_aflag_clear(om, PGA_WRITEABLE); 3638 if (invlva) 3639 pmap_invalidate_page(pmap, va); 3640 } else 3641 pte_store(pte, newpte); 3642 } 3643 3644 /* 3645 * If both the page table page and the reservation are fully 3646 * populated, then attempt promotion. 3647 */ 3648 if ((mpte == NULL || mpte->wire_count == NPTEPG) && 3649 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 && 3650 vm_reserv_level_iffullpop(m) == 0) 3651 pmap_promote_pde(pmap, pde, va); 3652 3653 sched_unpin(); 3654 rw_wunlock(&pvh_global_lock); 3655 PMAP_UNLOCK(pmap); 3656 return (KERN_SUCCESS); 3657} 3658 3659/* 3660 * Tries to create a 2- or 4MB page mapping. Returns TRUE if successful and 3661 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without 3662 * blocking, (2) a mapping already exists at the specified virtual address, or 3663 * (3) a pv entry cannot be allocated without reclaiming another pv entry. 3664 */ 3665static boolean_t 3666pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 3667{ 3668 pd_entry_t *pde, newpde; 3669 3670 rw_assert(&pvh_global_lock, RA_WLOCKED); 3671 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3672 pde = pmap_pde(pmap, va); 3673 if (*pde != 0) { 3674 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx" 3675 " in pmap %p", va, pmap); 3676 return (FALSE); 3677 } 3678 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) | 3679 PG_PS | PG_V; 3680 if ((m->oflags & VPO_UNMANAGED) == 0) { 3681 newpde |= PG_MANAGED; 3682 3683 /* 3684 * Abort this mapping if its PV entry could not be created. 3685 */ 3686 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m))) { 3687 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx" 3688 " in pmap %p", va, pmap); 3689 return (FALSE); 3690 } 3691 } 3692#ifdef PAE 3693 if ((prot & VM_PROT_EXECUTE) == 0) 3694 newpde |= pg_nx; 3695#endif 3696 if (va < VM_MAXUSER_ADDRESS) 3697 newpde |= PG_U; 3698 3699 /* 3700 * Increment counters. 3701 */ 3702 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE; 3703 3704 /* 3705 * Map the superpage. 3706 */ 3707 pde_store(pde, newpde); 3708 3709 pmap_pde_mappings++; 3710 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx" 3711 " in pmap %p", va, pmap); 3712 return (TRUE); 3713} 3714 3715/* 3716 * Maps a sequence of resident pages belonging to the same object. 3717 * The sequence begins with the given page m_start. This page is 3718 * mapped at the given virtual address start. Each subsequent page is 3719 * mapped at a virtual address that is offset from start by the same 3720 * amount as the page is offset from m_start within the object. The 3721 * last page in the sequence is the page with the largest offset from 3722 * m_start that can be mapped at a virtual address less than the given 3723 * virtual address end. Not every virtual page between start and end 3724 * is mapped; only those for which a resident page exists with the 3725 * corresponding offset from m_start are mapped. 3726 */ 3727void 3728pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 3729 vm_page_t m_start, vm_prot_t prot) 3730{ 3731 vm_offset_t va; 3732 vm_page_t m, mpte; 3733 vm_pindex_t diff, psize; 3734 3735 VM_OBJECT_ASSERT_LOCKED(m_start->object); 3736 3737 psize = atop(end - start); 3738 mpte = NULL; 3739 m = m_start; 3740 rw_wlock(&pvh_global_lock); 3741 PMAP_LOCK(pmap); 3742 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 3743 va = start + ptoa(diff); 3744 if ((va & PDRMASK) == 0 && va + NBPDR <= end && 3745 m->psind == 1 && pg_ps_enabled && 3746 pmap_enter_pde(pmap, va, m, prot)) 3747 m = &m[NBPDR / PAGE_SIZE - 1]; 3748 else 3749 mpte = pmap_enter_quick_locked(pmap, va, m, prot, 3750 mpte); 3751 m = TAILQ_NEXT(m, listq); 3752 } 3753 rw_wunlock(&pvh_global_lock); 3754 PMAP_UNLOCK(pmap); 3755} 3756 3757/* 3758 * this code makes some *MAJOR* assumptions: 3759 * 1. Current pmap & pmap exists. 3760 * 2. Not wired. 3761 * 3. Read access. 3762 * 4. No page table pages. 3763 * but is *MUCH* faster than pmap_enter... 3764 */ 3765 3766void 3767pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 3768{ 3769 3770 rw_wlock(&pvh_global_lock); 3771 PMAP_LOCK(pmap); 3772 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL); 3773 rw_wunlock(&pvh_global_lock); 3774 PMAP_UNLOCK(pmap); 3775} 3776 3777static vm_page_t 3778pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, 3779 vm_prot_t prot, vm_page_t mpte) 3780{ 3781 pt_entry_t *pte; 3782 vm_paddr_t pa; 3783 struct spglist free; 3784 3785 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 3786 (m->oflags & VPO_UNMANAGED) != 0, 3787 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 3788 rw_assert(&pvh_global_lock, RA_WLOCKED); 3789 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3790 3791 /* 3792 * In the case that a page table page is not 3793 * resident, we are creating it here. 3794 */ 3795 if (va < VM_MAXUSER_ADDRESS) { 3796 u_int ptepindex; 3797 pd_entry_t ptepa; 3798 3799 /* 3800 * Calculate pagetable page index 3801 */ 3802 ptepindex = va >> PDRSHIFT; 3803 if (mpte && (mpte->pindex == ptepindex)) { 3804 mpte->wire_count++; 3805 } else { 3806 /* 3807 * Get the page directory entry 3808 */ 3809 ptepa = pmap->pm_pdir[ptepindex]; 3810 3811 /* 3812 * If the page table page is mapped, we just increment 3813 * the hold count, and activate it. 3814 */ 3815 if (ptepa) { 3816 if (ptepa & PG_PS) 3817 return (NULL); 3818 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME); 3819 mpte->wire_count++; 3820 } else { 3821 mpte = _pmap_allocpte(pmap, ptepindex, 3822 PMAP_ENTER_NOSLEEP); 3823 if (mpte == NULL) 3824 return (mpte); 3825 } 3826 } 3827 } else { 3828 mpte = NULL; 3829 } 3830 3831 /* 3832 * This call to vtopte makes the assumption that we are 3833 * entering the page into the current pmap. In order to support 3834 * quick entry into any pmap, one would likely use pmap_pte_quick. 3835 * But that isn't as quick as vtopte. 3836 */ 3837 pte = vtopte(va); 3838 if (*pte) { 3839 if (mpte != NULL) { 3840 mpte->wire_count--; 3841 mpte = NULL; 3842 } 3843 return (mpte); 3844 } 3845 3846 /* 3847 * Enter on the PV list if part of our managed memory. 3848 */ 3849 if ((m->oflags & VPO_UNMANAGED) == 0 && 3850 !pmap_try_insert_pv_entry(pmap, va, m)) { 3851 if (mpte != NULL) { 3852 SLIST_INIT(&free); 3853 if (pmap_unwire_ptp(pmap, mpte, &free)) { 3854 pmap_invalidate_page(pmap, va); 3855 pmap_free_zero_pages(&free); 3856 } 3857 3858 mpte = NULL; 3859 } 3860 return (mpte); 3861 } 3862 3863 /* 3864 * Increment counters 3865 */ 3866 pmap->pm_stats.resident_count++; 3867 3868 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0); 3869#ifdef PAE 3870 if ((prot & VM_PROT_EXECUTE) == 0) 3871 pa |= pg_nx; 3872#endif 3873 3874 /* 3875 * Now validate mapping with RO protection 3876 */ 3877 if ((m->oflags & VPO_UNMANAGED) != 0) 3878 pte_store(pte, pa | PG_V | PG_U); 3879 else 3880 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED); 3881 return (mpte); 3882} 3883 3884/* 3885 * Make a temporary mapping for a physical address. This is only intended 3886 * to be used for panic dumps. 3887 */ 3888void * 3889pmap_kenter_temporary(vm_paddr_t pa, int i) 3890{ 3891 vm_offset_t va; 3892 3893 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE); 3894 pmap_kenter(va, pa); 3895 invlpg(va); 3896 return ((void *)crashdumpmap); 3897} 3898 3899/* 3900 * This code maps large physical mmap regions into the 3901 * processor address space. Note that some shortcuts 3902 * are taken, but the code works. 3903 */ 3904void 3905pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object, 3906 vm_pindex_t pindex, vm_size_t size) 3907{ 3908 pd_entry_t *pde; 3909 vm_paddr_t pa, ptepa; 3910 vm_page_t p; 3911 int pat_mode; 3912 3913 VM_OBJECT_ASSERT_WLOCKED(object); 3914 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 3915 ("pmap_object_init_pt: non-device object")); 3916 if (pseflag && 3917 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) { 3918 if (!vm_object_populate(object, pindex, pindex + atop(size))) 3919 return; 3920 p = vm_page_lookup(object, pindex); 3921 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3922 ("pmap_object_init_pt: invalid page %p", p)); 3923 pat_mode = p->md.pat_mode; 3924 3925 /* 3926 * Abort the mapping if the first page is not physically 3927 * aligned to a 2/4MB page boundary. 3928 */ 3929 ptepa = VM_PAGE_TO_PHYS(p); 3930 if (ptepa & (NBPDR - 1)) 3931 return; 3932 3933 /* 3934 * Skip the first page. Abort the mapping if the rest of 3935 * the pages are not physically contiguous or have differing 3936 * memory attributes. 3937 */ 3938 p = TAILQ_NEXT(p, listq); 3939 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size; 3940 pa += PAGE_SIZE) { 3941 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3942 ("pmap_object_init_pt: invalid page %p", p)); 3943 if (pa != VM_PAGE_TO_PHYS(p) || 3944 pat_mode != p->md.pat_mode) 3945 return; 3946 p = TAILQ_NEXT(p, listq); 3947 } 3948 3949 /* 3950 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and 3951 * "size" is a multiple of 2/4M, adding the PAT setting to 3952 * "pa" will not affect the termination of this loop. 3953 */ 3954 PMAP_LOCK(pmap); 3955 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa + 3956 size; pa += NBPDR) { 3957 pde = pmap_pde(pmap, addr); 3958 if (*pde == 0) { 3959 pde_store(pde, pa | PG_PS | PG_M | PG_A | 3960 PG_U | PG_RW | PG_V); 3961 pmap->pm_stats.resident_count += NBPDR / 3962 PAGE_SIZE; 3963 pmap_pde_mappings++; 3964 } 3965 /* Else continue on if the PDE is already valid. */ 3966 addr += NBPDR; 3967 } 3968 PMAP_UNLOCK(pmap); 3969 } 3970} 3971 3972/* 3973 * Routine: pmap_change_wiring 3974 * Function: Change the wiring attribute for a map/virtual-address 3975 * pair. 3976 * In/out conditions: 3977 * The mapping must already exist in the pmap. 3978 */ 3979void 3980pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 3981{ 3982 pd_entry_t *pde; 3983 pt_entry_t *pte; 3984 boolean_t are_queues_locked; 3985 3986 are_queues_locked = FALSE; 3987retry: 3988 PMAP_LOCK(pmap); 3989 pde = pmap_pde(pmap, va); 3990 if ((*pde & PG_PS) != 0) { 3991 if (!wired != ((*pde & PG_W) == 0)) { 3992 if (!are_queues_locked) { 3993 are_queues_locked = TRUE; 3994 if (!rw_try_wlock(&pvh_global_lock)) { 3995 PMAP_UNLOCK(pmap); 3996 rw_wlock(&pvh_global_lock); 3997 goto retry; 3998 } 3999 } 4000 if (!pmap_demote_pde(pmap, pde, va)) 4001 panic("pmap_change_wiring: demotion failed"); 4002 } else 4003 goto out; 4004 } 4005 pte = pmap_pte(pmap, va); 4006 4007 if (wired && !pmap_pte_w(pte)) 4008 pmap->pm_stats.wired_count++; 4009 else if (!wired && pmap_pte_w(pte)) 4010 pmap->pm_stats.wired_count--; 4011 4012 /* 4013 * Wiring is not a hardware characteristic so there is no need to 4014 * invalidate TLB. 4015 */ 4016 pmap_pte_set_w(pte, wired); 4017 pmap_pte_release(pte); 4018out: 4019 if (are_queues_locked) 4020 rw_wunlock(&pvh_global_lock); 4021 PMAP_UNLOCK(pmap); 4022} 4023 4024 4025 4026/* 4027 * Copy the range specified by src_addr/len 4028 * from the source map to the range dst_addr/len 4029 * in the destination map. 4030 * 4031 * This routine is only advisory and need not do anything. 4032 */ 4033 4034void 4035pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len, 4036 vm_offset_t src_addr) 4037{ 4038 struct spglist free; 4039 vm_offset_t addr; 4040 vm_offset_t end_addr = src_addr + len; 4041 vm_offset_t pdnxt; 4042 4043 if (dst_addr != src_addr) 4044 return; 4045 4046 if (!pmap_is_current(src_pmap)) 4047 return; 4048 4049 rw_wlock(&pvh_global_lock); 4050 if (dst_pmap < src_pmap) { 4051 PMAP_LOCK(dst_pmap); 4052 PMAP_LOCK(src_pmap); 4053 } else { 4054 PMAP_LOCK(src_pmap); 4055 PMAP_LOCK(dst_pmap); 4056 } 4057 sched_pin(); 4058 for (addr = src_addr; addr < end_addr; addr = pdnxt) { 4059 pt_entry_t *src_pte, *dst_pte; 4060 vm_page_t dstmpte, srcmpte; 4061 pd_entry_t srcptepaddr; 4062 u_int ptepindex; 4063 4064 KASSERT(addr < UPT_MIN_ADDRESS, 4065 ("pmap_copy: invalid to pmap_copy page tables")); 4066 4067 pdnxt = (addr + NBPDR) & ~PDRMASK; 4068 if (pdnxt < addr) 4069 pdnxt = end_addr; 4070 ptepindex = addr >> PDRSHIFT; 4071 4072 srcptepaddr = src_pmap->pm_pdir[ptepindex]; 4073 if (srcptepaddr == 0) 4074 continue; 4075 4076 if (srcptepaddr & PG_PS) { 4077 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr) 4078 continue; 4079 if (dst_pmap->pm_pdir[ptepindex] == 0 && 4080 ((srcptepaddr & PG_MANAGED) == 0 || 4081 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr & 4082 PG_PS_FRAME))) { 4083 dst_pmap->pm_pdir[ptepindex] = srcptepaddr & 4084 ~PG_W; 4085 dst_pmap->pm_stats.resident_count += 4086 NBPDR / PAGE_SIZE; 4087 } 4088 continue; 4089 } 4090 4091 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME); 4092 KASSERT(srcmpte->wire_count > 0, 4093 ("pmap_copy: source page table page is unused")); 4094 4095 if (pdnxt > end_addr) 4096 pdnxt = end_addr; 4097 4098 src_pte = vtopte(addr); 4099 while (addr < pdnxt) { 4100 pt_entry_t ptetemp; 4101 ptetemp = *src_pte; 4102 /* 4103 * we only virtual copy managed pages 4104 */ 4105 if ((ptetemp & PG_MANAGED) != 0) { 4106 dstmpte = pmap_allocpte(dst_pmap, addr, 4107 PMAP_ENTER_NOSLEEP); 4108 if (dstmpte == NULL) 4109 goto out; 4110 dst_pte = pmap_pte_quick(dst_pmap, addr); 4111 if (*dst_pte == 0 && 4112 pmap_try_insert_pv_entry(dst_pmap, addr, 4113 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) { 4114 /* 4115 * Clear the wired, modified, and 4116 * accessed (referenced) bits 4117 * during the copy. 4118 */ 4119 *dst_pte = ptetemp & ~(PG_W | PG_M | 4120 PG_A); 4121 dst_pmap->pm_stats.resident_count++; 4122 } else { 4123 SLIST_INIT(&free); 4124 if (pmap_unwire_ptp(dst_pmap, dstmpte, 4125 &free)) { 4126 pmap_invalidate_page(dst_pmap, 4127 addr); 4128 pmap_free_zero_pages(&free); 4129 } 4130 goto out; 4131 } 4132 if (dstmpte->wire_count >= srcmpte->wire_count) 4133 break; 4134 } 4135 addr += PAGE_SIZE; 4136 src_pte++; 4137 } 4138 } 4139out: 4140 sched_unpin(); 4141 rw_wunlock(&pvh_global_lock); 4142 PMAP_UNLOCK(src_pmap); 4143 PMAP_UNLOCK(dst_pmap); 4144} 4145 4146static __inline void 4147pagezero(void *page) 4148{ 4149#if defined(I686_CPU) 4150 if (cpu_class == CPUCLASS_686) { 4151#if defined(CPU_ENABLE_SSE) 4152 if (cpu_feature & CPUID_SSE2) 4153 sse2_pagezero(page); 4154 else 4155#endif 4156 i686_pagezero(page); 4157 } else 4158#endif 4159 bzero(page, PAGE_SIZE); 4160} 4161 4162/* 4163 * pmap_zero_page zeros the specified hardware page by mapping 4164 * the page into KVM and using bzero to clear its contents. 4165 */ 4166void 4167pmap_zero_page(vm_page_t m) 4168{ 4169 struct sysmaps *sysmaps; 4170 4171 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 4172 mtx_lock(&sysmaps->lock); 4173 if (*sysmaps->CMAP2) 4174 panic("pmap_zero_page: CMAP2 busy"); 4175 sched_pin(); 4176 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M | 4177 pmap_cache_bits(m->md.pat_mode, 0); 4178 invlcaddr(sysmaps->CADDR2); 4179 pagezero(sysmaps->CADDR2); 4180 *sysmaps->CMAP2 = 0; 4181 sched_unpin(); 4182 mtx_unlock(&sysmaps->lock); 4183} 4184 4185/* 4186 * pmap_zero_page_area zeros the specified hardware page by mapping 4187 * the page into KVM and using bzero to clear its contents. 4188 * 4189 * off and size may not cover an area beyond a single hardware page. 4190 */ 4191void 4192pmap_zero_page_area(vm_page_t m, int off, int size) 4193{ 4194 struct sysmaps *sysmaps; 4195 4196 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 4197 mtx_lock(&sysmaps->lock); 4198 if (*sysmaps->CMAP2) 4199 panic("pmap_zero_page_area: CMAP2 busy"); 4200 sched_pin(); 4201 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M | 4202 pmap_cache_bits(m->md.pat_mode, 0); 4203 invlcaddr(sysmaps->CADDR2); 4204 if (off == 0 && size == PAGE_SIZE) 4205 pagezero(sysmaps->CADDR2); 4206 else 4207 bzero((char *)sysmaps->CADDR2 + off, size); 4208 *sysmaps->CMAP2 = 0; 4209 sched_unpin(); 4210 mtx_unlock(&sysmaps->lock); 4211} 4212 4213/* 4214 * pmap_zero_page_idle zeros the specified hardware page by mapping 4215 * the page into KVM and using bzero to clear its contents. This 4216 * is intended to be called from the vm_pagezero process only and 4217 * outside of Giant. 4218 */ 4219void 4220pmap_zero_page_idle(vm_page_t m) 4221{ 4222 4223 if (*CMAP3) 4224 panic("pmap_zero_page_idle: CMAP3 busy"); 4225 sched_pin(); 4226 *CMAP3 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M | 4227 pmap_cache_bits(m->md.pat_mode, 0); 4228 invlcaddr(CADDR3); 4229 pagezero(CADDR3); 4230 *CMAP3 = 0; 4231 sched_unpin(); 4232} 4233 4234/* 4235 * pmap_copy_page copies the specified (machine independent) 4236 * page by mapping the page into virtual memory and using 4237 * bcopy to copy the page, one machine dependent page at a 4238 * time. 4239 */ 4240void 4241pmap_copy_page(vm_page_t src, vm_page_t dst) 4242{ 4243 struct sysmaps *sysmaps; 4244 4245 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 4246 mtx_lock(&sysmaps->lock); 4247 if (*sysmaps->CMAP1) 4248 panic("pmap_copy_page: CMAP1 busy"); 4249 if (*sysmaps->CMAP2) 4250 panic("pmap_copy_page: CMAP2 busy"); 4251 sched_pin(); 4252 *sysmaps->CMAP1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A | 4253 pmap_cache_bits(src->md.pat_mode, 0); 4254 invlcaddr(sysmaps->CADDR1); 4255 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M | 4256 pmap_cache_bits(dst->md.pat_mode, 0); 4257 invlcaddr(sysmaps->CADDR2); 4258 bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE); 4259 *sysmaps->CMAP1 = 0; 4260 *sysmaps->CMAP2 = 0; 4261 sched_unpin(); 4262 mtx_unlock(&sysmaps->lock); 4263} 4264 4265int unmapped_buf_allowed = 1; 4266 4267void 4268pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[], 4269 vm_offset_t b_offset, int xfersize) 4270{ 4271 struct sysmaps *sysmaps; 4272 vm_page_t a_pg, b_pg; 4273 char *a_cp, *b_cp; 4274 vm_offset_t a_pg_offset, b_pg_offset; 4275 int cnt; 4276 4277 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 4278 mtx_lock(&sysmaps->lock); 4279 if (*sysmaps->CMAP1 != 0) 4280 panic("pmap_copy_pages: CMAP1 busy"); 4281 if (*sysmaps->CMAP2 != 0) 4282 panic("pmap_copy_pages: CMAP2 busy"); 4283 sched_pin(); 4284 while (xfersize > 0) { 4285 a_pg = ma[a_offset >> PAGE_SHIFT]; 4286 a_pg_offset = a_offset & PAGE_MASK; 4287 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 4288 b_pg = mb[b_offset >> PAGE_SHIFT]; 4289 b_pg_offset = b_offset & PAGE_MASK; 4290 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 4291 *sysmaps->CMAP1 = PG_V | VM_PAGE_TO_PHYS(a_pg) | PG_A | 4292 pmap_cache_bits(a_pg->md.pat_mode, 0); 4293 invlcaddr(sysmaps->CADDR1); 4294 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(b_pg) | PG_A | 4295 PG_M | pmap_cache_bits(b_pg->md.pat_mode, 0); 4296 invlcaddr(sysmaps->CADDR2); 4297 a_cp = sysmaps->CADDR1 + a_pg_offset; 4298 b_cp = sysmaps->CADDR2 + b_pg_offset; 4299 bcopy(a_cp, b_cp, cnt); 4300 a_offset += cnt; 4301 b_offset += cnt; 4302 xfersize -= cnt; 4303 } 4304 *sysmaps->CMAP1 = 0; 4305 *sysmaps->CMAP2 = 0; 4306 sched_unpin(); 4307 mtx_unlock(&sysmaps->lock); 4308} 4309 4310/* 4311 * Returns true if the pmap's pv is one of the first 4312 * 16 pvs linked to from this page. This count may 4313 * be changed upwards or downwards in the future; it 4314 * is only necessary that true be returned for a small 4315 * subset of pmaps for proper page aging. 4316 */ 4317boolean_t 4318pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 4319{ 4320 struct md_page *pvh; 4321 pv_entry_t pv; 4322 int loops = 0; 4323 boolean_t rv; 4324 4325 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4326 ("pmap_page_exists_quick: page %p is not managed", m)); 4327 rv = FALSE; 4328 rw_wlock(&pvh_global_lock); 4329 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 4330 if (PV_PMAP(pv) == pmap) { 4331 rv = TRUE; 4332 break; 4333 } 4334 loops++; 4335 if (loops >= 16) 4336 break; 4337 } 4338 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) { 4339 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4340 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 4341 if (PV_PMAP(pv) == pmap) { 4342 rv = TRUE; 4343 break; 4344 } 4345 loops++; 4346 if (loops >= 16) 4347 break; 4348 } 4349 } 4350 rw_wunlock(&pvh_global_lock); 4351 return (rv); 4352} 4353 4354/* 4355 * pmap_page_wired_mappings: 4356 * 4357 * Return the number of managed mappings to the given physical page 4358 * that are wired. 4359 */ 4360int 4361pmap_page_wired_mappings(vm_page_t m) 4362{ 4363 int count; 4364 4365 count = 0; 4366 if ((m->oflags & VPO_UNMANAGED) != 0) 4367 return (count); 4368 rw_wlock(&pvh_global_lock); 4369 count = pmap_pvh_wired_mappings(&m->md, count); 4370 if ((m->flags & PG_FICTITIOUS) == 0) { 4371 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)), 4372 count); 4373 } 4374 rw_wunlock(&pvh_global_lock); 4375 return (count); 4376} 4377 4378/* 4379 * pmap_pvh_wired_mappings: 4380 * 4381 * Return the updated number "count" of managed mappings that are wired. 4382 */ 4383static int 4384pmap_pvh_wired_mappings(struct md_page *pvh, int count) 4385{ 4386 pmap_t pmap; 4387 pt_entry_t *pte; 4388 pv_entry_t pv; 4389 4390 rw_assert(&pvh_global_lock, RA_WLOCKED); 4391 sched_pin(); 4392 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 4393 pmap = PV_PMAP(pv); 4394 PMAP_LOCK(pmap); 4395 pte = pmap_pte_quick(pmap, pv->pv_va); 4396 if ((*pte & PG_W) != 0) 4397 count++; 4398 PMAP_UNLOCK(pmap); 4399 } 4400 sched_unpin(); 4401 return (count); 4402} 4403 4404/* 4405 * Returns TRUE if the given page is mapped individually or as part of 4406 * a 4mpage. Otherwise, returns FALSE. 4407 */ 4408boolean_t 4409pmap_page_is_mapped(vm_page_t m) 4410{ 4411 boolean_t rv; 4412 4413 if ((m->oflags & VPO_UNMANAGED) != 0) 4414 return (FALSE); 4415 rw_wlock(&pvh_global_lock); 4416 rv = !TAILQ_EMPTY(&m->md.pv_list) || 4417 ((m->flags & PG_FICTITIOUS) == 0 && 4418 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list)); 4419 rw_wunlock(&pvh_global_lock); 4420 return (rv); 4421} 4422 4423/* 4424 * Remove all pages from specified address space 4425 * this aids process exit speeds. Also, this code 4426 * is special cased for current process only, but 4427 * can have the more generic (and slightly slower) 4428 * mode enabled. This is much faster than pmap_remove 4429 * in the case of running down an entire address space. 4430 */ 4431void 4432pmap_remove_pages(pmap_t pmap) 4433{ 4434 pt_entry_t *pte, tpte; 4435 vm_page_t m, mpte, mt; 4436 pv_entry_t pv; 4437 struct md_page *pvh; 4438 struct pv_chunk *pc, *npc; 4439 struct spglist free; 4440 int field, idx; 4441 int32_t bit; 4442 uint32_t inuse, bitmask; 4443 int allfree; 4444 4445 if (pmap != PCPU_GET(curpmap)) { 4446 printf("warning: pmap_remove_pages called with non-current pmap\n"); 4447 return; 4448 } 4449 SLIST_INIT(&free); 4450 rw_wlock(&pvh_global_lock); 4451 PMAP_LOCK(pmap); 4452 sched_pin(); 4453 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 4454 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap, 4455 pc->pc_pmap)); 4456 allfree = 1; 4457 for (field = 0; field < _NPCM; field++) { 4458 inuse = ~pc->pc_map[field] & pc_freemask[field]; 4459 while (inuse != 0) { 4460 bit = bsfl(inuse); 4461 bitmask = 1UL << bit; 4462 idx = field * 32 + bit; 4463 pv = &pc->pc_pventry[idx]; 4464 inuse &= ~bitmask; 4465 4466 pte = pmap_pde(pmap, pv->pv_va); 4467 tpte = *pte; 4468 if ((tpte & PG_PS) == 0) { 4469 pte = vtopte(pv->pv_va); 4470 tpte = *pte & ~PG_PTE_PAT; 4471 } 4472 4473 if (tpte == 0) { 4474 printf( 4475 "TPTE at %p IS ZERO @ VA %08x\n", 4476 pte, pv->pv_va); 4477 panic("bad pte"); 4478 } 4479 4480/* 4481 * We cannot remove wired pages from a process' mapping at this time 4482 */ 4483 if (tpte & PG_W) { 4484 allfree = 0; 4485 continue; 4486 } 4487 4488 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 4489 KASSERT(m->phys_addr == (tpte & PG_FRAME), 4490 ("vm_page_t %p phys_addr mismatch %016jx %016jx", 4491 m, (uintmax_t)m->phys_addr, 4492 (uintmax_t)tpte)); 4493 4494 KASSERT((m->flags & PG_FICTITIOUS) != 0 || 4495 m < &vm_page_array[vm_page_array_size], 4496 ("pmap_remove_pages: bad tpte %#jx", 4497 (uintmax_t)tpte)); 4498 4499 pte_clear(pte); 4500 4501 /* 4502 * Update the vm_page_t clean/reference bits. 4503 */ 4504 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 4505 if ((tpte & PG_PS) != 0) { 4506 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++) 4507 vm_page_dirty(mt); 4508 } else 4509 vm_page_dirty(m); 4510 } 4511 4512 /* Mark free */ 4513 PV_STAT(pv_entry_frees++); 4514 PV_STAT(pv_entry_spare++); 4515 pv_entry_count--; 4516 pc->pc_map[field] |= bitmask; 4517 if ((tpte & PG_PS) != 0) { 4518 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 4519 pvh = pa_to_pvh(tpte & PG_PS_FRAME); 4520 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next); 4521 if (TAILQ_EMPTY(&pvh->pv_list)) { 4522 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++) 4523 if (TAILQ_EMPTY(&mt->md.pv_list)) 4524 vm_page_aflag_clear(mt, PGA_WRITEABLE); 4525 } 4526 mpte = pmap_lookup_pt_page(pmap, pv->pv_va); 4527 if (mpte != NULL) { 4528 pmap_remove_pt_page(pmap, mpte); 4529 pmap->pm_stats.resident_count--; 4530 KASSERT(mpte->wire_count == NPTEPG, 4531 ("pmap_remove_pages: pte page wire count error")); 4532 mpte->wire_count = 0; 4533 pmap_add_delayed_free_list(mpte, &free, FALSE); 4534 atomic_subtract_int(&cnt.v_wire_count, 1); 4535 } 4536 } else { 4537 pmap->pm_stats.resident_count--; 4538 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 4539 if (TAILQ_EMPTY(&m->md.pv_list) && 4540 (m->flags & PG_FICTITIOUS) == 0) { 4541 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4542 if (TAILQ_EMPTY(&pvh->pv_list)) 4543 vm_page_aflag_clear(m, PGA_WRITEABLE); 4544 } 4545 pmap_unuse_pt(pmap, pv->pv_va, &free); 4546 } 4547 } 4548 } 4549 if (allfree) { 4550 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 4551 free_pv_chunk(pc); 4552 } 4553 } 4554 sched_unpin(); 4555 pmap_invalidate_all(pmap); 4556 rw_wunlock(&pvh_global_lock); 4557 PMAP_UNLOCK(pmap); 4558 pmap_free_zero_pages(&free); 4559} 4560 4561/* 4562 * pmap_is_modified: 4563 * 4564 * Return whether or not the specified physical page was modified 4565 * in any physical maps. 4566 */ 4567boolean_t 4568pmap_is_modified(vm_page_t m) 4569{ 4570 boolean_t rv; 4571 4572 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4573 ("pmap_is_modified: page %p is not managed", m)); 4574 4575 /* 4576 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 4577 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 4578 * is clear, no PTEs can have PG_M set. 4579 */ 4580 VM_OBJECT_ASSERT_WLOCKED(m->object); 4581 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 4582 return (FALSE); 4583 rw_wlock(&pvh_global_lock); 4584 rv = pmap_is_modified_pvh(&m->md) || 4585 ((m->flags & PG_FICTITIOUS) == 0 && 4586 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m)))); 4587 rw_wunlock(&pvh_global_lock); 4588 return (rv); 4589} 4590 4591/* 4592 * Returns TRUE if any of the given mappings were used to modify 4593 * physical memory. Otherwise, returns FALSE. Both page and 2mpage 4594 * mappings are supported. 4595 */ 4596static boolean_t 4597pmap_is_modified_pvh(struct md_page *pvh) 4598{ 4599 pv_entry_t pv; 4600 pt_entry_t *pte; 4601 pmap_t pmap; 4602 boolean_t rv; 4603 4604 rw_assert(&pvh_global_lock, RA_WLOCKED); 4605 rv = FALSE; 4606 sched_pin(); 4607 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 4608 pmap = PV_PMAP(pv); 4609 PMAP_LOCK(pmap); 4610 pte = pmap_pte_quick(pmap, pv->pv_va); 4611 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW); 4612 PMAP_UNLOCK(pmap); 4613 if (rv) 4614 break; 4615 } 4616 sched_unpin(); 4617 return (rv); 4618} 4619 4620/* 4621 * pmap_is_prefaultable: 4622 * 4623 * Return whether or not the specified virtual address is elgible 4624 * for prefault. 4625 */ 4626boolean_t 4627pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 4628{ 4629 pd_entry_t *pde; 4630 pt_entry_t *pte; 4631 boolean_t rv; 4632 4633 rv = FALSE; 4634 PMAP_LOCK(pmap); 4635 pde = pmap_pde(pmap, addr); 4636 if (*pde != 0 && (*pde & PG_PS) == 0) { 4637 pte = vtopte(addr); 4638 rv = *pte == 0; 4639 } 4640 PMAP_UNLOCK(pmap); 4641 return (rv); 4642} 4643 4644/* 4645 * pmap_is_referenced: 4646 * 4647 * Return whether or not the specified physical page was referenced 4648 * in any physical maps. 4649 */ 4650boolean_t 4651pmap_is_referenced(vm_page_t m) 4652{ 4653 boolean_t rv; 4654 4655 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4656 ("pmap_is_referenced: page %p is not managed", m)); 4657 rw_wlock(&pvh_global_lock); 4658 rv = pmap_is_referenced_pvh(&m->md) || 4659 ((m->flags & PG_FICTITIOUS) == 0 && 4660 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m)))); 4661 rw_wunlock(&pvh_global_lock); 4662 return (rv); 4663} 4664 4665/* 4666 * Returns TRUE if any of the given mappings were referenced and FALSE 4667 * otherwise. Both page and 4mpage mappings are supported. 4668 */ 4669static boolean_t 4670pmap_is_referenced_pvh(struct md_page *pvh) 4671{ 4672 pv_entry_t pv; 4673 pt_entry_t *pte; 4674 pmap_t pmap; 4675 boolean_t rv; 4676 4677 rw_assert(&pvh_global_lock, RA_WLOCKED); 4678 rv = FALSE; 4679 sched_pin(); 4680 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 4681 pmap = PV_PMAP(pv); 4682 PMAP_LOCK(pmap); 4683 pte = pmap_pte_quick(pmap, pv->pv_va); 4684 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V); 4685 PMAP_UNLOCK(pmap); 4686 if (rv) 4687 break; 4688 } 4689 sched_unpin(); 4690 return (rv); 4691} 4692 4693/* 4694 * Clear the write and modified bits in each of the given page's mappings. 4695 */ 4696void 4697pmap_remove_write(vm_page_t m) 4698{ 4699 struct md_page *pvh; 4700 pv_entry_t next_pv, pv; 4701 pmap_t pmap; 4702 pd_entry_t *pde; 4703 pt_entry_t oldpte, *pte; 4704 vm_offset_t va; 4705 4706 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4707 ("pmap_remove_write: page %p is not managed", m)); 4708 4709 /* 4710 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 4711 * set by another thread while the object is locked. Thus, 4712 * if PGA_WRITEABLE is clear, no page table entries need updating. 4713 */ 4714 VM_OBJECT_ASSERT_WLOCKED(m->object); 4715 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 4716 return; 4717 rw_wlock(&pvh_global_lock); 4718 sched_pin(); 4719 if ((m->flags & PG_FICTITIOUS) != 0) 4720 goto small_mappings; 4721 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4722 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) { 4723 va = pv->pv_va; 4724 pmap = PV_PMAP(pv); 4725 PMAP_LOCK(pmap); 4726 pde = pmap_pde(pmap, va); 4727 if ((*pde & PG_RW) != 0) 4728 (void)pmap_demote_pde(pmap, pde, va); 4729 PMAP_UNLOCK(pmap); 4730 } 4731small_mappings: 4732 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 4733 pmap = PV_PMAP(pv); 4734 PMAP_LOCK(pmap); 4735 pde = pmap_pde(pmap, pv->pv_va); 4736 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found" 4737 " a 4mpage in page %p's pv list", m)); 4738 pte = pmap_pte_quick(pmap, pv->pv_va); 4739retry: 4740 oldpte = *pte; 4741 if ((oldpte & PG_RW) != 0) { 4742 /* 4743 * Regardless of whether a pte is 32 or 64 bits 4744 * in size, PG_RW and PG_M are among the least 4745 * significant 32 bits. 4746 */ 4747 if (!atomic_cmpset_int((u_int *)pte, oldpte, 4748 oldpte & ~(PG_RW | PG_M))) 4749 goto retry; 4750 if ((oldpte & PG_M) != 0) 4751 vm_page_dirty(m); 4752 pmap_invalidate_page(pmap, pv->pv_va); 4753 } 4754 PMAP_UNLOCK(pmap); 4755 } 4756 vm_page_aflag_clear(m, PGA_WRITEABLE); 4757 sched_unpin(); 4758 rw_wunlock(&pvh_global_lock); 4759} 4760 4761#define PMAP_TS_REFERENCED_MAX 5 4762 4763/* 4764 * pmap_ts_referenced: 4765 * 4766 * Return a count of reference bits for a page, clearing those bits. 4767 * It is not necessary for every reference bit to be cleared, but it 4768 * is necessary that 0 only be returned when there are truly no 4769 * reference bits set. 4770 * 4771 * XXX: The exact number of bits to check and clear is a matter that 4772 * should be tested and standardized at some point in the future for 4773 * optimal aging of shared pages. 4774 */ 4775int 4776pmap_ts_referenced(vm_page_t m) 4777{ 4778 struct md_page *pvh; 4779 pv_entry_t pv, pvf; 4780 pmap_t pmap; 4781 pd_entry_t *pde; 4782 pt_entry_t *pte; 4783 vm_paddr_t pa; 4784 int rtval = 0; 4785 4786 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4787 ("pmap_ts_referenced: page %p is not managed", m)); 4788 pa = VM_PAGE_TO_PHYS(m); 4789 pvh = pa_to_pvh(pa); 4790 rw_wlock(&pvh_global_lock); 4791 sched_pin(); 4792 if ((m->flags & PG_FICTITIOUS) != 0 || 4793 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL) 4794 goto small_mappings; 4795 pv = pvf; 4796 do { 4797 pmap = PV_PMAP(pv); 4798 PMAP_LOCK(pmap); 4799 pde = pmap_pde(pmap, pv->pv_va); 4800 if ((*pde & PG_A) != 0) { 4801 /* 4802 * Since this reference bit is shared by either 1024 4803 * or 512 4KB pages, it should not be cleared every 4804 * time it is tested. Apply a simple "hash" function 4805 * on the physical page number, the virtual superpage 4806 * number, and the pmap address to select one 4KB page 4807 * out of the 1024 or 512 on which testing the 4808 * reference bit will result in clearing that bit. 4809 * This function is designed to avoid the selection of 4810 * the same 4KB page for every 2- or 4MB page mapping. 4811 * 4812 * On demotion, a mapping that hasn't been referenced 4813 * is simply destroyed. To avoid the possibility of a 4814 * subsequent page fault on a demoted wired mapping, 4815 * always leave its reference bit set. Moreover, 4816 * since the superpage is wired, the current state of 4817 * its reference bit won't affect page replacement. 4818 */ 4819 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^ 4820 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 && 4821 (*pde & PG_W) == 0) { 4822 atomic_clear_int((u_int *)pde, PG_A); 4823 pmap_invalidate_page(pmap, pv->pv_va); 4824 } 4825 rtval++; 4826 } 4827 PMAP_UNLOCK(pmap); 4828 /* Rotate the PV list if it has more than one entry. */ 4829 if (TAILQ_NEXT(pv, pv_next) != NULL) { 4830 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next); 4831 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next); 4832 } 4833 if (rtval >= PMAP_TS_REFERENCED_MAX) 4834 goto out; 4835 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf); 4836small_mappings: 4837 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL) 4838 goto out; 4839 pv = pvf; 4840 do { 4841 pmap = PV_PMAP(pv); 4842 PMAP_LOCK(pmap); 4843 pde = pmap_pde(pmap, pv->pv_va); 4844 KASSERT((*pde & PG_PS) == 0, 4845 ("pmap_ts_referenced: found a 4mpage in page %p's pv list", 4846 m)); 4847 pte = pmap_pte_quick(pmap, pv->pv_va); 4848 if ((*pte & PG_A) != 0) { 4849 atomic_clear_int((u_int *)pte, PG_A); 4850 pmap_invalidate_page(pmap, pv->pv_va); 4851 rtval++; 4852 } 4853 PMAP_UNLOCK(pmap); 4854 /* Rotate the PV list if it has more than one entry. */ 4855 if (TAILQ_NEXT(pv, pv_next) != NULL) { 4856 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 4857 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 4858 } 4859 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval < 4860 PMAP_TS_REFERENCED_MAX); 4861out: 4862 sched_unpin(); 4863 rw_wunlock(&pvh_global_lock); 4864 return (rtval); 4865} 4866 4867/* 4868 * Apply the given advice to the specified range of addresses within the 4869 * given pmap. Depending on the advice, clear the referenced and/or 4870 * modified flags in each mapping and set the mapped page's dirty field. 4871 */ 4872void 4873pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice) 4874{ 4875 pd_entry_t oldpde, *pde; 4876 pt_entry_t *pte; 4877 vm_offset_t pdnxt; 4878 vm_page_t m; 4879 boolean_t anychanged, pv_lists_locked; 4880 4881 if (advice != MADV_DONTNEED && advice != MADV_FREE) 4882 return; 4883 if (pmap_is_current(pmap)) 4884 pv_lists_locked = FALSE; 4885 else { 4886 pv_lists_locked = TRUE; 4887resume: 4888 rw_wlock(&pvh_global_lock); 4889 sched_pin(); 4890 } 4891 anychanged = FALSE; 4892 PMAP_LOCK(pmap); 4893 for (; sva < eva; sva = pdnxt) { 4894 pdnxt = (sva + NBPDR) & ~PDRMASK; 4895 if (pdnxt < sva) 4896 pdnxt = eva; 4897 pde = pmap_pde(pmap, sva); 4898 oldpde = *pde; 4899 if ((oldpde & PG_V) == 0) 4900 continue; 4901 else if ((oldpde & PG_PS) != 0) { 4902 if ((oldpde & PG_MANAGED) == 0) 4903 continue; 4904 if (!pv_lists_locked) { 4905 pv_lists_locked = TRUE; 4906 if (!rw_try_wlock(&pvh_global_lock)) { 4907 if (anychanged) 4908 pmap_invalidate_all(pmap); 4909 PMAP_UNLOCK(pmap); 4910 goto resume; 4911 } 4912 sched_pin(); 4913 } 4914 if (!pmap_demote_pde(pmap, pde, sva)) { 4915 /* 4916 * The large page mapping was destroyed. 4917 */ 4918 continue; 4919 } 4920 4921 /* 4922 * Unless the page mappings are wired, remove the 4923 * mapping to a single page so that a subsequent 4924 * access may repromote. Since the underlying page 4925 * table page is fully populated, this removal never 4926 * frees a page table page. 4927 */ 4928 if ((oldpde & PG_W) == 0) { 4929 pte = pmap_pte_quick(pmap, sva); 4930 KASSERT((*pte & PG_V) != 0, 4931 ("pmap_advise: invalid PTE")); 4932 pmap_remove_pte(pmap, pte, sva, NULL); 4933 anychanged = TRUE; 4934 } 4935 } 4936 if (pdnxt > eva) 4937 pdnxt = eva; 4938 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 4939 sva += PAGE_SIZE) { 4940 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | 4941 PG_V)) 4942 continue; 4943 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 4944 if (advice == MADV_DONTNEED) { 4945 /* 4946 * Future calls to pmap_is_modified() 4947 * can be avoided by making the page 4948 * dirty now. 4949 */ 4950 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME); 4951 vm_page_dirty(m); 4952 } 4953 atomic_clear_int((u_int *)pte, PG_M | PG_A); 4954 } else if ((*pte & PG_A) != 0) 4955 atomic_clear_int((u_int *)pte, PG_A); 4956 else 4957 continue; 4958 if ((*pte & PG_G) != 0) 4959 pmap_invalidate_page(pmap, sva); 4960 else 4961 anychanged = TRUE; 4962 } 4963 } 4964 if (anychanged) 4965 pmap_invalidate_all(pmap); 4966 if (pv_lists_locked) { 4967 sched_unpin(); 4968 rw_wunlock(&pvh_global_lock); 4969 } 4970 PMAP_UNLOCK(pmap); 4971} 4972 4973/* 4974 * Clear the modify bits on the specified physical page. 4975 */ 4976void 4977pmap_clear_modify(vm_page_t m) 4978{ 4979 struct md_page *pvh; 4980 pv_entry_t next_pv, pv; 4981 pmap_t pmap; 4982 pd_entry_t oldpde, *pde; 4983 pt_entry_t oldpte, *pte; 4984 vm_offset_t va; 4985 4986 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4987 ("pmap_clear_modify: page %p is not managed", m)); 4988 VM_OBJECT_ASSERT_WLOCKED(m->object); 4989 KASSERT(!vm_page_xbusied(m), 4990 ("pmap_clear_modify: page %p is exclusive busied", m)); 4991 4992 /* 4993 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set. 4994 * If the object containing the page is locked and the page is not 4995 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 4996 */ 4997 if ((m->aflags & PGA_WRITEABLE) == 0) 4998 return; 4999 rw_wlock(&pvh_global_lock); 5000 sched_pin(); 5001 if ((m->flags & PG_FICTITIOUS) != 0) 5002 goto small_mappings; 5003 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 5004 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) { 5005 va = pv->pv_va; 5006 pmap = PV_PMAP(pv); 5007 PMAP_LOCK(pmap); 5008 pde = pmap_pde(pmap, va); 5009 oldpde = *pde; 5010 if ((oldpde & PG_RW) != 0) { 5011 if (pmap_demote_pde(pmap, pde, va)) { 5012 if ((oldpde & PG_W) == 0) { 5013 /* 5014 * Write protect the mapping to a 5015 * single page so that a subsequent 5016 * write access may repromote. 5017 */ 5018 va += VM_PAGE_TO_PHYS(m) - (oldpde & 5019 PG_PS_FRAME); 5020 pte = pmap_pte_quick(pmap, va); 5021 oldpte = *pte; 5022 if ((oldpte & PG_V) != 0) { 5023 /* 5024 * Regardless of whether a pte is 32 or 64 bits 5025 * in size, PG_RW and PG_M are among the least 5026 * significant 32 bits. 5027 */ 5028 while (!atomic_cmpset_int((u_int *)pte, 5029 oldpte, 5030 oldpte & ~(PG_M | PG_RW))) 5031 oldpte = *pte; 5032 vm_page_dirty(m); 5033 pmap_invalidate_page(pmap, va); 5034 } 5035 } 5036 } 5037 } 5038 PMAP_UNLOCK(pmap); 5039 } 5040small_mappings: 5041 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 5042 pmap = PV_PMAP(pv); 5043 PMAP_LOCK(pmap); 5044 pde = pmap_pde(pmap, pv->pv_va); 5045 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found" 5046 " a 4mpage in page %p's pv list", m)); 5047 pte = pmap_pte_quick(pmap, pv->pv_va); 5048 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 5049 /* 5050 * Regardless of whether a pte is 32 or 64 bits 5051 * in size, PG_M is among the least significant 5052 * 32 bits. 5053 */ 5054 atomic_clear_int((u_int *)pte, PG_M); 5055 pmap_invalidate_page(pmap, pv->pv_va); 5056 } 5057 PMAP_UNLOCK(pmap); 5058 } 5059 sched_unpin(); 5060 rw_wunlock(&pvh_global_lock); 5061} 5062 5063/* 5064 * Miscellaneous support routines follow 5065 */ 5066 5067/* Adjust the cache mode for a 4KB page mapped via a PTE. */ 5068static __inline void 5069pmap_pte_attr(pt_entry_t *pte, int cache_bits) 5070{ 5071 u_int opte, npte; 5072 5073 /* 5074 * The cache mode bits are all in the low 32-bits of the 5075 * PTE, so we can just spin on updating the low 32-bits. 5076 */ 5077 do { 5078 opte = *(u_int *)pte; 5079 npte = opte & ~PG_PTE_CACHE; 5080 npte |= cache_bits; 5081 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte)); 5082} 5083 5084/* Adjust the cache mode for a 2/4MB page mapped via a PDE. */ 5085static __inline void 5086pmap_pde_attr(pd_entry_t *pde, int cache_bits) 5087{ 5088 u_int opde, npde; 5089 5090 /* 5091 * The cache mode bits are all in the low 32-bits of the 5092 * PDE, so we can just spin on updating the low 32-bits. 5093 */ 5094 do { 5095 opde = *(u_int *)pde; 5096 npde = opde & ~PG_PDE_CACHE; 5097 npde |= cache_bits; 5098 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde)); 5099} 5100 5101/* 5102 * Map a set of physical memory pages into the kernel virtual 5103 * address space. Return a pointer to where it is mapped. This 5104 * routine is intended to be used for mapping device memory, 5105 * NOT real memory. 5106 */ 5107void * 5108pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode) 5109{ 5110 vm_offset_t va, offset; 5111 vm_size_t tmpsize; 5112 5113 offset = pa & PAGE_MASK; 5114 size = round_page(offset + size); 5115 pa = pa & PG_FRAME; 5116 5117 if (pa < KERNLOAD && pa + size <= KERNLOAD) 5118 va = KERNBASE + pa; 5119 else 5120 va = kva_alloc(size); 5121 if (!va) 5122 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 5123 5124 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE) 5125 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode); 5126 pmap_invalidate_range(kernel_pmap, va, va + tmpsize); 5127 pmap_invalidate_cache_range(va, va + size); 5128 return ((void *)(va + offset)); 5129} 5130 5131void * 5132pmap_mapdev(vm_paddr_t pa, vm_size_t size) 5133{ 5134 5135 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE)); 5136} 5137 5138void * 5139pmap_mapbios(vm_paddr_t pa, vm_size_t size) 5140{ 5141 5142 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK)); 5143} 5144 5145void 5146pmap_unmapdev(vm_offset_t va, vm_size_t size) 5147{ 5148 vm_offset_t base, offset; 5149 5150 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD) 5151 return; 5152 base = trunc_page(va); 5153 offset = va & PAGE_MASK; 5154 size = round_page(offset + size); 5155 kva_free(base, size); 5156} 5157 5158/* 5159 * Sets the memory attribute for the specified page. 5160 */ 5161void 5162pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma) 5163{ 5164 5165 m->md.pat_mode = ma; 5166 if ((m->flags & PG_FICTITIOUS) != 0) 5167 return; 5168 5169 /* 5170 * If "m" is a normal page, flush it from the cache. 5171 * See pmap_invalidate_cache_range(). 5172 * 5173 * First, try to find an existing mapping of the page by sf 5174 * buffer. sf_buf_invalidate_cache() modifies mapping and 5175 * flushes the cache. 5176 */ 5177 if (sf_buf_invalidate_cache(m)) 5178 return; 5179 5180 /* 5181 * If page is not mapped by sf buffer, but CPU does not 5182 * support self snoop, map the page transient and do 5183 * invalidation. In the worst case, whole cache is flushed by 5184 * pmap_invalidate_cache_range(). 5185 */ 5186 if ((cpu_feature & CPUID_SS) == 0) 5187 pmap_flush_page(m); 5188} 5189 5190static void 5191pmap_flush_page(vm_page_t m) 5192{ 5193 struct sysmaps *sysmaps; 5194 vm_offset_t sva, eva; 5195 5196 if ((cpu_feature & CPUID_CLFSH) != 0) { 5197 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 5198 mtx_lock(&sysmaps->lock); 5199 if (*sysmaps->CMAP2) 5200 panic("pmap_flush_page: CMAP2 busy"); 5201 sched_pin(); 5202 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | 5203 PG_A | PG_M | pmap_cache_bits(m->md.pat_mode, 0); 5204 invlcaddr(sysmaps->CADDR2); 5205 sva = (vm_offset_t)sysmaps->CADDR2; 5206 eva = sva + PAGE_SIZE; 5207 5208 /* 5209 * Use mfence despite the ordering implied by 5210 * mtx_{un,}lock() because clflush is not guaranteed 5211 * to be ordered by any other instruction. 5212 */ 5213 mfence(); 5214 for (; sva < eva; sva += cpu_clflush_line_size) 5215 clflush(sva); 5216 mfence(); 5217 *sysmaps->CMAP2 = 0; 5218 sched_unpin(); 5219 mtx_unlock(&sysmaps->lock); 5220 } else 5221 pmap_invalidate_cache(); 5222} 5223 5224/* 5225 * Changes the specified virtual address range's memory type to that given by 5226 * the parameter "mode". The specified virtual address range must be 5227 * completely contained within either the kernel map. 5228 * 5229 * Returns zero if the change completed successfully, and either EINVAL or 5230 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part 5231 * of the virtual address range was not mapped, and ENOMEM is returned if 5232 * there was insufficient memory available to complete the change. 5233 */ 5234int 5235pmap_change_attr(vm_offset_t va, vm_size_t size, int mode) 5236{ 5237 vm_offset_t base, offset, tmpva; 5238 pd_entry_t *pde; 5239 pt_entry_t *pte; 5240 int cache_bits_pte, cache_bits_pde; 5241 boolean_t changed; 5242 5243 base = trunc_page(va); 5244 offset = va & PAGE_MASK; 5245 size = round_page(offset + size); 5246 5247 /* 5248 * Only supported on kernel virtual addresses above the recursive map. 5249 */ 5250 if (base < VM_MIN_KERNEL_ADDRESS) 5251 return (EINVAL); 5252 5253 cache_bits_pde = pmap_cache_bits(mode, 1); 5254 cache_bits_pte = pmap_cache_bits(mode, 0); 5255 changed = FALSE; 5256 5257 /* 5258 * Pages that aren't mapped aren't supported. Also break down 5259 * 2/4MB pages into 4KB pages if required. 5260 */ 5261 PMAP_LOCK(kernel_pmap); 5262 for (tmpva = base; tmpva < base + size; ) { 5263 pde = pmap_pde(kernel_pmap, tmpva); 5264 if (*pde == 0) { 5265 PMAP_UNLOCK(kernel_pmap); 5266 return (EINVAL); 5267 } 5268 if (*pde & PG_PS) { 5269 /* 5270 * If the current 2/4MB page already has 5271 * the required memory type, then we need not 5272 * demote this page. Just increment tmpva to 5273 * the next 2/4MB page frame. 5274 */ 5275 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) { 5276 tmpva = trunc_4mpage(tmpva) + NBPDR; 5277 continue; 5278 } 5279 5280 /* 5281 * If the current offset aligns with a 2/4MB 5282 * page frame and there is at least 2/4MB left 5283 * within the range, then we need not break 5284 * down this page into 4KB pages. 5285 */ 5286 if ((tmpva & PDRMASK) == 0 && 5287 tmpva + PDRMASK < base + size) { 5288 tmpva += NBPDR; 5289 continue; 5290 } 5291 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) { 5292 PMAP_UNLOCK(kernel_pmap); 5293 return (ENOMEM); 5294 } 5295 } 5296 pte = vtopte(tmpva); 5297 if (*pte == 0) { 5298 PMAP_UNLOCK(kernel_pmap); 5299 return (EINVAL); 5300 } 5301 tmpva += PAGE_SIZE; 5302 } 5303 PMAP_UNLOCK(kernel_pmap); 5304 5305 /* 5306 * Ok, all the pages exist, so run through them updating their 5307 * cache mode if required. 5308 */ 5309 for (tmpva = base; tmpva < base + size; ) { 5310 pde = pmap_pde(kernel_pmap, tmpva); 5311 if (*pde & PG_PS) { 5312 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) { 5313 pmap_pde_attr(pde, cache_bits_pde); 5314 changed = TRUE; 5315 } 5316 tmpva = trunc_4mpage(tmpva) + NBPDR; 5317 } else { 5318 pte = vtopte(tmpva); 5319 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) { 5320 pmap_pte_attr(pte, cache_bits_pte); 5321 changed = TRUE; 5322 } 5323 tmpva += PAGE_SIZE; 5324 } 5325 } 5326 5327 /* 5328 * Flush CPU caches to make sure any data isn't cached that 5329 * shouldn't be, etc. 5330 */ 5331 if (changed) { 5332 pmap_invalidate_range(kernel_pmap, base, tmpva); 5333 pmap_invalidate_cache_range(base, tmpva); 5334 } 5335 return (0); 5336} 5337 5338/* 5339 * perform the pmap work for mincore 5340 */ 5341int 5342pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa) 5343{ 5344 pd_entry_t *pdep; 5345 pt_entry_t *ptep, pte; 5346 vm_paddr_t pa; 5347 int val; 5348 5349 PMAP_LOCK(pmap); 5350retry: 5351 pdep = pmap_pde(pmap, addr); 5352 if (*pdep != 0) { 5353 if (*pdep & PG_PS) { 5354 pte = *pdep; 5355 /* Compute the physical address of the 4KB page. */ 5356 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) & 5357 PG_FRAME; 5358 val = MINCORE_SUPER; 5359 } else { 5360 ptep = pmap_pte(pmap, addr); 5361 pte = *ptep; 5362 pmap_pte_release(ptep); 5363 pa = pte & PG_FRAME; 5364 val = 0; 5365 } 5366 } else { 5367 pte = 0; 5368 pa = 0; 5369 val = 0; 5370 } 5371 if ((pte & PG_V) != 0) { 5372 val |= MINCORE_INCORE; 5373 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 5374 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 5375 if ((pte & PG_A) != 0) 5376 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 5377 } 5378 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 5379 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && 5380 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) { 5381 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */ 5382 if (vm_page_pa_tryrelock(pmap, pa, locked_pa)) 5383 goto retry; 5384 } else 5385 PA_UNLOCK_COND(*locked_pa); 5386 PMAP_UNLOCK(pmap); 5387 return (val); 5388} 5389 5390void 5391pmap_activate(struct thread *td) 5392{ 5393 pmap_t pmap, oldpmap; 5394 u_int cpuid; 5395 u_int32_t cr3; 5396 5397 critical_enter(); 5398 pmap = vmspace_pmap(td->td_proc->p_vmspace); 5399 oldpmap = PCPU_GET(curpmap); 5400 cpuid = PCPU_GET(cpuid); 5401#if defined(SMP) 5402 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active); 5403 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 5404#else 5405 CPU_CLR(cpuid, &oldpmap->pm_active); 5406 CPU_SET(cpuid, &pmap->pm_active); 5407#endif 5408#ifdef PAE 5409 cr3 = vtophys(pmap->pm_pdpt); 5410#else 5411 cr3 = vtophys(pmap->pm_pdir); 5412#endif 5413 /* 5414 * pmap_activate is for the current thread on the current cpu 5415 */ 5416 td->td_pcb->pcb_cr3 = cr3; 5417 load_cr3(cr3); 5418 PCPU_SET(curpmap, pmap); 5419 critical_exit(); 5420} 5421 5422void 5423pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 5424{ 5425} 5426 5427/* 5428 * Increase the starting virtual address of the given mapping if a 5429 * different alignment might result in more superpage mappings. 5430 */ 5431void 5432pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 5433 vm_offset_t *addr, vm_size_t size) 5434{ 5435 vm_offset_t superpage_offset; 5436 5437 if (size < NBPDR) 5438 return; 5439 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 5440 offset += ptoa(object->pg_color); 5441 superpage_offset = offset & PDRMASK; 5442 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR || 5443 (*addr & PDRMASK) == superpage_offset) 5444 return; 5445 if ((*addr & PDRMASK) < superpage_offset) 5446 *addr = (*addr & ~PDRMASK) + superpage_offset; 5447 else 5448 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset; 5449} 5450 5451 5452#if defined(PMAP_DEBUG) 5453pmap_pid_dump(int pid) 5454{ 5455 pmap_t pmap; 5456 struct proc *p; 5457 int npte = 0; 5458 int index; 5459 5460 sx_slock(&allproc_lock); 5461 FOREACH_PROC_IN_SYSTEM(p) { 5462 if (p->p_pid != pid) 5463 continue; 5464 5465 if (p->p_vmspace) { 5466 int i,j; 5467 index = 0; 5468 pmap = vmspace_pmap(p->p_vmspace); 5469 for (i = 0; i < NPDEPTD; i++) { 5470 pd_entry_t *pde; 5471 pt_entry_t *pte; 5472 vm_offset_t base = i << PDRSHIFT; 5473 5474 pde = &pmap->pm_pdir[i]; 5475 if (pde && pmap_pde_v(pde)) { 5476 for (j = 0; j < NPTEPG; j++) { 5477 vm_offset_t va = base + (j << PAGE_SHIFT); 5478 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) { 5479 if (index) { 5480 index = 0; 5481 printf("\n"); 5482 } 5483 sx_sunlock(&allproc_lock); 5484 return (npte); 5485 } 5486 pte = pmap_pte(pmap, va); 5487 if (pte && pmap_pte_v(pte)) { 5488 pt_entry_t pa; 5489 vm_page_t m; 5490 pa = *pte; 5491 m = PHYS_TO_VM_PAGE(pa & PG_FRAME); 5492 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x", 5493 va, pa, m->hold_count, m->wire_count, m->flags); 5494 npte++; 5495 index++; 5496 if (index >= 2) { 5497 index = 0; 5498 printf("\n"); 5499 } else { 5500 printf(" "); 5501 } 5502 } 5503 } 5504 } 5505 } 5506 } 5507 } 5508 sx_sunlock(&allproc_lock); 5509 return (npte); 5510} 5511#endif 5512 5513#if defined(DEBUG) 5514 5515static void pads(pmap_t pm); 5516void pmap_pvdump(vm_paddr_t pa); 5517 5518/* print address space of pmap*/ 5519static void 5520pads(pmap_t pm) 5521{ 5522 int i, j; 5523 vm_paddr_t va; 5524 pt_entry_t *ptep; 5525 5526 if (pm == kernel_pmap) 5527 return; 5528 for (i = 0; i < NPDEPTD; i++) 5529 if (pm->pm_pdir[i]) 5530 for (j = 0; j < NPTEPG; j++) { 5531 va = (i << PDRSHIFT) + (j << PAGE_SHIFT); 5532 if (pm == kernel_pmap && va < KERNBASE) 5533 continue; 5534 if (pm != kernel_pmap && va > UPT_MAX_ADDRESS) 5535 continue; 5536 ptep = pmap_pte(pm, va); 5537 if (pmap_pte_v(ptep)) 5538 printf("%x:%x ", va, *ptep); 5539 }; 5540 5541} 5542 5543void 5544pmap_pvdump(vm_paddr_t pa) 5545{ 5546 pv_entry_t pv; 5547 pmap_t pmap; 5548 vm_page_t m; 5549 5550 printf("pa %x", pa); 5551 m = PHYS_TO_VM_PAGE(pa); 5552 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 5553 pmap = PV_PMAP(pv); 5554 printf(" -> pmap %p, va %x", (void *)pmap, pv->pv_va); 5555 pads(pmap); 5556 } 5557 printf(" "); 5558} 5559#endif 5560